JP2019114797A - Solid state image sensor and manufacturing method of the same - Google Patents

Abstract

To provide a solid state image sensor capable of increasing the number of saturated electrons that can be stored in a charge storage region of each pixel and manufacturing method of the same.SOLUTION: The solid state image sensor includes: a pixel having a charge storage region in a semiconductor layer; a transfer gate; and a pixel separation region. Included is a high concentration region, provided at a peripheral edge part excluding a peripheral edge part facing a transfer gate out of a peripheral edge part of the charge storage region, containing the same conductive type impurity as a conductive type of an impurity contained in the charge storage region at higher concentration than at a center part of the charge storage region.SELECTED DRAWING: Figure 4

Description

  Embodiments of the present invention relate to a solid-state imaging device and a method of manufacturing the solid-state imaging device.

  Conventionally, in a solid-state imaging device, a pixel separation area that electrically separates each of a plurality of photoelectric conversion elements arranged in two dimensions corresponding to each pixel of a captured image and each photoelectric conversion element is provided. And Each pixel photoelectrically converts incident light into a signal charge of an amount according to the amount of light received, and accumulates it in the charge accumulation region in each pixel.

  In such a solid-state imaging device, the larger the number of signal charges (the number of saturated electrons) that can be stored in the charge storage region, the wider the dynamic range of photoelectric conversion. However, in each pixel, the number of saturated electrons in the peripheral portion of the charge storage region may be smaller than that in the central portion of the charge storage region.

JP, 2010-27750, A

  An object of one embodiment is to provide a solid-state imaging device capable of increasing the number of saturated electrons that can be accumulated in the charge accumulation region of each pixel, and a method of manufacturing the solid-state imaging device.

  According to one embodiment, a solid state imaging device is provided. The pixel is provided with a pixel having a charge storage region in a semiconductor layer, a transfer gate, and a pixel separation region, and provided on the peripheral edge of the charge storage region except for the peripheral edge facing the transfer gate, the charge storage A high concentration region is provided which contains an impurity of the same conductivity type as that of the impurity contained in the region at a higher concentration than the central portion of the charge storage region.

FIG. 1 is a block diagram showing a schematic configuration of a digital camera provided with a solid-state imaging device according to an embodiment. FIG. 2 is a block diagram showing a schematic configuration of the solid-state imaging device according to the embodiment. FIG. 3 is a schematic plan view showing a portion corresponding to one pixel in the pixel array according to the embodiment. FIG. 4 is an explanatory view showing a schematic cross section taken along line A-A ′ of the pixel array shown in FIG. 3 according to the embodiment. FIG. 5 is an explanatory view showing a distribution of potentials in the charge storage region of the pixel according to the embodiment. FIG. 6 is an explanatory view in cross section showing the manufacturing process of the solid-state imaging device according to the embodiment. FIG. 7 is an explanatory view in cross section showing the manufacturing process of the solid-state imaging device according to the embodiment. FIG. 8 is an explanatory view in cross section showing the manufacturing process of the solid-state imaging device according to the embodiment. FIG. 9 is a schematic plan view showing a part of the surface on the light receiving surface side of the pixel array according to the modification of the embodiment.

  Hereinafter, a solid-state imaging device and a method of manufacturing the solid-state imaging device according to the embodiment will be described in detail with reference to the accompanying drawings. The present invention is not limited by this embodiment.

  FIG. 1 is a block diagram showing a schematic configuration of a digital camera 1 provided with a solid-state imaging device 14 according to the embodiment. As shown in FIG. 1, the digital camera 1 includes a camera module 11 and a post-processing unit 12.

  The camera module 11 includes an imaging optical system 13 and a solid-state imaging device 14. The imaging optical system 13 takes in light from a subject and forms a subject image. The solid-state imaging device 14 captures an object image formed by the imaging optical system 13, and outputs an image signal obtained by imaging to the post-processing unit 12. The camera module 11 is applied to an electronic device such as a camera-equipped mobile terminal other than the digital camera 1, for example.

  The post-processing unit 12 includes an image signal processor (ISP) 15, a storage unit 16, and a display unit 17. The ISP 15 performs signal processing of an image signal input from the solid-state imaging device 14. The ISP 15 performs high image quality processing such as noise removal processing, defective pixel correction processing, resolution conversion processing, and the like.

  Then, the ISP 15 outputs the image signal after signal processing to the storage unit 16, the display unit 17, and a signal processing circuit 21 (see FIG. 2) described later included in the solid-state imaging device 14 in the camera module 11. The image signal fed back from the ISP 15 to the camera module 11 is used for adjustment and control of the solid-state imaging device 14.

  The storage unit 16 stores an image signal input from the ISP 15 as an image. In addition, the storage unit 16 outputs the image signal of the stored image to the display unit 17 according to the user's operation or the like. The display unit 17 displays an image according to the image signal input from the ISP 15 or the storage unit 16. The display unit 17 is, for example, a liquid crystal display.

  Next, referring to FIG. 2, the solid-state imaging device 14 provided in the camera module 11 will be described. FIG. 2 is a block diagram showing a schematic configuration of the solid-state imaging device 14 according to the embodiment. As shown in FIG. 2, the solid-state imaging device 14 includes an image sensor 20 and a signal processing circuit 21.

  Here, a case will be described where the image sensor 20 is a so-called surface-illuminated CMOS (Complementary Metal Oxide Semiconductor) image sensor in which a wiring layer is formed on the surface of the pixel on which incident light is photoelectrically converted. . The image sensor 20 according to the embodiment is not limited to the front side illumination type CMOS image sensor, and may be any image sensor such as a back side illumination type CMOS image sensor or a CCD (Charge Coupled Device) image sensor. Good.

  The image sensor 20 includes a peripheral circuit 22 and a pixel array 23. The peripheral circuit 22 also includes a vertical shift register 24, a timing control unit 25, a CDS (correlated double sampling) 26, an ADC (analog-digital conversion unit) 27, and a line memory 28, which are mainly configured by analog circuits. Be done.

  The pixel array 23 is provided in an imaging region of the image sensor 20. In the pixel array 23, a plurality of photoelectric conversion elements corresponding to each pixel of a captured image are arranged in a two-dimensional array (matrix) in the horizontal direction (row direction) and the vertical direction (column direction).

  Then, the pixel array 23 causes the photoelectric conversion element of each pixel to generate a signal charge (for example, an electron) according to the incident light amount, and accumulates it in the charge accumulation region in each pixel. In the present embodiment, the dynamic range of photoelectric conversion by each pixel is expanded by increasing the number of saturated electrons that can be stored in each charge storage region.

  Each pixel of the pixel array 23 will be described in detail with reference to FIGS. The pixel array 23 acquires a signal of a voltage corresponding to the amount of charge photoelectrically converted by each pixel as a pixel signal indicating the luminance of each pixel in the captured image.

  The timing control unit 25 is a processing unit that outputs a pulse signal as a reference of operation timing to the vertical shift register 24, the CDS 26, the ADC 27, and the line memory 28. The vertical shift register 24 is a processing unit that outputs, to the pixel array 23, a selection signal for sequentially selecting, in units of rows, pixels from which signal charges are read out of a plurality of pixels arranged two-dimensionally in an array (matrix). .

  The pixel array 23 outputs, from the pixels to the CDS 26, the signal charges accumulated in the respective pixels selected in units of rows by the selection signal input from the vertical shift register 24 as the pixel signals indicating the luminance of the respective pixels in the captured image. .

  The CDS 26 is a processing unit that removes noise from the pixel signal input from the pixel array 23 by correlated double sampling and outputs the noise to the ADC 27. The ADC 27 is a processing unit that converts an analog pixel signal input from the CDS 26 into a digital pixel signal and outputs the digital pixel signal to the line memory 28. The line memory 28 is a processing unit that temporarily holds pixel signals input from the ADC 27 and outputs the pixel signals to the signal processing circuit 21 for each row of pixels in the pixel array 23.

  The signal processing circuit 21 is a processing unit that performs predetermined signal processing on pixel signals input from the line memory 28 and outputs the processed signal to the post-processing unit 12 and is mainly configured by a digital circuit. The signal processing circuit 21 performs signal processing such as lens shading correction, flaw correction, and noise reduction processing on the pixel signal, for example.

  As described above, in the image sensor 20, a plurality of pixels arranged in the pixel array 23 photoelectrically convert incident light into signal charges of an amount according to the amount of received light and accumulates the peripheral circuits 22 in each pixel. Imaging is performed by reading out the signal charge as a pixel signal.

  Next, the pixel array 23 according to the embodiment will be described with reference to FIGS. 3 to 5. FIG. 3 is a schematic plan view showing a portion corresponding to one pixel in the pixel array 23 according to the embodiment, and FIG. 4 is a line AA 'of the pixel array 23 shown in FIG. 3 according to the embodiment. It is explanatory drawing which shows the typical cross section by. FIG. 5 is an explanatory view showing the distribution of the potential potential in the charge storage region of the pixel according to the embodiment.

  In FIG. 3, in order to facilitate understanding of the configuration of the charge storage region in each pixel, a semiconductor region 52 of the second conductivity type, which will be described later, provided on the charge storage region, an antireflective film 34, a color filter CF, And the pixel in a state in which the microlens ML (see FIG. 4) is removed.

  As shown in FIG. 3, the pixel array 23 includes a semiconductor region 51 of the first conductivity type, a high concentration region 53, a transfer gate TRG, and a floating diffusion FD. The semiconductor region 51 of the first conductivity type is an N-type region in which an N-type impurity such as phosphorus is doped in the semiconductor layer, for example.

  The high concentration region 53 is provided at a position surrounding the side surface of the semiconductor region 51 of the first conductivity type except the side surface facing the transfer gate TRG. The impurity of the type is an N-type region doped at a higher concentration than the semiconductor region 51 of the first conductivity type. The semiconductor region 51 and the high concentration region 53 of the first conductivity type function as charge storage regions for storing signal charges photoelectrically converted by the pixels.

  The transfer gate TRG is provided on a region adjacent to the semiconductor region 51 of the first conductivity type in the semiconductor layer, and is formed of, for example, polysilicon. Further, the floating diffusion FD is a region in which an N-type impurity such as phosphorus is doped at a position facing the semiconductor region 51 of the first conductivity type in the semiconductor layer with the transfer gate TRG interposed therebetween.

  Further, the pixel array 23 is a surface pixel separation diffusion region 42 and an insulating member at a position surrounding the region where the semiconductor region 51 of the first conductivity type, the high concentration region 53, the transfer gate TRG, and the floating diffusion FD is provided in plan view. 43 is provided.

  The surface layer pixel isolation diffusion region 42 is a P-type region in which a semiconductor layer is doped with a P-type impurity such as boron, for example. The insulating member 43 is, for example, silicon oxide, and is provided in the surface element isolation diffusion region 42. The insulating member 43 is, for example, STI (Shallow Trench Isolation), and electrically isolates each pixel.

  The sectional structure of one pixel portion in the pixel array 23 is as shown in FIG. Specifically, focusing on one pixel in the pixel array 23, as shown in FIG. 4, the semiconductor substrate 31, the overflow drain layer 32 provided on the semiconductor substrate 31, and the semiconductor provided on the overflow drain layer 32. And an epitaxial layer 33 which is a layer.

  The semiconductor substrate 31 is, for example, a silicon substrate. The overflow drain layer 32 is a layer in which a P-type impurity such as boron is doped at the bottom of the epitaxial layer 33 provided on the semiconductor substrate 31. The epitaxial layer 33 is a layer in which silicon is epitaxially grown on the semiconductor substrate 31 and, for example, an N-type impurity such as phosphorus is contained at a relatively low concentration.

  Each pixel is provided directly on the semiconductor region 51 of the first conductivity type described above provided in the epitaxial layer 33, the high concentration region 53, and the semiconductor region 51 of the first conductivity type in the surface layer of the epitaxial layer 33. And a semiconductor region 52 of the second conductivity type.

  As described above, the semiconductor region 51 and the high concentration region 53 of the first conductivity type are N-type regions in which the N-type impurity such as phosphorus is doped in the epitaxial layer 33, for example. On the other hand, the semiconductor region 52 of the second conductivity type is a P-type region doped with a P-type impurity such as boron immediately above the semiconductor region 51 of the first conductivity type and the high concentration region 53 in the epitaxial layer 33. It is.

  Each pixel is separated from an adjacent pixel by a pixel separation region 40 penetrating the front and back of the epitaxial layer 33. The pixel separation region 40 is a deep layer pixel separation diffusion extending from the lower surface of the surface pixel separation diffusion region 42 to the upper surface of the overflow drain layer 32 and the insulating member 43 provided in the surface layer pixel separation diffusion region 42 and the surface layer pixel separation diffusion region 42 described above. And a region 41.

  The deep pixel separation diffusion region 41 is a P-type region in which the epitaxial layer 33 is doped with a P-type impurity such as boron, for example. Furthermore, each pixel includes an antireflective film 34, a color filter CF, and a microlens ML on the light receiving surface side.

  Each pixel photoelectrically converts light incident through the microlens ML, the color filter CF, and the anti-reflection film 34 into a signal charge, and accumulates the light in the semiconductor region 51 of the first conductivity type and the high concentration region 53.

  Then, each pixel transfers data from the semiconductor region 51 and the high concentration region 53 of the first conductivity type to the floating diffusion FD by applying a predetermined transfer voltage to the transfer gate TRG shown in FIG. Thereafter, each pixel amplifies a voltage corresponding to the signal charge transferred to the floating diffusion FD and outputs the amplified voltage to the CDS 26 (see FIG. 2).

  Such a pixel is, as described above, a high concentration region having a higher N-type impurity concentration than the first conductivity type semiconductor region 51 between the first conductivity type semiconductor region 51 and the surface layer pixel isolation diffusion region 42. Since 53 are provided, the number of saturated electrons that can be stored can be increased.

  Specifically, in a general pixel not provided with the high concentration region 53, as shown by a dotted line in FIG. 5, the potential potential of the peripheral portion in the charge storage region is the potential potential of the central portion in the charge storage region (FIG. Lower than the dashed line).

  This indicates that the depth of the quantum well for storing the signal charge is shallower in the peripheral portion than in the central portion of the charge storage region. That is, it means that the number of saturated electrons in the peripheral portion of the charge storage region is smaller than the number of saturated electrons in the central portion.

  The occurrence of this phenomenon is caused by the electrical conductivity of the N-type impurity contained in the peripheral portion of the charge storage region due to the P-type impurity contained in the surface layer pixel separation diffusion region 42 close to the peripheral portion of the charge storage region. It is because it is neutralized.

  Therefore, the pixels in the pixel array 23 have a high concentration of N-type impurity concentration higher than the first conductivity type semiconductor region 51 between the first conductivity type semiconductor region 51 and the surface layer pixel isolation diffusion region 42. An area 53 is provided. Thus, even if the high concentration region 53 is somewhat electrically neutralized by the P type impurity in the surface layer pixel isolation diffusion region 42 where the internal N type impurity is adjacent, the potential potential is shown by the solid line in FIG. Thus, it is higher than when the high concentration region 53 is not present.

  Therefore, each pixel in the pixel array 23 has a deeper quantum well at the peripheral portion in the charge storage region compared to a pixel without the high concentration region 53, so the number of saturated electrons of signal charge that can be stored is increased. And the dynamic range of photoelectric conversion can be expanded.

  In the high concentration region 53, if the N-type impurity concentration is higher than that of the semiconductor region 51 of the first conductivity type, the number of saturated electrons that can be accumulated can be increased compared to the pixel without the high concentration region 53. However, in the high concentration region 53, when the potential potential is made equal to the potential potential of the semiconductor region 51 of the first conductivity type, the N-type impurity concentration is 1 of the N-type impurity concentration in the semiconductor region 51 of the first conductivity type. It is preferable that the concentration be twice or more.

  In addition, as shown in FIG. 3, the high concentration region 53 surrounds the side surface of the semiconductor region 51 of the first conductivity type except the side surface facing the transfer gate TRG, and between the pixel isolation region 40 and the side surface. Provided in That is, the high concentration region 53 is not provided on the side of the semiconductor region 51 of the first conductivity type facing the transfer gate TRG.

  As a result, in the pixels in the pixel array 23, unnecessarily deep quantum wells are not formed at the edge on the transfer gate TRG side in the semiconductor region 51 of the first conductivity type. Therefore, when each pixel transfers the signal charge from the semiconductor region 51 and the high concentration region 53 of the first conductivity type to the floating diffusion FD, the signal charge remains in the charge storage region and an afterimage is generated in the captured image. It can be prevented.

  Next, a method of manufacturing the solid-state imaging device 14 according to the embodiment will be described with reference to FIGS. 6-8 is explanatory drawing by the cross sectional view which shows the manufacturing process of the solid-state imaging device 14 which concerns on embodiment.

  The manufacturing process of the solid-state imaging device 14 according to the embodiment is the same as the manufacturing process of a general solid-state imaging device except the manufacturing process of the pixel array 23. Therefore, here, the manufacturing process of the pixel array 23 will be described, and the description of the other processes will be omitted. In the following description, the same components as those shown in FIG. 3 and FIG. 4 will be assigned the same reference numerals as those shown in FIG. 2 and FIG.

  In the case of manufacturing the pixel array 23, first, as shown in FIG. 6A, for example, while doping a P-type impurity such as phosphorus on a semiconductor substrate 31 such as a silicon substrate, an epitaxial of silicon is epitaxially grown. The layer 33 is formed. Thereafter, a P-type impurity such as boron is ion-implanted into the bottom of the epitaxial layer 33, and an annealing process is performed to form the overflow drain layer 32.

  Subsequently, as shown in FIG. 6B, a resist 61 is applied on the surface of the epitaxial layer 33, and the resist 61 is patterned by photolithography to select the resist 61 on the formation region of the deep pixel separation diffusion region 41. Remove it.

  Then, using the patterned resist 61 as a mask, P-type impurities such as boron are ion-implanted into the epitaxial layer 33, for example. Here, P-type impurities are ion-implanted into the region from the position deeper than the surface layer portion of the epitaxial layer 33 to the upper surface of the overflow drain layer 32 a plurality of times. Thereafter, annealing is performed to form the deep pixel separation diffusion region 41, and the resist 61 is peeled off.

  Subsequently, as shown in FIG. 6C, a resist 62 is applied to the surface of the epitaxial layer 33, the resist 62 is patterned by photolithography, and the resist 62 on the formation region of the surface layer pixel isolation diffusion region 42 is selected. Remove it.

  Then, using the patterned resist 62 as a mask, P-type impurities such as boron are ion-implanted into the epitaxial layer 33, for example. Here, P-type impurities are ion-implanted into the surface layer portion of the epitaxial layer 33. Thereafter, by performing an annealing process, the surface layer pixel isolation diffusion region 42 is formed, and the resist 62 is peeled off.

  Subsequently, a resist 63 is applied on the epitaxial layer 33 and the surface layer pixel isolation diffusion region 42, and the resist 63 is patterned by photolithography as shown in FIG. 7A to form the surface pixel isolation diffusion region 42. The resist 63 on the center is selectively removed.

  Then, using the patterned resist 63 as a mask, the central portion of the surface layer pixel isolation diffusion region 42 is etched to form a trench in the form of a lattice in the surface layer pixel isolation diffusion region 42. Thereafter, the resist 63 is peeled off, and as shown in FIG. 7B, an insulating member 43 such as silicon oxide is laminated on the surface layer pixel isolation diffusion region 42 in which the trench is formed and on the epitaxial layer 33. Do.

  Subsequently, as shown by (c) in FIG. 7, the upper surface of the insulating member 43 and the upper surface of the epitaxial layer 33 are formed by grinding and polishing the surface of the insulating member 43 by CMP (Chemical Mechanical Polishing), for example. Make it flush. Thus, a pixel separation region 40 in the form of a lattice in plan view, which partitions the epitaxial layer 33, is formed.

  Subsequently, a resist 64 is applied on the epitaxial layer 33 and the pixel isolation region 40, and the resist 64 is patterned by photolithography as shown in (a) of FIG. Resist 64 is selectively removed.

  Then, using the patterned resist 64 as a mask, N-type impurities such as phosphorus are ion implanted into the epitaxial layer 33, for example. Here, N-type impurities are ion-implanted in a region deeper than the surface layer of the epitaxial layer 33. Thereafter, annealing is performed to form the semiconductor region 51 of the first conductivity type, and the resist 64 is peeled off.

  A resist 65 is applied on the epitaxial layer 33 and the pixel isolation region 40, and the resist 65 is patterned by photolithography as shown in FIG. 8B, and the periphery of the semiconductor region 51 of the first conductivity type is formed. Selectively remove the resist 65.

  Here, among the resists 65 on the four peripheral edges of the semiconductor region 51 of the first conductivity type, the resist 65 on the peripheral edge facing the transfer gate TRG shown in FIG. 3 is left without being removed. Keep it.

  Then, using the patterned resist 65 as a mask, an annealing treatment is performed by implanting ions of an N-type impurity such as phosphorus into the epitaxial layer 33, for example. Here, for example, assuming that the dose amount of the N-type impurity ion-implanted in the step of forming the semiconductor region 51 of the first conductivity type is 100, the ion implantation is performed such that the dose amount of the N-type impurity is 20 or more. I do.

  Note that this dose amount is an example, and if an additional N-type impurity is ion implanted into the peripheral portion of the first conductivity type semiconductor region 51, the dose amount of the N-type impurity here is the first ion. It is not limited to 20% at the time of injection.

  Thus, in the peripheral portion of the semiconductor region 51 of the first conductivity type, the peripheral portion excluding the peripheral portion facing the transfer gate TRG (see FIG. 3) is N-type more than the semiconductor region 51 of the first conductivity type. The high concentration region 53 having a high impurity concentration is formed.

  Thereafter, as shown in FIG. 8C, the resist 65 is peeled off, and a P-type impurity such as boron is ion-implanted into the surface layer of the epitaxial layer 33, for example, to perform an annealing process. The semiconductor region 52 of the second conductivity type is formed in the surface layer 33.

  Thereafter, the antireflective film 34, the color filter CF, and the microlens ML (see FIG. 4) are sequentially stacked on the structure shown in FIG. 8C, thereby completing the pixel array 23 shown in FIG. .

  In the above, the case where one floating diffusion FD is provided for one pixel has been described as an example, but in the pixel array according to the present embodiment, one floating diffusion is provided for a plurality of pixels. May be provided.

  Here, with reference to FIG. 9, a pixel array according to a modification in which one floating diffusion is provided for a plurality of pixels will be described. FIG. 9 is a schematic plan view showing a part of the surface on the light receiving surface side of the pixel array 23A according to the modification of the embodiment.

  In FIG. 9, in order to facilitate understanding of the configuration of the charge storage region in the pixel, the semiconductor region 52 of the second conductivity type provided on the charge storage region, the antireflective film 34, the color filter CF, and the microlens The pixel array 23A in the state where ML is removed is shown.

  As shown in FIG. 9, the pixel array 23A has a so-called two-pixel one-cell structure in which one floating diffusion FDA is provided for two pixels. As shown in the figure, the pixel array 23A includes two first conductivity type semiconductor regions 51a and 51b having a substantially rectangular shape in plan view in a region surrounded by the surface layer pixel isolation diffusion region 42A and the insulating member 43A. Prepare.

  In addition, the pixel array 23A includes transfer gates TRGa and TRGb on the nearest corners of the semiconductor regions 51a and 51b of the first conductivity type, respectively, and one shared between the transfer gates TRGa and TRGb. With one floating diffusion FDA.

  In the case of the pixel array 23A of such a two-pixel one-cell structure, among the peripheral portions of the semiconductor regions 51a and 51b of the first conductivity type, the high concentration is respectively provided Regions 53a and 53b are provided. The high concentration regions 53a and 53b are regions in which the impurity concentration of the first conductivity type (here, N type) is higher than that of the first conductivity type semiconductor regions 51a and 51b, similarly to the high concentration region 53 shown in FIG. is there.

  Thus, the pixel array 23A is more N-type than the first conductivity type semiconductor regions 51a and 51b between the first conductivity type semiconductor regions 51a and 51b and the N type surface layer pixel isolation diffusion region 42A. The high concentration regions 53a and 53b have high impurity concentrations. Therefore, even when the pixel array 23A has a two-pixel one-cell structure, the number of saturated electrons in each pixel can be increased.

  As described above, in the solid-state imaging device according to the embodiment, among the peripheral portions of the charge storage region in each pixel, in the peripheral portion excluding the peripheral portion facing the transfer gate, the conductivity type of the impurity included in the charge storage region A high concentration region including impurities of the same conductivity type at a higher concentration than the central portion of the charge storage region is provided.

  Thus, in the solid-state imaging device, the periphery of the charge storage region is obtained even if the first conductivity type impurity in the charge storage region is somewhat electrically neutralized by the second conductivity type impurity in the adjacent pixel separation region. It is possible to suppress a drop in the potential potential of the part. Therefore, the solid-state imaging device can increase the number of saturated electrons that can be stored in each pixel.

  While certain embodiments of the present invention have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and the gist of the invention, and are included in the invention described in the claims and the equivalent scope thereof.

  Reference Signs List 1 digital camera 11 camera module 12 post-processing unit 13 imaging optical system 14 solid-state imaging device 15 ISP 16 storage unit 17 display unit 20 image sensor 21 signal processing circuit 22 peripheral circuit 23, 23A Pixel array, 24 vertical shift register, 25 timing control unit, 26 CDS, 27 ADC, 28 line memory, 31 semiconductor substrate, 32 overflow drain layer, 33 epitaxial layer, 34 antireflective film, 40 pixel separation area, 41 deep pixel separation Diffusion region, 42, 42A surface layer pixel separation diffusion region, 43, 43A insulation member, 51, 51a, 51b semiconductor region of first conductivity type, 52 semiconductor region of second conductivity type, 53, 53a, 53b high concentration region, 61 ~ 65 re Strike, CF color filter, FD, FDA floating diffusion, ML microlenses, TRG, TRGa, TRGb transfer gate.

According to one embodiment, a solid state imaging device is provided. And a pixel having a charge storage region in the semiconductor layer, and a transfer gate, Ru and a pixel isolation region separating said pixels and other pixels. The pixel separation region is provided on the surface layer of the semiconductor layer, and a surface layer pixel separation region formed of an impurity region of a conductivity type different from the impurity contained in the charge storage region and an insulating member, and a lower surface of the surface layer pixel separation region. And a deep pixel separation region formed of an impurity region of the same conductivity type as the impurity of the surface layer pixel separation region. The surface layer of the semiconductor layer separated by the surface layer pixel separation region is provided on the periphery of the charge storage region except for the periphery facing the transfer gate, and the impurities included in the charge storage region A high concentration region including impurities of the same conductivity type as the conductivity type at a higher concentration than the central portion of the charge storage region is provided.

Claims (5)

A pixel having a charge storage region in a semiconductor layer, a transfer gate, and a pixel separation region;
The peripheral portion of the charge storage region is provided at the peripheral portion excluding the peripheral portion facing the transfer gate, and the central portion of the charge storage region is an impurity of the same conductivity type as the conductivity type of the impurity contained in the charge storage region. What is claimed is: 1. A solid-state imaging device comprising: a high concentration area including a higher concentration than the high concentration area. The transfer gate is
Provided on a region adjacent to the charge storage region in the semiconductor layer,
The charge storage region is
A semiconductor region of a first conductivity type provided in the semiconductor layer;
And a high concentration region provided between the pixel isolation region and a side surface excluding the side surface facing the transfer gate among the side surfaces of the semiconductor region of the first conductivity type. The solid-state imaging device according to claim 1. The pixel separation area is
The solid-state imaging device according to claim 2, wherein the region in contact with the high concentration region contains an impurity of a second conductivity type. The high concentration region is
The solid-state imaging device according to any one of claims 1 to 3, wherein the impurity concentration is at least 1.2 times the impurity concentration in the central portion of the charge storage region. Doping the semiconductor layer with an impurity of the first conductivity type to form a semiconductor region of the first conductivity type;
Among the peripheral portions of the semiconductor region of the first conductivity type, the peripheral region excluding the peripheral portion on the side where the transfer gate is formed is further doped with an impurity of the first conductivity type to form the semiconductor region of the first conductivity type Forming a high concentration region in which the impurity concentration of the first conductivity type is higher than that of the first conductivity type;
Forming a second conductivity type semiconductor region by doping an impurity of a second conductivity type directly on the semiconductor region of the first conductivity type and the high concentration region in the surface layer of the semiconductor layer;
Forming a transfer gate on a region adjacent to the semiconductor region of the second conductivity type in the semiconductor layer.

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