JP2019113786A - Display and method for manufacturing display - Google Patents

Abstract

A compact display device is realized. A display device includes an IC chip having terminals on a first surface, a second surface opposite to the first surface of the IC chip, and a side surface between the first surface and the second surface. a covering resin layer; a wiring layer provided on the IC chip and the resin layer and including wiring connected to the terminals; and a transistor provided on the wiring layer and including a transistor connected to the wiring. and an electro-optic layer overlying the transistor layer and including pixel electrodes connected to the transistors. [Selection drawing] Fig. 2

Description

  One of the embodiments of the present invention relates to a display device and a method of manufacturing the display device. In particular, the present invention relates to a display device in which an IC chip is provided on the back surface side of the array substrate, and a method of manufacturing the display device in which the IC chip is provided on the back surface side of the array substrate.

  In a display device with a touch sensor, a transistor layer forming a pixel circuit and a drive circuit is formed on a substrate, an electro-optical layer is formed on the pixel circuit, and a touch sensor is formed on the electro-optical layer. A driver IC chip for driving a pixel circuit and a driving circuit and a touch sensor IC chip for driving a touch sensor are mounted. The mounting of these IC chips is usually performed via a flexible printed circuit board (FPC) or in a COG (Chip On Glass) method (for example, Patent Document 1).

  As the above IC chip, for example, a GPU (Graphics Processing Unit), a memory, a power supply, and passive components such as a resistance element and a capacitance element are provided. These parts are protected by, for example, hermetic sealing. ing.

Unexamined-Japanese-Patent No. 2017-010066

  In a display device such as a smart phone which is required to be compact, there is a problem that when the parts such as the IC chip are hermetically sealed as described above, the degree of freedom in design of the display device is limited. And there existed a problem to which the manufacturing cost of a display apparatus will increase in connection with it.

  One of the embodiments of the present invention is to realize a compact display device. Alternatively, one of the problems is to reduce the manufacturing cost of the display device.

  In a display device according to an embodiment of the present invention, an IC chip having a terminal on a first surface, a second surface on the opposite side to the first surface of the IC chip, and the first surface and the second surface A resin layer covering a side surface between the wiring layer, a wiring layer provided on the IC chip and the resin layer and including a wiring connected to the terminal, and a wiring layer provided on the wiring layer and connected to the wiring A transistor layer including a transistor, and an electro-optical layer provided on the transistor layer and including a pixel electrode connected to the transistor.

  In a method of manufacturing a display device according to an embodiment of the present invention, an IC chip having a terminal on a first surface is disposed such that the terminal faces the support substrate side, and the IC chip is formed on the support substrate. Forming a resin layer covering a second surface opposite to the first surface and a side surface between the first surface and the second surface, peeling off the IC chip and the resin layer from the support substrate; A wiring layer including a wiring connected to a terminal is formed, a transistor layer including a transistor connected to the wiring is formed, and an electro-optical layer including a pixel electrode connected to the transistor is formed.

It is a top view which shows the outline | summary of the display apparatus which concerns on one Embodiment of this invention. BRIEF DESCRIPTION OF THE DRAWINGS It is sectional drawing which shows the outline | summary of the display apparatus which concerns on one Embodiment of this invention. FIG. 2 is a cross-sectional view showing a detailed structure of a transistor layer and an electro-optical layer of a display device according to an embodiment of the present invention. FIG. 7 is a cross-sectional view showing a method of manufacturing a display device according to an embodiment of the present invention. FIG. 7 is a cross-sectional view showing a method of manufacturing a display device according to an embodiment of the present invention. FIG. 7 is a cross-sectional view showing a method of manufacturing a display device according to an embodiment of the present invention. FIG. 7 is a cross-sectional view showing a method of manufacturing a display device according to an embodiment of the present invention. FIG. 7 is a cross-sectional view showing a method of manufacturing a display device according to an embodiment of the present invention. FIG. 7 is a cross-sectional view showing a method of manufacturing a display device according to an embodiment of the present invention. FIG. 7 is a cross-sectional view showing a method of manufacturing a display device according to an embodiment of the present invention. It is a top view which shows the outline | summary of the display apparatus which concerns on one Embodiment of this invention. It is a top view which shows the outline | summary of the display apparatus which concerns on one Embodiment of this invention. It is a top view which shows the outline | summary of the display apparatus which concerns on one Embodiment of this invention. BRIEF DESCRIPTION OF THE DRAWINGS It is sectional drawing which shows the outline | summary of the display apparatus which concerns on one Embodiment of this invention. FIG. 7 is a cross-sectional view showing a method of manufacturing a display device according to an embodiment of the present invention. FIG. 7 is a cross-sectional view showing a method of manufacturing a display device according to an embodiment of the present invention.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. The disclosure is merely an example, and those which can be easily conceived of by those skilled in the art by appropriately changing the nature of the invention are naturally included in the scope of the invention. Further, in order to make the description clearer, the width, thickness, shape, etc. of each part may be schematically represented as compared with the actual aspect. However, the illustrated shapes are merely examples and do not limit the interpretation of the present invention. Further, in the present specification and the drawings, elements similar to those described above with reference to the existing drawings may be given alphabets after the same reference numerals, and detailed description may be omitted as appropriate.

  In each embodiment of the present invention, the direction from the IC chip to the transistor layer is referred to as upward or upward. Conversely, the direction from the transistor layer to the IC chip is referred to as downward or downward. As described above, for convenience of explanation, although the term "upper" or "lower" is used for description, for example, the vertical relation between the IC chip and the transistor layer may be arranged to be opposite to that shown in the drawing. Further, in the following description, for example, the expression “transistor layer on the IC chip” only explains the vertical relation between the IC chip and the transistor layer as described above, and the other relation between the IC chip and the transistor layer A member may be arranged.

  "Display" refers to a structure that displays an image using an electro-optic layer. For example, the term display may refer to a display panel that includes an electro-optic layer, or refers to a structure in which other optical members (eg, polarizing members, backlights, touch panels, etc.) are attached to a display cell. In some cases. Here, the “electro-optical layer” may include a liquid crystal layer, an electroluminescent (EL) layer, an electrochromic (EC) layer, and an electrophoretic layer unless technical contradiction arises. Therefore, although an organic EL display device including an organic EL layer is illustrated as a display device in the embodiment described later, the application to a display device including the above-described other electro-optical layers is not excluded.

  As used herein, “α includes A, B or C”, “α includes any of A, B and C”, and “α includes one selected from the group consisting of A, B and C. The expression “” does not exclude the case where α includes a plurality of combinations of A to C unless otherwise specified. Furthermore, these expressions do not exclude the case where α contains other elements.

  The following embodiments can be combined with each other as long as no technical contradiction arises.

First Embodiment
A display device according to an embodiment of the present invention and a method of manufacturing the display device will be described with reference to FIGS. In addition, the display apparatus of embodiment shown below has flexibility.

[Configuration of Display Device 10]
The structure of the display apparatus 10 which concerns on one Embodiment of this invention is demonstrated using FIGS. 1-3. In the present embodiment, the display device 10 will be described using a top emission type organic EL display device that emits light upward. However, the display device 10 is not limited to the top emission type organic EL display device as described above. For example, as the display device 10, a reflective liquid crystal display device or an LED display can be used. Alternatively, if the IC chip is disposed so that the light emitted from the electro-optical layer is not blocked by the IC chip, a bottom emission organic EL display device or a transmissive liquid crystal display device may be used as the display device 10. it can.

  FIG. 1 is a top view showing an outline of a display device according to an embodiment of the present invention. As shown in FIG. 1, the display device 10 is divided into a display area 20 and a peripheral area 30. The display area 20 is an area for displaying an image. The peripheral area 30 is an area located around the display area 20. In the display area 20, the pixels 21 are arranged in a matrix. Although details will be described later, each pixel 21 is provided with a pixel electrode 23. Note that, as shown in FIG. 1, each pixel 21 is expressed as pixels 21 R, 21 G, and 21 B according to a display color, but when these are not particularly distinguished, they are simply referred to as a pixel 21. Similarly, the pixel electrode 23 may be expressed as the pixel electrodes 23R, 23G, and 23B depending on the display color, but when these are not particularly distinguished, they are simply referred to as the pixel electrode 23. In the peripheral area 30, a gate driver 31 and a source driver 33 are provided.

  In the display area 20, an IC chip 110 is provided. Although details will be described later, the pixel electrode 23 is provided above the transistor layer provided with the transistor, and the IC chip 110 is provided below the transistor layer. That is, in plan view, the IC chip 110 overlaps with the transistor provided in the transistor layer. Similarly, in plan view, the IC chip 110 overlaps the pixel electrode 23. Although FIG. 1 illustrates the configuration in which the IC chip 110 is provided in the display area 20, the IC chip 110 may be provided in the peripheral area 30.

  Each pixel 21 displays a single color, and includes, for example, a pixel 21R displaying red, a pixel 21G displaying green, and a pixel 21B displaying blue. These pixels 21R, 21G, and 21B are referred to as sub-pixels. These sub-pixels constitute a main pixel for displaying full color. In the following embodiments, the pixel 21 indicates a sub-pixel unless otherwise noted.

  Although the configuration in which the pixels 21 are arranged in a matrix is illustrated in the present embodiment, the present invention is not limited to this configuration. The pixels 21 are not limited to the matrix-like arrangement in the rectangular display area 20 as shown in FIG. 1, and can be arranged in accordance with the shape of an arbitrary display area.

  The gate driver 31 is provided at a position adjacent to the display area 20 in the lateral direction (position adjacent to the row direction). The gate drivers 31 are provided on both sides of the display area 20. Although not shown, in FIG. 1, gate lines extend in the row direction from the gate drivers 31 provided on both sides of the display area 20 toward the display area 20. The source driver 33 is provided at a position adjacent to the display area 20 in the vertical direction (position adjacent to the column direction). However, the gate driver 31 may be provided only on one side of the display area 20.

  The source driver 33 is provided on one side of the display area 20. Although not shown, in FIG. 1, source lines extend from the source driver 33 provided on one side of the display area 20 toward the display area 20 in the column direction. However, the source drivers 33 may be provided on both sides of the display area 20 in the column direction. When the gate driver 31 is provided above and below the display area 20, the source driver 33 is provided at one or both of the left and right of the display area 20.

  FIG. 2 is a cross-sectional view showing an outline of a display device according to an embodiment of the present invention. As shown in FIG. 2, the display device 10 has an IC chip circuit 100 and a display panel circuit 300. The display panel circuit 300 is provided on the IC chip circuit 100. The display panel circuit 300 and the IC chip circuit 100 are electrically connected to each other by the through electrode 319 penetrating the insulating layer included in the both. For example, the transistors constituting the gate driver 31 and the source driver 33 are controlled by the IC chip 110 included in the IC chip circuit 100.

  The IC chip circuit 100 includes an IC chip 110, a resin layer 120, and a wiring layer 130. The IC chip 110 has a chip first surface 115, a chip second surface 111 opposite to the chip first surface 115, and a chip side surface 113 between the chip first surface 115 and the chip second surface 111. The resin layer 120 covers the chip second surface 111 and the chip side surface 113. In FIG. 2, the chip second surface 111 and the chip side surface 113 are covered by the resin layer 120 without a gap. In other words, the entire surface of the second chip surface 111 is covered by the resin layer 120. Further, the entire surface of the chip side surface 113 is covered by the resin layer 120. However, a gap may be formed between the chip second surface 111 and the chip side surface 113 and the resin layer 120.

  The chip first surface 115 of the IC chip 110 is exposed from the resin layer 120. The resin first surface 121 of the resin layer 120 and the chip first surface 115 are aligned. In other words. The chip first surface 115 and the resin first surface 121 are on the same plane. However, the chip first surface 115 and the resin first surface 121 do not have to be completely on the same plane, and both may be approximately on the same plane. The IC chip 110 has a chip terminal 117 on the chip first surface 115.

  The wiring layer 130 is provided on the IC chip 110 and the resin layer 120. A plurality of wiring layers are stacked in the wiring layer 130 shown in FIG. The wiring layer 130 includes a first interlayer insulating layer 131, a first wiring layer 133, a second interlayer insulating layer 135, a second wiring layer 137, and a third interlayer insulating layer 139. The first interlayer insulating layer 131 is provided on the IC chip 110 and the resin layer 120. The first interlayer insulating layer 131 is provided with an opening reaching the chip terminal 117. The first wiring layer 133 is provided on the opening and the upper surface of the first interlayer insulating layer 131. The second interlayer insulating layer 135 is provided on the first interlayer insulating layer 131 and the first wiring layer 133. The second interlayer insulating layer 135 is provided with an opening that reaches the first wiring layer 133. The second wiring layer 137 is provided at the opening and the upper surface of the second interlayer insulating layer 135. The third interlayer insulating layer 139 is provided on the second interlayer insulating layer 135 and the second wiring layer 137. The first interlayer insulating layer 131, the second interlayer insulating layer 135, and the third interlayer insulating layer 139 may be an organic insulating layer or an inorganic insulating layer, and may be a stack of an organic insulating layer and an inorganic insulating layer. It may be A general conductive layer can be used as the first wiring layer 133 and the second wiring layer 137.

  As described above, the wiring formed by the first wiring layer 133 and the second wiring layer 137 is connected to the chip terminal 117. Then, as described later, the wiring is connected to a transistor included in the transistor layer 310. That is, the IC chip 110 is connected to the transistor layer 310 via the wiring layer 130.

  Although FIG. 2 exemplifies the configuration in which the wiring layer 130 is a multilayer wiring structure including two wiring layers, the present invention is not limited to this configuration. The wiring layer 130 may be a single layer or may have a multilayer wiring structure of three or more layers.

  The display panel circuit 300 includes a transistor layer 310 and an electro-optical layer 330. The transistor layer 310 is provided on the wiring layer 130. As described later, the transistors included in the transistor layer 310 are electrically connected to the wiring layer 130. The electro-optical layer 330 is provided on the transistor layer 310 and is electrically connected to the transistor layer 310. The electro-optical layer 330 has a display element that displays different colors according to each pixel 21. In the present embodiment, since the display device 10 is an organic EL display device, an organic EL layer is provided as a display element included in the electro-optical layer 330. The organic EL layer varies in display color depending on its material and structure.

  The transistor layer 310 includes a pixel circuit transistor 301 and a peripheral circuit transistor 303. The pixel circuit transistor 301 is a transistor that is disposed in the display area 20 and controls the display of each pixel 21. The peripheral circuit transistor 303 is a transistor disposed in the peripheral region 30 and included in the gate driver 31 or the source driver 33. A variety of transistors can be used as the pixel circuit transistor 301 and the peripheral circuit transistor 303. As these transistors, for example, a top gate type transistor in which a gate electrode is provided on a semiconductor layer in which a channel is formed via a gate insulating layer, and a gate electrode is provided below a semiconductor layer via a gate insulating layer. A bottom gate transistor or a transistor in which a semiconductor layer, a gate insulating layer, and a gate electrode are provided on side walls of the insulating layer can be used.

  The transistor layer 310 includes a fourth interlayer insulating layer 311, a source wiring layer 313, a drain wiring layer 315, a third wiring layer 317, and a fifth interlayer insulating layer 321 in addition to the above-described transistors. The fourth interlayer insulating layer 311 is provided with an opening that reaches the source region and the drain region of each of the pixel circuit transistor 301 and the peripheral circuit transistor 303. The source wiring layer 313, the drain wiring layer 315, and the third wiring layer 317 are connected to the corresponding transistors through the openings provided in the fourth interlayer insulating layer 311.

  In the third interlayer insulating layer 139 and the fourth interlayer insulating layer 311, an opening reaching a part of the second wiring layer 137 is provided. A through electrode 319 penetrating the third interlayer insulating layer 139 and the fourth interlayer insulating layer 311 is provided in this opening. The through electrode 319 is formed of a conductive layer provided in the same layer as the third wiring layer 317 described above. The through electrode 319 connects the second wiring layer 137 and the third wiring layer 317. That is, the peripheral circuit transistor 303 is connected to the wiring layer 130 via the through electrode 319. In the case where the above transistor is a bottom gate transistor, the fourth interlayer insulating layer 311 may be omitted. The fifth interlayer insulating layer 321 is provided with an opening that reaches a part of the drain wiring layer 315. The fourth interlayer insulating layer 311 and the fifth interlayer insulating layer 321 may be organic insulating layers, may be inorganic insulating layers, or may be stacked layers of organic insulating layers and inorganic insulating layers. A general conductive layer can be used as the source wiring layer 313, the drain wiring layer 315, the third wiring layer 317, and the through electrode 319.

  The electro-optical layer 330 includes the pixel electrode 23, the partition wall 331, the organic EL layer 333, and the common electrode 335. The pixel electrode 23 is connected to the drain wiring layer 315 through an opening provided in the fifth interlayer insulating layer 321. The partition wall 331 is provided on the fifth interlayer insulating layer 321 and the pixel electrode 23. The partition 331 is provided with an opening for exposing a part of the pixel electrode 23. The opening provided in the partition wall 331 exposes the region inside the pixel electrode 23 in plan view. In other words, the barrier rib 331 covers the pattern end of the pixel electrode 23. The partition 331 may be an organic insulating layer, an inorganic insulating layer, or a stack of an organic insulating layer and an inorganic insulating layer.

  The organic EL layer 333 is provided on each pixel electrode 23. The material and structure of the organic EL layer 333 differ depending on the display color of each pixel 21. The organic EL layer 333R emits red light by energizing the organic EL layer 333R. The organic EL layer 333G emits green light by energizing the organic EL layer 333G. The organic EL layer 333B emits blue light by energizing the organic EL layer 333B. Note that when these organic EL layers are not particularly distinguished, they are simply referred to as the organic EL layer 333. The common electrode 335 is provided on the organic EL layer 333 and the partition wall 331. The common electrode 335 is commonly provided to the plurality of organic EL layers 333. In other words, the common electrode 335 continuously covers the organic EL layers 333R, 333G, and 333B. When the display device 10 is a top emission type organic EL display device, a reflective metal can be used as the pixel electrode 23, and a translucent metal can be used as the common electrode 335.

  As described above, in the display device 10 according to the present embodiment, the through electrode 319 penetrating the third interlayer insulating layer 139 and the fourth interlayer insulating layer 311 and the wiring layer 130 provided under the transistor layer 310 are used. Since the transistor layer 310 and the IC chip 110 are connected, there is no need to separately provide the IC chip 110 and a wiring for connecting the IC chip 110 and the transistor layer 310 on the substrate. As a result, a display device that is more compact than in the past can be realized.

  In addition, the IC chip 110 has a structure in which the chip side surface 113 and the chip second surface 111 are covered by the resin layer 120. That is, the IC chip 110 is mechanically protected against external force. Therefore, the display device 10 with the IC chip 110 with high reliability can be realized.

[Configuration of Display Panel Circuit 300]
The configuration of the display panel circuit 300 will be described in detail with reference to FIG. The configuration of the display panel circuit 300 shown in FIG. 3 is merely an example, and the display panel circuit 300 is not limited to the configuration shown in FIG.

  FIG. 3 is a cross-sectional view showing the detailed structure of the transistor layer and the electro-optical layer of the display device according to the embodiment of the present invention. FIG. 3 is a schematic cross-sectional view across two adjacent pixels 21 (21R and 21G). A pixel circuit is formed in each pixel 21. The pixel circuit illustrated in FIG. 3 includes a drive transistor 210, a storage capacitor 230, an additional capacitor 250, and a light emitting element 260. The light emitting element 260 includes the pixel electrode 23, the organic EL layer 333, and the common electrode 335 in FIG. 2.

  Each element included in the pixel circuit is provided on the IC chip circuit 100 via the undercoat 208. The driving transistor 210 includes a semiconductor film 212, a gate insulating film 214, a gate electrode 216, a source electrode 220, and a drain electrode 222. The gate electrode 216 is arranged to intersect at least a part of the semiconductor film 212 with the gate insulating film 214 interposed therebetween. The semiconductor film 212 includes a source region 212a, a drain region 212b, and a channel 212c. The channel 212 c is a region where the semiconductor film 212 and the gate electrode 216 overlap. The channel 212c is provided between the source region 212a and the drain region 212b.

  The capacitor electrode 232 exists in the same layer as the gate electrode 216 and overlaps with the drain region 212 b through the gate insulating film 214. An interlayer insulating film 218 is provided over the gate electrode 216 and the capacitor electrode 232. Openings reaching the source region 212a and the drain region 212b are formed in the interlayer insulating film 218 and the gate insulating film 214, respectively, and the source electrode 220 and the drain electrode 222 are disposed inside these openings. The drain electrode 222 overlaps with the capacitor electrode 232 via the interlayer insulating film 218. A storage capacitor 230 is formed of the drain region 212 b, the capacitor electrode 232, the gate insulating film 214 therebetween, the capacitor electrode 232, the drain electrode 222, and the interlayer insulating film 218 therebetween. The drive transistor 210 and the storage capacitor 230 correspond to the transistor layer 310 in FIG. The source electrode 220 and the drain electrode 222 correspond to the source wiring layer 313 and the drain wiring layer 315 in FIG.

  A planarization film 240 is provided on the driving transistor 210 and the storage capacitor 230. The planarization film 240 is provided with an opening that reaches the drain electrode 222. A connection electrode 242 covering the opening and a part of the upper surface of the planarization film 240 is provided in contact with the drain electrode 222. An additional capacitance electrode 252 is provided on the planarizing film 240, and a capacitive insulating film 254 is formed to cover the connection electrode 242 and the additional capacitance electrode 252. The capacitive insulating film 254 exposes part of the connection electrode 242 at the opening of the planarization film 240. Accordingly, the pixel electrode 262 and the drain electrode 222 of the light emitting element 260 are electrically connected to each other through the connection electrode 242. An opening 256 is provided in the capacitive insulating film 254. The partition wall 258 provided over the capacitive insulating film 254 is in contact with the planarization film 240 through the opening 256. With the openings 256, impurities in the planarization film 240 can be removed through the openings 256, whereby the reliability of the pixel circuit and the light emitting element 260 can be improved. Note that the formation of the connection electrode 242 and the opening 256 is optional. The pixel electrode 262 corresponds to the pixel electrode 23 in FIG.

  A pixel electrode 262 is provided on the capacitive insulating film 254 so as to cover the connection electrode 242 and the additional capacitance electrode 252. The capacitive insulating film 254 is disposed between the additional capacitance electrode 252 and the pixel electrode 262, and the additional capacitance 250 is formed by this structure. The pixel electrode 262 is shared by the additional capacitance 250 and the light emitting element 260. Over the pixel electrode 262, a partition wall 258 covering an end of the pixel electrode 262 is provided. The structure from the undercoat 208 to the partition walls 258 may be referred to as an array substrate. The array substrate can be manufactured by applying known materials and methods, and thus the description thereof is omitted. The partition wall 258 corresponds to the partition wall 331 of FIG.

[Configuration of Light Emitting Element 260]
As shown in FIG. 3, the light emitting element 260 includes a pixel electrode 262, an organic EL layer 264, and a common electrode 272. The organic EL layer 264 and the common electrode 272 are provided to cover the pixel electrode 262 and the partition wall 258. In the example shown in FIG. 3, the organic EL layer 264 includes a hole injection / transport layer 266, a light emitting layer 268 (light emitting layers 268a and 268b), and an electron injection / transport layer 270. The hole injection / transport layer 266 and the electron injection / transport layer 270 are provided commonly to all the pixels 21 and shared by all the pixels 21. Similarly, the common electrode 272 covers the plurality of pixels 21 and is shared by the plurality of pixels 21. On the other hand, the light emitting layer 268 is individually provided for each pixel 21. The organic EL layer 264 and the common electrode 272 correspond to the organic EL layer 333 and the common electrode 335 in FIG.

  The structures and materials of the pixel electrode 262, the common electrode 272, and the organic EL layer 264 may be known ones. For example, the organic EL layer 264 may have various functional layers such as a hole blocking layer, an electron blocking layer, and an exciton blocking layer, in addition to the above configuration.

  The structure of the organic EL layer 264 may be the same between all the pixels 21, and part of the structure may be different between the adjacent pixels 21. For example, the structure or material of the light emitting layer 268 may be different between the adjacent pixels 21, and the other layers may have the same structure.

[Method of Manufacturing Display Device 10]
The manufacturing method of the display apparatus 10 of this embodiment is demonstrated using FIGS. 4-10. 4 to 10 are cross-sectional views showing a method of manufacturing a display device according to an embodiment of the present invention. Note that the vertical direction of the IC chip 110 in FIGS. 4 to 6 is opposite to the vertical direction of the IC chip 110 in FIG. That is, the upper side in FIG. 2 is the lower side in FIGS.

  As shown in FIG. 4, the IC chip 110 is disposed on the support substrate 400 via the adhesive layer 410. The IC chip 110 is disposed such that the chip terminal 117 provided on the surface of the IC chip 110 is disposed on the adhesive layer 410 side. In other words, the IC chip 110 having the chip terminal 117 on the chip first surface 115 is disposed on the support substrate 400 such that the chip terminal 117 faces the support substrate 400 side. In a later step, the resin layer 120 is formed on the chip second surface 111 side, and the wiring layer 130 is formed on the chip first surface 115 side.

  Before placing the IC chip 110 on the support substrate 400, the alignment marker 401 is formed on the surface of the support substrate 400, and the placement position of the IC chip 110 is determined using the alignment marker 401 as a mark. However, the alignment marker 401 may be formed on the adhesive layer 410. Here, as the adhesive layer 410, a member in which adhesion (or adhesion) is reduced by supply of stimulation can be used. For example, as the adhesive layer 410, a member whose adhesion strength is reduced by heating can be used.

  After disposing the IC chip 110 on the adhesive layer 410, as shown in FIG. 5, the resin layer 120 covering the chip second surface 111 and the chip side surface 113 of the IC chip 110 is formed. The resin layer 120 is formed such that the first resin surface 121 faces the support substrate 400. The resin layer 120 is formed by applying a liquid resin material. As the resin layer 120, materials such as epoxy resin and acrylic resin can be used. Alternatively, a film-like resin can be used as the resin layer 120. The film-like resin is a film having a thickness of several tens of μm to several hundreds of μm, and is in the form of a film before being attached to the adhesive layer 410. Such a film-like resin is attached to the adhesive layer 410 and the IC chip 110, and pressure heat treatment is performed.

  In the state where the film-like resin is simply attached to the adhesive layer 410 and the IC chip 110, a gap may be formed in the step portion between the adhesive layer 410 and the IC chip 110. In particular, it is difficult to form the resin layer 120 on the chip side surface 113 of the IC chip 110. However, by applying pressure heat treatment after attaching the film-like resin, the film-like resin having fluidity by heat flows into the above-mentioned voids and fills the voids. Thus, the resin layer 120 can be formed on the chip side surface 113 as well. By the above-described steps, the IC chip 110 and the resin layer 120 are formed such that the chip first surface 115 and the resin first surface 121 are located on the same plane.

  In the above manufacturing method, the method of forming the resin layer 120 using a film-like resin has been described, but the present invention is not limited to this manufacturing method. For example, the resin layer 120 may be formed by forming a resin material on the adhesive layer 410 and the IC chip 110 using a printing method or a coating method.

  As shown in FIG. 6, the IC chip 110 and the resin layer 120 are peeled off from the adhesive layer 410 by performing heat treatment at a temperature at which the adhesive strength of the adhesive layer 410 decreases. By this peeling, the chip first surface 115 including the chip terminals 117 of the IC chip 110 and the resin first surface 121 are exposed to the surface. In the present embodiment, the manufacturing method for peeling the IC chip 110 and the resin layer 120 from the adhesive layer 410 by heat treatment has been described, but the present invention is not limited to this manufacturing method. For example, in the case where a member whose adhesive strength is reduced by ultraviolet irradiation is used as the adhesive layer 410, the above peeling may be performed by performing ultraviolet irradiation treatment instead of heat treatment. In this manner, the support substrate 400 is peeled off, and the wiring layer 130, the transistor layer 310, and the electro-optical layer 330 are formed on the resin layer 120 as a substrate as described below. Is flexible.

  As shown in FIG. 7, the IC chip 110 and the resin layer 120 shown in FIG. 6 are turned upside down to form the wiring layer 130 on the IC chip 110 and the resin layer 120. Specifically, the first interlayer insulating layer 131 is formed on the IC chip 110 and the resin layer 120, and an opening for exposing the chip terminal 117 is formed in the first interlayer insulating layer 131. A conductive layer is formed in the opening formed on the first interlayer insulating layer 131 and in the first interlayer insulating layer 131. Then, the first wiring layer 133 is formed by performing photolithography and etching on the conductive layer. The wiring layer 130 is formed by forming the second interlayer insulating layer 135, the second wiring layer 137, and the third interlayer insulating layer 139 in the same manner as described above. The first interlayer insulating layer 131, the second interlayer insulating layer 135, and the third interlayer insulating layer 139 may be inorganic insulating layers or organic insulating layers. In this manner, the wiring layer 130 having the wiring connected to the chip terminal 117 is formed.

  As shown in FIG. 8, a part of the transistor layer 310 is formed on the wiring layer 130. Specifically, the pixel circuit transistor 301 and the peripheral circuit transistor 303 are formed on the third interlayer insulating layer 139, and the fourth interlayer insulating layer 311 is formed on these transistors. Although the pixel circuit transistor 301 and the peripheral circuit transistor 303 are not connected to the wiring layer 130 at this stage, they are connected to the wiring layer 130 through the through electrode 319 in a later step.

  As shown in FIG. 9, an opening 305 is formed in the fourth interlayer insulating layer 311, and an opening 307 is formed in the third interlayer insulating layer 139 and the fourth interlayer insulating layer 311. The opening 305 is formed at a position corresponding to the source electrode and the drain electrode of the pixel circuit transistor 301 and the peripheral circuit transistor 303. The opening 307 is formed at the connection position with the wiring layer 130 (second wiring layer 137).

  As shown in FIG. 10, a conductive layer is formed in the fourth interlayer insulating layer 311 and the openings 305 and 307, and the conductive layer is subjected to photolithography and etching to form a source wiring layer 313 and a drain wiring layer 315, The third wiring layer 317 and the through electrode 319 are formed. A fifth interlayer insulating layer 321 is formed on these wiring layers, an opening reaching the drain wiring layer 315 is formed in the fifth interlayer insulating layer 321, and a pixel electrode 23 is formed. Subsequently, a partition wall 331 covering the end of the pixel electrode 23 is formed. Then, by forming the organic EL layer 333 and the common electrode 335 on the pixel electrode 23, the electro-optical layer 330 is formed, and the display device 10 shown in FIG. 2 is completed.

  As described above, according to the method of manufacturing the display device 10 according to the present embodiment, after the IC chip 110 and the resin layer 120 are formed on the support substrate 400 and the adhesive layer 410, these are formed into the support substrate 400 and the adhesive layer 410. By peeling from the above, it is possible to realize a configuration in which the chip second surface 111 and the chip side surface 113 of the IC chip 110 are covered with resin. Thus, the mechanical strength of the IC chip 110 can be improved. In addition, a flat surface can be provided prior to formation of the interconnect layer 130. Further, by forming an opening reaching the wiring layer 130 together with forming an opening reaching the pixel circuit transistor 301 and the peripheral circuit transistor 303, the IC chip 110 and the peripheral circuit transistor 303 are connected in a simple process. Can.

Second Embodiment
A display device according to an embodiment of the present invention will be described with reference to FIG. In the display device 10A of the second embodiment, the IC chip is separated according to the function. In the display device 10A, IC chips separated for each function are arranged at positions suitable for each.

  FIG. 11 is a top view showing an outline of a display device according to an embodiment of the present invention. As shown in FIG. 11, in the display device 10A, a power supply IC chip 500A, a memory IC chip 510A, and a GPU 520A are separately disposed as IC chips. The power supply IC chip 500A supplies drive power for various circuits. The memory IC chip 510A stores various information necessary for the operation of the display device. For example, the memory IC chip 510A may function as a frame memory. When the memory IC chip 510A functions as a frame memory, the memory IC chip 510A may be disposed closer to the GPU 520A than the power IC chip 500A. The GPU 520A controls a drive circuit that supplies gradation data to the pixels arranged in the display area 20A. The GPU 520A can also be referred to as a pixel drive IC chip.

  In FIG. 11, the power supply IC chip 500A and the memory IC chip 510A are disposed in the display area 20A, and the GPU 520 is disposed across the display area 20A and the peripheral area 30A. However, the GPU 520 may be disposed only in the peripheral area 30A. The power supply IC chip 500A and the memory IC chip 510A may be disposed in the peripheral area 30A. The power supply IC chip 500A and the memory IC chip 510A are connected to the transistor of the transistor layer 310A in the display area 20A or the peripheral area 30A via the wiring layer 130A.

  As described above, according to the display device 10A according to the present embodiment, the degree of freedom in design is improved by disposing the IC chip separately for each function. For example, by disposing in the peripheral area 30A the GPU 520A that supplies a signal to the peripheral circuit (for example, the gate driver 31A) disposed in the peripheral area 30A, wiring resistance from the GPU 520A to the peripheral circuit can be reduced. Delay can be suppressed. Further, since the IC chip can be subdivided, when the display device 10A has flexibility, it is possible to suppress the influence of the inhibition on the bending by the IC chip.

Third Embodiment
A display device according to an embodiment of the present invention will be described with reference to FIG. Similar to the display device 10A of the second embodiment, in the display device 10B of the third embodiment, the IC chip is separated according to the function. Unlike the display device 10A, in the display device 10B, the GPU is separately disposed in the gate driver IC chip 521B and the source driver IC chip 523B.

  FIG. 12 is a top view showing an outline of a display device according to an embodiment of the present invention. As shown in FIG. 12, in the display device 10B, a gate driver IC chip 521B and a source driver IC chip 523B are separately disposed as GPUs. The gate driver IC chip 521B is provided at a position overlapping the gate driver 31B in the peripheral region 30B. The source driver IC chip 523B is provided at a position overlapping the source driver 33B in the peripheral area 30B. The gate driver IC chip 521B controls on / off of a transistor provided in the gate driver 31B. The source driver IC chip 523B controls gradation data supplied to a transistor provided in the source driver 33B.

  In other words, the gate driver IC chip 521B is disposed closer to the gate driver 31B than the source driver 33B. The source driver IC chip 523B is disposed closer to the source driver 33B than the gate driver 31B.

  As described above, according to the display device 10B according to the present embodiment, the GPU is separately disposed for each function, whereby the degree of freedom in design is improved. For example, by arranging the gate driver IC chip 521B near the gate driver 31B and arranging the source driver IC chip 523B near the source driver 33B, driver circuits controlled by each IC chip and each IC chip 110 chip And the wiring resistance between them can be reduced, and signal delay can be suppressed. Further, since the IC chip can be further subdivided, in the case where the display device 10B has flexibility, the influence of inhibition on bending by the IC chip can be suppressed.

Fourth Embodiment
A display device according to an embodiment of the present invention will be described using FIGS. 13 to 16. Similar to the display device 10A of the second embodiment, in the display device 10C of the fourth embodiment, the IC chip is separated according to the function. Unlike the display device 10A, the display device 10C is provided with a touch sensor on the top of the display device 10C, and has a touch sensor IC chip 601C that drives the touch sensor as an IC chip. The touch sensor IC chip 601C is provided in the lower part of the display device 10C, like the other IC chips.

  FIG. 13 is a top view showing an outline of a display device according to an embodiment of the present invention. As shown in FIG. 13, the display device 10C includes a touch sensor drive circuit 61C, a touch sensor detection circuit 62C, a touch sensor drive electrode 610C, and a touch sensor detection electrode 620C. The display device 10C further includes a touch sensor IC chip 601C as an IC chip. The touch sensor IC chip 601C is disposed separately from the power supply IC chip 500C, the memory IC chip 510C, and the GPU 520C. The touch sensor drive circuit 61C, the touch sensor detection circuit 62C, and the touch sensor IC chip 601C are provided in the peripheral area 30C. The touch sensor drive electrode 610C and the touch sensor detection electrode 620C are provided in the display area 20C. Although FIG. 13 illustrates the configuration in which the GPU 520C and the touch sensor IC chip 601C are provided in the peripheral area 30C, for example, only the touch sensor IC chip 601C is provided in the peripheral area 30C, and the other IC chips are display areas. It may be provided at 20C.

  A plurality of touch sensor drive electrodes 610C and a plurality of touch sensor detection electrodes 620C are provided. The touch sensor drive electrodes 610C extend in the column direction from the touch sensor drive circuit 61C. The touch sensor detection electrode 620C extends in the row direction from the touch sensor detection circuit 62C. The plurality of touch sensor drive electrodes 610C intersect with the plurality of touch sensor detection electrodes 620C. In other words, the plurality of touch sensor drive electrodes 610C and the plurality of touch sensor detection electrodes 620C are provided in a grid shape. Note that, as described below, the touch sensor drive electrode 610C and the touch sensor detection electrode 620C are provided in the same layer, and are provided in different layers only at locations where the both electrodes intersect. However, both electrodes described above may be provided in different layers.

  The touch sensor drive circuit 61C is controlled by the touch sensor IC chip 601C. The touch sensor detection circuit 62C receives a signal based on the touch of the detection subject (for example, a signal based on a change in capacitance between the touch sensor drive electrode 610C and the touch sensor detection electrode 620C). The signal received by the touch sensor detection circuit 62C is transmitted to the touch sensor IC chip 601C. The touch sensor IC chip 601C determines the presence or absence of a touch of the detection target based on the control signal supplied by the touch sensor drive circuit 61C and the signal received by the touch sensor detection circuit 62C. When the touch of the detection target is detected, the touch sensor IC chip 601C calculates coordinates at which the touch is detected. The object to be detected may be a dielectric such as a stylus as well as a dielectric such as a finger of a user who uses the display device.

  FIG. 14 is a cross-sectional view showing an outline of a display device according to an embodiment of the present invention. The sectional view of FIG. 14 is a line BB ′ of the display area 20C of FIG. 13, a line CC ′ of the peripheral area 30C adjacent to the display area 20C in the row direction, and a column direction with respect to the display area 20C. 10B is a cross-sectional view taken along the line DD 'of the peripheral region 30C adjacent thereto. As shown in FIG. 14, in the display device 10C, the power supply IC chip 500C is connected to the pixel circuit transistor 301C. Further, the GPU 520C is connected to the peripheral circuit transistor 303C. Further, the touch sensor IC chip 601C is connected to the touch sensor detection electrode 620C via the through electrode 630C.

  As shown in FIG. 14, a planarizing film 640C and a protective film 650C are provided on the display panel circuit 300C. The touch sensor layer 600C is provided on the protective film 650C. The touch sensor layer 600C includes a touch sensor drive electrode 610C, a touch sensor detection electrode 620C, a sixth interlayer insulating layer 660C, and a through electrode 630C. A resin layer 670C is provided on the touch sensor layer 600C. As described above, the touch sensor drive electrode 610C and the touch sensor detection electrode 620C are provided in the same layer. Where the two electrodes intersect, they intersect via the conductive layer provided with the through electrode 630C.

  In the region where the touch sensor IC chip 601C is provided, an opening 631C is provided in the insulating layer from the third interlayer insulating layer 139C to the sixth interlayer insulating layer 660C. The opening 631C exposes the second wiring layer 137C of the wiring layer 130C. An opening 633C is provided in the sixth interlayer insulating layer 660C in a region where the GPU 520C is provided. The opening 633C exposes the touch sensor detection electrode 620C. The through electrode 630C is provided on the sixth interlayer insulating layer 660C, the opening 631C, and the opening 633C. That is, the through electrode 630C connects the second wiring layer 137C exposed by the opening 631C and the touch sensor detection electrode 620C exposed by the opening 633C. The through electrode 630C is provided on the side wall portion of the opening 631C. In the opening 631C, the resin layer 670C is filled inside the through electrode 630C.

  An organic insulating layer is used as the planarization film 640C and the resin layer 670C. These organic insulating layers relieve the steps of the lower layer and provide a flat surface. An inorganic insulating layer is used as the protective film 650C. The inorganic insulating layer suppresses external moisture and oxygen from reaching, for example, the organic EL layer 333C. As the inorganic insulating layer, an insulating layer containing, for example, silicon nitride is used. The sixth interlayer insulating layer 660C may be separated from the touch sensor drive electrode 610C, the touch sensor detection electrode 620C, and the conductive layer provided with the through electrode 630C. Therefore, an organic insulating layer may be used as the sixth interlayer insulating layer 660C, and an inorganic insulating layer may be used.

  As described above, in the display device 10C according to the present embodiment, in addition to the same effect as the other embodiments, the opening 631C penetrating the insulating layer from the third interlayer insulating layer 139C to the sixth interlayer insulating layer 660C By filling the through electrode 630C and the resin layer 670C, stress applied to the through electrode 630C can be relaxed. Further, by filling the opening 631C with the through electrode 630C and the resin layer 670C, the adhesion of the touch sensor layer 600C to the display panel circuit 300C can be improved.

[Method of Manufacturing Display Device 10C]
A method of manufacturing the display device 10C according to the present embodiment will be described with reference to FIGS. FIG.15 and FIG.16 is sectional drawing which shows the manufacturing method of the display apparatus based on one Embodiment of this invention.

  The method of forming the IC chip circuit 100C and the display panel circuit 300C can be formed in the same manner as the method shown in FIGS. 4 to 10, and thus the description thereof is omitted here. As shown in FIG. 15, a planarizing film 640C and a protective film 650C are formed on the display panel circuit 300C. The touch sensor drive electrode 610C and the touch sensor detection electrode 620C are formed on the protective film 650C, and a sixth interlayer insulating layer 660C covering the electrodes is formed.

  As shown in FIG. 16, an opening 631C is formed in the insulating layer from the third interlayer insulating layer 139C to the sixth interlayer insulating layer 660C to expose the second wiring layer 137C, and an opening 633C is formed in the sixth interlayer insulating layer 660C. It forms and exposes the touch sensor detection electrode 620C. The openings 631C and 633C can be formed by irradiating the insulating layer to be an opening with laser light. Note that the openings 631C and the openings 633C may be irradiated with laser light of different conditions because the number of layers and the thickness of the layers of the insulating layer to be formed are different. In the case where the sixth interlayer insulating layer 660C is formed of a photosensitive resin, the opening may be formed in advance in the sixth interlayer insulating layer 660C in the region where the opening 633C and the opening 631C are formed.

  By forming the through electrode 630C on the sixth interlayer insulating layer 660C and in the openings 631C and 633C and forming the resin layer 670C, the display device 10C shown in FIG. 14 can be formed.

  The embodiments described above as the embodiments of the present invention can be implemented in combination as appropriate as long as they do not contradict each other. In addition, those in which a person skilled in the art appropriately adds, deletes or changes the design of components based on the display device of each embodiment or those in which steps are added, omitted or conditions changed are also included in the present invention. As long as it comprises the gist, it is included in the scope of the present invention.

  In the present specification, although the case of an EL display device is mainly illustrated as a disclosed example, an electronic paper type display having another self-light emitting display device, a liquid crystal display device, or an electrophoretic element as another application example Devices include any flat panel type display device. Moreover, it is applicable without particular limitation from medium size to large size.

  Even if other effects or effects different from the effects brought about by the aspects of the above-described embodiments are apparent from the description of the present specification or those which can be easily predicted by those skilled in the art, it is natural. It is understood that the present invention provides.

10: display device 20: display area 21: pixel 23: pixel electrode 30: peripheral area 31: gate driver 33: source driver 61C: touch sensor drive circuit 62C: touch sensor detection circuit 100: IC chip circuit, 110: IC chip, 111: second chip surface, 113: chip side surface, 115: first chip surface, 117: chip terminal, 120: resin layer, 121: first resin surface, 130: wiring layer, 131: first interlayer insulating layer, 133: first wiring layer, 135: second interlayer insulating layer, 137: second wiring layer, 139: third interlayer insulating layer, 208: undercoat, 210: drive transistor, 212: Semiconductor film, 212a: source region, 212b: drain region, 212c: channel, 214: gate insulating film, 216: gate electrode, 218: interlayer insulating film, 220: source electrode, 222: drain electrode, 230: storage capacity, 232: capacitance electrode, 240: planarizing film, 242: connection electrode, 250: additional capacitance, 252: addition Capacitive electrode, 254: Capacitive insulating film, 256: aperture, 258: partition wall, 260: light emitting element, 262: pixel electrode, 264: organic EL layer, 266: hole injection / transport layer, 268: light emitting layer, 270: electron injection -Transport layer, 272: common electrode, 300: display panel circuit, 301: pixel circuit transistor, 303: peripheral circuit transistor, 305, 307: opening, 310: transistor layer, 311: fourth interlayer insulating layer, 313: source wiring Layer, 315: drain wiring layer, 317: third wiring layer, 319: through electrode, 321: fifth interlayer insulating layer, 330: electro-optical layer, 331: partition wall, 333: organic EL layer, 335: common electrode, 400: support substrate, 401: alignment marker, 410: adhesive layer, 500A: power IC chip, 510A: memory IC chip, 521B: gate driver IC chip, 523B: source driver IC chip, 600C: touch sensor layer, 601C: touch sensor IC chip, 610C: touch sensor drive electrode, 620C: touch sensor detection electrode, 630C: penetration Electrode, 631C, 633C: opening, 640C: flattening film, 650C: protective film, 660C: sixth interlayer insulating layer, 670C: resin layer

Claims (11)

An IC chip having a terminal on the first side;
A second surface opposite to the first surface of the IC chip, and a resin layer covering a side surface between the first surface and the second surface;
A wiring layer including a wiring provided on the IC chip and the resin layer and connected to the terminal;
A transistor layer including a transistor provided on the wiring layer and connected to the wiring;
An electro-optical layer provided on the transistor layer and including a pixel electrode connected to the transistor;
A display device having   The display device according to claim 1, wherein the first surface of the IC chip and the surface on the wiring layer side of the resin layer are on the same plane. The wiring layer includes a first insulating layer,
The transistor layer includes a second insulating layer,
The display device according to claim 1, wherein the wiring and the transistor are connected to each other through a through electrode penetrating the first insulating layer and the second insulating layer.   The display device according to any one of claims 1 to 3, wherein the IC chip and the transistor overlap in plan view.   The display device according to any one of claims 1 to 4, wherein the IC chip and the pixel electrode overlap in a plan view. The IC chip includes a power supply IC chip for supplying power and a pixel drive IC chip for controlling a drive circuit for supplying gray scale data to the pixels.
The display device according to any one of claims 1 to 5, wherein the power supply IC chip and the pixel drive IC chip are disposed separately. The pixel driving IC chip includes a gate driver driving IC chip that controls on or off of the transistor, and a source driver driving IC chip that controls gray scale data supplied to the transistor.
The display device of claim 6, wherein the gate driver driving IC chip and the source driver driving IC chip are separately disposed. The transistor layer includes a gate driver controlled by the gate driver driving IC chip and a source driver controlled by the source driver driving IC chip,
The gate driver driving IC chip is disposed closer to the gate driver than the source driver.
The display device of claim 7, wherein the source driver driving IC chip is disposed closer to the source driver than the gate driver. And a touch sensor electrode disposed in a display area for displaying an image by the pixel electrode,
The IC chip includes a touch sensor IC connected to the touch sensor wiring,
The display device according to any one of claims 6 to 8, wherein the touch sensor IC is disposed separately from the power supply IC chip and the pixel drive IC chip.   The display device according to claim 9, wherein the touch sensor IC is disposed in a peripheral area around the display area. The IC chip having a terminal on the first surface is disposed such that the terminal faces the supporting substrate,
A resin layer is formed on the support substrate to cover a second surface opposite to the first surface of the IC chip and a side surface between the first surface and the second surface.
Peeling off the IC chip and the resin layer from the supporting substrate;
Forming a wiring layer including a wiring connected to the terminal;
Forming a transistor layer including a transistor connected to the wiring;
A manufacturing method of a display which forms an electro-optic layer containing a pixel electrode connected to the transistor.

Images