JP2019195028A - Storage device - Google Patents

Abstract

A novel storage device is provided. In a storage device having a control circuit and a plurality of memory cells, OS transistors are used as transistors included in the memory cells. The transistor has a gate and a back gate. The control circuit has a function of selecting a potential to be supplied to the gate from at least three potentials. One of the three potentials is a potential for turning on the transistor, the other one is a potential for making the information holding time of the memory cell 1 hour or more, and the other one is a potential for holding the information holding time of the memory cell. The potential is 10 years or more. A plurality of memory blocks each including a plurality of memory cells are provided, frequently accessed information is held in a memory block operating in a high speed operation mode, and other information is held in a memory block operating in a low speed operation mode. In the low-speed operation mode, the information retention time is long and the refresh frequency can be reduced. [Selection diagram] Figure 1

Description

One embodiment of the present invention relates to a memory device, a semiconductor device, or an electronic device using the memory device.

Note that one embodiment of the present invention is not limited to the above technical field. One embodiment of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. Alternatively, one embodiment of the invention disclosed in this specification and the like relates to a process, a machine, a manufacture, or a composition (composition of matter).

Note that in this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. A transistor and a semiconductor circuit are one embodiment of a semiconductor device. A display device (a liquid crystal display device, a light-emitting display device, or the like), a projection device, a lighting device, an electro-optical device, a power storage device, a memory device, a semiconductor circuit, an imaging device, an electronic device, or the like may be referred to as a semiconductor device. Alternatively, it may be said that these include semiconductor devices.

As a semiconductor thin film applicable to a transistor, a silicon-based semiconductor material is widely known, but an oxide semiconductor has attracted attention as another material. As oxide semiconductors, for example, not only single-component metal oxides such as indium oxide and zinc oxide but also multi-component metal oxides are known. In particular, research on In—Ga—Zn oxide (hereinafter also referred to as IGZO) has been actively conducted among multi-element metal oxides.

As a result of research on IGZO, a CAAC (c-axis aligned crystalline) structure and an nc (nanocrystalline line) structure, which are neither single crystal nor amorphous, have been found in oxide semiconductors (see Non-Patent Document 1 to Non-Patent Document 3). .) Non-Patent Document 1 and Non-Patent Document 2 also disclose a technique for manufacturing a transistor using an oxide semiconductor having a CAAC structure. Furthermore, Non-Patent Document 4 and Non-Patent Document 5 show that even an oxide semiconductor having lower crystallinity than the CAAC structure and the nc structure has a minute crystal.

Further, a transistor using IGZO as an active layer has extremely low off-state current (see Non-Patent Document 6), and an LSI and a display using the characteristics have been reported (see Non-Patent Document 7 and Non-Patent Document 8). .)

As one of storage devices, a DRAM (Dynamic Random Access Memory) is known. A DRAM has a cell array in which a plurality of memory cells are provided in a matrix, a plurality of bit lines, and a plurality of word lines. The memory cell is electrically connected to any one of the plurality of bit lines and any one of the plurality of word lines. A selection signal for selecting a memory cell to which information is written / read is supplied to the word line. Information is written to and read from the memory cell through a bit line.

Therefore, for example, when writing information to the memory cell X via the bit line A, the potential fluctuation of the bit line A may propagate as noise to the bit line B adjacent to the bit line A. Then, there is a case where information held in the memory cell Y electrically connected to the bit line B is rewritten unintentionally. As one method for suppressing the influence of such noise, a twist bit line method has been proposed (see Patent Document 1).

JP-A-2-244485

S. Yamazaki et al. "SID Symposium Digest of Technical Papers", 2012, volume 43, issue 1, p. 183-186 S. Yamazaki et al. , “Japan Journal of Applied Physics”, 2014, volume 53, Number 4S, p. 04ED18-1-04ED18-10 S. Ito et al. "The Proceedings of AM-FPD'13 Digest of Technical Papers", 2013, p. 151-154 S. Yamazaki et al. "ECS Journal of Solid State Science and Technology", 2014, volume 3, issue 9, p. Q3012-Q3022 S. Yamazaki, “ECS Transactions”, 2014, volume 64, issue 10, p. 155-164 K. Kato et al. "Japan Journal of Applied Physics", 2012, volume 51, p. 021201-1-021201-7 S. Matsuda et al. “2015 Symposium on VLSI Technology Digest of Technical Papers”, 2015, p. T216-T217 S. Amano et al. "SID Symposium Digest of Technical Papers", 2010, volume 41, issue 1, p. 626-629

An object of one embodiment of the present invention is to provide a highly integrated memory device. Another object is to provide a memory device that can operate at high speed. Another object is to provide a highly reliable memory device. Another object is to provide a memory device with low power consumption. Another object is to provide a novel storage device. Another object is to provide a novel semiconductor device.

Note that the description of these problems does not disturb the existence of other problems. Note that one embodiment of the present invention does not have to solve all of these problems. Issues other than these will be apparent from the description of the specification, drawings, claims, etc., and other issues can be extracted from the descriptions of the specification, drawings, claims, etc. It is.

One embodiment of the present invention includes a control circuit and a plurality of memory cells. Each of the plurality of memory cells includes a transistor and a capacitor. The transistor includes a gate, a back gate, The semiconductor layer of the transistor includes a metal oxide, and the control circuit has a function of selecting a potential supplied to the gate of the transistor from the first potential, the second potential, or the third potential, Is a potential that turns on the transistor, and the second potential and the third potential are potentials that turn the transistor off, and the second potential is higher than the third potential. This is a storage device.

Another embodiment of the present invention includes a control circuit and a plurality of memory cells. Each of the plurality of memory cells includes a transistor and a capacitor. The transistor includes a gate, One of the source and drain of the transistor is electrically connected to the capacitor, the other of the source and drain of the transistor is electrically connected to the bit line, and the gate is electrically connected to the word line. The control circuit is configured to supply a first potential to the word line and supply a charge from the bit line to the capacitor, and supply a second potential or a third potential to the word line to hold the charge. The memory device is characterized in that the second potential is higher than the third potential.

The second potential is, for example, a potential at which the charge retention time is 1 hour or longer. The third potential is, for example, a potential at which the charge retention time is 10 years or longer. It is preferable that a negative bias is supplied to the back gate. The metal oxide preferably contains at least one of indium and zinc.

Another embodiment of the present invention includes a plurality of storage blocks, each of the plurality of storage blocks includes a plurality of memory cells, and each of the plurality of memory cells includes a transistor, a capacitor, A transistor having a gate and a back gate, a semiconductor layer of the transistor including a metal oxide, and a memory block having a function of operating in a plurality of operation modes It is.

The operation mode is determined by a combination of a potential supplied to the gate and a potential supplied to the back gate. One of the plurality of operation modes is an operation mode for increasing the operation speed of the memory cell. Another one of the plurality of operation modes is an operation mode for extending the retention time of the memory cell.

Another embodiment of the present invention includes a plurality of storage blocks, each of the plurality of storage blocks includes a plurality of memory cells, and each of the plurality of memory cells includes a transistor, a capacitor, The transistor includes a gate and a back gate, the semiconductor layer of the transistor includes a metal oxide, the plurality of storage blocks include a first storage block that operates in the first operation mode, and a second storage block And a second storage block that operates in an operation mode.

The first operation mode is an operation mode for increasing the operation speed of the memory cell. The second operation mode is an operation mode for extending the retention time of the memory cell.

According to one embodiment of the present invention, a highly integrated memory device can be provided. Alternatively, a memory device that can operate at high speed can be provided. Alternatively, a highly reliable memory device can be provided. Alternatively, a memory device with low power consumption can be provided. Alternatively, a novel storage device can be provided. Alternatively, a novel semiconductor device can be provided.

Note that the description of these effects does not disturb the existence of other effects. Note that one embodiment of the present invention need not have all of these effects. It should be noted that the effects other than these are naturally obvious from the description of the specification, drawings, claims, etc., and it is possible to extract the other effects from the descriptions of the specification, drawings, claims, etc. It is.

FIG. 9 illustrates a configuration example of a storage device. The figure which shows the structural example of a storage block array. The figure which shows the structural example of a storage block array. The figure which shows the structural example of a storage block. FIG. 6 is a diagram showing a circuit configuration example of a memory cell and electrical characteristics of a transistor. FIG. 11 shows electrical characteristics of a transistor. The figure which shows the relationship between Vg for every S value, and holding time. The figure which shows the usage example of a group. FIG. 9 illustrates a configuration example of a semiconductor device. FIG. 9 illustrates a configuration example of a semiconductor device. 6A and 6B illustrate a structure example of a transistor. 6A and 6B illustrate a structure example of a transistor. 6A and 6B illustrate a structure example of a transistor. 6A and 6B illustrate a structure example of a transistor. 6A and 6B illustrate a structure example of a transistor. The figure which makes a product image. FIG. 9 illustrates a configuration example of an electronic device. FIG. 9 illustrates a configuration example of an electronic device. FIG. 9 illustrates a configuration example of an electronic device. FIG. 9 illustrates a configuration example of an electronic device.

Embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below. Note that in the structures of the invention described below, the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and description thereof is not repeated.

In addition, the position, size, range, and the like of each component illustrated in the drawings and the like may not represent the actual position, size, range, or the like in order to facilitate understanding of the invention. Therefore, the disclosed invention is not necessarily limited to the position, size, range, or the like disclosed in the drawings and the like. For example, in an actual manufacturing process, a layer or a resist mask may be lost unintentionally by a process such as etching, but may be omitted for easy understanding.

In particular, in a top view (also referred to as a “plan view”), a perspective view, and the like, some components may not be described in order to facilitate understanding of the invention. Moreover, description of some hidden lines may be omitted.

In the present specification and the like, ordinal numbers such as “first” and “second” are used to avoid confusion between components, and do not indicate any order or order such as process order or stacking order. In addition, even in terms that do not have an ordinal number in this specification and the like, an ordinal number may be added in the claims to avoid confusion between the constituent elements. Further, even terms having an ordinal number in this specification and the like may have different ordinal numbers in the claims. Even in the present specification and the like, terms with ordinal numbers are sometimes omitted in the claims.

Further, in this specification and the like, the terms “electrode” and “wiring” do not functionally limit these components. For example, an “electrode” may be used as part of a “wiring” and vice versa. Furthermore, the terms “electrode” and “wiring” include a case where a plurality of “electrodes” and “wirings” are integrally formed.

In the present specification and the like, the terms “upper” and “lower” do not limit that the positional relationship between the components is directly above or directly below and is in direct contact. For example, the expression “electrode B on the insulating layer A” does not require the electrode B to be formed in direct contact with the insulating layer A, and another configuration between the insulating layer A and the electrode B. Do not exclude things that contain elements.

In addition, since the functions of the source and the drain are switched with each other depending on operating conditions, such as when transistors with different polarities are used, or when the direction of current changes in circuit operation, which is the source or drain is limited. Is difficult. Therefore, in this specification, the terms source and drain can be used interchangeably.

In addition, in this specification and the like, when it is explicitly described that X and Y are connected, X and Y are electrically connected, and X and Y function. And the case where X and Y are directly connected are disclosed in this specification and the like. Therefore, it is not limited to a predetermined connection relationship, for example, the connection relationship shown in the figure or text, and anything other than the connection relation shown in the figure or text is also described in the figure or text.

In addition, in this specification and the like, “electrically connected” includes a case of being connected via “thing having some electric action”. Here, the “thing having some electric action” is not particularly limited as long as it can exchange electric signals between connection targets. Therefore, even in the case of being expressed as “electrically connected”, in an actual circuit, there is a case where there is no physical connection portion and the wiring is merely extended.

Note that the channel length refers to, for example, a region where a semiconductor (or a portion where current flows in the semiconductor when the transistor is on) and a gate electrode overlap with each other in a top view of the transistor, or a region where a channel is formed The distance between the source (source region or source electrode) and the drain (drain region or drain electrode) in FIG. Note that in one transistor, the channel length is not necessarily the same in all regions. That is, the channel length of one transistor may not be fixed to one value. Therefore, in this specification, the channel length is any one of values, the maximum value, the minimum value, or the average value in a region where a channel is formed.

The channel width is, for example, a region in which a semiconductor (or a portion in which a current flows in the semiconductor when the transistor is on) and a gate electrode overlap each other, or a source and a drain in a region where a channel is formed. This is the length of the part. Note that in one transistor, the channel width is not necessarily the same in all regions. That is, the channel width of one transistor may not be fixed to one value. Therefore, in this specification, the channel width is any one of values, the maximum value, the minimum value, or the average value in a region where a channel is formed.

Note that depending on the structure of the transistor, the channel width in a region where a channel is actually formed (hereinafter also referred to as “effective channel width”) and the channel width (hereinafter “apparently” shown in the top view of the transistor). Sometimes referred to as “channel width”). For example, when the gate electrode covers the side surface of the semiconductor layer, the effective channel width may be larger than the apparent channel width, and the influence may not be negligible. For example, in a fine transistor whose gate electrode covers a side surface of a semiconductor, the ratio of a channel formed on the side surface of the semiconductor may increase. In that case, the effective channel width is larger than the apparent channel width.

In such a case, it may be difficult to estimate the effective channel width by actual measurement. For example, in order to estimate the effective channel width from the design value, it is necessary to assume that the shape of the semiconductor is known. Therefore, it is difficult to accurately measure the effective channel width when the shape of the semiconductor is not accurately known.

Therefore, in this specification, the apparent channel width may be referred to as “surrounded channel width (SCW)”. In this specification, in the case where the term “channel width” is simply used, it may denote an enclosed channel width or an apparent channel width. Alternatively, in this specification, in the case where the term “channel width” is simply used, it may denote an effective channel width. Note that the channel length, channel width, effective channel width, apparent channel width, enclosed channel width, and the like can be determined by analyzing a cross-sectional TEM image or the like.

Note that in the case where the field-effect mobility of a transistor, the current value per channel width, and the like are calculated and calculated, the calculation may be performed using the enclosed channel width. In that case, the value may be different from that calculated using the effective channel width.

Note that the impurity of the semiconductor means, for example, a component other than the main component constituting the semiconductor. For example, an element having a concentration of less than 0.1 atomic% can be said to be an impurity. By including impurities, for example, DOS (Density of States) of a semiconductor may increase, carrier mobility may decrease, and crystallinity may decrease. In the case where the semiconductor is an oxide semiconductor, examples of the impurity that changes the characteristics of the semiconductor include a Group 1 element, a Group 2 element, a Group 13 element, a Group 14 element, a Group 15 element, and an oxide semiconductor. There are transition metals other than the main components of, for example, hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen and the like. In the case of an oxide semiconductor, water may also function as an impurity. In the case of an oxide semiconductor, oxygen vacancies may be formed, for example, by mixing impurities. In the case where the semiconductor is silicon, examples of impurities that change the characteristics of the semiconductor include group 1 elements, group 2 elements, group 13 elements, and group 15 elements excluding oxygen and hydrogen.

Further, in this specification, “parallel” means a state in which two straight lines are arranged at an angle of −10 ° to 10 °. Therefore, the case of −5 ° to 5 ° is also included. Further, “substantially parallel” means a state in which two straight lines are arranged at an angle of −30 ° to 30 °. “Vertical” and “orthogonal” mean a state in which two straight lines are arranged at an angle of 80 ° to 100 °. Therefore, the case of 85 ° to 95 ° is also included. Further, “substantially vertical” means a state in which two straight lines are arranged at an angle of 60 ° to 120 °.

In addition, in this specification, etc., the terms “same”, “same”, “equal”, “uniform” (including these synonyms), etc. with respect to the count value and the measured value, unless otherwise specified. And an error of plus or minus 20%.

In this specification and the like, in the case where a resist mask is formed by a photolithography method and an etching process is performed thereafter, the resist mask is removed after the etching process is finished unless otherwise specified.

In this specification and the like, the high power supply potential VDD (also referred to as “VDD” or “H potential”) indicates a power supply potential higher than the low power supply potential VSS. The low power supply potential VSS (also referred to as “VSS” or “L potential”) indicates a power supply potential lower than the high power supply potential VDD. In addition, a ground potential (also referred to as “GND” or “GND potential”) can be used as VDD or VSS. For example, when VDD is a ground potential, VSS is a potential lower than the ground potential, and when VSS is a ground potential, VDD is a potential higher than the ground potential.

In addition, when VSS is set as a reference potential (0 V), a potential lower than VSS may be referred to as “negative potential”, “negative voltage”, or “negative bias”. In addition, when VSS is a reference potential (0 V), a potential higher than VSS may be referred to as “positive potential”, “positive voltage”, or “positive bias”.

Note that the terms “film” and “layer” can be interchanged with each other depending on the case or circumstances. For example, the term “conductive layer” may be changed to the term “conductive film”. Alternatively, for example, the term “insulating film” may be changed to the term “insulating layer” in some cases.

The transistors described in this specification and the like are enhancement-type (normally-off-type) field effect transistors unless otherwise specified. The transistors described in this specification and the like are n-channel transistors unless otherwise specified. Therefore, the threshold voltage (also referred to as “Vth”) is assumed to be greater than 0 V unless otherwise specified.

(Embodiment 1)
A memory device according to one embodiment of the present invention is described with reference to drawings.

<Storage device 100>
FIG. 1 is a block diagram illustrating a configuration example of a storage device 100 which is one embodiment of the present invention.

The storage device 100 includes an input / output circuit 111 (IO Circuit), a control circuit 112 (Controller), an I2C receiver 113, a setting register 114 (Setting Register), an LVDS circuit 115, an LVDS circuit 116, a decoder 117 (Decoder), and a storage block array. 210 (Memory Block Array).

The control circuit 112 includes a register 118 (Reg_r) and a register 119 (Reg_w). The storage block array 210 includes n (n is an integer of 1 or more) storage blocks 211 (Memory Block) and a negative voltage generation circuit 218. In this specification and the like, the first storage block 211 is referred to as a storage block 211_1, and the i-th storage block 211 (i is an integer of 1 to n) is referred to as a storage block 211_i.

The n storage blocks 211 are divided into a plurality of groups. FIG. 2A illustrates an example in which eight storage blocks 211 (storage blocks 211_1 to 211_8) are divided into four groups. The first group 261_1 includes a storage block 211_1, and the second group 261_2 includes a storage block 211_2. The third group 261_3 includes the storage block 211_3 and the storage block 211_4, and the fourth group 261_4 includes the storage block 211_5 to the storage block 211_8.

A plurality of negative voltage generation circuits 218 may be provided. For example, as illustrated in FIG. 2B, a negative voltage generation circuit 218 (a negative voltage generation circuit 218_1 to a negative voltage generation circuit 218_4) may be provided for each group. 2B, the negative voltage generation circuit 218_1 has a function of supplying a negative voltage to the first group 261_1, and the negative voltage generation circuit 218_2 has a function of supplying a negative voltage to the second group 261_2. The negative voltage generation circuit 218_3 has a function of supplying a negative voltage to the third group 261_3, and the negative voltage generation circuit 218_4 has a function of supplying a negative voltage to the fourth group 261_4.

As shown in FIG. 3, a negative voltage generation circuit 218 (negative voltage generation circuit 218_1 to negative voltage generation circuit 218_8) may be provided for each storage block 211. In FIG. 4, the negative voltage generation circuit 218_1 has a function of supplying a negative voltage to the storage block 211_1, and the negative voltage generation circuit 218_2 has a function of supplying a negative voltage to the storage block 211_2. The negative voltage generation circuit 218_3 has a function of supplying a negative voltage to the storage block 211_3, and the negative voltage generation circuit 218_4 has a function of supplying a negative voltage to the storage block 211_4. The negative voltage generation circuit 218_5 has a function of supplying a negative voltage to the storage block 211_5, and the negative voltage generation circuit 218_6 has a function of supplying a negative voltage to the storage block 211_6. The negative voltage generation circuit 218_7 has a function of supplying a negative voltage to the storage block 211_7, and the negative voltage generation circuit 218_8 has a function of supplying a negative voltage to the storage block 211_8.

The input / output circuit 111 has a function of exchanging signals with an external device. The operating conditions of the storage device 100 are determined by setting parameters stored in the setting register 114. The setting parameter is written to the setting register 114 via the input / output circuit 111 and the I2C receiver 113. The I2C receiver 113 may be omitted depending on the purpose or application.

As an example of the setting parameter, there is designation information such as the refresh operation execution interval and circuit operation timing. The control circuit 112 has a function of determining an operation mode of the storage device 100 by processing a setting parameter and an external command signal. The control circuit 112 has a function of generating various control signals and controlling the operation of the entire storage device 100.

In addition, a reset signal res, an address signal ADDR [16: 0], a row address identification signal RAS (Row Address Strobe), and a column address identification signal CAS (Column Address Strobe) are externally transmitted to the control circuit 112 via the input / output circuit 111. A write control signal WE (Write Enable), a data read clock signal clk_r, write data WDATA [7: 0], and the like are supplied. The data read clock signal clk_r is supplied to the control circuit 112 via the transfer circuit LVDS_rx.

Further, the data write clock signal clk_t and the read data RDATA [7: 0] are supplied from the control circuit 112 to the input / output circuit 111. The data read clock signal clk_w is supplied to the input / output circuit 111 via the transfer circuit LVDS_tx. The transfer circuit LVDS_rx and the transfer circuit LVDS_tx are transfer circuits that operate according to the LVDS (Low voltage differential signaling) standard. Note that one or both of the transfer circuit LVDS_rx and the transfer circuit LVDS_tx may be omitted depending on the purpose or application.

The write data WDATA [7: 0] is transferred in synchronization with the data write clock signal clk_t and held in the register 119 in the control circuit 112. The control circuit 112 has a function of supplying data stored in the register 119 to the storage block array 210.

The data read from the storage block array 210 is held in the register 118 in the control circuit 112 as read data RDATA [7: 0]. The control circuit 112 has a function of transferring the read data RDATA [7: 0] to the input / output circuit 111 in synchronization with the data read clock signal clk_r.

The control circuit 112 also includes a column address signal C_ADDR [6: 0], a column selection enable signal CSEL_EN, a data latch signal DLAT, a global write enable signal GW_EN, a global read enable signal GR_EN, a global sense amplifier enable signal GSA_EN, and a global equalization enable. The signal GEQ_ENB, the local sense amplifier enable signal LSA_EN, the local equalization enable signal LEQ_ENB, and the word line address selection signal WL_ADDR [7: 0] are output.

The column address signal C_ADDR and the column selection enable signal CSEL_EN are supplied to the decoder 117.

<Storage block>
FIG. 4A is a block diagram illustrating a configuration example of the storage block 211_i. FIG. 4B is a perspective block diagram illustrating a configuration example of the local sense amplifier array 214 and the cell array 221 included in the memory block 211_i. Further, arrows indicating the X direction, the Y direction, and the Z direction are attached to FIG. The X direction, the Y direction, and the Z direction are directions orthogonal to each other.

The storage block 211_i includes a word line driver 212, a local sense amplifier driver 213, a local sense amplifier array 214, a global sense amplifier 215, a read / write selector 216, and a cell array 221.

The data latch signal DLAT, the global write enable signal GW_EN, and the global read enable signal GR_EN are supplied to the read / write selector 216. The global sense amplifier enable signal GSA_EN and the global equalization enable signal GEQ_ENB are supplied to the global sense amplifier 215. Local sense amplifier enable signal LSA_EN and local equalize enable signal EQ_ENB are supplied to local sense amplifier array 214. The word line address selection signal WL_ADDR [7: 0] is supplied to the word line driver 212.

The local sense amplifier array 214 includes a plurality of sense amplifiers 127 arranged in a matrix of f rows and g columns (f and g are both integers of 1 or more). In this specification and the like, the sense amplifier 127 in the first row and the first column is referred to as a sense amplifier 127 [1, 1]. The sense amplifier 127 in the k-th row and the h-th column (k is an integer of 1 to f. H is an integer of 1 to g) is referred to as a sense amplifier 127 [k, h].

The cell array 221 is provided over the local sense amplifier array 214. By providing the cell array 221 over the local sense amplifier array 214, the wiring length of the bit lines can be shortened.

The cell array 221 includes a plurality of memory cells 10 arranged in a matrix of p rows and q columns (p and q are both integers of 1 or more). The cell array 221 includes p word lines WL extending in the X direction (row direction) (not illustrated in FIG. 4B). Note that in this specification and the like, the j-th word line WL (j is an integer of 1 to p) is referred to as a word line WL [j].

One memory cell 10 is electrically connected to any one of word lines WL.

<Memory cell>
FIG. 5 shows a circuit configuration example of the memory cell 10. The memory cell 10 includes a transistor M1 and a capacitor element CA. Note that the transistor M1 includes a front gate (also simply referred to as a “gate”) and a back gate. The back gate is disposed so that the channel formation region of the semiconductor layer is sandwiched between the gate and the back gate. The names of the gate and the back gate are for convenience, and when one is called a “gate”, the other is called a “back gate”. Therefore, the names of the gate and the back gate can be used interchangeably. One of the gate and the back gate may be referred to as a “first gate” and the other may be referred to as a “second gate”.

One of the source and the drain of the transistor M1 is electrically connected to one electrode of the capacitor CA, and the other of the source and the drain of the transistor M1 is electrically connected to one of the bit line BL and the bit line BLB. The gate of the transistor M1 is electrically connected to one of the word line WLa and the word line WLb, and the back gate of the transistor M1 is electrically connected to the wiring BGL. The other electrode of the capacitive element CA is connected to the wiring CAL.

The wiring CAL functions as a wiring for applying a predetermined potential to the other electrode of the capacitor CA. A fixed potential such as VSS is preferably supplied to the wiring CAL at the time of data writing and data reading.

The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M1.

FIG. 5B illustrates an example of an Id-Vg characteristic which is one of the electrical characteristics of the transistor. The Id-Vg characteristic indicates a change in drain current (Id) with respect to a change in gate voltage (Vg). The horizontal axis in FIG. 5B indicates Vg on a linear scale. In addition, the vertical axis in FIG. 5B indicates Id on a log scale. As shown in FIG. 5B, when the positive bias voltage + Vbg is supplied as the back gate voltage (Vbg) to the wiring BGL, the Id-Vg characteristic shifts in the negative direction of Vg. When the voltage -Vbg that is a negative bias is supplied to the wiring BGL, the Id-Vg characteristic shifts in the positive direction of Vg. The shift amount of the Id-Vg characteristic is determined by the magnitude of the voltage supplied to the wiring BGL. By applying an arbitrary voltage to the wiring BGL, the threshold voltage of the transistor M1 can be increased or decreased.

Data writing and reading are performed by supplying a potential for turning on the transistor M1 to the word line WL, turning on the transistor M1, and turning on the bit line BL or the bit line BLB and one electrode of the capacitor CA. Is performed by electrically connecting the two.

Note that as the transistor M1, a transistor including an oxide semiconductor that is a kind of metal oxide for a semiconductor layer in which a channel is formed (also referred to as an “OS transistor”) is preferably used. For example, it is preferable to use an oxide semiconductor containing any one of indium, an element M (the element M is aluminum, gallium, yttrium, or tin) and zinc as a semiconductor layer in which a channel is formed. In particular, an oxide semiconductor including indium, gallium, and zinc is preferably used for the semiconductor layer of the OS transistor.

An OS transistor using an oxide semiconductor containing indium, gallium, and zinc has a characteristic of extremely low off-state current. By using an OS transistor as the transistor M1, the leakage current of the transistor M1 can be very low. That is, since the written data can be held for a long time by the transistor M1, the frequency of refreshing the memory cells can be reduced. Also, the refresh operation of the memory cell can be made unnecessary. In addition, since the leakage current is very low, multi-value data or analog data can be held in the memory cell.

Here, the temperature dependence of the Id-Vg characteristic which is one of the electrical characteristics of the transistor will be described.

FIG. 6A shows the Id-Vg characteristics of the OS transistor. FIG. 6B illustrates Id-Vg characteristics of a transistor in which silicon is used for a semiconductor layer in which a channel is formed (also referred to as a “Si transistor”). 6A and 6B both show Id-Vg characteristics of an n-channel transistor.

Both the OS transistor and the Si transistor have the property that Vth shifts in the negative direction as the temperature increases, and the subthreshold coefficient (also referred to as “S value”) increases as the temperature increases. As a result, Id (also referred to as “cut-off current”) when Vg is 0 V increases as the temperature increases.

An OS transistor hardly increases off-state current even in operation at high temperature (see FIG. 6A). In addition, the on-current of the OS transistor increases as the operating temperature increases. On the other hand, in the Si transistor, as the temperature rises, the off-current increases and the on-current decreases (see FIG. 6B). As the off-current increases, the voltage (information) written in the memory cell tends to decrease. That is, the information holding time is shortened and the refresh frequency of the memory cell is increased. Therefore, power consumption increases.

In this embodiment and the like, the holding time is a time until the voltage written in the memory cell is reduced from 100% to 60%. In other words, this is the time until the amount of charge written in the memory cell decreases from 100% to 60%.

As shown in FIGS. 6A and 5B, the OS transistor can reduce off-state current even at a high temperature by setting Vg and / or Vbg to a negative voltage. That is, by using an OS transistor as the transistor M1, an increase in the refresh frequency can be suppressed even in an operation at a high temperature, and the information holding time can be extended. Therefore, an increase in power consumption of the entire semiconductor device including the transistor M1 can be suppressed.

In this specification and the like, a DRAM using an OS transistor is referred to as DOSRAM (Dynamic Oxide Semiconductor Random Access Memory). A DOSRAM can be formed by applying an OS transistor as the transistor M1.

As described above, the S value of the OS transistor may fluctuate due to operation at a high temperature.
FIG. 7A shows a calculation result of Vg necessary to achieve a specific holding time when the S value of the OS transistor is 80 mV / dec, 180 mV / dec, or 200 mV / dec. FIG. 7B is a graph showing the relationship between the holding time and the calculated Vg. In FIG. 7B, the horizontal axis indicates the holding time in logarithm, and the vertical axis indicates Vg. Note that Vbg is fixed to a voltage at which the holding time is 1 hour when Vg is −0.8V.

7A and 7B, when the S value of the OS transistor is 80 mV / dec, about 40 days can be obtained by setting Vg to -1.04 V, and about one year by setting Vg to -1.12 V. It can be seen that the data can be retained for about 11 years by setting Vg to -1.2V. When the S value of the OS transistor is 120 mV / dec, Vg is set to −1.16V for about 40 days, Vg is set to −1.28V for about one year, and Vg is set to −1.4V. It can be seen that the data can be retained for about 11 years. When the S value of the OS transistor is 200 mV / dec, Vg is set to -1.4V for about 40 days, Vg is set to -1.6V for about one year, and Vg is set to -1.8V. It can be seen that the data can be retained for about 11 years.

When Vg for turning on the transistor M1 is VgH and Vg for turning off the transistor M1 is VgL, the voltages of VgH, VgL, and Vbg are changed for each group 261, and the memory cell 10 can be operated in different operation modes. . As an example, Table 1 shows four operation modes and shows the respective operation conditions. In this embodiment, the potential difference between VgH and VgL is 3.3V. However, the potential difference between VgH and VgL is not limited to 3.3V.

The voltages such as VgH, VgL, and Vbg shown in this embodiment and the like are examples, and are not limited to the values shown in this embodiment and the like. The value of VgH and / or VgL may be changed for each operation mode. However, if the absolute values of VgH and VgL are too large, the reliability is likely to be reduced. Further, when the value of VgH and / or VgL is changed for each operation mode, it is preferable that VgH and VgL are not changed as much as possible because the burden of circuit design increases.

[Normal mode]
In the normal mode, VgH is 2.5V, VgL is -0.8V, and Vbg is -3V. The read / write speed and retention time of information to / from the memory cell 10 in the normal mode are the basis of the operation of the storage block 211.

[High-speed mode]
In the high speed mode, VgH is set to 2.5V, VgL is set to -0.8V, and Vbg is set to 0V. By increasing the potential of Vbg, Vth of the transistor M1 can be decreased. Therefore, the operating speed of the transistor M1 can be increased without changing VgH and VgL. Further, Vbg may be a positive voltage depending on the electrical characteristics of the transistor and the like.

Further, the potential of Vbg may be increased when Vg is set to VgH, and the potential of Vbg may be decreased when Vg is set to VgL. By changing Vg and Vbg simultaneously, the operation speed of the transistor M1 can be further increased.

[Low speed mode]
In the low speed mode, VgH is set to 2.5V, VgL is set to -0.8V, and Vbg is set to -6V. By reducing the potential of Vbg, Vth of the transistor M1 can be increased. Therefore, the off-state current of the transistor M1 is reduced without changing VgH and VgL, and the holding time can be extended. Further, since the refresh interval can be extended, the power consumption of the storage block 211 can be reduced.

[Long retention mode]
In the long-term holding mode, VgL is set to -2V and Vbg is set to -6V. By setting VgL to −2 V and Vbg to −6 V, information can be held for a long period of 10 years or longer. Therefore, VgH is not substantially used in the long-term holding mode. When reading the information held in the storage block 211 operating in the long-term holding mode, the information may be temporarily operated in any of the above modes.

On the other hand, information may be read with VgH set to 2.5 V in the long-term holding mode. In this case, Vbg may be increased. However, when operating with VgL of −2 V and VgH of 2.5 V, the breakdown voltage of the transistor used for the word line driver needs to be 4.5 V or more. Therefore, in the long-term holding mode, for example, by setting VgH to the reference potential (0 V) and then setting VgL = −2 V, the long-term holding mode can be realized without changing the withstand voltage performance required for the driver.

Further, when the potential of VgL used in the long-term holding mode is sufficiently low, Vbg may be set to 0 V, or the back gate may be set in a floating state.

For example, the first group 261_1 can be operated in the high speed mode, the second group 261_2 can be operated in the normal mode, the third group 261_3 can be operated in the low speed mode, and the fourth group 261_4 can be operated in the long-term holding mode.

It is preferable to store (store) frequently accessed information in the first group 261_1 operating in the high-speed mode. For example, the storage block 211 close to the interface may be operated in the high speed mode.

Further, according to the access frequency, the information write destination can be assigned to either the second group 261_2 operating in the normal mode or the third group 261_3 operating in the low speed mode.

Information that is not used for a long time may be stored in the fourth group 261_4 operating in the long-term holding mode. For example, the fourth group 261_4 can be used as an auxiliary storage device (storage).

For example, as shown in FIG. 8A, the first group 261_1 functions as a register, the second group 261_2 functions as a cache, the third group 261_3 functions as a main memory (main memory), and the fourth group 261_4 functions as a storage. Good.

The register has a function of holding a result of arithmetic processing, setting information of the integrated circuit, and the like. The cache has a function of copying and holding a part of information held in the main memory. Data held in the cache can be used in place of the information held in the main memory. By copying frequently accessed data to the cache, the access speed can be increased. The storage has a function of holding data in the main memory and a function of outputting the held data to the main memory.

Further, as shown in FIG. 8B, the first group 261_1 may function as a cache, the second group 261_2 as a main memory, the third group 261_3 as a primary storage, and the fourth group 261_4 as a secondary storage. .

Also, as shown in FIG. 8C, the first group 261_1 may function as a primary cache, the second group 261_2 as a secondary cache, the third group 261_3 as a main memory, and the fourth group 261_4 as a storage. .

The control circuit 112 controls Vg, Vbg, the number of groups, the number of storage blocks 211 included in one group, the arrangement of the groups, the arrangement of the storage blocks 211 in the group, and the determination of the operation mode. For example, the number of storage blocks 211 included in one group can be changed as necessary.

Further, the operation mode of the storage block 211 may be changed every certain period. By periodically changing the operation mode of the storage block 211, characteristic deterioration can be prevented and the reliability of the storage device 100 can be improved.

According to one embodiment of the present invention, a single DOSRAM device can realize a storage device equivalent to a single SRAM (Static Random Access Memory), a storage device equivalent to an embedded DRAM (eDRAM), or the like. .

Further, by using an OS transistor as the transistor M1, the memory block array 210 can be operated in the above operation mode even under a high temperature environment.

This embodiment can be implemented in appropriate combination with the structures described in the other embodiments.

(Embodiment 2)
In this embodiment, a cross-sectional structure example of the memory device 100 is described with reference to drawings.

<Structural example of storage device>
FIG. 9 shows a partial cross section of the storage device 100. In the memory device 100 illustrated in FIG. 9, a local sense amplifier array 214 and a cell array 221 are stacked on a substrate 291. Circuits other than the cell array 221 are provided on the substrate 291 similarly to the local sense amplifier array 214. FIG. 9 illustrates the case where a single crystal semiconductor substrate (eg, a single crystal silicon substrate) is used as the substrate 291. A transistor included in the local sense amplifier array 214 has a source, a drain, and a channel formed in part of the substrate 291. The cell array 221 includes a thin film transistor (eg, an OS transistor).

[Local sense amplifier array 214]
In FIG. 9, the local sense amplifier array 214 includes a transistor 233a, a transistor 233b, and a transistor 233c on a substrate 291. FIG. 9 illustrates cross sections of the transistor 233a, the transistor 233b, and the transistor 233c in the channel length direction.

As described above, the channels of the transistors 233a, 233b, and 233c are formed in part of the substrate 291. In the case where high speed operation is required for the integrated circuit, a single crystal semiconductor substrate is preferably used as the substrate 291.

The transistor 233a, the transistor 233b, and the transistor 233c are electrically isolated from other transistors by the element isolation layer 292. The element isolation layer can be formed by using a LOCOS (Local Osidation of Silicon) method, an STI (Shallow Trench Isolation) method, or the like.

An insulating layer 293, an insulating layer 235, and an insulating layer 237 are provided over the transistor 233a, the transistor 233b, and the transistor 233c, and the electrode 238 is embedded in the insulating layer 237. The electrode 238 is electrically connected to one of a source and a drain of the transistor 233a through a contact plug 236.

An insulating layer 239, an insulating layer 240, and an insulating layer 241 are provided over the electrode 238 and the insulating layer 237, and the electrode 242 is embedded in the insulating layer 239, the insulating layer 240, and the insulating layer 241. . The electrode 242 is electrically connected to the electrode 238.

An insulating layer 243 and an insulating layer 244 are provided over the electrode 242 and the insulating layer 241, and the electrode 245 is embedded in the insulating layer 243 and the insulating layer 244. The electrode 245 is electrically connected to the electrode 242.

An insulating layer 246 and an insulating layer 247 are provided over the electrode 245 and the insulating layer 244, and the electrode 249 is embedded in the insulating layer 246 and the insulating layer 247. The electrode 249 is electrically connected to the electrode 245.

Further, the insulating layer 248 and the insulating layer 250 are provided over the electrode 249 and the insulating layer 247, and the electrode 251 is embedded in the insulating layer 248 and the insulating layer 250. The electrode 251 is electrically connected to the electrode 249.

[Cell array 221]
The cell array 221 is provided on the local sense amplifier array 214. In FIG. 9, the cell array 221 includes a transistor 368a, a transistor 368b, a capacitor 369a, and a capacitor 369b. In FIG. 9, the transistor 368a and the transistor 368b are cross-sectional views in the channel length direction. Note that the transistor 368a and the transistor 368b are transistors each having a back gate.

An oxide semiconductor that is a kind of metal oxide is preferably used for the semiconductor layers of the transistors 368a and 368b. That is, an OS transistor is preferably used for the transistors 368a and 368b.

The transistor 368a and the transistor 368b are provided over the insulating layer 361 and the insulating layer 362. An insulating layer 363 and an insulating layer 364 are provided over the insulating layer 362. The back gates of the transistors 368 a and 368 b are embedded in the insulating layers 363 and 364. An insulating layer 365 and an insulating layer 366 are provided over the insulating layer 364. An electrode 367 is embedded in the insulating layers 361 to 366. The electrode 367 is electrically connected to the electrode 251.

An insulating layer 371, an insulating layer 372, and an insulating layer 373 are formed over the transistor 368a, the transistor 368b, the capacitor 369a, and the capacitor 369b, and an electrode 375 is formed over the insulating layer 373. The electrode 375 is electrically connected to the electrode 367 through the contact plug 374.

An insulating layer 376, an insulating layer 377, an insulating layer 378, and an insulating layer 379 are provided over the electrode 375. An electrode 380 is embedded in the insulating layers 376 to 379. The electrode 380 is electrically connected to the electrode 375.

An insulating layer 381 and an insulating layer 382 are provided over the electrode 380 and the insulating layer 379.

<Modification>
FIG. 10 shows a partial cross section of the storage device 100A. The storage device 100A is a modification of the storage device 100. The storage device 100A includes a local sense amplifier array 214A and a cell array 221. The local sense amplifier array 214A and the cell array 221 are sequentially provided on the substrate 291. In the storage device 100A, an insulating substrate (eg, a glass substrate) is used as the substrate 291.

The local sense amplifier array 214A includes a transistor 268a, a transistor 268b, a capacitor 269a, and a capacitor 269b. Thin film transistors (for example, OS transistors) are used as transistors included in the local sense amplifier array 214A. The cell array 221 can be manufactured in the same manner as described above.

When all the transistors included in the local sense amplifier array 214A are OS transistors, the local sense amplifier array 214A can be a unipolar integrated circuit. When all the transistors included in the memory device 100A are OS transistors, the memory device 100A can be a unipolar memory device.

<Constituent materials>
〔substrate〕
There is no particular limitation on the material used for the substrate, but it is necessary that the substrate have heat resistance enough to withstand at least heat treatment performed later. For example, a single crystal semiconductor substrate using a material such as silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate using silicon germanium, or the like as the substrate can be used. Alternatively, an SOI substrate, a semiconductor substrate provided with a semiconductor element such as a strain transistor or a FIN transistor, or the like can be used. Alternatively, gallium arsenide, aluminum gallium arsenide, indium gallium arsenide, gallium nitride, indium phosphide, silicon germanium, or the like that can be used for a high electron mobility transistor (HEMT) may be used. That is, the substrate is not limited to a simple support substrate, and may be a substrate on which other devices such as transistors are formed.

As the substrate, a glass substrate such as barium borosilicate glass or alumino borosilicate glass, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like can be used. Note that a flexible substrate (flexible substrate) may be used as the substrate. In the case of using a flexible substrate, a transistor, a capacitor, or the like may be directly formed over the flexible substrate, or a transistor, a capacitor, or the like is formed over another manufacturing substrate, and then the flexible substrate is formed. You may peel and transpose. Note that a separation layer may be provided between the manufacturing substrate and a transistor, a capacitor, or the like in order to separate and transfer from the manufacturing substrate to the flexible substrate.

As the flexible substrate, for example, metal, alloy, resin or glass, or fiber thereof can be used. The flexible substrate used for the substrate is preferably as the linear expansion coefficient is low because deformation due to the environment is suppressed. For the flexible substrate used for the substrate, for example, a material having a linear expansion coefficient of 1 × 10 ⁻³ / K or less, 5 × 10 ⁻⁵ / K or less, or 1 × 10 ⁻⁵ / K or less may be used. Examples of the resin include polyester, polyolefin, polyamide (such as nylon and aramid), polyimide, polycarbonate, and acrylic. In particular, since aramid has a low coefficient of linear expansion, it is suitable as a flexible substrate.

[Insulation layer]
The insulating layer is made of aluminum nitride, aluminum oxide, aluminum nitride oxide, aluminum oxynitride, magnesium oxide, silicon nitride, silicon oxide, silicon nitride oxide, silicon oxynitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, A material selected from neodymium oxide, hafnium oxide, tantalum oxide, aluminum silicate, or the like is used as a single layer or a stacked layer. Alternatively, a material obtained by mixing a plurality of materials among oxide materials, nitride materials, oxynitride materials, and nitride oxide materials may be used.

Note that in this specification and the like, a nitrided oxide refers to a compound having a higher nitrogen content than oxygen. Further, oxynitride refers to a compound having a higher oxygen content than nitrogen. The content of each element can be measured using, for example, Rutherford Backscattering Spectrometry (RBS).

In the case where an oxide semiconductor which is a kind of metal oxide is used for the semiconductor layer, it is preferable to reduce the hydrogen concentration in the insulating layer in order to prevent an increase in the hydrogen concentration in the semiconductor layer. Specifically, the hydrogen concentration in the insulating layer is set to 2 × 10 ²⁰ atoms / cm ³ or less, preferably 5 × 10 ¹⁹ atoms / cm ³ or less in secondary ion mass spectrometry (SIMS). More preferably, it is 1 × 10 ¹⁹ atoms / cm ³ or less, and further preferably 5 × 10 ¹⁸ atoms / cm ³ or less. In particular, it is preferable to reduce the hydrogen concentration in the insulating layer in contact with the semiconductor layer.

In order to prevent an increase in the nitrogen concentration in the semiconductor layer, it is preferable to reduce the nitrogen concentration in the insulating layer. Specifically, the nitrogen concentration in the insulating layer is 5 × 10 ¹⁹ atoms / cm ³ or less in SIMS, preferably 5 × 10 ¹⁸ atoms / cm ³ or less, more preferably 1 × 10 ¹⁸ atoms / cm ³ or less. More preferably, it is 5 × 10 ¹⁷ atoms / cm ³ or less.

It is preferable that at least a region of the insulating layer in contact with the semiconductor layer and at least a region of the insulating layer in contact with the semiconductor layer have few defects, and are typically observed by an electron spin resonance (ESR) method. It is preferable that the signal is low. For example, the signal described above includes the E ′ center where the g value is observed at 2.001. The E ′ center is caused by silicon dangling bonds. For example, when a silicon oxide layer or a silicon oxynitride layer is used as the insulating layer, the spin density due to the E ′ center is 3 × 10 ¹⁷ spins / cm ³ or less, preferably 5 × 10 ¹⁶ spins / cm ³ or less. A silicon oxide layer or a silicon oxynitride layer may be used.

In addition to the above signal, a signal due to nitrogen dioxide (NO ₂ ) may be observed. The signal is split into three signals by N nuclear spins, each having a g value of 2.037 or more and 2.039 or less (referred to as the first signal), and a g value of 2.001 or more and 2.003. The g value is observed below (referred to as the second signal) and from 1.964 to 1.966 (referred to as the third signal).

For example, as the insulating layer, an insulating layer in which the spin density of a signal caused by nitrogen dioxide (NO ₂ ) is 1 × 10 ¹⁷ spins / cm ³ or more and less than 1 × 10 ¹⁸ spins / cm ³ is preferably used.

Note that nitrogen oxide (NO _x ) containing nitrogen dioxide (NO ₂ ) forms a level in the insulating layer. The level is located in the energy gap of the oxide semiconductor layer. Therefore, when nitrogen oxide (NO _x ) diffuses to the interface between the insulating layer and the oxide semiconductor layer, the level may trap electrons on the insulating layer side. As a result, trapped electrons remain in the vicinity of the interface between the insulating layer and the oxide semiconductor layer, so that the threshold voltage of the transistor is shifted in the positive direction. Therefore, when a film with a low content of nitrogen oxide is used for the insulating layer, a shift in threshold voltage of the transistor can be reduced.

For example, a silicon oxynitride layer can be used as the insulating layer that emits less nitrogen oxide (NO _x ). The silicon oxynitride layer is a film in which the amount of ammonia released is larger than the amount of nitrogen oxide (NO _x ) released in a temperature programmed desorption gas analysis (TDS: Thermal Desorption Spectroscopy). The discharge amount is 1 × 10 ¹⁸ pieces / cm ³ or more and 5 × 10 ¹⁹ pieces / cm ³ or less. The amount of ammonia released is the total amount when the temperature of the heat treatment in TDS is 50 ° C. or higher and 650 ° C. or lower, or 50 ° C. or higher and 550 ° C. or lower.

Since nitrogen oxide (NO _x ) reacts with ammonia and oxygen in the heat treatment, nitrogen oxide (NO _x ) is reduced by using an insulating layer that releases a large amount of ammonia.

In addition, at least one of the insulating layers in contact with the oxide semiconductor layer is preferably formed using an insulating layer from which oxygen is released by heating. Specifically, the amount of desorbed oxygen converted to oxygen atoms is 1.0 in TDS performed by heat treatment at a surface temperature of the insulating layer of 100 ° C. to 700 ° C., preferably 100 ° C. to 500 ° C. It is preferable to use an insulating layer with a size of 10 × 10 ¹⁸ atoms / cm ³ or higher, 1.0 × 10 ¹⁹ atoms / cm ³ or higher, or 1.0 × 10 ²⁰ atoms / cm ³ or higher. Note that in this specification and the like, oxygen released by heating is also referred to as “excess oxygen”.

The insulating layer containing excess oxygen can also be formed by performing treatment for adding oxygen to the insulating layer. The treatment for adding oxygen can be performed by heat treatment or plasma treatment in an oxidizing atmosphere. Alternatively, oxygen may be added by an ion implantation method, an ion doping method, a plasma immersion ion implantation method, or the like. As a gas used for the treatment for adding oxygen, an oxygen gas such as ¹⁶ O ₂ or ¹⁸ O ₂ , a gas containing oxygen such as a nitrous oxide gas, or an ozone gas can be given. Note that in this specification, treatment for adding oxygen is also referred to as “oxygen doping treatment”. The oxygen doping treatment may be performed by heating the substrate.

As the insulating layer, a heat-resistant organic material such as polyimide, acrylic resin, benzocyclobutene resin, polyamide, or epoxy resin can be used. In addition to the organic material, a low dielectric constant material (low-k material), a siloxane resin, PSG (phosphorus glass), BPSG (phosphorus boron glass), or the like can be used. Note that the insulating layer may be formed by stacking a plurality of insulating layers formed using these materials.

Note that the siloxane-based resin corresponds to a resin including a Si—O—Si bond formed using a siloxane-based material as a starting material. Siloxane resins may use organic groups (for example, alkyl groups and aryl groups) and fluoro groups as substituents. The organic group may have a fluoro group.

The method for forming the insulating layer is not particularly limited. Note that a baking step may be necessary depending on a material used for the insulating layer. In this case, the transistor can be efficiently manufactured by combining the baking process of the insulating layer and the other heat treatment process.

〔electrode〕
Examples of conductive materials for forming electrodes include aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, etc. A material containing one or more metal elements selected from the above can be used. Alternatively, a semiconductor with high electrical conductivity typified by polycrystalline silicon containing an impurity element such as phosphorus, or silicide such as nickel silicide may be used.

Alternatively, the above-described conductive material containing a metal element and oxygen may be used. Alternatively, the above-described conductive material containing a metal element and nitrogen may be used. For example, a conductive material containing nitrogen such as titanium nitride or tantalum nitride may be used. Indium tin oxide (ITO), indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc An oxide, indium gallium zinc oxide, or indium tin oxide to which silicon is added may be used. Alternatively, indium gallium zinc oxide containing nitrogen may be used.

A plurality of conductive layers formed using the above materials may be stacked. For example, a stacked structure in which the above-described material containing a metal element and a conductive material containing oxygen may be combined. Alternatively, a stacked structure in which the above-described material containing a metal element and a conductive material containing nitrogen are combined may be employed. Alternatively, a stacked structure of a combination of the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen may be employed. Alternatively, a stacked structure of a conductive material containing nitrogen and a conductive material containing oxygen may be used.

Note that in the case of using a stacked structure in which an oxide semiconductor is used for a semiconductor layer and the above-described material containing a metal element and a conductive material containing oxygen are used as a gate electrode, the conductive material containing oxygen is used as a semiconductor. It is good to provide on the layer side. By providing a conductive material containing oxygen on the semiconductor layer side, oxygen released from the conductive material can be easily supplied to the semiconductor layer.

As the electrode, for example, a highly embedded conductive material such as tungsten or polysilicon may be used. Alternatively, a conductive material with high embeddability and a barrier layer (diffusion prevention layer) such as a titanium layer, a titanium nitride layer, or a tantalum nitride layer may be used in combination. The electrode may be referred to as a “contact plug”.

In particular, it is preferable to use a conductive material that does not easily transmit impurities for the electrode in contact with the gate insulating layer. An example of a conductive material that hardly transmits impurities is tantalum nitride.

By using an insulating material that does not easily transmit impurities to the insulating layer and a conductive material that does not easily transmit impurities to the electrode and the electrode, diffusion of impurities to the transistor can be further suppressed. Thus, the reliability of the transistor can be further increased. That is, the reliability of the storage device can be further improved.

[Semiconductor layer]
As the semiconductor layer, a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, an amorphous semiconductor, or the like can be used alone or in combination. As the semiconductor material, for example, silicon or germanium can be used. Alternatively, a compound semiconductor such as silicon germanium, silicon carbide, gallium arsenide, an oxide semiconductor, or a nitride semiconductor, an organic semiconductor, or the like can be used.

In the case where an organic semiconductor is used as the semiconductor layer, a low molecular organic material having an aromatic ring, a π electron conjugated conductive polymer, or the like can be used. For example, rubrene, tetracene, pentacene, perylene diimide, tetracyanoquinodimethane, polythiophene, polyacetylene, polyparaphenylene vinylene, and the like can be used.

Note that a semiconductor layer may be stacked. In the case of stacking semiconductor layers, semiconductors having different crystal states may be used, or different semiconductor materials may be used.

In addition, since the band gap of an oxide semiconductor is 2 eV or more, a transistor with extremely low off-state current can be realized when an oxide semiconductor is used for a semiconductor layer. Specifically, the off-current per channel width of 1 μm is less than 1 × 10 ⁻²⁰ A and 1 × 10 ⁻²² A at a source-drain voltage of 3.5 V and room temperature (typically 25 ° C.). Or less than 1 × 10 ⁻²⁴ A. That is, the on / off ratio can be 20 digits or more. In addition, a transistor in which an oxide semiconductor is used for a semiconductor layer has high withstand voltage between a source and a drain. Thus, a highly reliable transistor can be provided. In addition, a transistor with a large output voltage and high withstand voltage can be provided. Further, a highly reliable storage device or the like can be provided. In addition, a memory device with a large output voltage and high withstand voltage can be provided.

In this specification and the like, a transistor in which crystalline silicon is used for a semiconductor layer in which a channel is formed is also referred to as a “crystalline Si transistor”.

A crystalline Si transistor tends to obtain a relatively high mobility than an OS transistor. On the other hand, a crystalline Si transistor is difficult to realize an extremely small off-state current like an OS transistor. Therefore, it is important that the semiconductor material used for the semiconductor layer is properly used depending on the purpose and application. For example, an OS transistor and a crystalline Si transistor may be used in combination depending on the purpose and application.

In the case where an oxide semiconductor layer is used as the semiconductor layer, the oxide semiconductor layer is preferably formed by a sputtering method. The oxide semiconductor layer is preferably formed by a sputtering method because the density of the oxide semiconductor layer can be increased. In the case where the oxide semiconductor layer is formed by a sputtering method, a rare gas (typically argon), oxygen, or a mixed gas of a rare gas and oxygen may be used as a sputtering gas. In addition, it is necessary to increase the purity of the sputtering gas. For example, as the oxygen gas or the rare gas used as the sputtering gas, a gas highly purified to have a dew point of −60 ° C. or lower, preferably −100 ° C. or lower is used. By forming a film using a highly purified sputtering gas, moisture and the like can be prevented from being taken into the oxide semiconductor layer as much as possible.

In the case where the oxide semiconductor layer is formed by a sputtering method, it is preferable to remove moisture in the deposition chamber included in the sputtering apparatus as much as possible. For example, it is preferable to evacuate the film formation chamber to a high vacuum (from about 5 × 10 ⁻⁷ Pa to about 1 × 10 ⁻⁴ Pa) using an adsorption-type vacuum exhaust pump such as a cryopump. In particular, the partial pressure of gas molecules corresponding to H ₂ O (gas molecules corresponding to m / z = 18) in the deposition chamber during standby of the sputtering apparatus is 1 × 10 ⁻⁴ Pa or less, preferably 5 × 10 ^{−. 5} Pa or less is preferable.

[Metal oxide]
An oxide semiconductor which is a kind of metal oxide preferably contains at least indium or zinc. In particular, it is preferable to contain indium and zinc. In addition to these, it is preferable that aluminum, gallium, yttrium, tin, or the like is contained. One or more kinds selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium may be included.

Here, a case where the oxide semiconductor includes indium, an element M, and zinc is considered. The element M is aluminum, gallium, yttrium, tin, or the like. Examples of other elements applicable to the element M include boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium. However, the element M may be a combination of a plurality of the aforementioned elements.

Note that in this specification and the like, metal oxides containing nitrogen may be collectively referred to as metal oxides. Further, a metal oxide containing nitrogen may be referred to as a metal oxynitride.

[Composition of metal oxide]
A structure of a CAC (Cloud-Aligned Composite) -OS that can be used for the transistor disclosed in one embodiment of the present invention is described below.

In addition, in this specification etc., it may describe as CAAC (c-axis aligned crystal) and CAC (Cloud-aligned Composite). Note that CAAC represents an example of a crystal structure, and CAC represents an example of a function or a material structure.

The CAC-OS or the CAC-metal oxide has a conductive function in part of the material and an insulating function in part of the material, and the whole material has a function as a semiconductor. Note that in the case where a CAC-OS or a CAC-metal oxide is used for an active layer of a transistor, the conductive function is a function of flowing electrons (or holes) serving as carriers, and the insulating function is a carrier. This function prevents electrons from flowing. By performing the conductive function and the insulating function in a complementary manner, a switching function (function to turn on / off) can be given to the CAC-OS or the CAC-metal oxide. In CAC-OS or CAC-metal oxide, by separating each function, both functions can be maximized.

Further, the CAC-OS or the CAC-metal oxide has a conductive region and an insulating region. The conductive region has the above-described conductive function, and the insulating region has the above-described insulating function. In the material, the conductive region and the insulating region may be separated at the nanoparticle level. In addition, the conductive region and the insulating region may be unevenly distributed in the material, respectively. In addition, the conductive region may be observed with the periphery blurred and connected in a cloud shape.

In CAC-OS or CAC-metal oxide, the conductive region and the insulating region are each dispersed in a material with a size of 0.5 nm to 10 nm, preferably 0.5 nm to 3 nm. There is.

Further, CAC-OS or CAC-metal oxide is composed of components having different band gaps. For example, CAC-OS or CAC-metal oxide includes a component having a wide gap caused by an insulating region and a component having a narrow gap caused by a conductive region. In the case of the configuration, when the carrier flows, the carrier mainly flows in the component having the narrow gap. In addition, the component having a narrow gap acts in a complementary manner to the component having a wide gap, and the carrier flows through the component having the wide gap in conjunction with the component having the narrow gap. Therefore, when the CAC-OS or the CAC-metal oxide is used for a channel formation region of a transistor, high current driving capability, that is, high on-state current and high field-effect mobility can be obtained in the on-state of the transistor.

That is, CAC-OS or CAC-metal oxide can also be referred to as a matrix composite or a metal matrix composite.

[Structure of metal oxide]
An oxide semiconductor (metal oxide) is classified into a single crystal oxide semiconductor and a non-single crystal oxide semiconductor. Examples of the non-single-crystal oxide semiconductor include a CAAC-OS (c-axis aligned crystal oxide semiconductor), a polycrystalline oxide semiconductor, an nc-OS (nanocrystalline oxide semiconductor), and a pseudo-amorphous oxide semiconductor (a-like oxide semiconductor). OS: amorphous-like oxide semiconductor) and amorphous oxide semiconductor.

The CAAC-OS has a c-axis orientation and a crystal structure in which a plurality of nanocrystals are connected in the ab plane direction and have a strain. Note that the strain refers to a portion where the orientation of the lattice arrangement changes between a region where the lattice arrangement is aligned and a region where another lattice arrangement is aligned in a region where a plurality of nanocrystals are connected.

Nanocrystals are based on hexagons, but are not limited to regular hexagons and may be non-regular hexagons. In addition, there may be a lattice arrangement such as a pentagon and a heptagon in the distortion. Note that in the CAAC-OS, it is difficult to check a clear crystal grain boundary (also referred to as a grain boundary) even in the vicinity of strain. That is, it can be seen that the formation of crystal grain boundaries is suppressed by the distortion of the lattice arrangement. This is because the CAAC-OS can tolerate distortion due to the fact that the arrangement of oxygen atoms is not dense in the ab plane direction and the bond distance between atoms changes due to substitution of metal elements. Because.

In addition, the CAAC-OS is a layered crystal in which a layer containing indium and oxygen (hereinafter referred to as an In layer) and a layer including elements M, zinc, and oxygen (hereinafter referred to as (M, Zn) layers) are stacked. There is a tendency to have a structure (also called a layered structure). Note that indium and the element M can be replaced with each other, and when the element M in the (M, Zn) layer is replaced with indium, it can also be expressed as an (In, M, Zn) layer. Further, when indium in the In layer is replaced with the element M, it can also be expressed as an (In, M) layer.

CAAC-OS is a metal oxide with high crystallinity. On the other hand, since it is difficult to confirm a clear crystal grain boundary in the CAAC-OS, it can be said that a decrease in electron mobility due to the crystal grain boundary hardly occurs. In addition, since the crystallinity of the metal oxide may be reduced due to entry of impurities, generation of defects, or the like, the CAAC-OS can be said to be a metal oxide with few impurities and defects (such as oxygen vacancies). Therefore, the physical properties of the metal oxide including a CAAC-OS are stable. Therefore, a metal oxide including a CAAC-OS is resistant to heat and has high reliability.

The nc-OS has periodicity in atomic arrangement in a minute region (for example, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In addition, the nc-OS has no regularity in crystal orientation between different nanocrystals. Therefore, orientation is not seen in the whole film. Therefore, the nc-OS may not be distinguished from an a-like OS or an amorphous oxide semiconductor depending on an analysis method.

The a-like OS is a metal oxide having a structure between the nc-OS and an amorphous oxide semiconductor. The a-like OS has a void or a low density region. That is, the a-like OS has lower crystallinity than the nc-OS and the CAAC-OS.

Oxide semiconductors (metal oxides) have various structures and have different characteristics. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, an nc-OS, and a CAAC-OS.

[Transistor with metal oxide]
Next, the case where the metal oxide is used for a channel formation region of a transistor will be described.

Note that by using the metal oxide for a channel formation region of a transistor, a transistor with high field-effect mobility can be realized. In addition, a highly reliable transistor can be realized.

For the transistor, a metal oxide with low carrier density is preferably used. In the case where the carrier density of the metal oxide film is lowered, the impurity concentration in the metal oxide film may be lowered and the defect level density may be lowered. In this specification and the like, a low impurity concentration and a low density of defect states are referred to as high purity intrinsic or substantially high purity intrinsic. For example, the metal oxide has a carrier density of less than 8 × 10 ¹¹ / cm ³ , preferably less than 1 × 10 ¹¹ / cm ³ , more preferably less than 1 × 10 ¹⁰ / cm ³ , and 1 × 10 ⁻⁹ / What is necessary is just to be cm ³ or more.

In addition, since a highly purified intrinsic or substantially highly purified intrinsic metal oxide film has a low defect level density, the trap level density may also be low.

In addition, the charge trapped in the trap level of the metal oxide takes a long time to disappear, and may behave as if it were a fixed charge. Therefore, a transistor including a metal oxide with a high trap state density in a channel formation region may have unstable electrical characteristics.

Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the metal oxide. In order to reduce the impurity concentration in the metal oxide, it is preferable to reduce the impurity concentration in the adjacent film. Impurities include hydrogen, nitrogen, alkali metal, alkaline earth metal, iron, nickel, silicon, and the like.

[impurities]
Here, the influence of each impurity in the metal oxide will be described.

In the metal oxide, when silicon or carbon, which is one of Group 14 elements, is included, a defect level is formed in the metal oxide. Therefore, the concentration of silicon and carbon in the metal oxide and the concentration of silicon and carbon in the vicinity of the interface with the metal oxide (concentration obtained by secondary ion mass spectrometry (SIMS)) are 2 × 10 ¹⁸ atoms / cm ³ or less, preferably 2 × 10 ¹⁷ atoms / cm ³ or less.

In addition, when the metal oxide contains an alkali metal or an alkaline earth metal, a defect level is formed and carriers may be generated. Therefore, a transistor in which a metal oxide containing an alkali metal or an alkaline earth metal is used for a channel formation region is likely to be normally on. Therefore, it is preferable to reduce the concentration of alkali metal or alkaline earth metal in the metal oxide. Specifically, the concentration of the alkali metal or alkaline earth metal in the metal oxide obtained by SIMS is set to 1 × 10 ¹⁸ atoms / cm ³ or less, preferably 2 × 10 ¹⁶ atoms / cm ³ or less.

In addition, when nitrogen is included in the metal oxide, electrons as carriers are generated, the carrier density is increased, and the n-type is easily obtained. As a result, a transistor in which a metal oxide containing nitrogen is used for a channel formation region is likely to be normally on. Therefore, in the metal oxide, nitrogen in the channel formation region is preferably reduced as much as possible. For example, the nitrogen concentration in the metal oxide is less than 5 × 10 ¹⁹ atoms / cm ³ , preferably 5 × 10 ¹⁸ atoms / cm ³ or less, more preferably 1 × 10 ¹⁸ atoms / cm ³ or less in SIMS, Preferably, it is 5 × 10 ¹⁷ atoms / cm ³ or less.

In addition, hydrogen contained in the metal oxide reacts with oxygen bonded to the metal atom to become water, so that oxygen vacancies may be formed. When hydrogen enters the oxygen vacancies, electrons serving as carriers may be generated. In addition, a part of hydrogen may be combined with oxygen bonded to a metal atom to generate electrons as carriers. Therefore, a transistor in which a metal oxide containing hydrogen is used for a channel formation region is likely to be normally on. For this reason, it is preferable that hydrogen in the metal oxide is reduced as much as possible. Specifically, in the metal oxide, the hydrogen concentration obtained by SIMS is less than 1 × 10 ²⁰ atoms / cm ³ , preferably less than 1 × 10 ¹⁹ atoms / cm ³ , more preferably 5 × 10 ¹⁸ atoms / cm 3. Less than ³ , more preferably less than 1 × 10 ¹⁸ atoms / cm ³ .

By using a metal oxide in which impurities are sufficiently reduced for a channel formation region of a transistor, stable electric characteristics can be imparted.

<Deposition method>
An insulating material for forming an insulating layer, a conductive material for forming an electrode, or a semiconductor material for forming a semiconductor layer can be formed by a sputtering method, a spin coating method, a CVD (Chemical Vapor Deposition) method (thermal CVD). Method, MOCVD (Metal Organic Chemical Deposition) method, PECVD (Plasma Enhanced CVD) method, high density plasma CVD (CVD) method, LPCVD (low pressure CVD) method, APCVD (low pressure CVD) method, APCVD ), ALD (Atomic Layer Deposition) method, or MBE (Molecular Beam Epitaxy) ) Method, or a PLD (Pulsed Laser Deposition) method, a dipping method, a spray coating method, a droplet discharge method (such as an inkjet method), or a printing method (such as screen printing or offset printing).

In the plasma CVD method, a high-quality film can be obtained at a relatively low temperature. When a film formation method that does not use plasma at the time of film formation, such as an MOCVD method, an ALD method, or a thermal CVD method, damage to the formation surface is unlikely to occur. For example, a wiring, an electrode, an element (a transistor, a capacitor, or the like) included in the memory device may be charged up by receiving an electric charge from plasma. At this time, a wiring, an electrode, an element, or the like included in the memory device may be destroyed by the accumulated charge. On the other hand, in the case of a film formation method that does not use plasma, such plasma damage does not occur, so that the yield of the memory device can be increased. In addition, since plasma damage during film formation does not occur, a film with few defects can be obtained.

The CVD method and the ALD method are film forming methods in which a film is formed by a reaction on the surface of an object to be processed, unlike a film forming method in which particles emitted from a target or the like are deposited. Therefore, it is a film forming method that is not easily affected by the shape of the object to be processed and has good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, and thus is suitable for covering the surface of an opening having a high aspect ratio. However, since the ALD method has a relatively low film formation rate, it may be preferable to use it in combination with another film formation method such as a CVD method with a high film formation rate.

In the CVD method and the ALD method, the composition of the obtained film can be controlled by the flow rate ratio of the source gases. For example, in the CVD method and the ALD method, a film having an arbitrary composition can be formed depending on the flow rate ratio of the source gases. Further, for example, in the CVD method and the ALD method, a film whose composition is continuously changed can be formed by changing the flow rate ratio of the source gas while forming the film. When film formation is performed while changing the flow rate ratio of the source gas, the time required for film formation can be shortened by the time required for conveyance and pressure adjustment compared to the case where film formation is performed using a plurality of film formation chambers. it can. Therefore, the productivity of the storage device may be increased.

Note that when a film is formed by the ALD method, it is preferable to use a gas containing no chlorine as a material gas.

This embodiment can be implemented in appropriate combination with the structures described in the other embodiments.

(Embodiment 3)
In this embodiment, structural examples of transistors that can be used for the memory device and the like described in the above embodiments are described.

<Structure Example 1 of Transistor>
A structural example of the transistor 510A is described with reference to FIGS. 11A, 11B, and 11C. FIG. 11A is a top view of the transistor 510A. FIG. 11B is a cross-sectional view taken along dashed-dotted line L1-L2 in FIG. FIG. 11C is a cross-sectional view illustrating a portion indicated by dashed-dotted line W1-W2 in FIG. Note that in the top view of FIG. 11A, some elements are omitted for clarity.

11A, 11B, and 11C, the transistor 510A, the insulating layer 511 functioning as an interlayer film, the insulating layer 512, the insulating layer 514, the insulating layer 516, the insulating layer 580, the insulating layer 582, and the insulating layer Layer 584 is shown. In addition, a conductive layer 546 (a conductive layer 546a and a conductive layer 546b) that is electrically connected to the transistor 510A and functions as a contact plug, and a conductive layer 503 that functions as a wiring are illustrated.

The transistor 510A includes a conductive layer 560 (a conductive layer 560a and a conductive layer 560b) that functions as a first gate electrode, a conductive layer 505 (a conductive layer 505a and a conductive layer 505b) that functions as a second gate electrode, An insulating layer 550 functioning as a first gate insulating film, an insulating layer 521 functioning as a second gate insulating layer, an insulating layer 522, an insulating layer 524, and an oxide 530 having a region where a channel is formed (oxide) 530a, an oxide 530b, and an oxide 530c), a conductive layer 542a functioning as one of a source and a drain, a conductive layer 542b functioning as the other of a source and a drain, and an insulating layer 574.

In the transistor 510A illustrated in FIG. 11, the oxide 530c, the insulating layer 550, and the conductive layer 560 are provided in the opening provided in the insulating layer 580 with the insulating layer 574 interposed therebetween. The oxide 530c, the insulating layer 550, and the conductive layer 560 are provided between the conductive layer 542a and the conductive layer 542b.

The insulating layer 511 and the insulating layer 512 function as interlayer films.

As the interlayer film, silicon oxide, silicon oxynitride, silicon nitride oxide, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO ₃ ) or (Ba, Sr) An insulating layer such as TiO ₃ (BST) can be used as a single layer or a stacked layer. Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulating layers. Alternatively, these insulating layers may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be stacked over the insulating layer.

For example, the insulating layer 511 preferably functions as a barrier film that prevents impurities such as water or hydrogen from entering the transistor 510A from the substrate side. Therefore, the insulating layer 511 is preferably formed using an insulating material having a function of suppressing diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms (the impurities are difficult to permeate). Alternatively, it is preferable to use an insulating material having a function of suppressing diffusion of at least one of oxygen (for example, oxygen atoms and oxygen molecules) (the oxygen is difficult to transmit). For example, aluminum oxide, silicon nitride, or the like may be used for the insulating layer 511. With this structure, diffusion of impurities such as hydrogen and water from the substrate side to the transistor 510A side than the insulating layer 511 can be suppressed.

For example, the insulating layer 512 preferably has a lower dielectric constant than the insulating layer 511. By using a material having a low dielectric constant as the interlayer film, parasitic capacitance generated between the wirings can be reduced.

The conductive layer 503 is formed so as to be embedded in the insulating layer 512. Here, the height of the upper surface of the conductive layer 503 and the height of the upper surface of the insulating layer 512 can be approximately the same. Note that although the conductive layer 503 has a single layer structure, the present invention is not limited to this. For example, the conductive layer 503 may have a multilayer structure including two or more layers. Note that the conductive layer 503 is preferably formed using a highly conductive material whose main component is tungsten, copper, or aluminum.

In the transistor 510A, the conductive layer 560 may function as a first gate (also referred to as a top gate) electrode. The conductive layer 505 may function as a second gate (also referred to as a bottom gate) electrode. In that case, the threshold voltage of the transistor 510A can be controlled by changing the potential applied to the conductive layer 505 independently without being linked to the potential applied to the conductive layer 560. In particular, by applying a negative potential to the conductive layer 505, the threshold voltage of the transistor 510A can be made higher than 0 V and the off-state current can be reduced. Therefore, when a negative potential is applied to the conductive layer 505, the drain current when the potential applied to the conductive layer 560 is 0 V can be made smaller than when a negative potential is not applied.

For example, when the conductive layer 505 and the conductive layer 560 are provided so as to overlap with each other, an electric field generated from the conductive layer 560 and an electric field generated from the conductive layer 505 when a potential is applied to the conductive layer 560 and the conductive layer 505. And the channel formation region formed in the oxide 530 can be covered.

That is, the channel formation region can be electrically surrounded by the electric field of the conductive layer 560 functioning as the first gate electrode and the electric field of the conductive layer 505 functioning as the second gate electrode. In this specification, a transistor structure in which a channel formation region is electrically surrounded by an electric field of the first gate electrode and the second gate electrode is referred to as a surrounded channel (S-channel) structure.

The insulating layer 514 and the insulating layer 516 function as interlayer films similarly to the insulating layer 511 or the insulating layer 512. For example, the insulating layer 514 preferably functions as a barrier film that prevents impurities such as water or hydrogen from entering the transistor 510A from the substrate side. With this structure, impurities such as hydrogen and water can be prevented from diffusing from the substrate side to the transistor 510A side with respect to the insulating layer 514. For example, the insulating layer 516 preferably has a lower dielectric constant than the insulating layer 514. By using a material having a low dielectric constant as an interlayer film, parasitic capacitance generated between wirings can be reduced.

In the conductive layer 505 functioning as the second gate, a conductive layer 505a is formed in contact with the inner walls of the openings of the insulating layer 514 and the insulating layer 516, and a conductive layer 505b is further formed inside. Here, the heights of the upper surfaces of the conductive layers 505a and 505b and the height of the upper surface of the insulating layer 516 can be approximately the same. Note that although the transistor 510A shows a structure in which the conductive layer 505a and the conductive layer 505b are stacked, the present invention is not limited to this. For example, the conductive layer 505 may be provided as a single layer or a stacked structure including three or more layers.

Here, the conductive layer 505a is preferably formed using a conductive material that has a function of suppressing diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms (the impurities are difficult to pass through). Alternatively, it is preferable to use a conductive material having a function of suppressing diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules) (the oxygen hardly transmits). Note that in this specification, the function of suppressing diffusion of impurities or oxygen is a function of suppressing diffusion of any one or all of the impurities and oxygen.

For example, when the conductive layer 505a has a function of suppressing diffusion of oxygen, the conductive layer 505b can be prevented from being oxidized to decrease the conductivity.

In the case where the conductive layer 505 also functions as a wiring, the conductive layer 505b is preferably formed using a highly conductive conductive material containing tungsten, copper, or aluminum as a main component. In that case, the conductive layer 503 is not necessarily provided. Note that although the conductive layer 505b is illustrated as a single layer, it may have a stacked structure, for example, a stack of titanium, titanium nitride, and the above conductive material.

The insulating layer 521, the insulating layer 522, and the insulating layer 524 have a function as a second gate insulating layer.

The insulating layer 522 preferably has a barrier property. Since the insulating layer 522 has barrier properties, the insulating layer 522 functions as a layer that suppresses entry of impurities such as hydrogen from the peripheral portion of the transistor 510A to the transistor 510A.

The insulating layer 522 includes, for example, aluminum oxide, hafnium oxide, aluminum and an oxide containing hafnium (hafnium aluminate), tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO ₃ ), or ( An insulating layer containing a so-called high-k material such as Ba, Sr) TiO ₃ (BST) is preferably used as a single layer or a stacked layer. As transistor miniaturization and higher integration progress, problems such as leakage current may occur due to a thinner gate insulating layer. By using a high-k material for the insulating layer functioning as the gate insulating layer, the gate potential during transistor operation can be reduced while maintaining the physical film thickness.

For example, the insulating layer 521 is preferably thermally stable. For example, since silicon oxide and silicon oxynitride are thermally stable, a stacked structure having a high thermal stability and a high relative dielectric constant can be obtained by combining an insulating layer of a high-k material and the insulating layer 522. Can do.

Note that although FIG. 11 illustrates a three-layer structure as the second gate insulating layer, a single layer or a stacked structure of two or more layers may be used. In that case, the present invention is not limited to a laminated structure made of the same material, and may be a laminated structure made of different materials.

The oxide 530 having a region functioning as a channel formation region includes an oxide 530a, an oxide 530b over the oxide 530a, and an oxide 530c over the oxide 530b. By including the oxide 530a below the oxide 530b, diffusion of impurities from the structure formed below the oxide 530a to the oxide 530b can be suppressed. In addition, by including the oxide 530c over the oxide 530b, diffusion of impurities from the structure formed above the oxide 530c to the oxide 530b can be suppressed. As the oxide 530, an oxide semiconductor that is one of the metal oxides described in the above embodiments can be used.

Note that the oxide 530 c is preferably provided in the opening provided in the insulating layer 580 with the insulating layer 574 interposed therebetween. When the insulating layer 574 has barrier properties, diffusion of impurities from the insulating layer 580 into the oxide 530 can be suppressed.

One of the conductive layers 542 functions as a source electrode and the other functions as a drain electrode.

The conductive layer 542a and the conductive layer 542b can be formed using a metal such as aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum, or tungsten, or an alloy containing the metal as a main component. . In particular, a metal nitride film such as tantalum nitride is preferable because it has a barrier property against hydrogen or oxygen and has high oxidation resistance.

Further, although a single layer structure is shown in FIG. 11, a stacked structure of two or more layers may be used. For example, a tantalum nitride film and a tungsten film are preferably stacked. Further, a titanium film and an aluminum film may be stacked. Also, a two-layer structure in which an aluminum film is stacked on a tungsten film, a two-layer structure in which a copper film is stacked on a copper-magnesium-aluminum alloy film, a two-layer structure in which a copper film is stacked on a titanium film, and a tungsten film A two-layer structure in which copper films are stacked may be used.

In addition, a titanium film or a titanium nitride film and a three-layer structure in which an aluminum film or a copper film is laminated on the titanium film or the titanium nitride film, and a titanium film or a titanium nitride film is further formed thereon, a molybdenum film or There is a three-layer structure in which a molybdenum nitride film and an aluminum film or a copper film are stacked over the molybdenum film or the molybdenum nitride film and a molybdenum film or a molybdenum nitride film is further formed thereon. Note that a transparent conductive material containing indium oxide, tin oxide, or zinc oxide may be used.

Further, a barrier layer may be provided over the conductive layer 542. The barrier layer is preferably formed using a substance having a barrier property against oxygen or hydrogen. With this structure, oxidation of the conductive layer 542 can be suppressed when the insulating layer 574 is formed.

For the barrier layer, for example, a metal oxide can be used. In particular, an insulating film having a barrier property against oxygen and hydrogen, such as aluminum oxide, hafnium oxide, and gallium oxide, is preferably used. Alternatively, silicon nitride formed by a CVD method may be used.

By including the barrier layer, the material selection range of the conductive layer 542 can be widened. For example, the conductive layer 542 can be formed using a material that has low oxidation resistance but high conductivity, such as tungsten or aluminum. For example, a conductor that can be easily formed or processed can be used.

The insulating layer 550 functions as a first gate insulating layer. The insulating layer 550 is preferably provided in the opening provided in the insulating layer 580 with the oxide 530c and the insulating layer 574 interposed therebetween.

As transistor miniaturization and higher integration progress, problems such as leakage current may occur due to a thinner gate insulating layer. In that case, the insulating layer 550 may have a stacked structure, like the second gate insulating layer. The insulating layer that functions as a gate insulating layer has a stacked structure of a high-k material and a thermally stable material, so that the gate potential during transistor operation can be reduced while maintaining the physical film thickness. It becomes. Moreover, it can be set as the laminated structure which is thermally stable and a high dielectric constant.

The conductive layer 560 functioning as the first gate electrode includes a conductive layer 560a and a conductive layer 560b over the conductive layer 560a. As in the conductive layer 505a, the conductive layer 560a is preferably formed using a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms. Alternatively, it is preferable to use a conductive material having a function of suppressing diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules).

When the conductive layer 560a has a function of suppressing diffusion of oxygen, the material selectivity of the conductive layer 560b can be improved. That is, by including the conductive layer 560a, oxidation of the conductive layer 560b can be suppressed and the conductivity can be prevented from decreasing.

As a conductive material having a function of suppressing oxygen diffusion, for example, tantalum, tantalum nitride, ruthenium, or ruthenium oxide is preferably used. For the conductive layer 560a, an oxide semiconductor that can be used as the oxide 530 can be used. In that case, by forming the conductive layer 560b by a sputtering method, the electrical resistance value of the conductive layer 560a can be reduced to obtain a conductor. This can be called an OC (Oxide Conductor) electrode.

The conductive layer 560b is preferably formed using a conductive material containing tungsten, copper, or aluminum as a main component. In addition, since the conductive layer 560 functions as a wiring, a highly conductive conductor is preferably used. For example, a conductive material containing tungsten, copper, or aluminum as a main component can be used. The conductive layer 560b may have a stacked structure, for example, a stack of titanium, titanium nitride, and the above conductive material.

An insulating layer 574 is provided between the insulating layer 580 and the transistor 510A. The insulating layer 574 may be formed using an insulating material having a function of suppressing diffusion of impurities such as water or hydrogen and oxygen. For example, aluminum oxide or hafnium oxide is preferably used. In addition, for example, metal oxide such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, or tantalum oxide, silicon nitride oxide, silicon nitride, or the like can be used.

By including the insulating layer 574, diffusion of water and impurities such as hydrogen included in the insulating layer 580 into the oxide 530b through the oxide 530c and the insulating layer 550 can be suppressed. Further, oxidation of the conductive layer 560 due to excess oxygen included in the insulating layer 580 can be suppressed.

The insulating layer 580, the insulating layer 582, and the insulating layer 584 function as interlayer films.

As in the insulating layer 514, the insulating layer 582 preferably functions as a barrier insulating film which suppresses entry of impurities such as water or hydrogen into the transistor 510A from the outside.

In addition, by using an insulating material with a resistivity of 1 × 10 ¹⁰ or more and 1 × 10 ¹⁵ Ωcm or less for the insulating layer 582, plasma damage caused during film formation or etching can be reduced. For example, silicon nitride having a resistivity of 1 × 10 ¹⁴ Ωcm or less, preferably 1 × 10 ¹³ Ωcm or less may be used for the insulating layer 582. Note that an insulating material having a resistivity of greater than or equal to 1 × 10 ^{10 and} less than or equal to 1 × 10 ¹⁵ Ωcm may be used for another insulating layer, not limited to the insulating layer 582. For example, silicon nitride having a resistivity of 1 × 10 ¹⁴ Ωcm or less, preferably 1 × 10 ¹³ Ωcm or less may be used for the insulating layer 584, the insulating layer 580, the insulating layer 524, and / or the insulating layer 516.

The insulating layer 580 and the insulating layer 584 preferably have a dielectric constant lower than that of the insulating layer 582, similarly to the insulating layer 516. By using a material having a low dielectric constant as the interlayer film, parasitic capacitance generated between the wirings can be reduced.

The transistor 510A may be electrically connected to another structure through a plug or a wiring such as the insulating layer 580, the insulating layer 582, and the conductive layer 546 embedded in the insulating layer 584.

As the material for the conductive layer 546, a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material can be used as a single layer or a stack, as in the case of the conductive layer 505. . For example, it is preferable to use a high melting point material such as tungsten or molybdenum that has both heat resistance and conductivity. Alternatively, it is preferably formed using a low-resistance conductive material such as aluminum or copper. Wiring resistance can be lowered by using a low-resistance conductive material.

For example, as the conductive layer 546, for example, by using a stacked structure of tantalum nitride which is a conductor having a barrier property against hydrogen and oxygen and tungsten having high conductivity, conductivity as a wiring is increased. While being held, diffusion of impurities from outside can be suppressed.

With the above structure, a semiconductor device including a transistor including an oxide semiconductor with high on-state current can be provided. Alternatively, a semiconductor device including a transistor including an oxide semiconductor with low off-state current can be provided. Alternatively, it is possible to provide a semiconductor device that suppresses fluctuations in electrical characteristics, has stable electrical characteristics, and has improved reliability.

<Structural Example 2 of Transistor>
A structural example of the transistor 510B will be described with reference to FIGS. 12A, 12B, and 12C. FIG. 12A is a top view of the transistor 510B. FIG. 12B is a cross-sectional view taken along dashed-dotted line L1-L2 in FIG. FIG. 12C is a cross-sectional view taken along dashed-dotted line W1-W2 in FIG. Note that in the top view of FIG. 12A, some elements are omitted for clarity.

A transistor 510B is a modification of the transistor. Therefore, in order to prevent the description from being repeated, differences from the above transistor will be mainly described.

12A to 12C, the conductive layer 542 (the conductive layer 542a and the conductive layer 542b) is not provided, and the region 531a and the region 531b are included in part of the exposed oxide 530b surface. One of the region 531a and the region 531b functions as a source region, and the other functions as a drain region. The insulating layer 573 is provided between the oxide 530b and the insulating layer 574.

A region 531 (a region 531a and a region 531b) illustrated in FIG. 12 is a region where the above element is added to the oxide 530b. The region 531 can be formed by using, for example, a dummy gate.

Specifically, a dummy gate may be provided over the oxide 530b, and the dummy gate may be used as a mask, and an element for reducing the resistance of the oxide 530b may be added. In other words, the element is added to a region where the oxide 530 does not overlap with the dummy gate, so that the region 531 is formed. In addition, as an addition method of the element, an ion implantation method in which an ionized source gas is added by mass separation, an ion doping method in which an ionized source gas is added without mass separation, a plasma immersion ion implantation method, or the like Can be used.

Note that typically, boron or phosphorus is given as an element for reducing the resistance of the oxide 530. Further, hydrogen, carbon, nitrogen, fluorine, sulfur, chlorine, titanium, rare gas, or the like may be used. Typical examples of the rare gas element include helium, neon, argon, krypton, and xenon. The concentration of the element may be measured using secondary ion mass spectrometry (SIMS) or the like.

In particular, boron and phosphorus are preferable because an amorphous silicon or low-temperature polysilicon production line apparatus can be used. Existing equipment can be diverted, and capital investment can be suppressed.

Subsequently, an insulating film to be the insulating layer 573 and an insulating film to be the insulating layer 574 may be formed over the oxide 530b and the dummy gate. By stacking the insulating film to be the insulating layer 573 and the insulating layer 574, a region where the region 531 overlaps with the oxide 530c and the insulating layer 550 can be provided.

Specifically, after an insulating film to be the insulating layer 580 is provided over the insulating film to be the insulating layer 574, a CMP (Chemical Mechanical Polishing) process is performed on the insulating film to be the insulating layer 580, whereby A part of the insulating film is removed to expose the dummy gate. Subsequently, when the dummy gate is removed, part of the insulating layer 573 in contact with the dummy gate may be removed. Therefore, the insulating layer 574 and the good insulating layer 573 are exposed on the side surface of the opening provided in the insulating layer 580, and a part of the region 531 provided in the oxide 530b is formed on the bottom surface of the opening. Exposed. Next, after an oxide film to be the oxide 530c, an insulating film to be the insulating layer 550, and a conductive film to be the conductive layer 560 are sequentially formed in the opening, CMP treatment or the like is performed until the insulating layer 580 is exposed. The transistor illustrated in FIG. 12 can be formed by removing part of the oxide film to be the oxide 530c, the insulating film to be the insulating layer 550, and the conductive film to be the conductive layer 560.

Note that the insulating layer 573 and the insulating layer 574 are not essential components. What is necessary is just to design suitably according to the transistor characteristic to request | require.

In the transistor illustrated in FIGS. 12A and 12B, an existing device can be diverted and the conductive layer 542 is not provided, so that cost can be reduced.

<Structure Example 3 of Transistor>
A structural example of the transistor 510C is described with reference to FIGS. 13A, 13B, and 13C. FIG. 13A is a top view of the transistor 510C. FIG. 13B is a cross-sectional view taken along dashed-dotted line L1-L2 in FIG. FIG. 13C is a cross-sectional view taken along dashed-dotted line W1-W2 in FIG. Note that in the top view of FIG. 13A, some elements are omitted for clarity.

The transistor 510C is a modification of the above transistor. Therefore, in order to prevent repetition of description, points different from the transistor 510A are mainly described.

The transistor 510C includes a region where the conductive layer 542 (the conductive layer 542a and the conductive layer 542b) overlaps with the oxide 530c, the insulating layer 550, the oxide 551, and the conductive layer 560. With such a structure, a transistor with high on-state current can be provided. In addition, a transistor with high controllability can be provided.

The conductive layer 560 functioning as the first gate electrode includes a conductive layer 560a and a conductive layer 560b over the conductive layer 560a. As in the conductive layer 505a, the conductive layer 560a is preferably formed using a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms. Alternatively, it is preferable to use a conductive material having a function of suppressing diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules).

When the conductive layer 560a has a function of suppressing diffusion of oxygen, the material selectivity of the conductive layer 560b can be improved. That is, by including the conductive layer 560a, oxidation of the conductive layer 560b can be suppressed and the conductivity can be prevented from decreasing.

In addition, in order to adjust Vth of the transistor, a material used for the conductive layer 560a may be determined in consideration of a work function. For example, the conductive layer 560a may be formed using titanium nitride and the conductive layer 560b may be formed using tungsten. The conductive layer 560a and the conductive layer 560b may be formed by a known film formation method such as a sputtering method, a CVD method, or an AFM method. Note that the film formation temperature when titanium nitride is formed by a CVD method is preferably 380 ° C. or higher and 500 ° C. or lower, and more preferably 400 ° C. or higher and 450 ° C. or lower.

The oxide 551 may be formed using a material similar to that of other insulating layers. As the oxide 551, an In-M-Zn oxide containing excess oxygen (the element M is aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, or the like) A metal oxide such as one or more selected from cerium, neodymium, hafnium, tantalum, tungsten, magnesium, or the like may be used. For example, an In—Ga—Zn oxide film is formed as the oxide 551 by a sputtering method. Specifically, for example, the film is formed using a sputtering gas containing oxygen using a target having an atomic ratio of In: Ga: Zn = 1: 3: 4. When the oxide 551 is formed by a sputtering method, the flow rate ratio of oxygen contained in the sputtering gas is preferably 70% or more, more preferably 80% or more, and more preferably 100%.

By using a gas containing oxygen as a sputtering gas, oxygen can be supplied not only to the oxide 551 but also to the insulating layer 550 which is a formation surface of the oxide 551. In addition, the amount of oxygen supplied to the insulating layer 550 can be increased by increasing the flow ratio of oxygen contained in the sputtering gas.

Further, when the oxide 551 is provided over the insulating layer 550, excess oxygen contained in the insulating layer 550 is hardly diffused into the conductive layer 560. Thus, the reliability of the transistor can be increased. Note that the oxide 551 may be omitted depending on purposes.

The insulating layer 574 is preferably provided so as to cover the top surface and side surfaces of the conductive layer 560, the side surfaces of the insulating layer 550, and the side surfaces of the oxide 530c. Note that the insulating layer 574 is preferably formed using an insulating material having a function of suppressing diffusion of impurities such as water or hydrogen and oxygen. For example, aluminum oxide or hafnium oxide is preferably used. In addition, for example, a metal oxide such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, or tantalum oxide, silicon nitride oxide, silicon nitride, or the like can be used.

By providing the insulating layer 574, oxidation of the conductive layer 560 can be suppressed. In addition, with the insulating layer 574, diffusion of water and impurities such as hydrogen included in the insulating layer 580 into the transistor 510C can be suppressed.

Further, an insulating layer 576 having a barrier property (the insulating layer 576a and the insulating layer 576b) may be provided between the conductive layer 546 and the insulating layer 580. By providing the insulating layer 576, it can be suppressed that oxygen in the insulating layer 580 reacts with the conductive layer 546 and the conductive layer 546 is oxidized.

In addition, by providing the insulating layer 576 having a barrier property, the range of selection of materials for conductors used for plugs and wirings can be increased. For example, the conductive layer 546 can be formed using a metal material that absorbs oxygen but has high conductivity.

<Structural Example 4 of Transistor>
A structural example of the transistor 510D will be described with reference to FIGS. 14A, 14B, and 14C. FIG. 14A is a top view of the transistor 510D. FIG. 14B is a cross-sectional view taken along dashed-dotted line L1-L2 in FIG. FIG. 14C is a cross-sectional view taken along dashed-dotted line W1-W2 in FIG. Note that in the top view of FIG. 14A, some elements are omitted for clarity.

A transistor 510D is a modification of the transistor. Therefore, in order to prevent repetition of description, points different from the transistor 510A are mainly described.

In the transistor 510D illustrated in FIG. 14, a conductive layer 547a is provided between the conductive layer 542a and the oxide 530b, and a conductive layer 547b is provided between the conductive layer 542b and the oxide 530b. Here, the conductive layer 542a (conductive layer 542b) extends beyond the upper surface of the conductive layer 547a (conductive layer 547b) and the side surface on the conductive layer 560 side, and has a region in contact with the upper surface of the oxide 530b. Here, the conductive layer 547 may be formed using a conductor that can be used for the conductive layer 542. Further, the conductive layer 547 is preferably at least thicker than the conductive layer 542.

The transistor 510D illustrated in FIG. 14 has the above structure; thus, the conductive layer 542 can be closer to the conductive layer 560 than the transistor 510A. Alternatively, the conductive layer 560 can overlap with the end portion of the conductive layer 542a and the end portion of the conductive layer 542b. Thus, the substantial channel length of the transistor 510D can be shortened, and the on-state current and frequency characteristics can be improved.

The conductive layer 547a (the conductive layer 547b) is preferably provided so as to overlap with the conductive layer 542a (the conductive layer 542b). With such a structure, in etching for forming an opening for embedding the conductive layer 546a (conductive layer 546b), the conductive layer 547a (conductive layer 547b) functions as a stopper, and the oxide 530b is over-etched. Can be prevented.

14 may have a structure in which the insulating layer 565 is provided in contact with the insulating layer 544. The insulating layer 544 preferably functions as a barrier insulating film which suppresses entry of impurities such as water or hydrogen and excess oxygen into the transistor 510D from the insulating layer 580 side. As the insulating layer 565, an insulating layer that can be used for the insulating layer 544 can be used. The insulating layer 544 may be formed using a nitride insulating material such as aluminum nitride, aluminum titanium nitride, titanium nitride, silicon nitride, or silicon nitride oxide, for example.

14 is different from the transistor 510A in FIG. 11 in that the conductive layer 505 may be provided with a single-layer structure. In this case, an insulating film to be the insulating layer 516 is formed over the patterned conductive layer 505, and the upper portion of the insulating film is removed by a CMP method or the like until the upper surface of the conductive layer 505 is exposed. Good. Here, the flatness of the upper surface of the conductive layer 505 is preferably improved. For example, the average surface roughness (Ra) of the upper surface of the conductive layer 505 may be 1 nm or less, preferably 0.5 nm or less, more preferably 0.3 nm or less. Accordingly, the flatness of the insulating layer formed over the conductive layer 505 can be improved, and the crystallinity of the oxide 530b and the oxide 530c can be improved.

<Structure Example 5 of Transistor>
A structural example of the transistor 510E is described with reference to FIGS. 15A, 15B, and 15C. FIG. 15A is a top view of the transistor 510E. FIG. 15B is a cross-sectional view taken along dashed-dotted line L1-L2 in FIG. FIG. 15C is a cross-sectional view taken along dashed-dotted line W1-W2 in FIG. Note that in the top view of FIG. 15A, some elements are omitted for clarity.

The transistor 510E is a modified example of the transistor. Therefore, in order to prevent the description from being repeated, differences from the above transistor will be mainly described.

In FIGS. 15A to 15C, the conductive layer 503 having a function as a second gate is also provided as a wiring without providing the conductive layer 503. The insulating layer 550 is provided over the oxide 530c, and the metal oxide 552 is provided over the insulating layer 550. In addition, the conductive layer 560 is provided over the metal oxide 552 and the insulating layer 570 is provided over the conductive layer 560. In addition, the insulating layer 571 is provided over the insulating layer 570.

The metal oxide 552 preferably has a function of suppressing oxygen diffusion. By providing the metal oxide 552 which suppresses diffusion of oxygen between the insulating layer 550 and the conductive layer 560, diffusion of oxygen into the conductive layer 560 is suppressed. That is, a decrease in the amount of oxygen supplied to the oxide 530 can be suppressed. Further, oxidation of the conductive layer 560 due to oxygen can be suppressed.

Note that the metal oxide 552 may function as part of the first gate. For example, an oxide semiconductor that can be used as the oxide 530 can be used as the metal oxide 552. In that case, the conductive layer 560 can be formed by a sputtering method, whereby the electric resistance value of the metal oxide 552 can be reduced to form a conductive layer. This can be called an OC (Oxide Conductor) electrode.

In addition, the metal oxide 552 may function as a part of the gate insulating layer. Therefore, when silicon oxide, silicon oxynitride, or the like is used for the insulating layer 550, the metal oxide 552 is preferably a metal oxide that is a high-k material with a high relative dielectric constant. By setting it as the said laminated structure, it can be set as the laminated structure stable with respect to a heat | fever, and a high dielectric constant. Therefore, it is possible to reduce the gate potential applied during transistor operation while maintaining the physical film thickness. In addition, the equivalent oxide thickness (EOT) of the insulating layer functioning as the gate insulating layer can be reduced.

Although the metal oxide 552 is shown as a single layer in the transistor 510E, a stacked structure of two or more layers may be used. For example, a metal oxide that functions as part of the gate electrode and a metal oxide that functions as part of the gate insulating layer may be stacked.

In the case where the metal oxide 552 serves as the gate electrode, the on-state current of the transistor 510E can be improved without weakening the influence of the electric field from the conductive layer 560. Alternatively, in the case of functioning as a gate insulating layer, the distance between the conductive layer 560 and the oxide 530 is maintained depending on the physical thickness of the insulating layer 550 and the metal oxide 552, so that the conductive layer 560 Leakage current with the oxide 530 can be suppressed. Therefore, by providing a stacked structure of the insulating layer 550 and the metal oxide 552, the physical distance between the conductive layer 560 and the oxide 530 and the electric field strength applied from the conductive layer 560 to the oxide 530 can be reduced. It can be easily adjusted as appropriate.

Specifically, the metal oxide 552 can be used as the metal oxide 552 by reducing the resistance of an oxide semiconductor that can be used for the oxide 530. Alternatively, a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, and the like can be used.

In particular, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), which is an insulating layer containing one or both of aluminum and hafnium. In particular, hafnium aluminate has higher heat resistance than a hafnium oxide film. Therefore, it is preferable because it is difficult to crystallize in a heat history in a later process. Note that the metal oxide 552 is not an essential component. What is necessary is just to design suitably according to the transistor characteristic to request | require.

The insulating layer 570 may be formed using an insulating material having a function of suppressing permeation of impurities such as water or hydrogen and oxygen. For example, aluminum oxide or hafnium oxide is preferably used. Thus, oxidation of the conductive layer 560 with oxygen from above the insulating layer 570 can be suppressed. In addition, impurities such as water or hydrogen from above the insulating layer 570 can be prevented from entering the oxide 230 through the conductive layer 560 and the insulating layer 550.

The insulating layer 571 functions as a hard mask. By providing the insulating layer 571, when processing the conductive layer 560, the side surface of the conductive layer 560 is substantially vertical. Specifically, the angle formed between the side surface of the conductive layer 560 and the substrate surface is 75 ° to 100 °, Preferably, it can be set to 80 degrees or more and 95 degrees or less.

Note that the insulating layer 571 may also serve as a barrier layer by using an insulating material having a function of suppressing transmission of impurities such as water or hydrogen and oxygen. In that case, the insulating layer 570 is not necessarily provided.

By selectively removing part of the insulating layer 570, the conductive layer 560, the metal oxide 552, the insulating layer 550, and the oxide 530c using the insulating layer 571 as a hard mask, the side surfaces thereof are substantially matched. In addition, a part of the surface of the oxide 530b can be exposed.

The transistor 510E includes a region 531a and a region 531b in part of the exposed surface of the oxide 530b. One of the region 531a and the region 531b functions as a source region, and the other functions as a drain region.

The formation of the region 531a and the region 531b is performed by introducing an impurity element such as phosphorus or boron into the exposed oxide 530b surface by using, for example, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, or a plasma treatment. This can be achieved. Note that the “impurity element” in this embodiment and the like refers to an element other than the main component elements.

In addition, a metal film is formed after part of the surface of the oxide 530b is exposed, and then heat treatment is performed, whereby elements contained in the metal film are diffused into the oxide 530b, so that the regions 531a and 531b are formed. You can also

In the region where the impurity element of the oxide 530b is introduced, the electrical resistivity decreases. For this reason, the region 531a and the region 531b may be referred to as “impurity region” or “low resistance region”.

By using the insulating layer 571 and / or the conductive layer 560 as a mask, the region 531a and the region 531b can be formed in a self-alignment manner. Accordingly, the region 531a and / or the region 531b and the conductive layer 560 do not overlap with each other, so that parasitic capacitance can be reduced. Further, no offset region is formed between the channel formation region and the source / drain region (the region 531a or the region 531b). By forming the region 531a and the region 531b in a self-aligned manner, an increase in on-state current, a reduction in threshold voltage, an improvement in operating frequency, and the like can be realized.

Note that an offset region may be provided between the channel formation region and the source / drain region in order to further reduce the off-state current. The offset region is a region having a high electrical resistivity and is a region where the impurity element is not introduced. The offset region can be formed by introducing the impurity element described above after the insulating layer 575 is formed. In this case, the insulating layer 575 also functions as a mask similarly to the insulating layer 571 and the like. Therefore, the impurity element is not introduced into the region of the oxide 530b overlapping with the insulating layer 575, and the electrical resistivity of the region can be kept high.

The transistor 510E includes the insulating layer 570, the conductive layer 560, the metal oxide 552, the insulating layer 550, and the insulating layer 575 on side surfaces of the oxide 530c. The insulating layer 575 is preferably an insulating layer with a low relative dielectric constant. For example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, silicon oxide having voids, or resin Preferably there is. In particular, silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon oxide having holes is preferably used for the insulating layer 575 because an excess oxygen region can be easily formed in the insulating layer 575 in a later step. Silicon oxide and silicon oxynitride are preferable because they are thermally stable. The insulating layer 575 preferably has a function of diffusing oxygen.

In addition, the transistor 510E includes the insulating layer 574 over the insulating layer 575 and the oxide 530. The insulating layer 574 is preferably formed by a sputtering method. By using a sputtering method, an insulating layer with few impurities such as water or hydrogen can be formed. For example, aluminum oxide may be used for the insulating layer 574.

Note that an oxide film formed by a sputtering method may extract hydrogen from a deposition target structure. Therefore, the insulating layer 574 absorbs hydrogen and water from the oxide 230 and the insulating layer 575, whereby the hydrogen concentration in the oxide 230 and the insulating layer 575 can be reduced.

This embodiment can be implemented in appropriate combination with the structures described in the other embodiments.

(Embodiment 4)
In this embodiment, a product image in which a memory device or a semiconductor device according to one embodiment of the present invention can be used, an electronic component and an electronic device to which the semiconductor device described in the above embodiments can be applied will be described.

<Product image>
First, FIG. 16 illustrates a product image in which a memory device or a semiconductor device according to one embodiment of the present invention can be used. A region 801 illustrated in FIG. 16 represents a high temperature characteristic (High T operation), a region 802 represents a high frequency characteristic (High f operation), a region 803 represents a low off characteristic (Ioff), and a region 804 represents a region 801. , Region 802 and region 803 are overlapped.

Note that in the case where the region 801 is to be filled, the region 801 can be roughly filled by applying a carbide or nitride such as silicon carbide or gallium nitride as a channel formation region of the transistor. In addition, when the region 802 is to be filled, the region 802 can be roughly filled by applying silicide such as single crystal silicon or crystalline silicon as a channel formation region of the transistor. In addition, when the region 803 is to be filled, an oxide semiconductor (OS) that is a kind of metal oxide can be used as the channel formation region of the transistor.

The memory device or the semiconductor device according to one embodiment of the present invention can be preferably used for a product in the range shown in the region 804, for example.

In conventional products, it is difficult to fill all of the region 801, the region 802, and the region 803. However, when an OS is used for a channel formation region of a transistor included in a memory device or a semiconductor device according to one embodiment of the present invention, particularly when a crystalline OS is used, a high temperature characteristic, a high frequency characteristic, and a low off characteristic A semiconductor device satisfying the above can be provided.

Note that as a product using the memory device or the semiconductor device according to one embodiment of the present invention in the range illustrated in the region 804, for example, an electronic device having a low power consumption and a high-performance CPU or the like is high in a high temperature environment. Examples include in-vehicle electronic components and electronic devices that require reliability. Next, examples of electronic components and electronic devices each including a memory device or a semiconductor device according to one embodiment of the present invention are described.

The semiconductor device according to one embodiment of the present invention can be mounted on various electronic devices. In particular, the semiconductor device according to one embodiment of the present invention can be used as a memory incorporated in an electronic device. Examples of electronic devices include relatively large game machines such as television devices, desktop or notebook personal computers, monitors for computers, digital signage (digital signage), and pachinko machines. In addition to electronic devices including a screen, a digital camera, a digital video camera, a digital photo frame, a mobile phone, a portable game machine, a portable information terminal, a sound reproducing device, and the like can be given.

The electronic device of one embodiment of the present invention may include an antenna. By receiving a signal with an antenna, video, information, and the like can be displayed on the display unit. In the case where the electronic device includes an antenna and a secondary battery, the antenna may be used for non-contact power transmission.

The electronic device of one embodiment of the present invention includes a sensor (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, It may have a function of measuring voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared).

The electronic device of one embodiment of the present invention can have a variety of functions. For example, a function for displaying various information (still images, moving images, text images, etc.) on the display unit, a touch panel function, a function for displaying a calendar, date or time, a function for executing various software (programs), and wireless communication A function, a function of reading a program or data recorded on a recording medium, and the like can be provided.

<Electronic parts>
Examples of electronic components in which the memory device 100 is incorporated are shown in FIGS.

FIG. 17A is a perspective view of the electronic component 700 and a substrate (mounting substrate 704) on which the electronic component 700 is mounted. An electronic component 700 illustrated in FIG. 17A is an IC semiconductor device, which includes a lead and a circuit portion. The electronic component 700 is mounted on a printed circuit board 702, for example. A plurality of such IC semiconductor devices are combined and each is electrically connected on the printed circuit board 702, whereby the mounting substrate 704 is completed.

As the circuit portion of the electronic component 700, the memory device 100 described in the above embodiment is provided. In FIG. 17A, QFP (Quad Flat Package) is applied to the package of the electronic component 700, but the form of the package is not limited to this.

FIG. 17B is a perspective view of the electronic component 730. The electronic component 730 is an example of SiP (System in package) or MCM (Multi Chip Module). In the electronic component 730, an interposer 731 is provided on a package substrate 732 (printed substrate), and a semiconductor device 735 and a plurality of storage devices 100 are provided on the interposer 731.

In the electronic component 730, an example in which the storage device 100 is used as a high bandwidth memory (HBM) is illustrated. For the semiconductor device 735, an integrated circuit such as a CPU, a GPU, or an FPGA can be used.

As the package substrate 732, a ceramic substrate, a plastic substrate, a glass epoxy substrate, or the like can be used. As the interposer 731, a silicon interposer, a resin interposer, or the like can be used.

The interposer 731 includes a plurality of wirings and has a function of electrically connecting a plurality of integrated circuits having different terminal pitches. The plurality of wirings are provided in a single layer or multiple layers. In addition, the interposer 731 has a function of electrically connecting an integrated circuit provided over the interposer 731 to an electrode provided on the package substrate 732. For these reasons, the interposer is sometimes called a “redistribution substrate” or an “intermediate substrate”. In some cases, a through electrode is provided in the interposer 731 and the integrated circuit and the package substrate 732 are electrically connected using the through electrode. In the silicon interposer, TSV (Through Silicon Via) can be used as the through electrode.

A silicon interposer is preferably used as the interposer 731. Since a silicon interposer does not require an active element, it can be manufactured at a lower cost than an integrated circuit. On the other hand, since the wiring formation of the silicon interposer can be performed by a semiconductor process, it is easy to form a fine wiring which is difficult with the resin interposer.

In the HBM, it is necessary to use many wirings in order to realize a wide memory bandwidth. For this reason, the interposer for mounting the HBM is required to form fine and high-density wiring. Therefore, it is preferable to use a silicon interposer as the interposer for mounting the HBM.

In addition, in SiP, MCM, and the like using a silicon interposer, reliability is unlikely to deteriorate due to a difference in expansion coefficient between the integrated circuit and the interposer. In addition, since the silicon interposer has high surface flatness, poor connection between an integrated circuit provided on the silicon interposer and the silicon interposer hardly occurs. In particular, a silicon interposer is preferably used in a 2.5D package (2.5-dimensional mounting) in which a plurality of integrated circuits are arranged side by side on the interposer.

Further, a heat sink (heat radiating plate) may be provided so as to overlap with the electronic component 730. In the case where a heat sink is provided, it is preferable that the height of the integrated circuit provided on the interposer 731 is uniform. For example, in the electronic component 730 described in this embodiment, it is preferable that the memory device 100 and the semiconductor device 735 have the same height.

In order to mount the electronic component 730 on another substrate, an electrode 733 may be provided on the bottom of the package substrate 732. FIG. 17B illustrates an example in which the electrode 733 is formed using a solder ball. By providing solder balls in a matrix on the bottom of the package substrate 732, BGA (Ball Grid Array) mounting can be realized. Alternatively, the electrode 733 may be formed using a conductive pin. By providing conductive pins in a matrix at the bottom of the package substrate 732, PGA (Pin Grid Array) mounting can be realized.

The electronic component 730 is not limited to BGA and PGA, and can be mounted on another substrate using various mounting methods. For example, SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-readed Package), or QFN (Quad Flat Non-leak method) be able to.

<Electronic equipment>
Next, an example of an electronic device including the electronic component will be described with reference to FIGS.

The robot 7100 includes an illuminance sensor, a microphone, a camera, a speaker, a display, various sensors (such as an infrared sensor, an ultrasonic sensor, an acceleration sensor, a piezo sensor, an optical sensor, and a gyro sensor), a movement mechanism, and the like. The electronic component 730 includes a processor and the like and has a function of controlling these peripheral devices. For example, the electronic component 700 has a function of storing data acquired by a sensor.

The microphone has a function of detecting acoustic signals such as a user's voice and environmental sound. The speaker has a function of emitting audio signals such as voice and warning sound. The robot 7100 can analyze an audio signal input via a microphone and emit a necessary audio signal from a speaker. The robot 7100 can communicate with a user using a microphone and a speaker.

The camera has a function of imaging the surroundings of the robot 7100. In addition, the robot 7100 has a function of moving using a moving mechanism. The robot 7100 can capture a surrounding image using a camera, analyze the image, and detect the presence or absence of an obstacle when moving.

The flying object 7120 includes a propeller, a camera, a battery, and the like, and has a function of flying autonomously. The electronic component 730 has a function of controlling these peripheral devices.

For example, image data photographed with a camera is stored in the electronic component 700. The electronic component 730 can analyze the image data and detect the presence or absence of an obstacle when moving. Further, the remaining amount of the battery can be estimated from the change in the storage capacity of the battery by the electronic component 730.

The cleaning robot 7140 has a display arranged on the upper surface, a plurality of cameras arranged on the side, brushes, operation buttons, various sensors, and the like. Although not shown, the cleaning robot 7300 includes a tire, a suction port, and the like. The cleaning robot 7300 is self-propelled, can detect dust, and can suck dust from a suction port provided on the lower surface.

For example, the electronic component 730 can analyze an image captured by the camera and determine whether there is an obstacle such as a wall, furniture, or a step. In addition, when an object that is likely to be entangled with the brush such as wiring is detected by image analysis, the rotation of the brush can be stopped.

An automobile 7160 is shown as an example of the moving object. The automobile 7160 includes an engine, tires, brakes, a steering device, a camera, and the like. For example, the electronic component 730 performs control for optimizing the traveling state of the automobile 7160 based on data such as navigation information, speed, engine state, gear selection state, and brake usage frequency. For example, image data taken with a camera is stored in the electronic component 700.

In the above description, the automobile is described as an example of the moving body, but the moving body is not limited to the automobile. For example, a moving object can include a train, a monorail, a ship, a flying object (helicopter, unmanned aerial vehicle (drone), airplane, rocket), and the like, and the computer of one embodiment of the present invention is applied to these moving objects. Thus, a system using artificial intelligence can be provided.

The electronic component 700 and / or the electronic component 730 can be incorporated in a TV device 7200 (television receiver), a smartphone 7210, a PC 7220 (personal computer), 7230, a game machine 7240, a game machine 7260, or the like.

For example, the electronic component 730 incorporated in the TV device 7200 can function as an image engine. For example, the electronic component 730 performs image processing such as noise removal and resolution up-conversion.

A smartphone 7210 is an example of a portable information terminal. A smartphone 7210 includes a microphone, a camera, a speaker, various sensors, and a display unit. These peripheral devices are controlled by the electronic component 730.

PC 7220 and PC 7230 are examples of a notebook PC and a stationary PC, respectively. A keyboard 7232 and a monitor device 7233 can be connected to the PC 7230 wirelessly or by wire.

The game machine 7240 is an example of a portable game machine. The game machine 7260 is an example of a home-use game machine. A controller 7262 is connected to the game machine 7260 wirelessly or by wire. The controller 7262 can also incorporate the electronic component 700 and / or the electronic component 730.

A game machine to which the semiconductor device of one embodiment of the present invention is applied is not limited thereto. As the game machine using the semiconductor device of one embodiment of the present invention, for example, an arcade game machine installed in an amusement facility (game center, amusement park, or the like), a pitching machine for batting practice installed in a sports facility, or the like can be given. It is done.

An alarm device 8100 illustrated in FIG. 19A is a residential fire alarm, and includes a detection portion and a semiconductor device 8101. By using the electronic component 700 and / or the electronic component 730 described above for the semiconductor device 8101, the alarm device 8100 can save power. Further, stable operation can be realized even in a high temperature environment. Therefore, the reliability of the alarm device 8100 can be increased.

An air conditioner illustrated in FIG. 19A includes an indoor unit 8200 and an outdoor unit 8204. The indoor unit 8200 includes a housing 8201, an air blowing port 8202, a semiconductor device 8203, and the like. FIG. 19A illustrates the case where the semiconductor device 8203 is provided in the indoor unit 8200; however, the semiconductor device 8203 may be provided in the outdoor unit 8204. Alternatively, the semiconductor device 8203 may be provided in both the indoor unit 8200 and the outdoor unit 8204. By using the electronic component 700 and / or the electronic component 730 described above for the semiconductor device 8203, the air conditioner can save power. Further, stable operation can be realized even in a high temperature environment. Therefore, the reliability of the air conditioner can be increased.

An electric refrigerator-freezer 8300 illustrated in FIG. 19A includes a housing 8301, a refrigerator door 8302, a refrigerator door 8303, a semiconductor device 8304, and the like. In FIG. 19A, the semiconductor device 8304 is provided in the housing 8301. By using the electronic component 700 and / or the electronic component 730 for the semiconductor device 8304, the electric refrigerator-freezer 8300 can save power. Further, stable operation can be realized even in a high temperature environment. Therefore, the reliability of the electric refrigerator-freezer 8300 can be increased.

Note that in this embodiment, an electric refrigerator-freezer and an air conditioner have been described as examples of electrical appliances. The semiconductor device of one embodiment of the present invention can also be used for other electrical appliances. Other electrical appliances include, for example, vacuum cleaners, microwave ovens, microwave ovens, rice cookers, water heaters, IH cookers, water servers, air conditioners (including air conditioners), washing machines, dryers, audiovisual equipment, etc. Can be mentioned.

FIG. 19B illustrates an example of an electric vehicle. An electric vehicle 9700 is equipped with a secondary battery 9701. The output of the power of the secondary battery 9701 is adjusted by the control circuit 9702 and supplied to the driving device 9703. The control circuit 9702 is controlled by a processing device 9704 including a semiconductor device (not shown). By using the electronic component 700 and / or the electronic component 730 described above for the control circuit 9702 and the processing device 9704, the electric vehicle 9700 can save power. Further, stable operation can be realized even in a high temperature environment. Thus, the reliability of the electric vehicle 9700 can be increased.

Drive device 9703 is configured by a DC motor or an AC motor alone, or a combination of an electric motor and an internal combustion engine. The processing device 9704 is based on input information such as operation information (acceleration, deceleration, stop, etc.) of the driver of the electric vehicle 9700 and information at the time of travel (information such as uphill and downhill, load information on the drive wheels, etc.). The control signal is output to the control circuit 9702. The control circuit 9702 controls the output of the driving device 9703 by adjusting the electric energy supplied from the secondary battery 9701 according to the control signal of the processing device 9704. When an AC motor is mounted, an inverter that converts direct current to alternating current is also built in, although not shown.

A computer 5400 illustrated in FIG. 20A is an example of a large computer. The computer 5400 stores a plurality of rack mount computers 5420 in a rack 5410.

The computer 5420 can have a configuration shown in a perspective view of FIG. 20B, the computer 5420 includes a motherboard 5430, and the motherboard includes a plurality of slots 5431, a plurality of connection terminals 5432, and a plurality of connection terminals 5433. A PC card 5421 is inserted into the slot 5431. In addition, the PC card 5421 includes a connection terminal 5423, a connection terminal 5424, and a connection terminal 5425, and each is connected to the motherboard 5430.

A PC card 5421 illustrated in FIG. 20C is an example of a processing board including a CPU, a GPU, a storage device, and the like. The PC card 5421 has a board 5422. The board 5422 includes a connection terminal 5423, a connection terminal 5424, a connection terminal 5425, a semiconductor device 5426, a semiconductor device 5427, a semiconductor device 5428, and a connection terminal 5429. Note that FIG. 20C illustrates a semiconductor device other than the semiconductor device 5426 and the semiconductor device 5427. These semiconductor devices are described below as a semiconductor device 5426, a semiconductor device 5427, and a semiconductor device. The description of the device 5428 may be referred to.

The connection terminal 5429 has a shape that can be inserted into the slot 5431 of the motherboard 5430, and the connection terminal 5429 functions as an interface for connecting the PC card 5421 and the motherboard 5430. Examples of the standard of the connection terminal 5429 include PCIe.

The connection terminal 5423, the connection terminal 5424, and the connection terminal 5425 can be used as an interface for supplying power, inputting a signal, and the like to the PC card 5421, for example. Further, for example, an interface for outputting a signal calculated by the PC card 5421 can be used. Examples of the standards of the connection terminal 5423, the connection terminal 5424, and the connection terminal 5425 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). When video signals are output from the connection terminal 5423, the connection terminal 5424, and the connection terminal 5425, HDMI (registered trademark) or the like can be given as the standard for each.

The semiconductor device 5426 has a terminal (not shown) for inputting and outputting signals. By inserting the terminal into a socket (not shown) provided in the board 5422, the semiconductor device 5426 and the board 5422 are connected. Can be electrically connected.

The semiconductor device 5427 has a plurality of terminals, and the semiconductor device 5427 and the board 5422 are electrically connected to the wiring provided in the board 5422 by, for example, reflow soldering. be able to. As the semiconductor device 5427, for example, a field programmable gate array (FPGA), a GPU, a CPU, and the like can be given. As the semiconductor device 5427, an electronic component 730 can be used.

The semiconductor device 5428 has a plurality of terminals, and the semiconductor device 5428 and the board 5422 are electrically connected to the wiring provided in the board 5422 by, for example, reflow soldering. be able to. As the semiconductor device 5428, for example, a memory device or the like can be given. As the semiconductor device 5428, an electronic component 700 can be used.

The computer 5400 can also function as a parallel computer. By using the computer 5400 as a parallel computer, for example, it is possible to perform large-scale calculations necessary for artificial intelligence learning and inference.

By using the semiconductor device of one embodiment of the present invention for the above various electronic devices, the electronic device can be reduced in size, increased in speed, or reduced in power consumption. Further, since heat generation from the circuit can be reduced with low power consumption, the influence of the heat generation on the circuit itself, peripheral circuits, and modules can be reduced. Further, stable operation can be realized even in a high temperature environment. Therefore, the reliability of the electronic device can be increased.

This embodiment can be implemented in appropriate combination with the structures described in the other embodiments.

10 memory cell 100 storage device 111 input / output circuit 112 control circuit 113 C receiver 114 setting register 115 LVDS circuit 116 LVDS circuit 117 decoder 118 register 119 register 127 sense amplifier 210 storage block array 211 storage block 212 word line driver 213 local sense amplifier driver 214 Local sense amplifier array 215 Global sense amplifier 216 Selector 218 Negative voltage generation circuit 221 Cell array

Claims (15)

A control circuit and a plurality of memory cells;
Each of the plurality of memory cells includes a transistor and a capacitor.
The transistor has a gate and a back gate,
The semiconductor layer of the transistor comprises a metal oxide;
The control circuit includes:
The potential supplied to the gate of the transistor is
A function of selecting from the first potential, the second potential, or the third potential;
The first potential is a potential that turns on the transistor;
The second potential and the third potential are potentials that turn off the transistor,
The memory device, wherein the second potential is higher than the third potential. A control circuit and a plurality of memory cells;
Each of the plurality of memory cells includes a transistor and a capacitor.
The transistor has a gate and a back gate,
One of a source and a drain of the transistor is electrically connected to a capacitor;
The other of the source and the drain of the transistor is electrically connected to the bit line;
The gate is electrically connected to a word line;
The control circuit includes:
A function of supplying a first potential to the word line and supplying a charge from the bit line to the capacitor;
A function of supplying the second potential or the third potential to the word line to hold the charge;
Have
The memory device, wherein the second potential is higher than the third potential. In claim 1,
2. The memory device according to claim 1, wherein the second potential is a potential at which the charge retention time is one hour or longer. In claim 1 or claim 2,
The storage device according to claim 3, wherein the third potential is a potential that makes the charge retention time 10 years or longer. In any one of Claims 1 thru | or 4,
A storage device, wherein a negative bias is supplied to the back gate. In any one of Claims 1 thru | or 5,
The memory device, wherein the metal oxide includes at least one of indium and zinc. Having a plurality of storage blocks;
Each of the plurality of storage blocks has a plurality of memory cells;
Each of the plurality of memory cells includes a transistor and a capacitor.
The transistor has a gate and a back gate,
The semiconductor layer of the transistor comprises a metal oxide;
The storage device has a function of operating in a plurality of operation modes. In claim 7,
The memory device according to claim 1, wherein the operation mode is determined by a combination of a potential supplied to the gate and a potential supplied to the back gate. In claim 7 or claim 8,
One of the plurality of operation modes is:
A memory device characterized by being in an operation mode for increasing an operation speed of a memory cell. In claim 9,
Another one of the plurality of operation modes is:
A memory device characterized by being in an operation mode for extending a retention time of a memory cell. In any one of Claims 7 to 10,
The memory device, wherein the metal oxide includes at least one of indium and zinc. Having a plurality of storage blocks;
Each of the plurality of storage blocks has a plurality of memory cells;
Each of the plurality of memory cells includes a transistor and a capacitor.
The transistor has a gate and a back gate,
The semiconductor layer of the transistor comprises a metal oxide;
The plurality of storage blocks are:
A first storage block operating in a first operation mode;
A second memory block operating in a second operation mode;
A storage device comprising: In claim 12,
The first operation mode is:
A memory device characterized by being in an operation mode for increasing an operation speed of a memory cell. In claim 12 or claim 13,
The second operation mode is:
A memory device characterized by being in an operation mode for extending a retention time of a memory cell. In any one of Claims 12 to 14,
The memory device, wherein the metal oxide includes at least one of indium and zinc.