JP2019180110A - Power conversion device - Google Patents

Abstract

A voltage sensor is attached to an intermediate capacitor constituting a power converter. An abnormal voltage in the voltage sensor is detected. A first switching element to a fourth switching element, an input-side capacitor, an intermediate capacitor, an output-side capacitor, a current sensor, a first voltage sensor for detecting a voltage across the intermediate capacitor, and an output-side capacitor A second voltage sensor that detects a voltage between both ends, and a controller that controls an on-time ratio of the switching element so that a target value of the intermediate capacitor matches the detection value of the first voltage sensor. The difference between the target value of the intermediate capacitor and the detection value of the first voltage sensor is determined, and it is compared whether the absolute value of the difference is greater than the abnormality determination threshold. If the absolute value is greater than the abnormality determination threshold, A power converter, wherein it is determined that a voltage abnormality has occurred. [Selection] Fig. 21

Description

  The present application relates to a power conversion device.

  The power conversion device includes a DC / DC converter. For example, a DC / DC converter disclosed in Patent Document 1 has a low-voltage side smoothing capacitor that holds a low-voltage side voltage, and a negative-side terminal connected to the negative-side terminal of the low-voltage side smoothing capacitor to hold a high-voltage side voltage. A high-voltage side smoothing capacitor; a first semiconductor circuit having one end connected to the negative-side terminal of the low-voltage side smoothing capacitor; and one end connected to the other end of the first semiconductor circuit and the other end via the reactor. And a second semiconductor circuit connected to the positive terminal of the low voltage side smoothing capacitor.

  The DC / DC converter further includes a third semiconductor circuit having one end connected to the other end of the second semiconductor circuit, and one end connected to the other end of the third semiconductor circuit and the other end connected to the high voltage. A fourth semiconductor circuit connected to the positive terminal of the side smoothing capacitor, one end connected to an intermediate connection point of the first semiconductor circuit and the second semiconductor circuit, and the other end of the third semiconductor circuit And a charge / discharge capacitor connected to an intermediate connection point between the semiconductor circuit and the fourth semiconductor circuit, and a control device for controlling the semiconductor circuits.

  This DC / DC converter can perform at least one of a step-up operation function and a step-down operation function. In order to perform the function of the boosting operation, both the first and second semiconductor circuits have the function of a switching element, and both the third and fourth semiconductor circuits have the function of a diode element. Yes. The DC / DC converter converts the input voltage of the low-voltage side smoothing capacitor into a boosted voltage by the on / off switching function of the switching element provided in the first and second semiconductor circuits when performing the boosting operation. And output to the high-voltage side smoothing capacitor.

  In order to execute the function of the step-down operation, both the third and fourth semiconductor circuits have a switching element function, and both the first and second semiconductor circuits have a diode element function. It is When the step-down operation is performed, the DC / DC converter converts the input voltage of the high-voltage side smoothing capacitor into a step-down voltage by the on / off switching function of the switching element provided in the third and fourth semiconductor circuits. And output to the low-pressure side smoothing capacitor.

  The control device includes a first calculation unit, a second calculation unit, and an opening / closing control unit. The first calculation unit may calculate a difference voltage between the command value of the high-voltage side voltage and the detection value of the high-voltage voltage, or a difference voltage between the command value of the low-voltage voltage and the detection value of the low-voltage voltage. Based on this, a first calculation value is calculated. The second calculation unit calculates a second calculation value based on a voltage difference between a voltage command value of the charge / discharge capacitor and a voltage detection value of the charge / discharge capacitor.

  The open / close control unit obtains an energization rate based on the first calculated value and the second calculated value. Further, the open / close control unit includes a first semiconductor circuit and a second semiconductor circuit having the on / off switching function based on a current ratio, or a third semiconductor circuit and a fourth semiconductor having the on / off switching function. By controlling the opening / closing operation of the circuit, the high-voltage side voltage or the low-voltage side voltage and the voltage of the charge / discharge capacitor are controlled.

  Patent Document 2 discloses another power conversion device. This power conversion device includes a DC / DC power conversion unit that boosts a DC voltage from an input power source, controls the voltage to a predetermined DC voltage, and outputs the voltage to a load. Further, the power conversion device includes a voltage sensor, a setting unit, a timer, and an abnormality detection unit. The voltage sensor detects the voltage of the intermediate capacitor that performs the charge / discharge operation by switching of the DC / DC power converter. The setting unit includes voltage setting means for setting a detection start voltage value for detecting an undervoltage of the voltage stored in the intermediate capacitor, and time setting means for setting a predetermined determination time.

  The timer measures time from the time when the intermediate capacitor can be charged after the operation of the DC / DC power converter is started. The abnormality detection unit is configured such that the voltage stored in the intermediate capacitor is equal to or higher than the detection start voltage value set by the voltage setting unit even when the time measured by the timer exceeds the predetermined determination time set by the time setting unit. If the voltage does not rise to 0, it is detected as an undervoltage of the intermediate capacitor. The control of the DC / DC power conversion unit is stopped when the abnormality detection unit detects an undervoltage of the intermediate capacitor.

Japanese Patent No. 5457559 Patent 5814056

  However, in the power conversion device described in Patent Document 1, since there is no means for detecting an abnormality in the voltage of the charge / discharge capacitor, when the voltage becomes an abnormal value, the voltage deviates from the voltage command value. . There is concern that the switching element may be overvoltage destroyed by applying a voltage higher than expected to the switching element.

  In addition, the power conversion device described in Patent Document 2 has a timer that measures time from the time when the intermediate capacitor can be charged. If the voltage of the intermediate capacitor does not rise above the detection start voltage value even after the measurement time has elapsed, the voltage sensor that detects the intermediate capacitor voltage is determined to be abnormal. For this reason, when a fixing abnormality that is an abnormality that fixes the detection value of the voltage sensor in a region equal to or higher than the detection start voltage value occurs, the abnormality of the voltage sensor cannot be detected.

  The power converter disclosed in the present application has been made to solve the above-described problems in the power converter. That is, the present application relates to an intermediate capacitor provided in the power converter, and an object thereof is to obtain a power converter capable of detecting a voltage abnormality in a first voltage sensor that detects the voltage of the intermediate capacitor. is there.

  The power converter disclosed in the present application includes a first switching element having a negative electrode side terminal, a positive electrode side terminal, and a gate, the negative electrode side terminal being connected to the negative electrode side of the DC power supply, a negative electrode side terminal, and a positive electrode A second switching element having a side terminal and a gate, the negative side terminal being connected to the positive side terminal of the first switching element, a negative side terminal, a positive side terminal, and a gate; A third switching element having a side terminal connected to a positive electrode side terminal of the second switching element; a negative electrode side terminal; a positive electrode side terminal; and a gate. The negative electrode side terminal is a positive electrode side of the third switching element. A fourth switching element connected to the terminal, a reactor connected in series with the DC power supply, an input side capacitor connected in parallel with the DC power supply, and one end of the second switch An intermediate capacitor connected to the negative terminal of the first switching element, the other end connected to the positive terminal of the third switching element, one end connected to the negative terminal of the first switching element, and the other end An output-side capacitor connected to the positive-side terminal of the fourth switching element, a current sensor that detects a current flowing through the reactor, a first voltage sensor that detects a voltage across the intermediate capacitor, and an output-side capacitor A second voltage sensor for detecting a voltage at both ends, a driver having a switching element and connected to both ends of the output-side capacitor, and calculating a target value of the intermediate capacitor from a detection value of the second voltage sensor; The first switch is set so that the calculated target value of the intermediate capacitor matches the detection value of the first voltage sensor. A controller for controlling an on-time ratio of the switching element, an on-time ratio of the second switching element, an on-time ratio of the third switching element, and an on-time ratio of the fourth switching element, A difference between a target value of the intermediate capacitor and a detection value of the first voltage sensor is obtained, and when the absolute value of the difference is larger than an abnormality determination threshold, it is determined that a voltage abnormality has occurred. is there.

  The power converter disclosed in the present application includes a first switching element having a negative electrode side terminal, a positive electrode side terminal, and a gate, the negative electrode side terminal being connected to the negative electrode side of the DC power supply, a negative electrode side terminal, and a positive electrode A second switching element having a side terminal and a gate, the negative side terminal being connected to the positive side terminal of the first switching element, a negative side terminal, a positive side terminal, and a gate; A third switching element having a side terminal connected to a positive electrode side terminal of the second switching element; a negative electrode side terminal; a positive electrode side terminal; and a gate. The negative electrode side terminal is a positive electrode side of the third switching element. A fourth switching element connected to the terminal, a reactor connected in series with the DC power supply, an input side capacitor connected in parallel with the DC power supply, and one end of the second switch An intermediate capacitor connected to the negative terminal of the first switching element, the other end connected to the positive terminal of the third switching element, one end connected to the negative terminal of the first switching element, and the other end An output-side capacitor connected to the positive-side terminal of the fourth switching element, a current sensor that detects a current flowing through the reactor, a first voltage sensor that detects a voltage across the intermediate capacitor, and an output-side capacitor A second voltage sensor for detecting a voltage at both ends, a driver having a switching element and connected to both ends of the output-side capacitor, and calculating a target value of the intermediate capacitor from a detection value of the second voltage sensor; The first switch is set so that the calculated target value of the intermediate capacitor matches the detection value of the first voltage sensor. A controller for controlling an on-time ratio of the switching element, an on-time ratio of the second switching element, an on-time ratio of the third switching element, and an on-time ratio of the fourth switching element, A difference between a target value of the intermediate capacitor and a detection value of the first voltage sensor is obtained, and when the absolute value of the difference is larger than an abnormality determination threshold, it is determined that a voltage abnormality has occurred. is there. Therefore, according to this power converter, it is possible to detect a voltage abnormality in the first voltage sensor that detects the voltage of the intermediate capacitor.

It is a circuit diagram for demonstrating the power converter device in connection with embodiment. It is a circuit diagram for demonstrating the internal structure of the controller in connection with embodiment. It is a circuit diagram for demonstrating the operation mode A in connection with embodiment. It is a circuit diagram for demonstrating the operation mode B in connection with embodiment. It is a circuit diagram for demonstrating the operation mode C in connection with embodiment. It is a circuit diagram for demonstrating the operation mode D in connection with embodiment. It is a figure for demonstrating the sticking abnormality of the 1st voltage sensor in connection with embodiment, and is a voltage waveform diagram made into object when the V0 detection value is larger than V0 target value. It is a figure for demonstrating the sticking abnormality of the 1st voltage sensor in connection with embodiment, and is a voltage waveform diagram made into object when the V0 detection value is smaller than V0 target value. It is a figure for demonstrating ON fixation abnormality of the 1st semiconductor switching circuit concerning embodiment, and is a circuit diagram which shows four types of operation modes. It is a figure which shows the time chart for demonstrating the ON fixation abnormality of the 1st semiconductor switching circuit in connection with embodiment. It is a figure for demonstrating ON fixation abnormality of the 2nd semiconductor switching circuit in connection with embodiment, and is a circuit diagram which shows four types of operation modes. It is a figure which shows the time chart for demonstrating the ON fixation abnormality of the 2nd semiconductor switching circuit in connection with embodiment. It is a figure for demonstrating ON fixation abnormality of the 3rd semiconductor switching circuit in connection with embodiment, and is a circuit diagram which shows four types of operation modes. It is a figure which shows the time chart for demonstrating the on-fixation abnormality of the 3rd semiconductor switching circuit in connection with embodiment. It is a figure for demonstrating ON fixation abnormality of the 4th semiconductor switching circuit in connection with embodiment, and is a circuit diagram which shows four types of operation modes. It is a figure which shows the time chart for demonstrating ON fixation abnormality of the 4th semiconductor switching circuit in connection with embodiment. It is a figure for demonstrating the off sticking abnormality of the 1st semiconductor switching circuit in connection with embodiment, and is a circuit diagram which shows four types of operation modes. It is a figure which shows the time chart for demonstrating the off sticking abnormality of the 1st semiconductor switching circuit in connection with embodiment. It is a figure for demonstrating the OFF sticking abnormality of the 2nd semiconductor switching circuit in connection with embodiment, and is a circuit diagram which shows four types of operation modes. It is a figure which shows the time chart for demonstrating the off sticking abnormality of the 2nd semiconductor switching circuit in connection with embodiment. It is a flow figure for judging V0 voltage abnormality concerning an embodiment. In embodiment, it is explanatory drawing which showed the electric current path | route at the time of carrying out soft start control of switching element S1 and switching element S3 at the time of S1 on adhering. In embodiment, it is explanatory drawing which showed the voltage change at the time of carrying out soft start control of switching element S1 and S3 at the time of S1 on adhering. It is a timing chart for demonstrating the soft start control in connection with embodiment. FIG. 24A is a diagram illustrating the operation of the gate signal G1. FIG. 24B is a diagram illustrating the operation of the gate signal G2. FIG. 24C is a diagram illustrating the operation of the gate signal G3. FIG. 24D is a diagram illustrating the operation of the gate signal G4. FIG. 24E is a diagram illustrating operations of V0, V1, and V2. In embodiment, it is explanatory drawing which showed the electric current path | route at the time of carrying out soft start control of switching element S1 and switching element S3 at the time of S2 on adhering. FIG. 25A is a diagram showing a current path in operation mode A. FIG. FIG. 25B is a diagram showing a current path in the operation mode D. In embodiment, it is explanatory drawing which showed the voltage change and electric current change at the time of carrying out soft start control of switching element S1 and switching element S3 at the time of S2 adhering. FIG. 26A is an explanatory diagram showing a voltage change when the soft start control is performed. FIG. 26B is an explanatory diagram showing changes in current when soft-start control is performed. In embodiment, it is explanatory drawing which showed the electric current path | route at the time of carrying out soft start control of switching element S1 and switching element S3 at the time of S3 adhering fixation. In embodiment, it is explanatory drawing which showed the voltage change at the time of carrying out soft start control of switching element S1 and switching element S3 at the time of S3 adhering fixation. In embodiment, it is explanatory drawing which showed the electric current path | route at the time of carrying out soft start control of switching element S1 and switching element S3 at the time of S4 on adhering. FIG. 29A is a diagram illustrating a current path in the operation mode B. FIG. FIG. 29B is a diagram illustrating a current path in the operation mode D. In embodiment, it is explanatory drawing which showed the voltage change at the time of carrying out soft start control of switching element S1 and switching element S3 at the time of S4 on adhering. In embodiment, it is explanatory drawing which showed the electric current path | route at the time of performing soft start control of switching element S2 at the time of S1 adhering fixation. FIG. 31A is a diagram illustrating a current path in the operation mode A. FIG. FIG. 32B is a diagram showing a current path in the operation mode D. In embodiment, it is explanatory drawing which showed the voltage change and current change at the time of carrying out soft start control of switching element S2 at the time of S1 adhering fixation. FIG. 32A is an explanatory diagram showing a voltage change when the soft start control is performed. FIG. 32B is an explanatory diagram showing changes in current when soft-start control is performed. In embodiment, it is explanatory drawing which showed the electric current path | route at the time of carrying out soft start control of switching element S2 at the time of S3 on adhering. In embodiment, it is explanatory drawing which showed the voltage change at the time of carrying out soft start control of switching element S2 at the time of S3 on adhering. In embodiment, it is explanatory drawing which showed the electric current path | route at the time of carrying out soft start control of the switching element S2 at the time of S4 on adhering. In embodiment, it is explanatory drawing which showed the voltage change at the time of carrying out soft start control of switching element S2 at the time of S4 on adhering. In embodiment, it is explanatory drawing which showed the electric current path | route at the time of carrying out soft start control of switching element S1 at the time of S4 on adhering. In embodiment, it is explanatory drawing which showed the voltage change at the time of carrying out soft start control of the switching element S1 at the time of S4 on adhering. FIG. 6 is a flowchart for explaining abnormality type determination processing according to the first embodiment. 10 is a flowchart for explaining an abnormality type determination process according to Embodiment 2. FIG. FIG. 10 is a flowchart for explaining abnormality type determination processing according to the third embodiment.

  A power conversion apparatus according to an embodiment of the present application will be described below with reference to the drawings. In the drawings, the same or similar components are denoted by the same reference numerals, and the sizes and scales of the corresponding components are independent of each other. For example, when the same component part that is not changed is illustrated in cross-sectional views in which a part of the configuration is changed, the size and scale of the same component part may be different. Moreover, although the power converter device is actually provided with a plurality of members, only the portions necessary for the description are shown and the other portions are omitted for the sake of simplicity.

Embodiment 1 FIG.
Hereinafter, Embodiment 1 of the present application will be described. FIG. 1 is a circuit diagram of a power conversion device for explaining an embodiment of the present application. As shown in the figure, the power conversion apparatus 100 includes a DC / DC converter 50, a motor driver 51, a controller 6, and the like. Further, a DC power source 101 (or a battery) is connected between the input side (low voltage side) of the power converter 100, that is, between the terminal P1 and the terminal N1. A motor 102 is connected via the motor driver 51 between the output side (high voltage side) of the power converter 100, that is, between the terminal P2 and the terminal N2.

  The DC / DC converter 50 includes a reactor 1 (L1), a first semiconductor switching circuit 2a, a second semiconductor switching circuit 2b, a third semiconductor switching circuit 2c, a fourth semiconductor switching circuit 2d, and a low-voltage side capacitor 3 (C1), a high-voltage side capacitor 4 (C2), an intermediate capacitor 5 (C0), a current sensor 7, a first voltage sensor 8, a second voltage sensor 9, and the like. Current sensor 7 detects a current flowing through reactor 1 (L1). The first voltage sensor 8 detects the voltage (V0 true value) across the intermediate capacitor 5, also referred to as an intermediate voltage. The second voltage sensor 9 detects a voltage (V2 true value) across the high-voltage side capacitor 4 that is also called an output voltage.

  The first semiconductor switching circuit 2a to the fourth semiconductor switching circuit 2d are composed of switching elements S1 to S4 and a diode connected in reverse parallel thereto. For example, an IGBT (Insulated Gate Bipolar Transistor) is applied to the switching elements S1 to S4. Further, a sense terminal through which a sense current flows is provided at the emitter terminals (negative terminal) of the first semiconductor switching circuit 2a to the fourth semiconductor switching circuit 2d. Here, the sense current indicates a current obtained by dividing the collector current, and each sense terminal is connected to the controller 6.

  The controller 6 controls the first semiconductor switching circuit 2a, the second semiconductor switching circuit 2b, the third semiconductor switching circuit 2c, the fourth semiconductor switching circuit 2d, the motor driver 51, and the motor 102. The motor driver 51 is a DC / AC inverter that converts a DC voltage into an AC voltage in order to drive the motor 102. For example, the motor driver 51 is configured by connecting six pairs of semiconductor switching circuits, which are composed of a switching element and a diode connected in antiparallel thereto, with a full bridge connection. The controller 6 can control the operation of the motor driver 51 by transmitting a control signal MD to the motor driver 51.

  The DC / DC converter 50 is a bidirectional type capable of bidirectional power conversion between a low voltage side (input side) and a high voltage side (output side). The input voltage (low voltage side voltage; first voltage) V1 input between the low voltage side terminals (terminal P1 and terminal N1) is boosted to a voltage equal to or higher than V1, and the output voltage after boosting (high voltage side voltage; first voltage) 2 voltage) V2 is output between the high-voltage side terminals (terminal P2 and terminal N2). The first semiconductor switching circuit 2a, the second semiconductor switching circuit 2b, the third semiconductor switching circuit 2c, and the fourth semiconductor switching circuit 2d are connected in series.

  One end of the first semiconductor switching circuit 2a is connected to the negative terminal of the low voltage side capacitor 3 (C1; input side capacitor). The second semiconductor switching circuit 2b has one end connected to the other end of the first semiconductor switching circuit 2a and the other end connected to the positive terminal of the low voltage side capacitor 3 via the reactor 1 (L1). One end of the third semiconductor switching circuit 2c is connected to the other end of the second semiconductor switching circuit 2b. The fourth semiconductor switching circuit 2d has one end connected to the other end of the third semiconductor switching circuit 2c and the other end connected to the positive terminal of the high voltage side capacitor 4 (C2; output side capacitor).

  The intermediate capacitor 5 (C0) has one end connected to an intermediate connection point between the first semiconductor switching circuit 2a and the second semiconductor switching circuit 2b, and the other end connected to the third semiconductor switching circuit 2c and the fourth semiconductor switching circuit 2d. Connected to an intermediate connection point. The gate signals G1 to G4 are generated by the controller 6 for the first semiconductor switching circuit 2a to the fourth semiconductor switching circuit 2d. The controller 6 turns on / off the first semiconductor switching circuit 2a to the fourth semiconductor switching circuit 2d at the switching frequency fsw (switching period Tsw).

  The operation of the DC / DC converter 50 is described in detail in Patent Document 1 (Japanese Patent No. 5457559) filed by the present applicant, and will be briefly described here. As an operation state of the DC / DC converter 50 in a steady state, a state in which the motor 102 is driven by power supplied from the DC power source 101 to the motor 102 (power running operation), and a power generated by the motor 102 in a power generation state is a direct current. There are two states (regenerative operation) that are supplied to the power supply 101.

  FIG. 2 is a circuit diagram for explaining the controller in the embodiment of the present application. The controller 6 includes a CPU 6a (Central Processing Unit) and a storage device 6b. The controller 6 transmits gate signals G1 to G4 to the first semiconductor switching circuit 2a to the fourth semiconductor switching circuit 2d. In this embodiment, when the gate signals G1 to G4 are High, the first semiconductor switching circuit 2a to the fourth semiconductor switching circuit 2d are turned on (see FIGS. 24A to 24D).

  The function of the controller 6 is realized by software, firmware, or a combination of software and firmware. Software and firmware are described as programs and stored in the storage device 6b. The CPU 6a (processing circuit) implements the functions of each unit by reading and executing the program stored in the storage device 6b. That is, the controller 6 includes a storage device 6b for storing a program in which each step is executed as a result when executed by the processing circuit.

  These programs can be said to cause the computer to execute the procedure and method of the controller 6. Here, the storage device 6b is, for example, RAM (Random Access Memory), ROM (Read-Only Memory), flash memory, EPROM (Erasable Programmable ROM), EEPROM (Electrically Erasable Programmable ROM, etc.). This includes a semiconductor memory, a magnetic disk, a flexible disk, an optical disk, a compact disk, a mini disk, a DVD, and the like.

  The operation mode of the DC / DC converter 50 according to the embodiment of the present application will be described with reference to the circuit diagrams shown in FIGS. As operation modes of the DC / DC converter 50 in the steady state, an operation mode A, an operation mode B, an operation mode C, and an operation mode D are defined. FIG. 3 shows an operation mode A of the DC / DC converter 50. In the operation mode A, the first semiconductor switching circuit 2a and the second semiconductor switching circuit 2b are turned on, and the third semiconductor switching circuit 2c and the fourth semiconductor switching circuit 2d are turned off.

  During the power running operation in the operation mode A, the energy is stored in the reactor 1 (L1), and during the regenerative operation, the energy of the reactor 1 (L1) is released. Switching element S1 (first switching element), switching element S2 (second switching element), switching element S3 (third switching element), and switching element S4 (fourth switching element) are respectively connected to negative terminal S-, It has a positive terminal S + and a gate Sg.

  FIG. 4 shows an operation mode B of the DC / DC converter 50. In the operation mode B, the first semiconductor switching circuit 2a and the third semiconductor switching circuit 2c are on, and the second semiconductor switching circuit 2b and the fourth semiconductor switching circuit 2d are off. During the power running operation, energy is stored in the intermediate capacitor 5, and during the regenerative operation, the energy of the intermediate capacitor 5 is released.

  FIG. 5 shows an operation mode C of the DC / DC converter 50. In the operation mode C, the second semiconductor switching circuit 2b and the fourth semiconductor switching circuit 2d are on, and the first semiconductor switching circuit 2a and the third semiconductor switching circuit 2c are off. During the power running operation, the energy of the intermediate capacitor 5 is released, and during the regenerative operation, the energy is stored in the intermediate capacitor 5.

  FIG. 6 shows an operation mode D of the DC / DC converter 50. In the operation mode D, the third semiconductor switching circuit 2c and the fourth semiconductor switching circuit 2d are on, and the first semiconductor switching circuit 2a and the second semiconductor switching circuit 2b are off. During the power running operation, the reactor 1 (L1) energy is released, and during the regenerative operation, the reactor 1 (L1) energy is accumulated. The DC / DC converter 50 appropriately adjusts the time ratio of these operation modes A to D to change the input voltage V1 (low voltage) input between the terminals P1 and N1 to an arbitrary voltage. The voltage can be boosted and output between the terminal P2 and the terminal N2 as the output voltage V2 (high voltage side voltage).

  When the step-up ratio N of the output voltage V2 with respect to the input voltage V1 is less than twice, “operation mode B → operation mode D → operation mode C → operation mode D” is repeated. By repeating this process, the input voltage V1 is boosted from 1 to 2 times and output as the output voltage V2, while maintaining the voltage (V0) across the intermediate capacitor 5 at a voltage half that of V2. . When the step-up ratio N of the output voltage V2 with respect to the input voltage V1 is twice or more, “operation mode A → operation mode B → operation mode A → operation mode C” is repeated. By repeating this operation, the input voltage V1 is boosted to an arbitrary voltage more than twice and output as the output voltage V2 while maintaining the voltage (V0) across the intermediate capacitor 5 at a voltage half that of V2.

  By the way, in the DC / DC converter 50, the detected value (V0 detected value: detected value of the first voltage sensor) of the voltage (V0) across the intermediate capacitor 5 detected by the first voltage sensor 8 and the voltage across the intermediate capacitor 5 are detected. The controller 6 performs feedback control so that the target value of (V0) (V0 target value; target value of the intermediate capacitor) matches. Here, the target value of the intermediate capacitor (V0 target value) is 2 minutes of the detected value of the voltage V2 across the high-voltage capacitor 4 detected by the second voltage sensor 9 (V2 detected value: detected value of the second voltage sensor). The voltage of 1. Therefore, even if an abnormality occurs in the first voltage sensor 8, if the abnormality cannot be detected, feedback control is performed so that the erroneous V0 detection value matches the V0 target value. It will shift.

  As an example of the abnormality of the first voltage sensor 8, there is a state where the V0 detection value (detection value of the first voltage sensor) is fixed to a value other than the V0 true value (V0 target value). This phenomenon is hereinafter referred to as a sticking abnormality. The first voltage sensor fixation abnormality (V0 sensor fixation abnormality) in the embodiment of the present application will be described with reference to voltage waveform diagrams. FIG. 7 is a voltage waveform diagram when a sticking abnormality occurs such that V0 detection value> V0 target value. In this case, the positive difference of the V0 detection value with respect to the V0 target value does not become zero, and as a result of feedback control, V0 true value = 0V.

  On the other hand, FIG. 8 is a voltage waveform diagram in the case where a sticking abnormality (V0 sensor sticking abnormality) in which V0 detection value <V0 target value occurs. In this case, the negative difference of the V0 detection value with respect to the V0 target value does not become zero, and as a result of feedback control, V0 true value = output voltage V2. Further, in this DC / DC converter 50, even when any one of the first semiconductor switching circuit to the fourth semiconductor switching circuit fails, the V0 target value and the V0 detection value are set as in the case of the fixing abnormality of the first voltage sensor. The difference increases.

  In addition to the first voltage sensor sticking abnormality, there are an on-sticking abnormality and an off-sticking abnormality. An on-fixation abnormality of the first semiconductor switching circuit according to the embodiment will be described with reference to the drawings. FIG. 9 is a circuit diagram showing a current path in each operation mode. On the other hand, FIG. 10 is a timing chart in each operation mode. In the operation mode C, when the first semiconductor switching circuit 2a has an on-fixing abnormality (the first switching element on-fixing abnormality), the high-voltage side capacitor 4 (C2) → the fourth semiconductor switching circuit 2d (S4) → the intermediate capacitor 5 (C0) → first semiconductor switching circuit 2a (S1) → high voltage side capacitor 4 (C2) is short-circuited. Since the intermediate capacitor 5 (C0) and the high voltage side capacitor 4 (C2) are short-circuited, as a result, V0 true value = V2 true value. Therefore, the difference between the V0 target value and the V0 detection value becomes large.

  An on-fixing abnormality of the second semiconductor switching circuit according to the embodiment (on-fixing abnormality of the second switching element) will be described with reference to the drawings. FIG. 11 is a circuit diagram showing a current path in each operation mode. On the other hand, FIG. 12 is a timing chart. When an on-fixation abnormality occurs in the second semiconductor switching circuit 2b, in the operation mode B, the intermediate capacitor 5 (C0) → the third semiconductor switching circuit 2c (S3) → the second semiconductor switching circuit 2b (S2) → the intermediate capacitor 5 Short-circuit along the path (C0). Since the intermediate capacitor 5 (C0) is short-circuited, as a result, V0 true value = 0V. Therefore, the difference between the V0 target value and the V0 detection value becomes large.

  The on-fixing abnormality (third switching element on-fixing abnormality) of the third semiconductor switching circuit according to the embodiment will be described with reference to the drawings. FIG. 13 is a circuit diagram showing a current path in each operation mode. On the other hand, FIG. 14 is a timing chart. When an on-fixation abnormality occurs in the third semiconductor switching circuit 2c, in the operation mode A and the operation mode C, the intermediate capacitor 5 (C0) → the third semiconductor switching circuit 2c (S3) → the second semiconductor switching circuit 2b (S2) → Short-circuit along the path of intermediate capacitor 5 (C0). Since the intermediate capacitor 5 (C0) is short-circuited, as a result, V0 true value = 0V. Therefore, the difference between the V0 target value and the V0 detection value becomes large.

  An on-fixing abnormality of the fourth semiconductor switching circuit according to the embodiment (an on-fixing abnormality of the fourth switching element) will be described with reference to the drawings. FIG. 15 is a circuit diagram showing a current path in each operation mode. On the other hand, FIG. 16 is a timing chart. When an on-fixation abnormality occurs in the fourth semiconductor switching circuit 2d, in the operation mode A and the operation mode B, the high-voltage side capacitor 4 (C2) → the fourth semiconductor switching circuit 2d (S4) → the intermediate capacitor 5 (C0) → the second 1 Short circuit through the path of the semiconductor switching circuit 2a (S1) → high-voltage side capacitor 4 (C2). Since the intermediate capacitor 5 (C0) and the high voltage side capacitor 4 (C2) are short-circuited, as a result, V0 true value = V2 true value. Therefore, the difference between the V0 target value and the V0 detection value becomes large.

  An off-fixing abnormality (first switching element off-fixing abnormality) of the first semiconductor switching circuit according to the embodiment will be described with reference to the drawings. FIG. 17 is a circuit diagram showing a current path in each operation mode. On the other hand, FIG. 18 is a timing chart. When an off-fixation abnormality occurs in the first semiconductor switching circuit 2a, there is no current path in the operation mode A, and the reactor 1 (L1) cannot be excited. In the subsequent operation mode B, there is no current path, and the intermediate capacitor 5 (C0) cannot be charged. In the operation mode C, the intermediate capacitor 5 (C0) is discharged. As a result, V0 true value = 0V and V2 true value = V1 true value. Therefore, the difference between the V0 target value and the V0 detection value becomes large.

  An off-fixing abnormality of the second semiconductor switching circuit according to the embodiment (an off-fixing abnormality of the second switching element) will be described with reference to the drawings. FIG. 19 is a circuit diagram showing a current path in each operation mode. On the other hand, FIG. 20 is a timing chart. When an off-fixing abnormality occurs in the second semiconductor switching circuit 2b, there is no current path in the operation mode A, and the reactor 1 (L1) cannot be excited. In the subsequent operation mode B, the intermediate capacitor 5 (C0) is charged, so that V0 true value = V1 true value. In the subsequent operation mode A, there is no current path, and reactor 1 (L1) cannot be excited. In the operation mode C, there is no current path and the intermediate capacitor 5 (C0) is not discharged. As a result, V0 true value = V1 true value remains. Therefore, the difference between the V0 target value and the V0 detection value becomes large.

  As described above, the fixing abnormality of the first voltage sensor 8, the ON fixing abnormality of the first semiconductor switching circuit 2a, the ON fixing abnormality of the second semiconductor switching circuit 2b, the ON fixing abnormality of the third semiconductor switching circuit 2c, the fourth semiconductor In the case of the on-fixing abnormality of the switching circuit 2d, the off-fixing abnormality of the first semiconductor switching circuit 2a, and the off-fixing abnormality of the second semiconductor switching circuit 2b, the V0 true value is from the V0 target value (1/2 of the V2 detection value). It becomes an abnormal state that deviates. That is, the difference between the V0 target value and the V0 detection value increases. Such an abnormality is called a V0 voltage abnormality. In the present application, the controller 6 determines abnormality in V0 voltage by executing abnormality detection processing described below.

  FIG. 21 is a flowchart for determining the V0 voltage abnormality according to the embodiment. As shown in the figure, first, the V0 target value is calculated by V2 detection value × 0.5 (step S11). Next, by comparing the absolute value of the difference between the V0 target value calculated in step S11 and the V0 detection value with the abnormality determination threshold value, it is determined whether or not a V0 voltage abnormality has occurred (step S12). When the abnormality determination condition is satisfied in step S12, the process proceeds to step S13, and it is determined that a V0 voltage abnormality has occurred. If the abnormality determination condition is not satisfied in step S12, the process proceeds to step S14, and it is determined that no V0 voltage abnormality has occurred. The abnormality determination threshold may be determined in consideration of the error of the second voltage sensor 9 and the error of the first voltage sensor 8.

  By the way, this V0 voltage abnormality includes seven types of abnormality as described above. In this embodiment, after determining the V0 voltage abnormality, the abnormal part is further specified (abnormality type determination process). First, the on-duty ratio (S1_Duty: S1 on-time ratio) of the gate signal G1 of the first semiconductor switching circuit 2a (switching element S1) and the on-duty ratio of the gate signal G3 of the third semiconductor switching circuit 2c (switching element S3) ( By performing soft start control that gradually changes S3_Duty: S3 ON time ratio) from 0% to 100%, the on-fixing abnormality of the second semiconductor switching circuit 2b (switching element S2) is determined.

  FIG. 22 is a circuit diagram showing a current path when the switching element S1 and the switching element S3 are soft-start controlled when S1 is on in the embodiment disclosed in the present application. On the other hand, FIG. 23 is an explanatory diagram showing a voltage change when the soft start control is performed on the switching element S1 and the switching element S3 when S1 is on. As shown in the figure, when S1 is fixed on, the initial voltage of V0 is V2.

  At this time, when the soft start control is performed on the switching element S1 and the switching element S3, current flows through the path of the operation mode B (where the current direction is the regenerative direction), V0 gradually decreases, and V0 = V1. Further, as will be described later, since the motor driver 51 is driven and controlled so that the power transmission is in the power running direction, the high-voltage side voltage V2 gradually decreases to V2 = V0 = V1 = Vbatt. Here, Vbatt indicates the voltage across the DC power supply 101 (first voltage). Accordingly, in this case, an abnormality such as an overcurrent or an overvoltage does not occur, that is, an abnormality such as an overcurrent or an overvoltage can be avoided.

  24A to 24E are timing charts for explaining soft start control according to the embodiment. FIG. 24A is a timing chart showing a switching pattern of the first semiconductor switching circuit 2a (switching element S1). FIG. 24B is a timing chart showing a switching pattern of the second semiconductor switching circuit 2b (switching element S2). FIG. 24C is a timing chart showing a switching pattern of the third semiconductor switching circuit 2c (switching element S3). FIG. 24D is a timing chart showing a switching pattern of the fourth semiconductor switching circuit 2d (switching element S4).

  FIG. 24E is a timing chart showing voltage changes of V1, V0, and V2. As shown in FIGS. 24A to 24D, soft start control is performed on the switching elements S1 and S3, and the switching elements S2 and S4, which are semiconductor switching circuits not performing soft start control, are turned off. The first semiconductor switching circuit 2a to the fourth semiconductor switching circuit 2d are turned on when the gate signals G1 to G4 are High and turned off when the gate signals G1 to G4 are Low. As shown in FIG. 24E, the soft start control starts in the state of V1 = V2 = Vbatt.

  In this case, during the period when the gate signal G1 is High, current flows through the path of the operation mode B, V0 gradually increases, and converges to V0 = V1 (= V2 = Vbat). The soft start time Tsoft is set so that the component with the smallest rated current is not destroyed. The set value is determined in advance by simulation or the like so that the current flowing between the capacitors is less than the rated current of the component. In addition, the flowing current increases in accordance with the potential difference between the capacitors. The soft start time Tsoft may be calculated by simulation or the like on the assumption that the maximum potential difference is assumed.

  Next, in the embodiment, the case where the soft start control is performed on the switching element S1 and the switching element S3 when S2 is fixed will be described with reference to the drawings. 25A and 25B are circuit diagrams showing current paths. On the other hand, FIG. 26A is an explanatory diagram showing a voltage change, and FIG. 26B is an explanatory diagram showing a current change. In the case of S2 on fixation, the initial voltage of V0 is 0V. At this time, when soft start control is performed on switching element S1 and switching element S3, reactor 1 (L1) accumulates energy because current flows through the path of operation mode A when S1 is on. Since current flows through the path of the operation mode D when S1 is off, energy accumulated in the reactor 1 (L1) is released, and V2 increases.

  By repeating the on / off operation of the switching element S1, V2 gradually increases. At that time, the current IL flowing through the reactor 1 (L1) also gradually increases. Therefore, when the overvoltage threshold value (V2 threshold value 3) of V2 is set to a predetermined value and the condition of V2 ≧ overvoltage threshold value (V2 threshold value 3) is satisfied, it is possible to determine whether S2 is on. Further, when the IL overcurrent threshold (IL threshold) is set to a predetermined value and IL ≧ overcurrent threshold is satisfied, it is possible to determine whether S2 is on. Note that the overvoltage threshold (V2 threshold 3) may be set in consideration of an error of the first voltage sensor 8 or the like as the V2 maximum voltage when the switching element S2 is not fixed on. Similarly, the overcurrent threshold may be set in consideration of the error of the current sensor 7 and the like in the IL maximum current when S2 is not fixed on.

  Next, in the embodiment, current paths and voltage changes when the switching element S1 and the switching element S3 are soft-start controlled when S3 is fixed on will be described with reference to the drawings. FIG. 27 is a circuit diagram showing a current path. On the other hand, FIG. 28 is an explanatory diagram showing a voltage change. As shown in the figure, in the case of S3 on fixation, the initial voltage of V0 is 0V. At this time, when the switching element S1 and the switching element S3 are soft-start controlled, a current flows through the path of the operation mode B. V0 gradually increases to V0 = V1 (= Vbatt). Further, as described later, since the motor driver 51 is driven and controlled so that the power transmission is in the power running direction, V2 gradually decreases, and V2 = V0 = V1 = Vbatt. Accordingly, in this case, an abnormality such as an overcurrent or an overvoltage does not occur, that is, an abnormality such as an overcurrent or an overvoltage can be avoided.

  Next, in the first embodiment, a current path and a voltage change when the switching element S1 and the switching element S3 are soft-start controlled when S4 is on will be described with reference to the drawings. FIG. 29A and FIG. 29B are circuit diagrams showing current paths. On the other hand, FIG. 30 is an explanatory diagram showing a voltage change. As shown in the figure, in the case of S4 on fixation, the initial voltage of V0 is V2. At this time, when the switching element S1 and the switching element S3 are soft-start controlled, a current flows through the path of the operation mode B and the operation mode D. V0 and V2 gradually decrease to V1 = V0 = V2 = Vbatt. Therefore, in this case, an abnormality such as an overcurrent or an overvoltage does not occur, that is, an abnormality such as an overcurrent or an overvoltage can be avoided.

  Note that when the switching element S1 and the switching element S3 are soft-start controlled when the S1 is off, as shown in FIG. 18, when the V0 voltage is abnormal, V1 = V2 and V0 = 0V. Since no current flows in the circuit, no abnormality such as overcurrent occurs and the voltage state does not change. Further, when the switching element S1 and the switching element S3 are soft-started when S2 is fixed off, as shown in FIG. 20, when the V0 voltage is abnormal, V1 = V0 = V2. Since no current flows in the circuit, no abnormality such as overcurrent occurs and the voltage state does not change.

  Further, a case where the soft start control is performed on the switching element S1 and the switching element S3 when the V0 sensor is stuck abnormally will be described. As shown in FIG. 7, when a sticking abnormality occurs such that V0 detection value> V0 target value, V0 = 0V. When the switching element S1 is turned on, a current flows through the path of the operation mode B (see FIG. 27). Since the soft start control is performed, an abnormality such as an overcurrent does not occur and the state becomes V1 = V0 = V2 = Vbatt.

  Further, as shown in FIG. 8, when a sticking abnormality occurs where V0 detection value <V0 target value, V0 = V2. When the switching element S3 is turned on, a current flows through a path (see FIGS. 29A and 29B) in the operation mode B (however, the direction of the current is the regenerative direction). Since the soft start control is performed, an abnormality such as an overcurrent does not occur and the state becomes V1 = V0 = V2 = Vbatt.

  As described above, when the V0 voltage abnormality occurs, when the switching element S1 and the switching element S3 are soft-start controlled, an abnormality newly occurs only when S2 is fixed on. Therefore, the S2 on-fixing abnormality can be determined from the seven types of abnormality included in the V0 voltage abnormality.

  Next, after the soft start control of the switching elements S1 and S3, the on-duty ratio (S2_Duty: S2 on time ratio) of the gate signal G2 of the second semiconductor switching circuit 2b (switching element S2) is 0% to 100%. Implement soft start control that gradually changes to. Thereby, the on-fixing of the switching element S1 or the on-fixing abnormality of the switching element S3 is determined.

  Next, in the embodiment disclosed in the present application, current paths and voltage changes when the switching element S2 is soft-start controlled when S1 is fixed will be described with reference to the drawings. 31A and 31B are circuit diagrams showing current paths. On the other hand, FIG. 32A is an explanatory diagram showing a voltage change, and FIG. 32B is an explanatory diagram showing a current change. As shown in the figure, the voltage state after the soft start control of the switching element S1 and the switching element S3 when S1 is fixed is V1 = V0 = V2 = Vbatt.

  If the switching element S2 is soft-start controlled at this time, the reactor 1 (L1) accumulates energy through the path of the operation mode A when S2 is on. When S2 is off, energy stored in reactor 1 (L1) is released through the path of operation mode D, and V2 increases. By repeating the on / off operation of the switching element S2, V2 gradually increases. At that time, the current IL flowing through the reactor 1 (L1) also gradually increases. Therefore, the S1 on-fixation abnormality can be determined in the same manner as described with reference to FIGS. 26A and 26B.

  Next, a current path and a voltage change when the switching element S2 is soft-start controlled when S3 is fixed in the first embodiment disclosed in the present application will be described with reference to the drawings. FIG. 33 is a circuit diagram showing a current path. On the other hand, FIG. 34 is an explanatory diagram showing a voltage change. As shown in the figure, the voltage state after the soft start control of the switching element S1 and the switching element S3 in the case where S3 is fixed is V1 = V0 = V2 = Vbatt. If the switching element S2 is soft-start controlled at this time, it is short-circuited along the path C0 → S3 → S2 → C0 when S2 is on. As a result, a short circuit current flows through the path.

  This short-circuit current is detected by the controller 6 by comparing the sense current and the short-circuit current threshold. In other words, when the condition of sense current ≧ short circuit current threshold is satisfied, the S3 on-fixation abnormality can be determined. The short-circuit current threshold may be set in consideration of the shunt ratio of the sense terminal and the like for the maximum current when no short-circuit abnormality has occurred. In this example, the short circuit abnormality is detected by the current flowing through the first semiconductor switching circuit 2a to the fourth semiconductor switching circuit 2d. For example, the short circuit abnormality is detected by a gate voltage or a collector voltage which is a known technique. It may be a method.

  Next, in the embodiment disclosed in the present application, current paths and voltage changes when the switching element S2 is soft-start controlled when S4 is fixed will be described with reference to the drawings. FIG. 35 is a circuit diagram showing a current path. On the other hand, FIG. 36 is an explanatory diagram showing a voltage change. As shown in the figure, the voltage state after the soft start control of the switching element S1 and the switching element S3 when S4 is fixed is V1 = V0 = V2 = Vbatt.

  At this time, if the switching element S2 is soft-start controlled, a current flows through the path of the operation mode C when S2 is on. V0 gradually decreases to a state of V1 + V0 = V2, that is, a state of V1 = V2 = Vbatt and V0 = 0V. Therefore, in this case, an abnormality such as an overcurrent or an overvoltage does not occur, that is, it is possible to avoid an abnormality such as an overcurrent or an overvoltage.

  Note that when the soft start control is performed on the switching element S2 when S1 is fixed to OFF, as described above, V1 = V2 and V0 = 0V. Since no current flows in the circuit, abnormalities such as overcurrent do not occur and the voltage state does not change. Further, when S2 is soft-start controlled when the V0 sensor is stuck abnormally, the voltage changes from the state of V1 = V0 = V2 = Vbatt as described above. The current path and voltage change in this case are the same as those in FIGS. The state of V1 = V2 = Vbatt and V0 = 0V is established, and an abnormality such as an overcurrent does not occur, that is, an abnormality such as an overcurrent can be avoided.

  As described above, when the V0 voltage abnormality occurs, when the switching element S2 and the switching element S3 are soft-start controlled and then the switching element S2 is soft-start controlled, A new abnormality occurs. Therefore, the S1 on-fixing abnormality or the S3 on-fixing abnormality can be determined from the seven types of abnormality included in the V0 voltage abnormality. In addition to the switching element S2, for example, the switching element S4 may be simultaneously soft-start controlled.

  In this case, when S1 is on, the voltage change shown in FIG. 32A and the current change shown in FIG. 32B are made. For this reason, a new abnormality occurs and it is possible to determine the S1 ON sticking. When S3 is on, a short circuit current flows through the path shown in FIG. For this reason, a new abnormality occurs and it is possible to determine the S3 on sticking. Finally, after performing soft start control of the switching element S1 and the switching element S3, the switching element S2 is soft start controlled, and then the switching element S1 is soft start controlled. Thereby, S4 ON sticking abnormality is determined.

  Next, in the embodiment disclosed in the present application, the current path and voltage change when the switching element S1 is soft-start controlled when S4 is fixed on will be described with reference to the drawings. FIG. 37 is a circuit diagram showing a current path. On the other hand, FIG. 38 is an explanatory diagram showing a voltage change. As shown in the figure, the soft start control is performed on the switching element S1 and the switching element S3 when S4 is fixed on.

  Thereafter, the voltage state when the switching element S2 is soft-start controlled is V1 = V0 = V2 = Vbatt. At this time, when the soft start control of the switching element S1 is performed, a short circuit occurs along the path C2-> S4-> C0-> S1-> C2 when S1 is on. As a result, a short circuit current flows through the path. Therefore, similarly to the description with reference to FIGS. 33 and 34, it is possible to determine the S4 ON sticking abnormality.

  In addition, when the switching element S1 is soft-started when S2 is fixed off, as described above, the state is V1 = V0 = V2. Since no current flows in the circuit, no abnormality such as overcurrent occurs and the voltage state does not change. Further, when the switching element S1 is soft-start controlled when the V0 sensor is stuck abnormally, the voltage changes from the state of V1 = V2 = Vbatt and V0 = 0V as described above. In this case, a current flows through the path of the operation mode B as in FIGS. V1 = V0 = V2 = Vbatt, and no abnormality such as overcurrent occurs.

  As described above, when the V0 voltage abnormality occurs, the switching element S1 and the switching element S3 are soft-start controlled, then the switching element S2 is soft-start controlled, and then the switching element S1 is soft-start controlled. In the case of S4 on fixation, a new abnormality occurs. Therefore, the S4 ON sticking abnormality can be determined from the seven types of abnormality included in the V0 voltage abnormality.

  In addition to the switching element S1, for example, the switching element S3 may be simultaneously soft-start controlled. Further, the switching element S1 may be turned on, or the switching element S1 and the switching element S3 may be turned on. In these cases, since a short-circuit current flows through the path shown in FIG. 37, it is possible to determine the S4 ON sticking abnormality.

  FIG. 39 is a flowchart for explaining the abnormality type determination process in the first embodiment disclosed in the present application. This process is performed when a V0 voltage abnormality has occurred. As shown in the drawing, first, the gates of the switching elements constituting the first semiconductor switching circuit 2a to the fourth semiconductor switching circuit 2d and the gates of the switching elements constituting the motor driver 51 are all turned off (step S21). Next, it is determined whether V2 is equal to or less than V2 threshold 1 (first threshold) (step S22). If the determination condition is satisfied, the process proceeds to step S23, and if not, the process is repeated. This process is performed to prevent overvoltage breakdown of the motor driver 51.

  The V2 threshold value 1 (first threshold value) is determined so that the switching elements constituting the motor driver 51 are not destroyed in consideration of a surge voltage or the like. Next, the motor driver 51 and the motor 102 are controlled so that the power transmission is in the power running direction (step S23). This process is performed to discharge the high-voltage capacitor 4. Specifically, the controller 6 turns on all the gates of the switching elements constituting the motor driver 51.

  Next, it is determined whether V2 is equal to or less than V2 threshold 2 (second threshold) (step S24). If the determination condition is satisfied, the process proceeds to step S25. If the determination condition is not satisfied, this process is repeated. This process is performed to prevent overvoltage breakdown of the first semiconductor switching circuit 2a to the fourth semiconductor switching circuit 2d. The V2 threshold 2 (second threshold) is determined so that the semiconductor switching circuit is not destroyed in consideration of a surge voltage or the like.

  Next, soft start control is performed on the switching element S1 and the switching element S3 (step S25). In other words, S1_Duty and S3_Duty are divided by a predetermined change amount. The gate signals of the second semiconductor switching circuit 2b and the fourth semiconductor switching circuit 2d that are not subjected to the soft start control are turned off. The purpose of this process is to generate an abnormality in the case of S2 on fixation, and to charge the intermediate capacitor 5 (C0) so that a short-circuit current can be generated during the second soft start control described later to identify S3 on fixation It is to be.

  The soft start time is set so that the component with the smallest rated current will not be destroyed. The set value is determined in advance by simulation or the like so that the current flowing between the capacitors is less than the rated current of the component. In addition, the flowing current increases in accordance with the potential difference between the capacitors. For this reason, it is preferable to calculate the soft start time based on the assumed maximum potential difference condition, simulation, or the like.

  Next, V2 is V2 threshold 3 (overvoltage threshold; third threshold) or higher, IL is IL threshold (overcurrent threshold) or higher, and a short-circuit current is generated (current exceeding the short-circuit current threshold flows). It is determined whether or not established (step S26). When the abnormality determination condition in step S26 is satisfied, the process proceeds to step S27, and the on-fixation abnormality of the second semiconductor switching circuit 2b is determined. If the abnormality determination condition is not satisfied, step S26 is repeated until S1_Duty and S3_Duty reach 100% (until step S28 is satisfied). When S1_Duty and S3_Duty become 100%, switching element S1 and switching element S3 are turned off (step S29).

  Next, at least switching element S2 among switching elements S1 (first switching element) to switching element S4 (fourth switching element) is subjected to soft start control (step S30). Gate signals of the first semiconductor switching circuit 2a, the third semiconductor switching circuit 2c, and the fourth semiconductor switching circuit 2d that are not subjected to the soft start control are turned off. The purpose of this process is to generate an abnormality in the case of S1 on-fixing or S3 on-fixing, and to generate a short-circuit current in the third soft start control to be described later so that S4 on-fixing can be specified. 5 (C0) is discharged. The soft start time is determined in the same manner as described above.

  Next, V2 is V2 threshold 3 (overvoltage threshold; third threshold) or higher, IL is IL threshold (overcurrent threshold) or higher, and a short-circuit current is generated (current exceeding the short-circuit current threshold flows). It is determined whether or not it is established (step S31). When the abnormality determination condition of step S31 is satisfied, the process proceeds to step S32, and the on-fixation abnormality of the first semiconductor switching circuit 2a and the third semiconductor switching circuit 2c is determined. If the abnormality determination condition is not satisfied, step S31 is repeated until S2_Duty reaches 100% (until step S33 is satisfied).

  When S2_Duty becomes 100%, the switching element S2 is turned off (step S34). Next, at least switching element S1 among switching elements S1 (first switching element) to switching element S4 (fourth switching element) is subjected to soft start control (step S35). The gate signals from the second semiconductor switching circuit to the fourth semiconductor switching circuit that are not subjected to the soft start control are turned off. The purpose of this process is to generate an abnormality when S4 is on. The soft start time is determined in the same manner as described above.

  Next, it is determined whether or not a short-circuit current is generated (step S36). If the determination condition is satisfied, the process proceeds to step S37, and the on-fixation abnormality of the fourth semiconductor switching circuit 2d is determined. If the determination condition is not satisfied, step S36 is repeated until S1_Duty reaches 100% (until step S38 is satisfied). When S1_Duty becomes 100%, the semiconductor switching circuit S1 is turned off (step S39). Finally, S1 off sticking, S2 off sticking, and V0 sensor sticking abnormality are determined (step S40).

  As described above, in the power conversion device according to this embodiment, the abnormality of the voltage of the intermediate capacitor (V0 voltage) is determined by determining whether or not the detection value of the first voltage sensor deviates from the predetermined target value by a predetermined value or more. Abnormal) can be determined. Further, by determining whether an overvoltage, an overcurrent, or a short-circuit current occurs when soft start control is performed on the first semiconductor switching circuit and the third semiconductor switching circuit when the V0 voltage abnormality occurs, An on-fixation abnormality of the second semiconductor switching circuit can be determined.

  Note that the overvoltage does not occur when the semiconductor switching circuit is simply turned on rather than soft-start controlled. Therefore, by performing the soft start control, a new abnormality can be generated and the abnormality detection rate can be increased as compared with the case where the power is simply turned on. Further, if the above-described abnormality does not occur when the first semiconductor switching circuit and the third semiconductor switching circuit are soft-start controlled, at least the second semiconductor switching circuit is soft-start controlled. At this time, it is possible to determine whether the first semiconductor switching circuit or the third semiconductor switching circuit is on-fixed by determining whether or not the abnormality occurs.

  Further, at least when the second semiconductor switching circuit is soft-start controlled, if the abnormality does not occur, at least the first semiconductor switching circuit is soft-start controlled. At that time, by determining whether or not a short circuit abnormality occurs, it is possible to determine an on-fixation abnormality of the fourth semiconductor switching circuit. Further, if the abnormality does not occur at least when the first semiconductor switching circuit is soft-start controlled, it is determined whether the first semiconductor switching circuit is stuck off, the second semiconductor switching circuit is stuck off, or the V0 sensor is stuck abnormally. it can.

  In addition, after determining the V0 voltage abnormality, the high voltage side capacitor and the motor driver are controlled by controlling the motor and the motor driver so as to discharge the charge of the high voltage side capacitor when the detection value of the second voltage sensor is equal to or lower than the predetermined value. Can be prevented. Further, it is possible to determine an abnormality by detecting that the high-voltage side voltage increases in the event of an abnormality. Furthermore, after determining the V0 voltage abnormality, when the detection value of the second voltage sensor is equal to or lower than a predetermined value, at least one of the first semiconductor switching circuit to the fourth semiconductor switching circuit is turned on, thereby causing the first semiconductor switching The overvoltage breakdown of the circuit to the fourth semiconductor switching circuit can be prevented.

  Therefore, the power conversion device disclosed in the present application includes a first switching element having a negative electrode side terminal, a positive electrode side terminal, and a gate, and the negative electrode side terminal connected to the negative electrode side of the DC power supply, and a negative electrode side terminal. A second switching element connected to the positive terminal of the first switching element, a negative terminal, a positive terminal, and a gate, The negative electrode side terminal has a third switching element connected to the positive electrode side terminal of the second switching element, a negative electrode side terminal, a positive electrode side terminal, and a gate, and the negative electrode side terminal of the third switching element A fourth switching element connected to the positive terminal, a reactor connected in series with the DC power source, an input side capacitor connected in parallel with the DC power source, An intermediate capacitor connected to the negative terminal of the second switching element and the other end connected to the positive terminal of the third switching element; one end connected to the negative terminal of the first switching element; An output-side capacitor connected to a positive-side terminal of the fourth switching element; a current sensor that detects a current flowing through the reactor; a first voltage sensor that detects a voltage across the intermediate capacitor; and the output-side capacitor A second voltage sensor for detecting a voltage at both ends, a driver having a switching element and connected to both ends of the output-side capacitor, and calculating a target value of the intermediate capacitor from a detection value of the second voltage sensor; The calculated target value of the intermediate capacitor matches the detected value of the first voltage sensor. A controller for controlling an on-time ratio of the first switching element, an on-time ratio of the second switching element, an on-time ratio of the third switching element, and an on-time ratio of the fourth switching element. A difference between a target value of the intermediate capacitor and a detection value of the first voltage sensor is obtained, and it is determined that a voltage abnormality has occurred when an absolute value of the difference is larger than an abnormality determination threshold value. Is.

  Further, the power conversion device disclosed in the present application is a power conversion device including a semiconductor switching circuit, a capacitor that performs a charge / discharge operation by switching of the semiconductor switching circuit, and a voltage detection unit that detects a voltage of the capacitor. In the power converter, the abnormality of the voltage of the capacitor is determined when a detection value of the voltage detection unit deviates from a predetermined target value by a predetermined value or more.

  The power converter disclosed in the present application has a low voltage side connected to a DC power supply, a regenerative load connected to the output side, a low voltage side capacitor that holds a low voltage side voltage, and a negative electrode that is a negative electrode of the low voltage side capacitor. A high-voltage side capacitor that holds a high-voltage side voltage, a negative terminal is connected to the negative electrode of the low-voltage side capacitor, a negative terminal is connected to the other end of the first semiconductor switching circuit, and the other end Is connected to the positive electrode of the input-side capacitor via the reactor, one end is connected to the other end of the second semiconductor switching circuit, the other end is connected to the third semiconductor switching circuit. A fourth semiconductor switching circuit connected to the other end of the circuit, the other end connected to the positive electrode of the high-voltage side capacitor; An intermediate capacitor connected to a connection point between the first semiconductor switching circuit and the second semiconductor switching circuit and connected to a connection point between the third semiconductor switching circuit and the fourth semiconductor switching circuit, and a voltage of the intermediate capacitor are detected. In the power converter including a controller that controls the voltage of the intermediate capacitor to a predetermined target value by controlling an on-time ratio of the first voltage sensor and the first to fourth semiconductor switching circuits, In the power converter, the abnormality of the voltage of the intermediate capacitor is determined when a detected value deviates from a predetermined target value by a predetermined value or more.

  The controller is characterized in that, after determining an abnormality in the voltage of the intermediate capacitor, when a predetermined semiconductor switching circuit is turned on, if a predetermined abnormality occurs, the controller identifies an abnormal location. In addition, a load driving unit that drives the load is provided, and the controller is capable of controlling the load and the load driving unit, and discharges the charge of the high-voltage side capacitor after determining an abnormality in the voltage of the intermediate capacitor. As described above, the load and the load driving unit are controlled.

  The controller further comprises second voltage detection means for detecting the voltage of the high-voltage side capacitor, and the controller discharges the charge of the high-voltage side capacitor when the detected value of the voltage detection means is a predetermined value or less. The load and the load driving unit are controlled. The controller determines an on-fixation abnormality of the second semiconductor switching circuit when a predetermined abnormality occurs when the first semiconductor switching circuit and the third semiconductor switching circuit are soft-start controlled. Is.

  Further, when a predetermined abnormality does not occur in the power conversion device, at least the second semiconductor switching circuit among the first to fourth semiconductor switching circuits is soft-start controlled, and when a predetermined abnormality occurs, the first It is determined that one semiconductor switching circuit or the third semiconductor switching circuit is in an on-fixing abnormality. When the predetermined abnormality does not occur in the power conversion device described above, at least the first semiconductor switching circuit is turned on among the first to fourth semiconductor switching circuits, and when the predetermined abnormality occurs, the fourth The semiconductor switching circuit is determined to be on-fixed abnormality.

  Further, at least the first semiconductor switching circuit among the first to fourth semiconductor switching circuits is subjected to soft start control, and when a predetermined abnormality occurs, it is determined that the fourth semiconductor switching circuit is on-fixed abnormality. It is a feature. When a predetermined abnormality does not occur in the power conversion device described above, it is determined that the first semiconductor switching circuit is off-fixed abnormally, the second semiconductor switching circuit is off-fixed abnormally, or the first voltage sensor is fixed abnormally It is characterized by.

  The power conversion device further includes a reactor current detection unit that detects a current flowing through the reactor, and identifies an abnormal location when a detection value of the current detection unit is equal to or greater than a predetermined value. First to fourth current detection means for detecting a current flowing in each of the first to fourth semiconductor switching circuits is provided, and an abnormal location is specified when at least one of the detection values of the current detection means is equal to or greater than a predetermined value. It is the power converter device characterized by the above. The power conversion device includes a second voltage detection unit that detects a voltage of the high-voltage side capacitor, and identifies an abnormal portion when a detection value of the voltage detection unit is a predetermined value or more.

Embodiment 2. FIG.
Hereinafter, the power converter concerning Embodiment 2 indicated by this application is explained. The circuit configuration of the power conversion device according to the present embodiment is the same as the circuit configuration shown in FIG. Moreover, since the abnormality detection process until it determines V0 voltage abnormality is the same as that of Embodiment 1, description is abbreviate | omitted.

  FIG. 40 is a flowchart for explaining the abnormality type determination process according to the second embodiment disclosed in the present application. This process is performed when a V0 voltage abnormality has occurred. Since the processing from step S21 to step S24 is the same as that of the first embodiment, the description thereof will be omitted, and the description will be made from step S101. First, at least one of the switching elements S1 to S4 is turned on (step S101). Next, it is determined whether or not any of the conditions that IL is greater than or equal to the IL threshold (overcurrent threshold) and a short-circuit current occurs (a current greater than the short-circuit current threshold flows) is satisfied (step S102).

  When the determination condition of step S102 is satisfied, the process proceeds to step S103, and any of the on-fixing abnormality of the switching element S1 to the switching element S4 or the V0 sensor fixing abnormality is determined. If the determination condition is not satisfied, all the gates are turned off (step S104). Finally, V0 voltage abnormality is determined (step S105). In addition, when the V0 voltage abnormality has occurred, the current path and voltage change when switching element S1 to switching element S4 are turned on are as follows.

  First, the current path and voltage change when S1 is on will be described. When the switching element S2 is turned on when S1 is fixed, current continues to flow along the path C1 → L1 → S2 → S1 shown in FIGS. 25A and 25B. Therefore, IL ≧ IL threshold (overcurrent threshold) or a short-circuit current is generated, and it is possible to determine an on-fixation abnormality.

  Further, when the switching element S3 is turned on when S1 is fixed, current continues to flow until V0 = V1 in the path C0 → S3 → L1 → C1 → S1 → C0 shown in FIG. For this reason, the on-fixation abnormality can be determined as described above. Further, when switching element S4 is turned on when S1 is fixed, no current flows because the voltage state before turning on switching element S4 is V0 = V2. Therefore, no abnormality such as overcurrent occurs.

  Next, a description will be given of when S2 is on. When the switching element S1 is turned on when S2 is fixed, current continues to flow through the path C1-> L1-> S2-> S1 shown in FIGS. 25A and 25B. Therefore, IL ≧ IL threshold (overcurrent threshold) or a short-circuit current is generated, and it is possible to determine an on-fixing abnormality. Further, when the switching element S3 is turned on when S2 is fixed, no current flows because the voltage state before turning on the switching element S3 is V0 = 0V.

  Therefore, no abnormality such as overcurrent occurs. Further, when the switching element S4 is turned on when S2 is fixed, the current continues to flow until V1 + V0 = V2 through the path C2-> S4-> C0-> S2-> L1-> C1-> C2. This route is a route having a current direction opposite to that shown in FIG. For this reason, the on-fixation abnormality can be determined as described above.

  Next, the S3 ON sticking abnormality will be described. When the switching element S1 is turned on when S3 is fixed, current continues to flow until V0 = V1 in the path C1-> L1-> S3-> C0-> S1-> C1 shown in FIG. Therefore, IL ≧ IL threshold (overcurrent threshold) or a short-circuit current is generated, and it is possible to determine an on-fixation abnormality.

  Further, when the switching element S2 is turned on when S3 is fixed, no current flows because the voltage state before the switching element S2 is turned on is V0 = 0V. Therefore, no abnormality such as overcurrent occurs. Further, when the switching element S4 is turned on when S3 is fixed, current continues to flow until V2 = V1 in the path C2-> S4-> S3-> L1-> C1-> C2 shown in FIGS. 29A and 29B. For this reason, the on-fixation abnormality can be determined as described above.

  Next, a description will be given of when the S4 is on. When the switching element S1 is turned on when S4 is fixed, no current flows because the voltage state before turning on the switching element S1 is V0 = V2. Therefore, no abnormality such as overcurrent occurs. Further, when the switching element S2 is turned on when S4 is fixed, current continues to flow until V1 + V0 = V2 in the path C1, L1, S2, C0, S4, C2, and C1 shown in FIG.

  Therefore, IL ≧ IL threshold (overcurrent threshold) or a short-circuit current is generated, and it is possible to determine an on-fixation abnormality. Furthermore, when the switching element S3 is turned on when S4 is fixed, current continues to flow until V2 = V1 in the path C2-> S4-> S3-> L1-> C1-> C2 shown in FIGS. 29A and 29B. For this reason, the on-fixation abnormality can be determined as described above.

  Next, a description will be given of when the V0 sensor is stuck abnormally. In the case of sticking abnormality in which V0 detection value> V0 target value, the same as in the above S3 ON sticking. When the switching element S1 or the switching element S4 is turned on, IL ≧ IL threshold (overcurrent threshold) or a short-circuit current is generated, and it is possible to determine an on-fixing abnormality. In the case of a sticking abnormality in which V0 detection value <V0 target value, the same as in the above-described S4 ON sticking. When the switching element S2 or the switching element S3 is turned on, IL ≧ IL threshold (overcurrent threshold) or a short-circuit current is generated, and it is possible to determine an on-fixing abnormality.

  Next, the S1 off sticking abnormality will be described. The voltage states in this case are V1 = V2 and V0 = 0V. When the switching element S2 is turned on when S1 is fixed off, since V1 + V0 = V2 has already been established, no current flows and no abnormality such as overcurrent occurs. Further, when the switching element S3 is turned on, there is no current path, and therefore no abnormality such as overcurrent occurs. Further, when the switching element S4 is turned on, since V1 + V0 = V2 has already been established, no current flows and no abnormality such as overcurrent occurs.

  Finally, the S2 off sticking abnormality will be described. The voltage state in this case is V1 = V0 = V2. When switching element S1 or switching element S3 is turned on when S2 is fixed, V0 = V1 has already been established, so that no current flows and no abnormality such as overcurrent occurs. Further, when the switching element S4 is turned on, there is no current path, so that no abnormality such as overcurrent occurs.

  Although the case where any one of the switching elements S1 to S4 is turned on has been described, the switching elements S1 and S3 may be turned on simultaneously. In this case, the current path and the voltage change are not different from the case where either the switching element S1 or the switching element S3 is turned on. Similarly, since the current path and the voltage change do not change from when either switching element S2 or switching element S4 is turned on, switching element S2 and switching element S4 may be simultaneously turned on.

  As described above, in the power conversion device according to the present embodiment, when a V0 voltage abnormality occurs, an overcurrent or a current is generated when at least one of the first semiconductor switching circuit to the fourth semiconductor switching circuit is turned on. By determining whether or not a short-circuit current occurs, it is possible to determine whether the first semiconductor switching circuit to the fourth semiconductor switching circuit is on or abnormally fixed.

  The power conversion device disclosed in the present embodiment includes second voltage detection means for detecting the voltage of the high-voltage side capacitor, and the controller is configured such that when the detection value of the voltage detection means is equal to or less than a predetermined value, At least one of the first to fourth semiconductor switching circuits is turned on. The controller, when a predetermined abnormality occurs when at least one of the first to fourth semiconductor switching circuits is turned on, the on-fixing abnormality of any of the first to fourth semiconductor switching circuits or the first It is a power converter characterized by determining that the voltage sensor is stuck abnormally.

Embodiment 3 FIG.
Hereinafter, the power converter concerning Embodiment 3 indicated by this application is explained. The circuit configuration of the power conversion device according to the present embodiment is the same as the circuit configuration shown in FIG. Further, the abnormality detection process until the V0 voltage abnormality is determined is the same as that in the first embodiment, and thus the description thereof is omitted.

  FIG. 41 is a flowchart for explaining the abnormality type determination processing according to the third embodiment disclosed in the present application. This process is performed when a V0 voltage abnormality has occurred. Since the processing from step S21 to step S24 is the same as that of the first embodiment, description thereof will be omitted, and description will be given from step S106. First, at least one of the switching elements S1 to S4 is soft-start controlled (step S106). The gate signal of the semiconductor switching circuit that does not perform the soft start control is turned off.

  Next, V2 is V2 threshold 3 (overvoltage threshold; third threshold) or higher, IL is IL threshold (overcurrent threshold) or higher, and a short-circuit current is generated (current exceeding the short-circuit current threshold flows). It is determined whether or not established (step S26). When the abnormality determination condition in step S26 is satisfied, the process proceeds to step S108, and the S1 on fixing abnormality or the S2 on fixing abnormality is determined. If the abnormality determination condition is not satisfied, step S26 is repeated until the duty (ON time ratio) of the gate signal of the semiconductor switching circuit that has performed the soft start control reaches 100% (until step S107 is satisfied). When the duty (on time ratio) reaches 100%, all the gates are turned off (step S104). Finally, V0 voltage abnormality is determined (step S105).

  In addition, when the V0 voltage abnormality occurs, the current path and the voltage change when the switching element S1 or the switching element S2 is soft-start controlled are as follows. First, the current path and voltage change when S1 is on will be described. When the switching element S2 is soft-start controlled when the S1 is fixed, the S1 ON fixed abnormality can be determined by the occurrence of an increase in V2 or an increase in IL as in the description of FIGS. 26A and 26B.

  In addition, when the switching element S3 is soft-start controlled when S1 is fixed, a current gradually flows until V0 = V1 in the path C0 → S3 → L1 → C1 → S1 → C0 shown in FIG. Therefore, no abnormality such as overcurrent occurs. Further, when S4 is soft-start controlled when S1 is fixed, no current flows because the voltage state before turning on the switching element S4 is V0 = V2. Therefore, no abnormality such as overcurrent occurs.

  Next, the S2 ON sticking abnormality will be described. When the soft start control of the switching element S1 is performed when S2 is fixed, an S2 ON fixing abnormality can be determined by occurrence of an increase in V2 or an increase in IL as described above. Further, when the switching element S3 is soft-start controlled when S2 is fixed, no current flows because the voltage state before the switching element S3 is turned on is V0 = 0V. Therefore, no abnormality such as overcurrent occurs. Further, when the switching element S4 is soft-start controlled when S2 is fixed, current flows gradually through the path C2, S4, C0, S2, L1, C1, and C2 until V1 + V0 = V2. This route is a route having a current direction opposite to that shown in FIG. Therefore, no abnormality such as overcurrent occurs.

  Next, the S3 ON sticking abnormality will be described. When the soft start control of the switching element S1 is performed when S3 is fixed, abnormalities such as overcurrent or overvoltage do not occur as in the description of FIGS. In addition, when the switching element S2 is soft-start controlled when S3 is fixed, no current flows because the voltage state before the switching element S2 is turned on is V0 = 0V. Therefore, no abnormality such as overcurrent occurs. Further, when the soft start control is performed on the switching element S4 when S3 is fixed, current flows gradually until V2 = V1 in the path C2-> S4-> S3-> L1-> C1-> C2 shown in FIGS. 29A and 29B. Therefore, no abnormality such as overcurrent occurs.

  Next, the S4 ON sticking abnormality will be described. When the switching element S1 is soft-start controlled when S4 is fixed on, no current flows because the voltage state before the switching element S1 is turned on is V0 = V2. Therefore, no abnormality such as overcurrent occurs. Further, when the switching element S2 is soft-start controlled when S4 is fixed, current flows gradually through the path C1, L1, S2, C0, S4, C2, and C1 shown in FIG. 35 until V1 + V0 = V2. Therefore, no abnormality such as overcurrent occurs.

  Further, when the soft start control is performed on the switching element S3 when S4 is fixed, current flows gradually until V2 = V1 in the path C2-> S4-> S3-> L1-> C1-> C2 shown in FIGS. 29A and 29B. Accordingly, when the switching element S3 is soft-start controlled when S4 is fixed, abnormality such as overcurrent does not occur.

  Next, the S1 off sticking abnormality, the S2 off sticking abnormality, or the V0 sensor sticking abnormality will be described. As described above, when performing the soft start control, when switching from the operation mode A to the operation mode D, when the switching element S1 and the switching element S4 are turned on, the switching element S2 and the switching element S3 are turned on. In any of the operations, an abnormality such as an increase in V2, an increase in IL, or a short-circuit current occurs. In the case of S1 off fixation, S2 off fixation, or V0 sensor fixation, if any one of the switching elements S1 to S4 is soft-start controlled, the operation in which the above abnormality does not occur.

  Although the case where any one of the switching elements S1 to S4 is subjected to the soft start control has been described, the switching elements S1 and S3 may be simultaneously subjected to the soft start control. In this case, the current path and the voltage change are not different from the case where either the switching element S1 or the switching element S3 is soft-start controlled. Similarly, since either the switching element S2 or the switching element S4 is soft-start controlled and the current path and the voltage change are not changed, the switching element S2 and the switching element S4 may be simultaneously soft-start controlled.

  As described above, in the power conversion device according to the present embodiment, when a V0 voltage abnormality occurs, an overvoltage occurs when soft start control is performed on at least one of the first semiconductor switching circuit to the fourth semiconductor switching circuit. In addition, by determining whether an overcurrent or a short-circuit current is generated, it is possible to determine whether the first semiconductor switching circuit or the second semiconductor switching circuit is on-fixed.

  In the above-described embodiment, it is conceivable to provide the controller 6 with an abnormality counter. When the abnormality determination condition is satisfied, the abnormality counter is counted up. When the count value of the abnormality counter exceeds the threshold, determination of V0 voltage abnormality and each on-fixation abnormality is performed. Thereby, instantaneous abnormality determination can be excluded and reliable abnormality determination can be performed.

  In the power conversion device disclosed in the present embodiment, the controller performs soft start control that gradually changes at least one on-time ratio of the first to fourth semiconductor switching circuits from 0% to 100%. The power conversion device is characterized in that when a predetermined abnormality occurs sometimes, the first or second semiconductor switching circuit is determined to be on-fixed abnormality.

  Furthermore, in the above-described embodiment, the first semiconductor switching circuit 2a to the fourth semiconductor switching circuit 2d have been described as an example configured by an IGBT and a diode. However, instead of the IGBT, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), It is good also as JFET (Junction Field Effect Transistor).

  When a MOSFET is used for the first semiconductor switching circuit 2a to the fourth semiconductor switching circuit 2d, a body diode of the MOSFET may be used instead of the diode. The first semiconductor switching circuit 2a to the fourth semiconductor switching circuit 2d may be formed of a wide band gap semiconductor having a band gap larger than that of silicon, for example, silicon carbide (SiC), a gallium nitride material, or diamond. .

  Note that the technology disclosed in the specification of the present application is not limited to the above-described first to third embodiments, and it is needless to say that all possible combinations of these embodiments are included. In addition, the technology disclosed in the specification of the present application can be freely combined with each other within the scope of the disclosed technical idea, or can be appropriately modified or omitted.

  DESCRIPTION OF SYMBOLS 1 Reactor, 2a 1st semiconductor switching circuit, 2b 2nd semiconductor switching circuit, 2c 3rd semiconductor switching circuit, 2d 4th semiconductor switching circuit, 3 Low voltage side capacitor, 4 High voltage side capacitor, 5 Intermediate capacitor, 6 Controller, 6a CPU 6b Memory device 7 Current sensor 8 First voltage sensor 9 Second voltage sensor 50 DC / DC converter 51 Motor driver 100 Power converter 101 DC power supply 102 Motor

Claims (16)

A first switching element having a negative electrode side terminal, a positive electrode side terminal, and a gate, the negative electrode side terminal being connected to the negative electrode side of the DC power supply;
A second switching element having a negative electrode side terminal, a positive electrode side terminal, and a gate, the negative electrode side terminal being connected to the positive electrode side terminal of the first switching element;
A third switching element having a negative electrode side terminal, a positive electrode side terminal, and a gate, the negative electrode side terminal being connected to the positive electrode side terminal of the second switching element;
A fourth switching element having a negative electrode side terminal, a positive electrode side terminal, and a gate, the negative electrode side terminal being connected to the positive electrode side terminal of the third switching element;
A reactor connected in series with the DC power source;
An input side capacitor connected in parallel with the DC power source;
An intermediate capacitor having one end connected to the negative terminal of the second switching element and the other end connected to the positive terminal of the third switching element;
An output-side capacitor having one end connected to the negative-side terminal of the first switching element and the other end connected to the positive-side terminal of the fourth switching element;
A current sensor for detecting a current flowing through the reactor;
A first voltage sensor for detecting a voltage across the intermediate capacitor;
A second voltage sensor for detecting a voltage across the output-side capacitor;
A driver having a switching element and connected to both ends of the output-side capacitor;
The target value of the intermediate capacitor is calculated from the detection value of the second voltage sensor, and the ON time of the first switching element is set so that the calculated target value of the intermediate capacitor matches the detection value of the first voltage sensor. A controller for controlling a ratio, an on-time ratio of the second switching element, an on-time ratio of the third switching element, and an on-time ratio of the fourth switching element,
The controller is
A power obtained by calculating a difference between a target value of the intermediate capacitor and a detection value of the first voltage sensor, and determining that a voltage abnormality has occurred when an absolute value of the difference is larger than an abnormality determination threshold value. Conversion device. If the controller determines that a voltage abnormality has occurred,
Turning off the gate of the first switching element, the gate of the second switching element, the gate of the third switching element, the gate of the fourth switching element, and the gate of the switching element included in the driver;
A first determination operation for comparing the detection value of the second voltage sensor and the first threshold is performed,
2. The power conversion device according to claim 1, wherein when it is determined that a detection value of the second voltage sensor is larger than the first threshold, the first determination operation is performed again. The controller performs a first determination operation for comparing the detection value of the second voltage sensor and the first threshold value,
When it is determined that the detection value of the second voltage sensor is smaller than the first threshold, the gate of the switching element of the driver is turned on,
Performing a second determination operation for comparing a detection value of the second voltage sensor with a second threshold;
The power converter according to claim 2, wherein when the detection value of the second voltage sensor is determined to be larger than the second threshold, the second determination operation is performed again. When the controller determines that the detection value of the second voltage sensor is smaller than the second threshold as a result of performing the second determination operation,
The power conversion device according to claim 3, wherein soft start control of the first switching element and soft start control of the third switching element are performed. The controller performs a soft start control of the first switching element and a soft start control of the third switching element,
5. The power conversion device according to claim 4, wherein when an abnormality corresponding to the first abnormality determination condition occurs, it is determined that an on-fixation abnormality of the second switching element has occurred. When the controller performs soft start control of the first switching element and soft start control of the third switching element,
5. The power conversion device according to claim 4, wherein when the abnormality corresponding to the first abnormality determination condition does not occur, soft start control of the second switching element is performed. The controller performs a soft start control of the second switching element,
The abnormality according to claim 6, wherein when an abnormality corresponding to the first abnormality determination condition occurs, it is determined that an on-fixation abnormality of the first switching element or an on-fixation abnormality of the third switching element has occurred. Power conversion device. In the case where the controller does not generate an abnormality corresponding to the first abnormality determination condition when performing the soft start control of the second switching element,
The power conversion apparatus according to claim 6, wherein soft start control of the first switching element is performed.   9. The controller according to claim 8, wherein the controller determines that an on-fixation abnormality of the fourth switching element has occurred when a short-circuit current occurs as a result of performing the soft start control of the first switching element. 9. The power converter described. When the controller performs soft start control of the first switching element and no short-circuit current occurs,
9. The power according to claim 8, wherein it is determined that any one of an off-fixing abnormality of the first switching element, an off-fixing abnormality of the second switching element, and a fixing abnormality of the first voltage sensor has occurred. Conversion device. When the controller determines that the detection value of the second voltage sensor is smaller than the second threshold as a result of performing the second determination operation,
The power converter according to claim 3, wherein at least one of the first switching element, the second switching element, the third switching element, and the fourth switching element is turned on. The controller has turned on at least one of the first switching element, the second switching element, the third switching element, and the fourth switching element,
When an abnormality corresponding to the second abnormality determination condition occurs, the first switching element is turned on, the second switching element is turned on, the third switching element is turned on, and the fourth switching element is turned on. The power converter according to claim 11, wherein it is determined that any one of an abnormality and a fixing abnormality of the first voltage sensor has occurred. When the controller determines that the detection value of the second voltage sensor is smaller than the second threshold as a result of performing the second determination operation,
4. The power conversion device according to claim 3, wherein at least one soft start control is performed among the first switching element, the second switching element, the third switching element, and the fourth switching element. 5. The controller performs at least one soft start control among the first switching element, the second switching element, the third switching element, and the fourth switching element, and as a result, the abnormality corresponding to the first abnormality determination condition If this happens,
The power conversion device according to claim 13, wherein it is determined that an on-fixing abnormality of the first switching element or an on-fixing abnormality of the second switching element has occurred. In the abnormality corresponding to the first abnormality determination condition,
The detection value of the second voltage sensor is larger than the third threshold;
When the detected value of the current sensor is larger than the overcurrent threshold,
When a short-circuit current occurs,
Is included, The power converter device of any one of Claim 5, 6, 14 characterized by the above-mentioned. In the abnormality corresponding to the second abnormality determination condition,
When the detected value of the current sensor is larger than the overcurrent threshold,
When a short-circuit current occurs,
The power conversion device according to claim 12, wherein:

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