JP2019176080A - Conduction inspection device, prober, and static eliminator - Google Patents

Abstract

An object of the present invention is to provide a continuity inspection device, a prober, and a static eliminator capable of automatically and easily inspecting the presence or absence of continuity of a chuck lead wire. The semiconductor device is electrically connected to a support surface of a wafer provided on a wafer chuck of a prober, the conductive support surface being in contact with a back electrode of a semiconductor chip formed on a back surface of the wafer. In the wiring continuity inspection device, a first component that is one of the first relay and the first resistor connected to the other end opposite to the one end of the wiring, and a first component connected to the first component and grounded. (1) a second component that is the other of the first relay and the first resistor, an additional wire connected to the support surface, and a current loop forming unit connected to the additional wire, the power loop including at least a power source, A current loop forming unit that forms a current loop including at least the first component, the second component, and the power supply, and a determination unit that determines whether a current from the power supply flows through the current loop. [Selection] Figure 2

Description

  The present invention relates to a continuity inspection apparatus, a prober, and a charge removal apparatus used in a wafer test system for inspecting electrical characteristics of a plurality of semiconductor chips formed on a wafer.

  A plurality of semiconductor chips having the same electric element circuit are formed on the surface of a wafer (also referred to as a semiconductor wafer). Before the wafer is cut into individual semiconductor chips by a dicer, the electrical characteristics of the individual semiconductor chips are inspected by a wafer test system (see Patent Document 1 and Patent Document 2). This wafer test system includes a prober and a tester.

  The prober moves the wafer chuck and a probe card having a probe (also referred to as a probe needle) relative to each other in a state where the wafer is fixed on the wafer chuck, thereby moving the probe to the electrode (also referred to as an electrode pad) of each semiconductor chip. Make electrical contact. The tester supplies various test signals to the electrodes of each semiconductor chip via the terminals connected to the probe, and receives and analyzes signals output from the electrodes in response to the supply of the test signals, The electrical characteristics of each semiconductor chip (such as whether or not it operates normally) are inspected.

  Semiconductor chips such as power transistors, field effect transistors, IGBTs (Insulated Gate Bipolar Transistors), LEDs (light emitting diodes), and semiconductor lasers have electrodes (surface electrodes) formed on the surface and also on the back surface. An electrode (back electrode) is formed. For example, a gate electrode and an emitter electrode are formed on the surface of the IGBT, and a collector electrode is formed on the back surface thereof.

  A wafer chuck of a wafer test system corresponding to such a semiconductor chip inspection has a support surface that supports the wafer in contact with the back surface of the wafer and has a conductive support surface that acts as a measurement electrode of the tester ( (Wafer mounting surface) is provided (see Patent Document 3). This support surface is electrically connected to a tester via a chuck lead wire (wiring) drawn from the wafer chuck. When inspecting a semiconductor chip, various measurements are performed in a state where the wafer is held on a wafer chuck and the probe is brought into contact with the surface electrode of the semiconductor chip formed on the surface of the wafer. At this time, depending on the measurement conditions, the back electrode of the above-described semiconductor chip is applied with a voltage, a current, or the like from a tester, or is grounded.

Japanese Patent No. 4068127 JP 2003-218175 A Japanese Patent No. 2970893

  By the way, since the wafer chuck moves around and the temperature becomes high, the above-described chuck lead wire tends to be easily cut by being exposed to severe conditions both mechanically and thermally. If this chuck lead wire is cut, voltage and current cannot be applied to the support surface of the wafer chuck, that is, the back surface electrode of the semiconductor chip of the wafer, or signals from the back surface electrode cannot be detected. An accurate inspection of the semiconductor chip cannot be performed.

  For this reason, in the past, the person in charge regularly checked the continuity of the chuck lead wire using a handy tester during periodic inspections, etc. However, it is not known that the chuck lead wire was disconnected until the periodic inspection. The wafer may be inspected with the chuck lead wire disconnected.

  Therefore, for example, as described in Patent Document 3, an inspection power source that applies an inspection voltage to the chuck lead wire, a conversion transformer that extracts an output waveform from a current flowing in the chuck lead wire, an output waveform from the conversion transformer, and a reference A method for providing a wafer test system with a determination unit that compares the waveform with each other to determine whether or not the chuck lead wire is conductive (disconnected) is conceivable.

  However, according to the method described in Patent Document 3, the presence or absence of conduction of the chuck lead wire can be automatically inspected, but the apparatus configuration becomes large. For this reason, there is a strong demand for automatically and simply inspecting the presence or absence of conduction of the chuck lead wire.

  Since the wafer chuck is charged with electric charges (static electricity), and the wafer on the wafer chuck is also charged, the semiconductor chip surface electrode and the probe are brought into contact when the wafer is inspected. There is a possibility that an arc caused by discharge occurs between the chip and the probe and damages the semiconductor chip. For this reason, for example, as described in Patent Document 2, by connecting a resistance (high resistance) to a connection line electrically connected to the wafer chuck, and further connecting a grounded relay to this resistance, A method of removing the charge from the wafer chuck is conceivable.

  However, in order to accurately inspect each semiconductor chip, the wafer chuck needs to be in a high insulation state (a state that is not affected by an external leakage current or the like). In this method, a resistor is disposed between the wafer chuck and the relay. For this reason, the connection state between the wafer chuck and the resistor is maintained even after the relay is switched from ON to OFF after the charge removal of the wafer chuck. As a result, the leak current generated from the resistance may affect the inspection of each semiconductor chip or may adversely affect the semiconductor chip.

  The present invention has been made in view of such circumstances, and a first object thereof is to provide a continuity inspection apparatus and a prober that can automatically and easily inspect the presence or absence of continuity of a chuck lead wire. A second object is to provide a static eliminator capable of minimizing the occurrence of leakage current.

  A continuity testing apparatus for achieving the first object of the present invention includes a wafer chuck that holds a wafer on which a plurality of semiconductor chips are formed, a probe that contacts a surface electrode of the semiconductor chip formed on the surface of the wafer, A wiring supporter electrically connected to a conductive support surface which is in contact with a back surface electrode of a semiconductor chip formed on the back surface of the wafer, which is provided on a wafer chuck of a prober including In the continuity testing device, a first component that is one of a first relay and a first resistor connected to the other end opposite to one end of the wiring connected to the support surface, and the first component connected to the first component; A second component that is the other of the grounded first relay and the first resistor, an additional wiring connected to the support surface, and a current loop forming unit connected to the additional wiring, including at least a power source and wiring Comprising additional wiring, the first component, and a current loop forming unit configured to form a second component, and at least including current loop power, a determining unit that the current from the power source to determine whether or not through the current loop, the.

  According to this continuity testing apparatus, it is possible to determine whether or not the wiring is conductive by determining whether or not a current flows in the current loop.

  In the continuity testing device according to another aspect of the present invention, the current loop forming unit includes a second relay and a second resistor connected to the other end on the opposite side of the one end of the additional wiring connected to the support surface. A third component, a second relay connected to the third component, a fourth component that is the other of the second resistors, and a power source connected to the fourth component and grounded, and the second resistor The voltage detection part which detects the voltage of this is provided, and a determination part performs determination based on the detection result of a voltage detection part. Thereby, it can be determined whether a current flows into a current loop based on the voltage detection result of the 2nd resistance by a voltage detection part.

  The continuity testing apparatus according to another aspect of the present invention includes a relay control unit that individually switches between a closed state and an open state of both the first relay and the second relay, and the determination unit is operated by the relay control unit. The determination is performed based on the detection result of the voltage detection unit in a state where both the first relay and the second relay are switched to the closed state. Thereby, it can be determined whether a current flows into a current loop based on the voltage detection result of the 2nd resistance by a voltage detection part.

  In the continuity testing device according to another aspect of the present invention, the first component is a first relay and the second component is a first resistor. Thereby, by turning off the first relay, the first resistance can be separated from the support surface in the shortest time, so that the leakage current can be minimized.

  In the continuity testing apparatus according to another aspect of the present invention, a connector provided at the other end of the wiring, the connector connected to both the tester for testing the electrical characteristics of the semiconductor chip and the first component Is provided.

  A prober for achieving the first object of the present invention is a wafer chuck that holds a wafer on which a plurality of semiconductor chips are formed, and that is in contact with the back electrode of the semiconductor chip formed on the back surface of the wafer. A wafer chuck having a support surface, a probe in contact with a surface electrode of a semiconductor chip formed on the surface of the wafer, and the above-described continuity inspection apparatus.

  A static eliminator for achieving the second object of the present invention comprises a wafer chuck that holds a wafer on which a plurality of semiconductor chips are formed, and a probe that contacts a surface electrode of the semiconductor chip formed on the surface of the wafer. Wiring electrically connected to the conductive support surface that contacts the back surface electrode of the semiconductor chip formed on the back surface of the semiconductor chip formed on the back surface of the wafer, and connected to the wiring. And a first resistor connected to the first relay and grounded.

  According to the static eliminator, the first resistance can be separated from the support surface in the shortest time by turning off the first relay, so that the leakage current can be minimized.

  The continuity inspection apparatus and prober of the present invention can automatically and easily inspect for the presence or absence of continuity of the chuck lead wire. In addition, the static eliminator of the present invention can minimize the occurrence of leakage current.

1 is a schematic diagram of a wafer test system. It is explanatory drawing for demonstrating a chuck lead wire and an additional circuit. It is the schematic of the static elimination circuit of a comparative example. It is explanatory drawing for demonstrating a current loop and a power supply. It is a functional block diagram of the general control part of a prober. It is a flowchart which shows the flow of the process of the static elimination of a wafer chuck | zipper by an additional circuit, the continuity inspection of a chuck lead wire, and the self-diagnosis of each relay.

[Configuration of wafer test system]
FIG. 1 is a schematic diagram of a wafer test system 9. Hereinafter, the upper and upper surfaces in the Z-axis direction, which is the vertical direction in the drawing, are appropriately referred to as “upper” and “upper surface”, and the lower and lower surfaces in the Z-axis direction are appropriately referred to as “lower” and “lower surface”.

  The wafer test system 9 inspects the electrical characteristics of each of a plurality of semiconductor chips (not shown) formed on the wafer W and having electrodes (not shown) formed on both surfaces. The wafer test system 9 includes a prober 10 and a tester 30.

  The prober 10 brings the probe 25 into contact with a surface electrode (not shown) formed on the surface of each semiconductor chip (not shown) on the wafer W, and also has a back electrode (not shown) formed on the back surface of each semiconductor chip. A conductive support surface 16a of a wafer chuck 16 (to be described later) is brought into contact with (illustrated). The tester 30 is electrically connected to the probe 25 and the support surface 16a, and inspects the electrical characteristics of each semiconductor chip.

  The prober 10 includes a base 11, a base 12, a Y stage 13, an X stage 14, a Zθ stage 15, a wafer chuck 16, a probe position detection camera 18, a probe height detector 20, and a height. Adjustment mechanisms 21 and 27, a wafer alignment camera 19, a head stage 22, a card holder 23, a probe card 24, and a probe 25 are provided.

  A substantially flat base 12 is fixed to the upper surface of the base 11. Note that a leg member may be used instead of the base 11, or the base 11 may be omitted.

  A substantially flat Y stage 13 is supported on the upper surface of the base 12 so as to be movable in the Y-axis direction via a Y moving portion (not shown). The Y moving part is provided on the upper surface of the base 12 and is parallel to the Y axis, a slider provided on the lower surface of the Y stage 13 and engaged with the guide rail, and moves the Y stage 13 in the Y axis direction. A drive mechanism such as a motor. By driving the Y moving unit, the Y stage 13 and the later-described X stage 14 and Zθ stage 15 are moved integrally on the base 12 in the Y-axis direction.

  A substantially flat plate-like X stage 14 is supported on the upper surface of the Y stage 13 through an X moving unit (not shown) so as to be movable in the X axis direction. The X moving unit is provided on the upper surface of the Y stage 13 and parallel to the X axis, the slider provided on the lower surface of the X stage 14 and engaged with the guide rail, and moves the X stage 14 in the X axis direction. And a drive mechanism such as a motor to be driven. By driving the X moving unit, the X stage 14 and a later-described Zθ stage 15 are moved integrally on the Y stage 13 in the X-axis direction.

  A Zθ stage 15 and height adjusting mechanisms 21 and 27 are provided on the upper surface of the X stage 14. A Zθ moving unit (not shown) is provided inside the Zθ stage 15. A wafer chuck 16 is held on the upper surface of the Zθ stage 15 via a Zθ moving unit (not shown). The Zθ moving unit includes, for example, an elevating mechanism that can move the upper surface of the Zθ stage 15 in the Z-axis direction, and a rotating mechanism that rotates the upper surface around the Z-axis. Therefore, the Zθ moving unit moves the wafer chuck 16 held on the upper surface of the Zθ stage 15 in the Z-axis direction and rotates it around the Z-axis axis.

  The wafer chuck 16 holds the wafer W from the back side. The wafer chuck 16 is supported by the Y stage 13, the X stage 14, and the Zθ stage 15 described above so as to be movable in the XYZ axial directions, and is rotatable around the Z axis. It is supported. Thereby, the wafer W held by the wafer chuck 16 and a probe 25 described later can be relatively moved.

  The support surface 16a of the wafer W, which is the upper surface of the wafer chuck 16, is subjected to various metal plating such as aluminum plating or gold plating, and has conductivity. The support surface 16a is in contact with a back electrode (not shown) of each semiconductor chip of the wafer W. The support surface 16a is connected to the tester 30 via a chuck lead wire 40 (see FIG. 2) described later, and acts as a measurement electrode of the tester 30. Thereby, according to various measurement conditions at the time of inspection of each semiconductor chip (not shown) of the wafer W, a voltage, a current, or the like is applied to the back surface electrode of each semiconductor chip from the tester 30 via the support surface 16a. Or it is grounded.

  The height adjustment mechanism 21 moves the probe position detection camera 18 described later up and down in the Z-axis direction. Further, the height adjustment mechanism 27 moves up and down in the Z-axis direction of a probe height detector 20 described later. The height adjusting mechanisms 21 and 27 may be any known linear moving mechanism, and for example, a linear guide mechanism and a ball screw mechanism are used.

  The head stage 22 forms, for example, a top plate of a housing (not shown) of the prober 10, and is supported above the wafer chuck 16 (wafer W) by a support (not shown). The head stage 22 is formed in a substantially annular shape, and a substantially annular card holder 23 for holding the probe card 24 is provided at the center thereof. That is, the head stage 22 holds the probe card 24 via the card holder 23.

  The probe card 24 has a plurality of probes 25. These probes 25 are arranged on the probe card 24 in a pattern corresponding to the arrangement pattern of the surface electrodes of each semiconductor chip (not shown) of the wafer W to be inspected.

  The probe position detection camera 18 is attached to the height adjustment mechanism 21. The probe position detection camera 18 is, for example, a camera equipped with a needle alignment microscope, and photographs the probe 25 of the probe card 24 from below. Based on the image of the probe 25 photographed by the probe position detection camera 18, the position of the probe 25 can be detected. Specifically, the XY coordinates of the tip position of the probe 25 are detected from the position coordinates of the probe position detection camera 18, and the Z coordinate of the tip position of the probe 25 is detected from the focal position of the probe position detection camera 18.

  The wafer alignment camera 19 is supported by a support column (not shown) provided on the base 12 and photographs the semiconductor chip (not shown) of the wafer W held by the wafer chuck 16 from above. Based on the image of the semiconductor chip taken by the wafer alignment camera 19, the position of the electrode of the semiconductor chip can be detected. Thereby, based on the information obtained by the wafer alignment camera 19 and the position information of the tip of the probe 25 obtained by the probe position detection camera 18, the two in the XY plane between the probe 25 and the electrode of the semiconductor chip of the wafer W are obtained. Dimensional alignment (alignment) can be performed.

  The probe height detector 20 is attached to the above-described height adjustment mechanism 27 on the X stage 14. The probe height detector 20 detects the height of the tip of the probe 25 from the reference plane that serves as a reference for the height of the probe position detection camera 18. The probe height detector 20 is a contact type detector, and detects the height of the tip of the probe 25 by physically contacting the tip of the probe 25. Here, the reference plane is a plane that serves as a reference for the height of the prober 10 in general, and is set arbitrarily (for example, the upper surface of the X stage 14).

  The above-described height adjusting mechanism 21 adjusts the probe position detection camera 18 to a height away from the tip of the probe 25 by a working distance based on the detection result of the height of the tip of the probe 25. Thereby, it is prevented that the probe position detection camera 18 is raised too much and the probe position detection camera 18 collides with the tip of the probe 25.

  The tester 30 includes a tester body 31 and a contact ring 32 provided on the tester body 31. The probe card 24 is provided with a terminal connected to each probe 25. The contact ring 32 includes spring probes arranged in an arrangement pattern that can contact each terminal of the probe card 24.

  The tester body 31 is held with respect to the prober 10 by a support mechanism (not shown). The tester body 31 is electrically connected to a surface electrode of a semiconductor chip (not shown) via a probe card 24, a probe 25, etc., and is not connected via a chuck lead wire 40 (see FIG. 2), a support surface 16a, etc. It is electrically connected to the back electrode of the illustrated semiconductor chip. The tester body 31 inspects the electrical characteristics of the semiconductor chip by applying a current or voltage to the semiconductor chip.

[Chuck lead wire and additional circuit]
FIG. 2 is an explanatory diagram for explaining the chuck lead wire 40 and the additional circuit 42. As shown in FIG. 2, the chuck lead wire 40 corresponds to the wiring of the present invention, and electrically connects the support surface 16a and the tester 30 (tester body 31). The chuck lead wire 40 includes one end 40a electrically connected to the support surface 16a, and the other end 40b opposite to the one end 40a, and is electrically connected to a connector 44 described later. And an end portion 40b. The type of the chuck lead wire 40 (wiring) is not particularly limited.

  The additional circuit 42 functions as a continuity inspection device of the present invention as a whole, and a part of the additional circuit 42 functions as a static elimination device of the present invention. The additional circuit 42 performs continuity inspection (disconnection inspection) of the chuck lead wire 40 and a wafer chuck. Sixteen charges are discharged. The additional circuit 42 includes a connector 44, a static elimination circuit 50 (first relay 46 and first resistor 48), an additional lead wire 52, a second relay 54, a second resistor 56, a power source 58, and a detection circuit. 60.

  The connector 44 is electrically connected to the other end portion 40b of the chuck lead wire 40 as described above. In addition to the other end portion 40b, the connector 44 is individually connected to the tester 30 and the first relay 46 that constitutes the static elimination circuit 50. Accordingly, the support surface 16a and the tester 30 are electrically connected via the chuck lead wire 40 and the connector 44, and the support surface 16a and the static elimination circuit 50 (first relay 46) are electrically connected. .

  The static eliminator 50 corresponds to the static eliminator of the present invention, and is connected to the first relay 46 electrically connected to the connector 44 (that is, the other end 40b), and connected to the first relay 46 and grounded. A first resistor 48. In the present embodiment, one first relay 46 of the static elimination circuit 50 corresponds to the first component of the present invention, and the other first resistor 48 corresponds to the second component of the present invention. As described above, the wafer chuck 16 is charged with electric charges (static electricity). As a result, the wafer W on the wafer chuck 16 is also charged. For this reason, the static elimination circuit 50 neutralizes charges (static electricity) charged on the wafer chuck 16.

  The first relay 46 is in a closed state (connected state) in which both the chuck lead wire 40 and the support surface 16a (hereinafter abbreviated as the support surface 16a) and the first resistor 48 are electrically connected. And an open state (disconnected state) in which both electrical connections are released. The type of the first relay 46 is not particularly limited. In the present specification, switching the first relay 46 to the closed state is defined as “on”, and conversely, switching to the open state is defined as “off”. The on / off switching of the first relay 46 is controlled by the overall control unit 62 described later.

  The first relay 46 is turned on when the wafer chuck 16 is neutralized and when a later-described chuck lead 40 is inspected for electrical connection, and electrically connects the support surface 16 a and the like to the first resistor 48. In addition, the first relay 46 is turned off during the inspection of the electrical characteristics of each semiconductor chip (not shown), and the electrical connection between the support surface 16a and the first resistor 48 is released.

  The first resistor 48 is a current limiting resistor that prevents electric charges (static electricity) charged on the wafer chuck 16 from flowing all at once toward the ground side when the first relay 46 is turned on at the time of static elimination of the wafer chuck 16. Yes, high resistance is used. As a result, when the first relay 46 is turned on during static elimination of the wafer chuck 16, the charge charged in the wafer chuck 16 can be gradually discharged to the ground side via the first resistor 48, and as a result. The wafer chuck 16 is neutralized.

  Next, in comparison with the static elimination circuit 50 of this embodiment and the static elimination circuit 200 (refer FIG. 3) of a comparative example, the effect of the static elimination circuit 50 of this embodiment is demonstrated in detail. In addition, this invention is not limited to description of the following effects.

  FIG. 3 is a schematic diagram of a static elimination circuit 200 of a comparative example. In the comparative example shown in FIG. 3, the same reference numerals are given to the same functions or configurations as those of the present embodiment, and the description thereof is omitted. As shown in FIG. 3, in the static eliminator circuit 200 of the comparative example, the first resistor 48 is first electrically connected to the connector 44 as disclosed in Japanese Patent Application Laid-Open No. 2003-218175 (the above Patent Document 2). And a first relay 46 that is grounded to the first resistor 48 is connected.

  Also in the static eliminator circuit 200 of this comparative example, by turning on the first relay 46, the charge charged to the wafer chuck 16 is grounded via the first resistor 48, as in the static eliminator circuit 50 of the present embodiment. Can gradually discharge to the side.

  However, since the first resistor 48 is disposed between the wafer chuck 16 and the first relay 46 in the static elimination circuit 200 of the comparative example, even when the first relay 46 is switched off, the support surface 16a and the like The connection with the first resistor 48 is maintained. On the other hand, since the first resistor 48 is a high resistance body, there is a possibility that a leakage current may occur when the first relay 46 is turned off. When a leak current is generated from the first resistor 48, the leak current is mixed into a signal output from the back electrode (not shown) when inspecting each semiconductor chip (not shown) on the wafer W, whereby each semiconductor chip. This may affect the inspection of the semiconductor chip or adversely affect each semiconductor chip. Therefore, in order to accurately inspect each semiconductor chip, the wafer chuck 16 needs to be in a highly insulated state (a state that is not affected by an external leakage current or the like). It is not preferable to connect components.

  In contrast to the static elimination circuit 200 of the comparative example, in the static elimination circuit 50 of the present embodiment, the first relay 46 is first electrically connected to the connector 44 as shown in FIG. A first resistor 48 grounded to one relay 46 is electrically connected. Accordingly, the first resistor 48 can be separated from the support surface 16a or the like in the shortest time by turning off the first relay 46 at the time of inspection of each semiconductor chip. As a result, the leakage current due to the static elimination circuit 50 added for static elimination can be minimized.

  Returning to FIG. 2, the additional lead wire 52 corresponds to the additional wiring of the present invention, and its one end 52a is connected to the support surface 16a. Thereby, the chuck lead wire 40 and the additional lead wire 52 are electrically connected via the support surface 16a. In addition, the second relay 54 is electrically connected to the other end 52 b opposite to the one end 52 a of the additional lead wire 52. The type of additional lead wire 52 (wiring) is not particularly limited. In the present embodiment, a part of both the chuck lead wire 40 and the additional lead wire 52 are accommodated in the cable (registered trademark) bear 64.

  The second relay 54 corresponds to a third component of the present invention, and is in a closed state in which both of a second resistor 56 and a power source 58 described later are electrically connected to each other and the additional lead wire 52. It is possible to switch between (connected state) and an open state (non-connected state) where both electrical connections are released. The type of the second relay 54 is not particularly limited. Further, in the present specification, also for the second relay 54, switching to the closed state is defined as “on”, and conversely switching to the open state is defined as “off”. The on / off switching of the second relay 54 is controlled by an overall control unit 62 described later, like the first relay 46.

  The second relay 54 is turned on during a continuity test of the chuck lead wire 40 described later, and electrically connects the second resistor 56 and the power source 58 to the additional lead wire 52. The second relay 54 is turned off when the wafer chuck 16 is neutralized and when the electrical characteristics of each semiconductor chip (not shown) are inspected, and the second resistor 56 and the power source 58 are electrically connected to the additional lead wire 52. Disconnect.

  The second resistor 56 corresponds to the fourth component of the present invention, and is electrically connected to the second relay 54. The second resistor 56 is a current limiting resistor similar to the first resistor 48, and a high resistance body is used. As will be described in detail later, the voltage (both ends voltage, potential difference) of the second resistor 56 is used to determine whether the chuck lead wire 40 is conductive (disconnected).

  FIG. 4 is an explanatory diagram for explaining the current loop CR and the power source 58. As shown in FIGS. 2 and 4, the power source 58 is connected to the second resistor 56 and grounded. Since the power source 58 and the first resistor 48 described above are so-called frame ground (for example, connected to a ground electrode or a metal housing), the power source 58 and the first resistor 48 are electrically connected. Yes. For this reason, the chuck lead wire 40, the first relay 46, the first resistor 48, the additional lead wire 52, the second relay 54, the second resistor 56, and the power supply 58 constitute a current loop CR. Therefore, the second relay 54, the second resistor 56, and the power source 58 function as a current loop forming unit of the present invention.

  The power supply 58 supplies current (voltage application) to the current loop CR during the continuity test of the chuck lead wire 40 described later, that is, in a state where both the first relay 46 and the second relay 54 are turned on. . As a result, when the chuck lead wire 40 is conductive (not disconnected), that is, when the current loop CR is configured, a current Is (micro current) flows through the current loop CR.

  The detection circuit 60 corresponds to the voltage detection unit of the present invention, and is a voltmeter that detects the voltage (both ends voltage, potential difference) of the second resistor 56. When the chuck lead wire 40 is conducting while both the first relay 46 and the second relay 54 are on, the current Is flows through the current loop CR described above. In this case, if the voltage V applied to the current loop CR by the power source 58, the resistance value of the first resistor 48 is R1, and the resistance value of the second resistor 56 is R2, the second resistor 56 detected by the detection circuit 60. Is detected as “V × (R2 / (R1 + R2))”. Therefore, for example, when R1 = R2, the detection voltage of the second resistor 56 is “V / 2”. In the following description, “R1 = R2” will be described in order to prevent complication of the description.

  On the other hand, even when both the first relay 46 and the second relay 54 are turned on, if the chuck lead wire 40 is disconnected, the current Is from the power source 58 does not flow through the current loop CR. . Therefore, in this case, the detection voltage by the detection circuit 60 is “V”.

  By referring to the detection voltage by the detection circuit 60 in this way, it is possible to determine whether or not the current Is flows in the current loop CR, that is, whether or not the chuck lead wire 40 is conductive (there is no disconnection). Then, the detection circuit 60 outputs the voltage detection result of the second resistor 56 to the overall control unit 62.

  Conversely, when the conduction of the chuck lead wire 40 is confirmed, the voltage detection result of the second resistor 56 by the detection circuit 60 can be used for self-diagnosis of the first relay 46 and the second relay 54.

  For example, when both the first relay 46 and the second relay 54 are turned on and the detection voltage by the detection circuit 60 is “V / 2”, both the first relay 46 and the second relay 54 are normal. It can be determined that there is. On the other hand, when both the first relay 46 and the second relay 54 are turned on and the detection voltage by the detection circuit 60 becomes “V”, at least one of the first relay 46 and the second relay 54 is actually Can be determined not to be turned on, that is, at least one of them is abnormal. Further, when at least one of the first relay 46 and the second relay 54 is turned off, when the detection voltage by the detection circuit 60 becomes “V / 2”, both the first relay 46 and the second relay 54 are Since it is actually turned on, it can be determined that at least one of the first relay 46 and the second relay 54 is abnormal.

  FIG. 5 is a functional block diagram of the overall control unit 62 of the prober 10 (or the wafer test system 9, which is the same hereinafter). The overall control unit 62 includes, for example, various arithmetic units including a central processing unit (CPU) or a field-programmable gate array (FPGA), a processing unit, a memory, and the like, and performs overall control of operations of each unit of the prober 10. In FIG. 5, among the multiple functions of the overall control unit 62, only functions related to static elimination of the wafer chuck 16 by the additional circuit 42, continuity inspection of the chuck lead wire 40, and self-diagnosis of the relays 46 and 54 are provided. The functions relating to the other control of the prober 10 such as the inspection of the wafer W shown in the drawing are well-known techniques and are not shown.

  Connected to the overall control unit 62 are an operation unit 70 for receiving various operation inputs, a display unit 72 for performing various displays, the relays 46 and 54, the power source 58, and the detection circuit 60 described above, as well as each unit of the prober 10. Has been. The overall control unit 62 functions as an additional circuit control unit 76, a determination unit 80, and a self-diagnosis unit 82 by executing a predetermined control program.

  The additional circuit control unit 76 turns on and off each of the relays 46 and 54 when the charge removal of the wafer chuck 16 by the additional circuit 42, the continuity test of the chuck lead wire 40, and the self-diagnosis of each of the relays 46 and 54 are started. The power supply 58 is turned on / off. That is, the additional circuit control unit 76 functions as a relay control unit of the present invention.

  Note that the static elimination, continuity inspection, and self-diagnosis by the additional circuit 42 are performed at an arbitrary timing when the inspection of each semiconductor chip (not shown) is not performed, that is, when the probe 25 is separated from the wafer W. For example, the timing at which the wafer chuck 16 is retracted downward by the Zθ stage 15, the timing at which the wafer W is loaded or unloaded onto the wafer chuck 16, the timing at which the semiconductor chip is indexed, and the like are given as examples. Note that the static elimination, the continuity test, and the self-diagnosis may be started in response to a start operation to the operation unit 70.

  The additional circuit control unit 76 turns on only the first relay 46 at an arbitrary timing for executing the static elimination or upon receiving an input of the static elimination start operation to the operation unit 70. Further, the additional circuit control unit 76 turns on both the relays 46 and 54 and turns on the power source 58 at an arbitrary timing for executing the continuity test or upon receiving an input of the continuity test start operation to the operation unit 70. Let Further, the additional circuit control unit 76 turns on and off each of the relays 46 and 54 one or more times at the timing when the self-diagnosis is executed or receives an input of the self-diagnosis start operation to the operation unit 70, and turns on the power source 58. Let

  When the continuity test is started, that is, when both the first relay 46 and the second relay 54 are turned on and the power supply 58 is turned on, the determination unit 80 determines the second resistance 56 input from the detection circuit 60. Based on the voltage detection result, it is determined whether or not the current Is flows in the current loop CR. As a result, the determination unit 80 can determine whether the chuck lead wire 40 is conductive. As described above, when the voltage of the second resistor 56 is “V / 2”, the determination unit 80 determines that the current Is flows in the current loop CR, and the chuck lead wire 40 is turned on. It is determined that On the other hand, when the voltage of the second resistor 56 is “V”, the determination unit 80 determines that the current Is does not flow in the current loop CR and determines that the chuck lead wire 40 is disconnected. .

  Then, the determination unit 80 outputs the presence / absence of conduction of the chuck lead wire 40 to the display unit 72. Thereby, the display unit 72 displays whether the chuck lead wire 40 is conductive or not (disconnected). In addition to the monitor that performs screen display (image display), the display unit 72 includes a speaker that performs audio display (audio output).

  When the self-diagnosis is performed, that is, when each of the relays 46 and 54 is turned on and the power source 58 is turned on, the self-diagnosis unit 82 outputs the voltage detection result of the second resistor 56 input from the detection circuit 60. Based on this, self-diagnosis of each relay 46, 54 is performed. As described above, when the self-diagnosis unit 82 turns on both the relays 46 and 54, for example, when the detection voltage by the detection circuit 60 is "V / 2", both the relays 46 and 54 are provided. When the detected voltage is “V”, it is determined that at least one of the relays 46 and 54 is abnormal. Further, the self-diagnosis unit 82 determines that at least one of the relays 46 and 54 is abnormal when the detection voltage by the detection circuit 60 becomes “V / 2” when at least one of the relays 46 and 54 is turned off. It is determined that

  Then, the self-diagnosis unit 82 outputs the self-diagnosis results of the relays 46 and 54 to the display unit 72. Thereby, the self-diagnosis result of each of the relays 46 and 54 is displayed on the display unit 72.

[Operation of additional circuit of this embodiment]
FIG. 6 is a flowchart showing the flow of processing of static elimination of the wafer chuck 16, continuity inspection of the chuck lead wire 40, and self-diagnosis of the relays 46 and 54 by the additional circuit 42 having the above-described configuration.

<Continuity test>
As shown in FIG. 6, the additional circuit control unit 76 receives the input of the continuity test start operation to the operation unit 70 at an arbitrary timing for executing the continuity test (YES in step S1), and each of the relays 46, 54. Are turned on (step S2) and the power source 58 is turned on (step S3). On the other hand, the detection circuit 60 starts voltage detection of the second resistor 56 in accordance with the power supply 58 being turned on, and outputs the voltage detection result of the second resistor 56 to the determination unit 80 (step S4).

  When the voltage of the second resistor 56 is “V / 2”, the determination unit 80 determines that the current Is flows in the current loop CR, that is, determines that the chuck lead wire 40 is conductive ( Step S5). On the other hand, when the voltage of the second resistor 56 is “V”, the determination unit 80 determines that the current Is is not flowing in the current loop CR, that is, determines that the chuck lead wire 40 is disconnected ( Step S5). Then, the determination unit 80 outputs the determination result to the display unit 72. Thereby, the determination result of the presence or absence of conduction of the chuck lead wire 40 is displayed on the display unit 72 (step S6).

<Static elimination>
The additional circuit control unit 76 turns on the first relay 46 at any timing for executing the static elimination or upon receiving an input of the static elimination start operation to the operation unit 70 (NO in step S1, YES in step S7) (step S1). S8). As a result, since the electric charge charged in the wafer chuck 16 is discharged to the ground side via the first resistor 48, the wafer chuck 16 is discharged.

<Self-diagnosis>
The additional circuit control unit 76 receives the input of the self-diagnosis start operation to the operation unit 70 at any timing for executing the self-diagnosis of the relays 46 and 54 (NO in both step S1 and step S7), and supplies power 58 is turned on (step S9). Further, in accordance with the power supply 58 being turned on, the detection circuit 60 starts voltage detection of the second resistor 56 and outputs the voltage detection result to the self-diagnosis unit 82 (step S10).

  Next, the additional circuit control unit 76 individually turns on and off each of the relays 46 and 54 once (step S11). Then, as described above, the self-diagnosis unit 82 is based on the voltage detection result of the second resistor 56 input from the detection circuit 60 while the relays 46 and 54 are being turned on / off. The self-diagnosis is performed, and the diagnosis result is output to the display unit 72 (step S12). Thereby, the self-diagnosis result of each relay 46 and 54 is displayed on the display part 72 (step S13).

[Effect of this embodiment]
As described above, according to the additional circuit 42 of the present embodiment, the current loop CR is formed by the additional lead wire 52 and the like, whether or not the current Is flows through the current loop CR, that is, the second resistor 56 by the detection circuit 60. Whether or not the chuck lead wire 40 is conductive can be determined only by detecting whether or not the voltage detection result is “V / 2”. The additional circuit 42 can be easily constructed simply by combining known relays 46 and 54, resistors 48 and 56, a power source 58, and a detection circuit 60 (such as a voltmeter). As a result, the presence or absence of conduction of the chuck lead wire 40 can be automatically and easily inspected.

  In the static eliminator circuit 50 of the present embodiment, the first relay 46 is electrically connected to the connector 44 first, and the first resistor 48 grounded is electrically connected to the first relay 46. Therefore, the first resistor 48 can be separated from the chuck lead wire 40 and the like in the shortest time by turning off the first relay 46 when inspecting each semiconductor chip. As a result, the leakage current caused by the static elimination circuit 50 can be minimized, so that the leakage current affects the inspection of each semiconductor chip (not shown) on the wafer W or adversely affects each semiconductor chip. Is prevented.

[Others]
In the above embodiment, the second relay 54, the second resistor 56, and the power source 58 are connected to the additional lead wire 52 (the other end 52b) in this order, but depending on whether the second relay 54 is turned on or off. As long as the supply of the current Is to the current loop CR can be turned on / off, the order is not particularly limited. Further, in the above embodiment, the first relay 46 and the first resistor 48 are connected to the connector 44 in order in order to minimize the leakage current due to the static elimination circuit 50. However, it is necessary to consider the leakage current. If not, the first resistor 48 and the first relay 46 may be connected to the connector 44 in this order.

  In the above-described embodiment, the first resistor 48 and the second resistor 56 have been described using a single resistor as an example. However, the first resistor 48 and the second resistor 56 include a plurality of resistors (electronic components equivalent to resistors, or (Including electronic components other than resistors).

  In the above embodiment, the voltage of the second resistor 56 is detected by the detection circuit 60, but the voltage of the first resistor 48 is detected by the detection circuit 60, and the determination by the determination unit 80 and self-diagnosis based on the voltage detection result. Diagnosis by the unit 82 may be performed.

  In the above embodiment, the power source 58 is connected to the additional lead wire 52 side, but the power source 58 may be connected to the static elimination circuit 50.

  In the above embodiment, the case where the tester 30 is connected to the connector 44 (the other end portion 40b of the chuck lead wire 40) in addition to the static elimination circuit 50 has been described as an example, but various devices other than the tester 30 are described. Or this invention is applicable also when a measuring instrument etc. are connected. In addition, when the purpose is to eliminate static electricity from the wafer chuck 16, only the static elimination circuit 50 may be connected to the connector 44.

9 ... Wafer test system,
10 ... Prober,
16 ... wafer chuck,
16a ... support surface,
30 ... Tester,
40 ... Chuck lead wire,
42. Additional circuit,
44 ... Connector,
46 ... 1st relay,
48 ... first resistor,
50: Static elimination circuit,
52 ... Additional lead wire,
54 ... second relay,
56 ... second resistance,
58 ... Power supply,
60... Detection circuit,
62 ... Overall control unit,
80 ... determination part,
82 ... Self-diagnosis department

Claims (7)

A wafer chuck provided on the wafer chuck of a prober, comprising: a wafer chuck for holding a wafer on which a plurality of semiconductor chips are formed; and a probe in contact with a surface electrode of the semiconductor chip formed on the surface of the wafer. In a wiring continuity inspection apparatus that is electrically connected to a conductive support surface that is in contact with a back surface electrode of the semiconductor chip formed on the back surface of the wafer,
A first component that is one of a first relay and a first resistor connected to the other end opposite to one end of the wiring connected to the support surface;
A second component that is the other of the first relay and the first resistor connected to the first component and grounded;
Additional wiring connected to the support surface;
A current loop forming unit connected to the additional wiring, the current loop forming unit including at least a power source and forming a current loop including at least the wiring, the additional wiring, the first component, the second component, and the power source A loop forming section;
A determination unit that determines whether or not a current from the power source flows through the current loop;
A continuity testing apparatus comprising: The current loop forming unit is
A third component that is one of a second relay and a second resistor connected to the other end opposite to the one end of the additional wiring connected to the support surface;
A fourth component that is the other of the second relay and the second resistor connected to the third component;
The power source connected to the fourth component and grounded;
With
A voltage detector for detecting the voltage of the second resistor;
The continuity test apparatus according to claim 1, wherein the determination unit performs the determination based on a detection result of the voltage detection unit. A relay control unit that individually switches between a closed state and an open state of both the first relay and the second relay;
The determination unit performs the determination based on a detection result of the voltage detection unit in a state in which both the first relay and the second relay are switched to the closed state by the relay control unit. The continuity test device described.   The continuity inspection device according to any one of claims 1 to 3, wherein the first component is the first relay and the second component is the first resistor.   5. The connector according to claim 1, further comprising: a connector provided at the other end of the wiring, the connector being connected to both the tester for inspecting electrical characteristics of the semiconductor chip and the first component. The continuity test apparatus according to claim 1. A wafer chuck for holding a wafer on which a plurality of semiconductor chips are formed and having a conductive support surface in contact with a back electrode of the semiconductor chip formed on the back surface of the wafer;
A probe in contact with a surface electrode of the semiconductor chip formed on the surface of the wafer;
The continuity testing device according to any one of claims 1 to 5,
Prober equipped with. A support surface of the wafer provided on the wafer chuck of a prober comprising a wafer chuck for holding a wafer on which a plurality of semiconductor chips are formed and a probe that contacts a surface electrode of the semiconductor chip formed on the surface of the wafer. And a wiring electrically connected to a conductive support surface in contact with a back surface electrode of the semiconductor chip formed on the back surface of the wafer;
A first relay connected to the wiring;
A first resistor connected to the first relay and grounded;
A static eliminator comprising:

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