JP2019165165A - Silicon carbide semiconductor device and manufacturing method thereof - Google Patents

Abstract

Provided is a SiC semiconductor device having a structure in which a deep layer and a trench gate structure do not overlap while achieving a low on-resistance value and a low saturation current. A width of a part of a JFET part on a side of a p-type base region is wider than a part of the part on a side of an n + type substrate. Further, by making the side surface of the JFET portion 2a tapered and narrowing the width of the portion of the JFET portion 2a on the side of the n + type substrate 1, when the drain voltage Vd becomes higher than the voltage during normal operation, The part 2a is pinched off immediately.

Description

  The present invention relates to a silicon carbide (hereinafter referred to as SiC) semiconductor device having a trench gate structure and a method for manufacturing the same.

  In recent years, SiC has attracted attention as a power device material that can provide high electric field breakdown strength. Since the SiC semiconductor device has a high electric field breakdown strength, a large current can be controlled. Therefore, it is expected to be utilized for controlling a hybrid car motor.

  In a SiC semiconductor device, it is effective to increase the channel density in order to flow a larger current, and a SiC semiconductor device having a trench gate structure has been proposed as a structure capable of increasing the channel density (for example, Patent Documents). 1).

  In such a SiC semiconductor device, it is necessary to reduce the on-resistance value in order to reduce the switching loss. However, the value of the current flowing through the semiconductor element when the load is short-circuited increases in inverse proportion to the on-resistance value of the semiconductor element. Become. That is, the smaller the on-resistance value, the larger the saturation current when the load is short-circuited. As a result, the semiconductor element is easily damaged by self-heating, so that the tolerance of the SiC semiconductor device when the load is short-circuited is lowered. As described above, there is a trade-off relationship between the reduction of the on-resistance value and the improvement of the withstand capability of the SiC semiconductor device at the time of load short-circuit, but the improvement of this trade-off relationship, that is, the low on-resistance value and the low saturation current A balance is desired.

JP, 2006-66780, A

  The inventors of the present invention have studied a structure capable of achieving both a low on-resistance value and a low saturation current for an SiC semiconductor device having a MOSFET having a trench gate structure. As a result, a p-type deep layer deeper than the trench gate is disposed on both sides of the trench gate to form a JFET portion between adjacent p-type deep layers, and when the drain voltage becomes higher than in normal operation, the JFET The structure where the part is pinched off was found.

For example, an n ⁻ type drift layer, a p type base region, and an n ⁺ type source region are sequentially formed on an n ⁺ type substrate, and penetrate the p type base region and the n ⁺ type source region to form an n ⁻ type drift layer. A trench gate structure is provided with a gate electrode in the reaching trench. Further, n ^- so as to extend from the bottom of the p-type base region in the type drift layer on an n ⁺ -type substrate, at least the side surface of the p-type deep layer is formed, further p-type deep layer on both sides of the trench gate structure n ^- The structure is provided with an n-type adjustment layer having a higher concentration than the type drift layer.

In such a structure, a JFET portion is constituted by a portion disposed between adjacent p-type deep layers in the n ⁻ -type drift layer. When the drain voltage during normal operation is applied, the depletion layer extends from the p-type deep layer in the n-type adjustment layer, so that the depletion layer of the JFET portion and the n-type adjustment layer is extended. A current path is secured at a portion where there is no current, and a current flows. For this reason, reduction of on-resistance can be aimed at.

  On the other hand, when the drain voltage becomes higher than during normal operation such as when a load is short-circuited, the depletion layer extending from the p-type deep layer further extends from the n-type adjustment layer to the JFET portion, and the JFET portion is completely depleted and pinched off. Therefore, it becomes possible to suppress the saturation current and to achieve both reduction of on-resistance.

However, the width and impurity concentration of the JFET portion and the n-type adjustment layer must be defined so that the JFET portion and the n-type adjustment layer are pinched off when the drain voltage becomes higher than that during normal operation. For this reason, the widths of the JFET portion and the n-type adjustment layer cannot be increased too much. As a result, when a mask shift occurs when forming a p-type deep layer with respect to the n ⁻ -type drift layer and when forming a trench for forming the trench gate structure, the side surface of the trench gate structure becomes a p-type. It turns out that it may overlap with the deep layer. In such a structure, a channel cannot be formed on one side surface of the trench gate structure, and current cannot flow, so that there is a problem that the on-resistance cannot be reduced.

  In view of the above-described points, an object of the present invention is to provide a SiC semiconductor device having a structure in which a deep layer and a trench gate structure do not overlap with each other, and a method for manufacturing the same, while achieving both a low on-resistance value and a low saturation current.

  In order to achieve the above object, a SiC semiconductor device according to claim 1 is formed on a substrate of a first or second conductivity type (1) made of SiC, and has a lower impurity concentration than the substrate. A low-concentration layer (2) made of first-conductivity-type SiC, a second-conduction-type deep layer (3) made of SiC of the second-conductivity type formed on the low-concentration layer, and a low-concentration layer The first conductivity type JFET portion (2a) formed on the layer and sandwiched between the deep layers is disposed between the JFET portion and the deep layer, and the first conductivity type impurity concentration is higher than that of the JFET portion. A depletion layer adjustment layer (20) having a high concentration, a base layer (6) of a second conductivity type formed on the deep layer, the JFET portion and the depletion layer adjustment layer, and a base region; A source region made of SiC of the first conductivity type having a higher concentration than the low concentration layer ( ) And reaches the JFET part through the source region and the base region, and in the linear gate trench (9) whose longitudinal direction is one direction, a part of the base region is defined as a channel region on the channel region. A trench gate structure having a formed gate insulating film (10) and a gate electrode (11) formed on the gate insulating film, and a contact hole is formed while covering the gate electrode and the gate insulating film. And an interlayer insulating film (12), a source electrode (13) electrically connected to the source region through a contact hole, and a drain electrode (14) formed on the back side of the substrate. Then, a channel region is formed by applying a gate voltage to the gate electrode, and a source voltage and a voltage during normal operation are applied as a drain voltage to the drain electrode, so that An inversion type semiconductor element in which a current flows between the electrode and the drain electrode is configured.

  In such a configuration, the JFET portion is formed at a position corresponding to the trench gate and extends along the longitudinal direction of the gate trench, and is wider on the trench gate side than on the substrate side. When the normal operation voltage is applied as the voltage, the depletion layer extending from the deep layer is stopped at the depletion layer adjustment layer, and when the drain voltage is higher than the normal operation, the JFET The JFET part is pinched off by the depletion layer at a position on the substrate side of the part.

  Thus, the width of the portion on the base region side is wider than the portion on the substrate side in the JFET portion. For this reason, even if a mask shift occurs when forming the gate trench, the gate trench can be positioned in the JFET portion and can be prevented from overlapping the deep layer. Therefore, the channel region can be accurately formed on both side surfaces of the trench gate structure, and it is possible to prevent the on-resistance from being reduced.

  In addition, since the side surface of the JFET part is tapered and the width of the substrate side part of the JFET part is narrowed, the JFET part is immediately pinched off when the drain voltage becomes higher than the voltage during normal operation. You can make it happen. For this reason, it is possible to maintain a low saturation current and to improve the tolerance of the SiC semiconductor device due to a load short circuit or the like.

  Therefore, it is possible to provide a SiC semiconductor device having a structure in which the deep layer and the trench gate structure do not overlap while achieving both a low on-resistance value and a low saturation current.

  In addition, the code | symbol in the bracket | parenthesis of each said means shows an example of a corresponding relationship with the specific means as described in embodiment mentioned later.

It is sectional drawing of the SiC semiconductor device concerning 1st Embodiment. It is sectional drawing which showed the mode at the time of normal operation | movement of the SiC semiconductor device shown in FIG. It is sectional drawing which showed the mode at the time of the load short circuit of the SiC semiconductor device shown in FIG. It is sectional drawing of a SiC semiconductor device when mask shift | offset | difference generate | occur | produced. FIG. 2 is a cross-sectional view of the SiC semiconductor device shown in FIG. 1 during a manufacturing process. FIG. 4B is a cross-sectional view of the SiC semiconductor device during a manufacturing step following that of FIG. 4A. FIG. 4B is a cross-sectional view of the SiC semiconductor device during a manufacturing step following that of FIG. 4B. FIG. 4D is a cross-sectional view of the SiC semiconductor device during a manufacturing step following that of FIG. 4C; FIG. 4D is a cross-sectional view of the SiC semiconductor device during a manufacturing step following that of FIG. 4D. FIG. 4D is a cross-sectional view of the SiC semiconductor device during a manufacturing step following that of FIG. 4E; It is sectional drawing of the SiC semiconductor device concerning 2nd Embodiment. FIG. 6 is a cross-sectional view of the SiC semiconductor device shown in FIG. 5 during the manufacturing process. FIG. 6B is a cross sectional view of the SiC semiconductor device during a manufacturing step following that of FIG. 6A; FIG. 6B is a sectional view of the SiC semiconductor device during the manufacturing process following FIG. 6B. FIG. 6D is a cross-sectional view of the SiC semiconductor device during a manufacturing step following that of FIG. 6C; FIG. 6D is a cross-sectional view of the SiC semiconductor device during a manufacturing step following that of FIG. 6D. FIG. 6E is a cross-sectional view of the SiC semiconductor device during a manufacturing step following that of FIG. 6E. FIG. 6D is a cross-sectional view of the SiC semiconductor device during a manufacturing step following that of FIG. 6F. FIG. 6G is a cross-sectional view of the SiC semiconductor device during a manufacturing step following that of FIG. 6G. It is sectional drawing of the SiC semiconductor device concerning 3rd Embodiment. It is sectional drawing of the SiC semiconductor device concerning 4th Embodiment. FIG. 9 is a cross-sectional view of the SiC semiconductor device shown in FIG. 8 during manufacturing process. FIG. 9B is a cross-sectional view of the SiC semiconductor device during a manufacturing step following that of FIG. 9A; FIG. 9B is a cross-sectional view of the SiC semiconductor device during a manufacturing step following that of FIG. 9B;

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, parts that are the same or equivalent to each other will be described with the same reference numerals.

(First embodiment)
A first embodiment will be described. As shown in FIG. 1, the SiC semiconductor device according to the present embodiment has a vertical MOSFET formed as a semiconductor element. The vertical MOSFET is formed in the cell region of the SiC semiconductor device, and the SiC semiconductor device is configured by forming the outer peripheral breakdown voltage structure so as to surround the cell region. Only shown. In the following description, the horizontal direction in FIG. 1 is the width direction, and the vertical direction is the thickness direction or depth direction.

The SiC semiconductor device is formed using an n ⁺ type substrate 1 made of SiC as a semiconductor substrate. The n ⁺ type substrate 1 is composed of an off substrate having a predetermined off angle. For example, in the n ⁺ type substrate 1, the plane orientation of the main surface is the (0001) Si plane, and the <11-20> direction is the off direction. The off direction means “a direction parallel to a vector obtained by projecting the normal vector of the growth surface onto the (0001) plane”. The n-type impurity concentration of the n ⁺ -type substrate 1 is preferably as high as possible. However, the concentration is, for example, 1 × 10 ^{18 to} 3 × 10 ¹⁹ / cm ^3, and the phosphorus concentration is 5 × 10 ¹⁸ / cm ³ here. The thickness of the n ⁺ type substrate 1 is, for example, 10 to 500 μm, and is 100 μm here.

An n ⁻ type low concentration layer 2 made of SiC is formed on the main surface of n ⁺ type substrate 1. The n ⁻ type low concentration layer 2 is connected to a JFET portion 2 a having a narrow width at a position away from the n ⁺ type substrate 1. In this specification, the n ^- type low-concentration layer 2 and the JFET portion 2a are described as separate structures for convenience, but each of these n-type layers serves as a drift layer. The JFET portion 2a may be configured with the same impurity concentration as the n ⁻ type low concentration layer 2 or may be configured with a different impurity concentration.

The n-type impurity concentration of the n ⁻ -type low concentration layer 2 is, for example, 5 × 10 ¹⁵ to 2 × 10 ¹⁶ / cm ³ , and here the phosphorus concentration is 8.0 × 10 ¹⁵ / cm ³ . The thickness of the n ⁻ -type low concentration layer 2 is, for example, 6 to 15 μm, here 12 μm. Further, the n-type impurity concentration of the JFET portion 2a is the same as that of the n ⁻ -type low concentration layer 2 here. The thickness of the JFET portion 2a is, for example, 1.0 to 5.0 μm, and is 2.0 μm here.

Further, the JFET portion 2a has a strip shape extending along the longitudinal direction of a trench gate structure to be described later, and the side surface of the JFET portion 2a is tapered to have a trapezoidal cross-sectional shape. Specifically, the width of the JFET portion 2a, n ⁺ is changing in the thickness direction of the mold substrate 1, the JFET portion 2a so that the width in comparison with the opposite side in the n ⁺ -type substrate 1 side is narrower The side surface is tapered.

Among the widths of the JFET portion 2a, the width on the n ⁺ type substrate 1 side is set in consideration of pinch-off conditions and saturation current suppression, as will be described later. Further, when the JFET portion 2a is formed by buried growth, the JFET portion 2a is embedded, and when the p-type deep layer 3 is formed by buried growth, the JFET portion 2a stands without falling down before filling. The width on the n ⁺ type substrate 1 side is set. The width of the JFET portion 2a opposite to the n ⁺ type substrate 1 is made larger than the width of a trench gate structure described later, and from the boundary position between the n ⁺ type source region 7 and the p ⁺ type contact region 8 Is also set so that the end of the JFET portion 2a is located on the trench gate structure side. In the present embodiment, the width of one cell is set to 2.0 μm, for example. In this case, the width on the n ⁺ -type substrate 1 side in the JFET portion 2a is, for example, 0.3 to 0.7 μm, and is 0.4 μm here. Further, the width of the JFET portion 2a opposite to the n ⁺ -type substrate 1 is set to 0.6 to 1.6 μm, for example, and is set to 0.6 μm, for example.

A p-type deep layer 3 made of SiC is formed on both sides of the JFET portion 2a, and a high-concentration n-type layer 20 is formed between the JFET portion 2a and the p-type deep layer 3. The p-type deep layer 3 is configured with substantially the same thickness as the JFET portion 2a. The p-type impurity concentration of the p-type deep layer 3 is, for example, 1 × 10 ¹⁷ to 2 × 10 ¹⁸ / cm ^3, and the aluminum concentration is set to 5.0 × 10 ¹⁷ / cm ³ here. Also, the p-type deep layer 3, JFET portion 2a inversely related, i.e. such that the width in comparison with the opposite side is wider in n ⁺ -type substrate 1 side, the side surface of the p-type deep layer 3 is tapered The cross-sectional shape is a trapezoid. Here, the width of one cell is set to 2.0 μm, the width on the n ⁺ type substrate 1 side of the p-type deep layer 3 is 1.5 μm, and the width on the opposite side to the n ⁺ type substrate 1 is 1.3 μm. In FIG. 1, the p-type deep layer 3 is depicted only on the left and right halves, but the cross-sectional shape becomes trapezoidal by connecting the p-type deep layers 3 in adjacent cells.

The high concentration n-type layer 20 is formed at least between the JFET portion 2a and the p-type deep layer 3, and in this embodiment, the bottom side of the p-type deep layer 3, that is, the n ⁻ -type low concentration. It is also formed at the boundary position with the layer 2. The high-concentration n-type layer 20 functions as a depletion layer adjustment layer, and has an n-type impurity concentration higher than that of the JFET portion 2a. The n-type impurity concentration and width of the high-concentration n-type layer 20 are determined based on the amount of depletion layer extension from the p-type deep layer 3 during normal operation. The n-type impurity concentration of the high-concentration n-type layer 20 is, for example, 3 × 10 ¹⁷ to 1 × 10 ¹⁹ / cm ^3, and here the phosphorus concentration is 1.0 × 10 ¹⁸ / cm ³ . The thickness of the high-concentration n-type layer 20 is set to 0.03 to 0.2 μm, for example, and is 0.05 μm here.

A p-type base region 6 made of SiC is formed on the JFET portion 2a, the high-concentration n-type layer 20, and the p-type deep layer 3. Furthermore, an n ⁺ type source region 7 and a p ⁺ type contact region 8 made of SiC are formed on the p type base region 6. The n ⁺ type source region 7 is formed on the portion of the p type base region 6 corresponding to the JFET portion 2a. The p ⁺ -type contact region 8 is a region for electrically connecting the p-type base region 6 to a source electrode 13 to be described later. On the portion corresponding to the p-type deep layer 3 in the p-type base region 6. Is formed.

The p-type base region 6 is thinner than the p-type deep layer 3 and has a low p-type impurity concentration. The p-type impurity concentration of the p-type base region 6 is, for example, 5 × 10 ¹⁶ to 4 × 10 ¹⁷ / cm ³ , and here the aluminum concentration is 2.0 × 10 ¹⁷ / cm ³ . The thickness of the p-type base region 6 is, for example, 0.3 to 1.5 μm, and is 0.8 μm here.

The n ⁺ type source region 7 has an n type impurity concentration higher than that of the JFET portion 2a. The n type impurity concentration of the n ⁺ type source region 7 is, for example, 5 × 10 ^{18 to} 3 × 10 ²⁰ / cm ^3, and the aluminum concentration is 1.0 × 10 ²⁰ / cm ³ here. The thickness of the n ⁺ -type source region 7 is, for example, 0.2 to 0.6 μm, and is 0.4 μm here.

The p ⁺ type contact region 8 has a higher p type impurity concentration than the p type base region 6. The p-type impurity concentration of the p ⁺ -type contact region 8 is, for example, 5 × 10 ^{18 to} 3 × 10 ²⁰ / cm ^3, and here, the aluminum concentration is 1.0 × 10 ²⁰ / cm ³ . The thickness of the p ⁺ -type contact region 8 is, for example, 0.2 to 0.7 μm, and is 0.4 μm here.

Further, a gate trench having, for example, a width of 0.4 to 1.2 μm and a depth of 0.7 to 3.0 μm so as to penetrate the p-type base region 6 and the n ⁺ -type source region 7 and reach the JFET portion 2a. 9 is formed. Here, the width of the gate trench 9 is 0.4 μm and the depth is 2.0 μm. The p-type base region 6 and the n ⁺ -type source region 7 are arranged so as to be in contact with the side surface of the gate trench 9.

  The width of the gate trench 9 is arbitrary, but the lower limit value is set in consideration of the feasibility of anisotropic etching and the embedding property of the gate electrode 11 to be described later. The width is set in consideration of the width of the JFET portion 2a and mask displacement.

Although the maximum value of the mask displacement expected when forming the gate trench 9 is determined for each apparatus, for example, it is expected to shift within a maximum range of 0.1 μm in the width direction with the target position as the center. For this reason, the combined width of the JFET portion 2a closest to the p-type base region 6 and the high-concentration n-type layer 20 disposed on both sides thereof is larger than the width of the gate trench 9 by 0.1 × 2 μm or more. It is. For example, as described above, when the width of the JFET portion 2a opposite to the n ⁺ -type substrate 1 is 0.6 μm and the width of the high-concentration n-type layer 20 is 0.05 μm, the p-type base region 6 side The combined width of the JFET portion 2a and the high-concentration n-type layer 20 disposed on both sides thereof is 0.7 μm. In this case, the width of the gate trench 9 is set to be 0.2 μm or more smaller than 0.7 μm, and as described above, for example, 0.4 μm.

  The gate trench 9 is formed in a line layout in which the horizontal direction in FIG. 1 is the width direction, the normal direction is the longitudinal direction, and the vertical direction is the depth direction. Although only one gate trench 9 is shown in FIG. 1, a plurality of gate trenches 9 are arranged at equal intervals in the left-right direction on the page, and are arranged so as to be sandwiched between the p-type deep layers 3, respectively. It is made into a shape. For example, the cell pitch that is the pitch of the gate trench 9, that is, the half cell pitch that is half of the arrangement interval of the adjacent gate trenches 9 is, for example, 2.0 μm.

Further, a portion of the p-type base region 6 located on the side surface of the gate trench 9 is defined as a channel region that connects the n ⁺ -type source region 7 and the JFET portion 2a when the vertical MOSFET is operated. A gate insulating film 10 is formed on the inner wall surface of the included gate trench 9. The gate insulating film 10 is composed of an oxide film or the like, and has a thickness of, for example, 75 nm. A gate electrode 11 made of doped Poly-Si is formed on the surface of the gate insulating film 10, and the gate trench 9 is completely filled with the gate insulating film 10 and the gate electrode 11.

A source electrode 13 and the like are formed on the surfaces of the n ⁺ -type source region 7 and the p ⁺ -type contact region 8 with an interlayer insulating film 12 interposed therebetween. Although not shown, a gate wiring is formed on the surface of the gate electrode 11. A layer is formed. The source electrode 13 and the gate wiring layer are composed of a plurality of metals such as Ni / Al. Of the plurality of metals, at least the n-type SiC, specifically, the n ⁺ -type source region 7 or the portion in contact with the gate electrode 11 in the case of n-type doping is made of a metal capable of ohmic contact with the n-type SiC. Yes. In addition, at least a portion of the plurality of metals that contacts the p-type SiC, specifically, the p ⁺ -type contact region 8 is made of a metal that can make ohmic contact with the p-type SiC. The source electrode 13 is electrically insulated by being formed on the interlayer insulating film 12. The source electrode 13 is in electrical contact with the n ⁺ type source region 7 and the p ⁺ type contact region 8 through a contact hole formed in the interlayer insulating film 12.

Further, on the back side of the n ⁺ -type substrate 1 n ⁺ -type substrate 1 and electrically connected to the drain electrode 14 are formed. With such a structure, an n-channel type inverted MOSFET having a trench gate structure is formed. A cell region is configured by arranging a plurality of such vertical MOSFETs. An SiC semiconductor device is configured by forming an outer peripheral breakdown voltage structure such as a guard ring (not shown) so as to surround a cell region where such a vertical MOSFET is formed.

  The SiC semiconductor device having the vertical MOSFET configured as described above operates as follows.

  First, a channel region is not formed in the p-type base region 6 in a state before the gate voltage Vg is applied to the gate electrode 11. Therefore, even if a positive voltage applied during normal operation, for example, 2 V, is applied to the drain electrode 14, it cannot reach the p-type base region 6, and a current flows between the source electrode 13 and the drain electrode 14. Does not flow. For this reason, the SiC semiconductor device of the present embodiment is a normally-off type semiconductor element in which no current flows between the drain and source when the gate voltage Vg is not applied.

Further, when the gate voltage Vg is 0 V and the source voltage Vs is 0 V when the drain voltage Vd, for example, 1200 V, which is higher than that in the normal operation is applied, the p-type base region 6 and the p-type deep layer 3 A depletion layer extends from between the n ⁻ type low concentration layer 2 and the JFET portion 2a. Since the p-type impurity concentration of the p-type base region 6 is as high as 2.0 × 10 ¹⁷ / cm ³ , the depletion layer almost extends to the JFET portion 2a side, and the p-type base region 6 punches through. There is nothing. For this reason, no current flows through the vertical MOSFET at this time.

  Further, since adjacent p-type deep layers 3 are connected by a depletion layer, an electric field is hardly applied to the trench gate structure. In this case, the electric field strength is less than 1 MV / cm at the maximum. For this reason, not only the trench gate structure is not destroyed, but also high reliability in the gate life can be obtained.

  Next, when a gate voltage Vg of 20 V, for example, is applied to the gate electrode 11 in a state where the source voltage Vs is 0 V and the drain voltage Vd is 1-2 V, for example, the vertical MOSFET is turned on. That is, since the channel region is formed in the p-type base region 6 in contact with the gate trench 9 when the gate voltage is applied, the vertical MOSFET performs an operation of passing a current between the drain and the source.

More specifically, electrons injected from the source electrode 13 through the n ⁺ -type source region 7 pass through the channel region to the bottom of the trench gate structure, that is, the JFET portion 2a and the high-concentration n-type layer 20. At this time, the drain voltage Vd is 2 V, and since the high-concentration n-type layer 20 is disposed between the JFET portion 2a and the p-type deep layer 3, the high-concentration n-type layer 20 is a depletion layer. By functioning as an adjustment layer, the following operation is performed.

  Specifically, as shown by a one-dot chain line in FIG. 2A, when the drain voltage Vd is a voltage applied during normal operation, for example, 2 V, the high-concentration n-type layer 20 from the p-type deep layer 3 side is used. The depletion layer that extends to only extends a width smaller than the thickness of the high concentration n-type layer 20. That is, the high-concentration n-type layer 20 functions as a layer that stops the extension of the depletion layer. For this reason, the extension of the depletion layer into the JFET portion 2a is suppressed, and the current can flow without narrowing the current path in the JFET portion 2a. Therefore, a low on-resistance can be achieved.

  Further, a portion of the high-concentration n-type layer 20 where the depletion layer does not extend also functions as a current path. Since the high-concentration n-type layer 20 has an n-type impurity concentration higher than that of the JFET portion 2a and has a low resistance, the high-concentration n-type layer 20 functions as a current path. The on-resistance can be further reduced as compared with the case where only the JFET portion 2a becomes a current path.

Here, when a load short circuit or the like occurs, the drain voltage Vd increases to, for example, 750 V, and becomes higher than the voltage during normal operation. At this time, since 20 V is applied as the gate voltage Vg, a channel region is formed. Therefore, electrons injected from the source electrode 13 reach the bottom of the trench gate structure through the n ⁺ type source region 7 and the channel region.

However, since the drain voltage Vd is higher than the voltage during normal operation, the depletion layer extending from the p-type deep layer 3 side to the high-concentration n-type layer 20 extends beyond the thickness of the high-concentration n-type layer 20. Thus, as indicated by a chain line in FIG. 2B, n ^- -type low concentration layer to the depletion layer spreads so as to enter into 2, the JFET portion 2a, in particular the portion of the ^{n +} -type substrate 1 side of the JFET portion 2a Is pinched off immediately. For this reason, a large resistance is applied to the JFET portion 2a and the n ⁻ -type low concentration layer 2, and electrons reaching the bottom of the trench gate structure do not easily reach the n ⁺ -type substrate 1. Therefore, no current flows, a low saturation current can be maintained, and the tolerance of the SiC semiconductor device due to a load short circuit or the like can be improved.

  Therefore, it is possible to provide a SiC semiconductor device that can achieve both a low on-resistance value and a low saturation current.

  Note that the relationship between the drain voltage Vd and the width of the depletion layer is determined based on the thickness of the high-concentration n-type layer 20 and the n-type impurity concentration. For this reason, the thickness and the n-type impurity concentration of the high-concentration n-type layer 20 and the JFET portion 2a are set so that the JFET portion 2a is pinched off when the voltage becomes slightly higher than the drain voltage Vd during normal operation. ing. As a result, the JFET portion 2a can be pinched off even with a low drain voltage Vd.

  The on-resistance and saturation current of the SiC semiconductor device having the vertical MOSFET having the structure of the present embodiment were examined by simulation. Specifically, as shown in FIG. 1, the case where the trench gate structure and the center position in the width direction of each of the JFET portions 2a are on the same line, that is, the case where there is no mask displacement when forming the gate trench 9 is investigated. It was. Further, as shown in FIG. 3, when the center position in the width direction of each of the trench gate structure and the JFET portion 2a is shifted, the case where the mask shift becomes the maximum value when forming the gate trench 9 is also examined. It was. Regarding the on-resistance, the gate voltage was 20 V, the source voltage Vs was 0 V, and the drain voltage Vd was 2 V. The saturation current was examined with a gate voltage of 20 V, a source voltage Vs of 0 V, and a drain voltage Vd of 750 V.

As a result, in the structure of FIG. 1, the on-resistance was 1.89 mΩ · cm ² and the saturation current was 4593 A / cm ² . In the case of the structure shown in FIG. 3, the on-resistance was 1.91 mΩ · cm ² and the saturation current was 4383 A / cm ² . In other words, the same low on-resistance and low saturation current can be achieved regardless of the presence or absence of mask displacement.

  Therefore, by adopting the structure of this embodiment, even if a mask shift occurs when forming the gate trench 9 for forming the trench gate structure, the SiC semiconductor that can achieve both a low on-resistance value and a low saturation current. Can be a device.

In the present embodiment, the high-concentration n-type layer 20 is also formed at the boundary position between the n ⁻ -type low-concentration layer 2 and the p-type deep layer 3. For this reason, the amount of extension of the depletion layer extending from the p-type deep layer 3 to the n ⁻ -type low concentration layer 2 side is also suppressed, and the current path is suppressed from being narrowed by spreading the depletion layer to the JFET portion 2a side. It is possible to further reduce the on-resistance.

  Further, although examples of n-type impurity concentrations and thicknesses such as the JFET portion 2a and the high-concentration n-type layer 20 are shown, these are merely examples. For example, for the JFET portion 2a and the high concentration n-type layer 20, the n-type impurity concentration and width may be set so as to satisfy a desired pinch-off condition.

  For example, the JFET portion 2a can be designed as a condition for pinching off at 10% of the breakdown voltage of the semiconductor element, for example. In that case, the n-type impurity concentration Nd1 and the width W1 of the JFET portion 2a are set so that the following formula 1 is satisfied, where the n-type impurity concentration is Nd1, the width is W1, the pinch-off voltage is Vp1, the elementary charge is q1, and the dielectric constant is ε1. design.

(Formula 1) Vp1 = (q1 × Nd1 × W1 ² ) / 2ε1 <10% of the breakdown voltage of the semiconductor element
On the other hand, the high-concentration n-type layer 20 can be designed as a condition that does not pinch off at 0.1% of the breakdown voltage of the semiconductor element, for example. In this case, the n-type impurity concentration of the high-concentration n-type layer 20 is Nd2, the thickness on the side surface of the p-type deep layer 3 is W2, the pinch-off voltage is Vp2, the elementary charge is q2, and the dielectric constant is ε2, The n-type impurity concentration Nd2 and the thickness W2 are designed so as to satisfy the above.

(Expression ² ) Vp2 = (q2 × Nd2 × W2 ² ) / 2ε2> 0.1% of the breakdown voltage of the semiconductor element
In this way, the n-type impurity concentration and width of the JFET portion 2a and the high-concentration n-type layer 20 may be set based on the required pinch-off conditions.

  Next, a manufacturing method of the SiC semiconductor device including the vertical MOSFET having the n-channel type inversion trench gate structure according to the present embodiment will be described with reference to cross-sectional views in the manufacturing process shown in FIGS. 4A to 4F. explain.

[Step shown in FIG. 4A]
First, an n ⁺ type substrate 1 is prepared as a semiconductor substrate. Then, n ⁻ type low concentration layer 2 made of SiC is formed on the main surface of n ⁺ type substrate 1 by epitaxial growth. In the case of the present embodiment, since the JFET portion 2a has the same impurity concentration as that of the n ⁻ type low concentration layer 2, the thickness obtained by adding the thickness of the JFET portion 2a as the n type SiC layer for constituting the JFET portion 2a Thus, the n ⁻ type low concentration layer 2 is epitaxially grown.

[Step shown in FIG. 4B]
Etching is performed while covering a region where the JFET portion 2a is to be formed with a mask (not shown) to form a trench 2b in which the region where the p-type deep layer 3 is to be formed is opened. At this time, for example, the trench 2b can be formed by a Bosch process, and the lateral etching is superior to the vertical etching so that the width of the trench 2b gradually increases from the entrance to the bottom of the trench 2b. Etching is performed.

[Step shown in FIG. 4C]
The mask used at the time of etching is used as it is, or a new mask is formed, and, for example, phosphorus is obliquely ion-implanted as an n-type impurity, thereby doping the inner wall surface of the trench 2b with the n-type impurity. Although the oblique ion implantation may be continuously performed at the same angle, the angle is changed so that the n-type impurity can be surely implanted into the side surface of the trench 2b while reaching the depth of the trench 2b. However, it is preferable to do so. Thereby, the high concentration n-type layer 20 is formed in the region doped with the n-type impurity, and the n ⁻ -type low concentration layer 2 other than the high concentration n-type layer 20 located between the trenches 2b is formed. The JFET portion 2a is formed by the portion.

[Step shown in FIG. 4D]
The mask used at the time of ion implantation is used as it is or a new mask is formed, and p-type SiC is epitaxially grown in a state where the tips of the JFET portion 2a and the high-concentration n-type layer 20 are covered. Thereby, p-type SiC is selectively epitaxially grown in the trench 2b, and the p-type deep layer 3 is formed.

[Step shown in FIG. 4E]
Subsequently, the mask covering the tips of the JFET portion 2a and the high-concentration n-type layer 20 is removed, and CMP (chemical mechanical polishing) or the like is performed as necessary to perform the JFET portion 2a, the high-concentration n-type layer 20 and The surface of the p-type deep layer 3 is planarized. Thereafter, the p-type base region 6 is formed by epitaxially growing p-type SiC on these surfaces.

[Step shown in FIG. 4F]
Using a mask (not shown), for example, phosphorus is ion-implanted as an n-type impurity into the surface layer portion of the p-type base region 6 to form an n ⁺ -type source region 7 and, for example, aluminum is ion-implanted as a p-type impurity. The p ⁺ type contact region 8 is formed by the above.

Further, after forming a mask (not shown) on the n ⁺ -type source region 7 and the like, a region where the gate trench 9 is to be formed in the mask is opened. Then, by performing anisotropic etching such as RIE (Reactive Ion Etching) using the mask, the gate trench 9 is formed.

  At this time, the formation position of the gate trench 9 may be shifted due to mask displacement. For example, it is expected that the center position of the gate trench 9 is shifted by 0.1 μm at the maximum with respect to the center position of the JFET portion 2a.

However, since the width of the portion on the p-type base region 6 side is wider than the portion on the n ⁺ -type substrate 1 side in the JFET portion 2a, the gate trench 9 can be positioned in the JFET portion 2a. The p-type deep layer 3 can be prevented from overlapping.

Then, after removing the mask, for example, thermal oxidation is performed to form the gate insulating film 10, and the gate insulating film 10 covers the inner wall surface of the gate trench 9 and the surface of the n ⁺ -type source region 7. Then, after depositing Poly-Si doped with p-type impurities or n-type impurities, this is etched back to leave the Poly-Si at least in the gate trench 9 to form the gate electrode 11.

Although the subsequent steps are not shown, an interlayer insulating film 12 made of, for example, an oxide film is formed so as to cover the surfaces of the gate electrode 11 and the gate insulating film 10. Further, after forming a mask (not shown) on the surface of the interlayer insulating film 12, a portion corresponding to the p ⁺ -type contact region 8 in the mask and its vicinity are opened. Thereafter, the interlayer insulating film 12 is patterned using a mask to form a contact hole exposing the p ⁺ type contact region 8 and the n ⁺ type source region 7.

Further, after forming an electrode material composed of, for example, a stacked structure of a plurality of metals on the surface of the interlayer insulating film 12, the source electrode 13 and the like are formed by patterning the electrode material, and then the n ⁺ type substrate 1 is formed. A drain electrode 14 is formed on the back side. Thereby, the SiC semiconductor device according to the present embodiment is completed.

As described above, in the SiC semiconductor device of the present embodiment, the width of the portion on the p-type base region 6 side of the JFET portion 2a is wider than the portion on the n ⁺ -type substrate 1 side. For this reason, even if a mask shift occurs when forming the gate trench 9, the gate trench 9 can be positioned in the JFET portion 2 a and can be prevented from overlapping the p-type deep layer 3. Therefore, the channel region can be accurately formed on both side surfaces of the trench gate structure, and it is possible to prevent the on-resistance from being reduced.

Further, the side surface of the JFET portion 2a is tapered, and the width of the portion of the JFET portion 2a on the n ⁺ type substrate 1 side is narrowed. For this reason, when the drain voltage Vd becomes higher than the voltage at the time of normal operation, the JFET portion 2a is immediately pinched off, so that a low saturation current can be maintained, and a SiC semiconductor caused by a load short circuit or the like. It becomes possible to improve the tolerance of the apparatus.

  Therefore, it is possible to provide a SiC semiconductor device having a structure in which the p-type deep layer 3 and the trench gate structure do not overlap while achieving both a low on-resistance value and a low saturation current.

(Second Embodiment)
A second embodiment will be described. In this embodiment, the manufacturing method is changed with respect to the first embodiment, and the other parts are the same as those in the first embodiment. Therefore, only the parts different from the first embodiment will be described.

In the present embodiment, the method for forming the JFET portion 2a, the p-type deep layer 3, and the high-concentration n-type layer 20 is changed with respect to the first embodiment. Therefore, as shown in FIG. 5, in the present embodiment, the high concentration n-type layer is located at the boundary between the p-type deep layer 3 and the n ⁻ -type low concentration layer 2 with respect to the SiC semiconductor device of the first embodiment. It is set as the structure where 20 is not provided.

  A method for manufacturing the SiC semiconductor device according to the present embodiment will be described with reference to FIGS. 6A to 6H.

First, as a step shown in FIG. 6A, an n ⁻ type low concentration layer 2 made of SiC is formed on the main surface of the n ⁺ type substrate 1 by epitaxial growth. This step is the same as in FIG. 4A, but the thickness of the n ⁻ type low concentration layer 2 is set to a thickness that does not take into account the thickness of the JFET portion 2a.

Next, as a process shown in FIG. 6B, a p-type SiC layer for forming the p-type deep layer 3 is epitaxially grown on the surface of the n ⁻ -type low concentration layer 2. Then, as a process shown in FIG. 6C, the surface of the portion of the p-type SiC layer that is finally left as the p-type deep layer 3 is covered with a mask (not shown), and then etched to form trenches in the region where the JFET portion 2a is to be formed. 3a is formed. At this time, the width of the entrance side of the trench 3a is made wider than the bottom side. Further, as a process shown in FIG. 6D, a high concentration n-type layer 20 is formed by oblique ion implantation of n-type impurities into the inner wall surface of the trench 3a, and as a process shown in FIG. 6E, the high concentration n-type layer 20 is formed by etching. Of these, the portion formed at the bottom of the trench 3a is removed. Thereafter, in FIG. 6F to FIG. 6H and the like, FIG. 4E and FIG. 4F described in the first embodiment and subsequent steps are performed. Thereby, the SiC semiconductor device of this embodiment shown in FIG. 5 is completed.

  In this way, the trench 3a is formed in the p-type deep layer 3, and the n-type impurity is ion-implanted into the inner wall of the trench 3a to form the high-concentration n-type layer 20, and the JFET is embedded in the trench 3a. The part 2a can also be formed. Also with such a manufacturing method, a SiC semiconductor device that can achieve both low on-resistance and low saturation current can be manufactured as in the first embodiment. In the case of this embodiment, since the width of the entrance side of the trench 3a is wider than the bottom side, the JFET portion 2a can be epitaxially grown in the trench 3a with good embedding.

Although the high concentration n-type layer 20 formed at the bottom of the trench 3a is removed here, it may not be removed. If the high-concentration n-type layer 20 is left, the amount of depletion layer extending from the p-type deep layer 3 on the boundary position side with the JFET portion 2a in the n ⁻ -type low-concentration layer 2 during normal operation can be suppressed. Since the current path can be prevented from narrowing, a lower on-resistance can be achieved.

(Third embodiment)
A third embodiment will be described. This embodiment is different from the first and second embodiments in the n ^- type low concentration layer 2 and the n-type impurity concentration of the JFET portion 2a, and the others are the same as the first and second embodiments. Since it is the same, only a different part from 1st, 2nd embodiment is demonstrated. In addition, although the case where this embodiment is applied to the structure of 1st Embodiment is demonstrated here, it can apply similarly to the structure of 2nd Embodiment.

As shown in FIG. 7, in this embodiment, the n-type impurity of the JFET portion 2 a is set lower than the n-type impurity concentration of the n ⁻ -type low concentration layer 2. For example, the n-type impurity concentration of the JFET portion 2a is set to 1 × 10 ¹⁵ / cm ³ .

  In such a configuration, the off-time operation is the same as that of the SiC semiconductor device of the first embodiment, but the on-time operation is as follows.

That is, the current path is formed by performing the same operation as that of the SiC semiconductor device of the first embodiment even when the device is on, but the resistance value of the JFET portion 2a is reduced by reducing the n-type impurity concentration of the JFET portion 2a. Becomes higher. For this reason, even if the drain voltage Vd rises to, for example, 750 V due to a load short circuit or the like, the saturation current can be reduced as much as the resistance value in the JFET portion 2a is increased. As a result of simulation with a gate voltage of 20 V, a source voltage Vs of 0 V, and a drain voltage Vd of 750 V, the on-resistance was 1.91 mΩ · cm ² , but the saturation current was reduced to 2500 A / cm ² . Such a configuration is effective when it is desired to further reduce the saturation current.

  The manufacturing method of the SiC semiconductor device of this embodiment is the same as that of the first and second embodiments, and it is only necessary to reduce the n-type impurity concentration in the epitaxial growth when the JFET portion 2a is formed.

(Fourth embodiment)
A fourth embodiment will be described. In the present embodiment, the on-resistance is further reduced as compared to the first to third embodiments, and the other aspects are the same as those of the first to third embodiments, and thus the first to third embodiments. Only different parts will be described. In addition, although the case where this embodiment is applied to the structure of 2nd Embodiment is demonstrated here, it can apply similarly to the structure of 1st, 3rd embodiment.

  As shown in FIG. 8, in this embodiment, the n-type current distribution layer 4 is formed in the surface layer portion of the JFET portion 2a.

The n-type current distribution layer 4 is a layer that allows the current flowing through the channel region to diffuse in the width direction, and has a higher concentration than the JFET portion 2a. The n-type current distribution layer 4 has an n-type impurity concentration of, for example, 1 × 10 ¹⁸ to 1 × 10 ²⁰ / cm ^3, and is set to 1 × 10 ¹⁹ / cm ³ here. The thickness of the n-type current spreading layer 4 is, for example, 0.2 to 0.6 μm, and is 0.4 μm here.

In this way, by forming the n-type current distribution layer 4, in addition to being able to reduce the resistance value as compared with the case where only the JFET portion 2a is configured, it is possible to diffuse the current in the width direction, thereby further reducing the on-resistance. Can be achieved. As a result of simulation with a gate voltage of 20 V, a source voltage Vs of 0 V, and a drain voltage Vd of 2 V, the on-resistance was 1.80 mΩ · cm ² . Further, when the drain voltage Vd was changed to 750 V under these conditions, the saturation current was 4839 A / cm ² . Such a configuration is effective when the on-resistance is desired to be lowered, although the saturation current is slightly higher than in the first embodiment.

  The manufacturing method of the SiC semiconductor device according to this embodiment is basically the same as that of the first to third embodiments, and it is only necessary to epitaxially grow the n-type current distribution layer 4 as it is on the JFET portion 2a. . For example, in the case of the structure of the second embodiment, after performing the same process as in FIGS. 6A to 6E, when the JFET portion 2a is selectively epitaxially grown as shown in FIG. 9A, the trench 3a is buried. Before the end, the n-type current distribution layer 4 is formed by increasing the n-type impurity concentration. Thereafter, in FIG. 9B, FIG. 9C, etc., FIG. 4E and FIG. 4F described in the first embodiment and subsequent steps are performed. Thereby, the SiC semiconductor device of this embodiment shown in FIG. 8 is completed.

(Other embodiments)
The present invention is not limited to the embodiment described above, and can be appropriately changed within the scope described in the claims.

  For example, the above-described embodiments are not irrelevant to each other and can be combined as appropriate unless the combination is clearly impossible.

  In addition, the width of the JFET portion 2a does not have to be a tapered shape with a constant inclination in the entire region in the depth direction, and the inclination angle may be changed.

  Moreover, the impurity concentration of each part may not be constant. For example, a structure having an impurity concentration gradient in which the p-type impurity concentration decreases as the p-type deep layer 3 approaches the drain electrode 14 and increases as the p-type deep layer 3 approaches the source electrode 13 may be employed.

  Similarly, the dimensions and impurity concentrations of the respective parts constituting the SiC semiconductor device described in the above embodiments are merely examples. What is necessary is just to set suitably the dimension and impurity concentration of each part based on the pinch-off conditions of the JFET part 2a, etc.

  As an example, the half cell pitch can be changed, for example, the half cell pitch can be widened, for example, 3 μm. Further, the p-type deep layer 3 can be made thin to increase the impurity concentration. However, those listed here are only examples, and other dimensions and impurity concentrations may be used.

In the first embodiment and the like, an n-channel type vertical MOSFET in which the first conductivity type is n-type and the second conductivity type is p-type has been described as an example. An inverted p-channel type vertical MOSFET may be used. In the above description, a vertical MOSFET has been described as an example of a semiconductor element, but the present invention can be applied to an IGBT having a similar structure. The IGBT only changes the conductivity type of the n ⁺ type substrate 1 from the n-type to the p-type with respect to the above-described embodiments, and the other structures and manufacturing methods are the same as those in the above-described embodiments.

2 n ⁻ type low concentration layer 2 a JFET portion 3 p type deep layer 4 n type current spreading layer 6 p type base region 7 n ⁺ type source region 10 gate insulating film 11 gate electrode 13 source electrode 14 drain electrode

Claims (8)

A silicon carbide semiconductor device comprising an inversion type semiconductor element,
A first or second conductivity type substrate (1) made of silicon carbide;
A low concentration layer (2) made of silicon carbide of the first conductivity type formed on the substrate and having a lower impurity concentration than the substrate;
A second conductivity type deep layer (3) made of silicon carbide of the second conductivity type formed on the low concentration layer;
A first conductivity type JFET portion (2a) formed on the low concentration layer and disposed between the deep layers;
A depletion layer adjusting layer (20) disposed between the JFET portion and the deep layer and having a first conductivity type impurity concentration higher than that of the JFET portion;
A second conductivity type base region (6) formed on the deep layer, the JFET portion and the depletion layer adjustment layer;
A source region (7) formed on the base region and made of silicon carbide of the first conductivity type having a higher concentration than the low concentration layer;
A part of the base region is defined as a channel region in a linear gate trench (9) that extends through the source region and the base region to reach the JFET portion and has one direction as a longitudinal direction. A trench gate structure comprising: a gate insulating film (10) formed on the gate insulating film; and a gate electrode (11) formed on the gate insulating film;
An interlayer insulating film (12) covering the gate electrode and the gate insulating film and having contact holes formed therein;
A source electrode (13) electrically connected to the source region through the contact hole;
A drain electrode (14) formed on the back side of the substrate,
The channel region is formed by applying a gate voltage to the gate electrode, and a normal operation voltage is applied to the drain electrode as a drain voltage via the source region and the JFET portion. An inversion type semiconductor element that allows current to flow between the source electrode and the drain electrode,
The JFET portion is formed at a position corresponding to the trench gate structure and extends along the longitudinal direction of the gate trench, and is wider on the trench gate structure side than the substrate side,
When the normal operation voltage is applied as the drain voltage, the depletion layer extending from the deep layer is stopped at the depletion layer adjustment layer, and the drain voltage is higher than the normal operation voltage. Is applied, the JFET portion is pinched off by the depletion layer at a position on the substrate side in the JFET portion.   2. The width of the JFET portion closest to the base region and the depletion layer adjusting layer located on both sides of the JFET portion is 0.2 μm or more larger than the width of the trench gate structure. The silicon carbide semiconductor device described.   The silicon carbide semiconductor device according to claim 1, wherein the depletion layer adjustment layer is also formed between the deep layer and the low concentration layer.   4. The silicon carbide semiconductor device according to claim 1, wherein a first conductivity type impurity concentration of the JFET portion is lower than a first conductivity type impurity concentration of the low concentration layer. 5.   The surface layer portion of the JFET portion is provided with a first conductivity type current spreading layer (4) having a first conductivity type impurity concentration higher than that of the JFET portion. The silicon carbide semiconductor device described in 1. A method for manufacturing a silicon carbide semiconductor device comprising an inversion type semiconductor element,
Providing a first or second conductivity type substrate (1) made of silicon carbide;
Forming a low concentration layer (2) made of silicon carbide of the first conductivity type having a lower impurity concentration than the substrate on the substrate;
On the low concentration layer, a second conductivity type deep layer (3) made of second conductivity type silicon carbide, and a first conductivity type JFET portion (2a) disposed between the deep layers, Forming a depletion layer adjustment layer (20) disposed between the JFET portion and the deep layer and having a first conductivity type impurity concentration higher than that of the JFET portion;
Forming a base region (6) made of silicon carbide of the second conductivity type on the deep layer, the JFET portion, and the depletion layer adjustment layer;
Forming a source region (7) made of silicon carbide of the first conductivity type having a higher concentration than the low concentration layer on the base region;
After forming the line-shaped gate trench (9) extending through the source region and the base region to reach the JFET portion and having one direction as a longitudinal direction, a part of the base region is formed in the gate trench. Forming a trench gate structure by forming a gate insulating film (10) on the channel region as a channel region, and further forming a gate electrode (11) on the gate insulating film;
Forming an interlayer insulating film (12) covering the gate electrode and the gate insulating film;
Forming a contact hole in the interlayer insulating film;
Forming a source electrode (13) electrically connected to the source region through the contact hole;
By forming a drain electrode (14) on the back side of the substrate,
The channel region is formed by applying a gate voltage to the gate electrode, and a normal operation voltage is applied to the drain electrode as a drain voltage via the source region and the JFET portion. Forming an inversion type semiconductor element for passing a current between the source electrode and the drain electrode,
In forming the deep layer and the JFET portion and the depletion layer adjustment layer,
The JFET portion is formed at a position corresponding to the trench gate structure and extends along the longitudinal direction of the gate trench, and further, the width on the trench gate structure side is wider than the substrate side,
When the voltage at the time of the normal operation is applied as the drain voltage, the width at the position of the substrate side of the JFET portion and the depletion layer adjusting layer is the amount of extension of the depletion layer extending from the deep layer. A method of manufacturing a silicon carbide semiconductor device, which is stopped at the depletion layer adjustment layer and has a width that allows the JFET portion to be pinched off by the depletion layer when a higher voltage than the normal operation is applied as the drain voltage. Forming the deep layer and the JFET portion and the depletion layer adjustment layer,
Forming a first conductivity type silicon carbide layer constituting the JFET portion on the low concentration layer;
Forming a trench (2b) for opening a region where the deep layer is to be formed in the silicon carbide layer;
Forming the depletion layer adjusting layer by implanting the first conductivity type obliquely into the inner wall surface of the trench;
The silicon carbide semiconductor device according to claim 6, further comprising: forming the deep layer by filling the trench after the depletion layer adjustment layer is formed with a silicon carbide layer of a second conductivity type. Manufacturing method. Forming the deep layer and the JFET portion and the depletion layer adjustment layer,
Forming a second conductivity type silicon carbide layer constituting the deep layer on the low concentration layer;

Forming a trench (3a) for opening a region where the JFET portion is to be formed in the silicon carbide layer;
Forming the depletion layer adjusting layer by implanting the first conductivity type obliquely into the inner wall surface of the trench;
The silicon carbide semiconductor device according to claim 6, further comprising: forming the JFET portion by burying the trench after the depletion layer adjusting layer is formed with a silicon carbide layer of a first conductivity type. Manufacturing method.

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