JP2019153985A - Imaging apparatus - Google Patents

Abstract

To provide an imaging apparatus that can suitably realize AD conversion with a large number of conversion bits.SOLUTION: The imaging apparatus includes: a pixel that outputs a pixel signal; an amplification unit that amplifies the pixel signal; a determination unit that determines a magnitude relationship between an amplified output signal output from the amplification unit and a threshold; and an AD converter for converting the amplified output signal into a digital signal, configured to perform a first AD conversion when it is determined that the amplified output signal is equal to or lower than the threshold value and perform a second AD conversion when it is determined that the amplified output signal is greater than the threshold. When the AD converter performs the second AD conversion, the AD converter converts the amplified output signal into a digital signal in a range in which the amplified output signal takes a value equal to or greater than a reference value on the basis of the threshold.SELECTED DRAWING: Figure 1

Description

  The present invention relates to an imaging apparatus.

  In an imaging apparatus having an AD conversion unit that converts a pixel signal output from a pixel into a digital signal, a method of performing signal processing by using a plurality of gains is known. In Patent Document 1, after a signal is roughly distributed using a plurality of reference voltages, AD conversion with a small number of conversion bits is performed, and calibration is performed by a signal processing circuit at a subsequent stage to increase the number of bits for AD conversion. An imaging device is described. Patent Document 2 discloses a method for reducing an offset between converted digital signals in an imaging apparatus that selects a plurality of reference voltages having different amounts of change per unit time according to an amplified output signal and uses them for AD conversion. Are listed.

JP 2011-250039 A JP 2014-140152 A

  However, in Patent Document 1, when an AD conversion with a larger number of conversion bits is to be realized, an overlapping portion of data to be calibrated increases, and a circuit, a memory for performing calibration, and power consumption increase. There was a problem that. Further, in Patent Document 2, a detailed study is not made on processing of an output signal in which a reference signal having a large change amount per unit time and a reference signal having a small change amount per unit time overlap.

  The present invention has been made in view of the above problems. An object of the present invention is to provide an imaging apparatus that can suitably realize AD conversion having a large number of conversion bits.

The present invention employs the following configuration. That is,
A pixel that outputs a pixel signal;
An amplifying unit for amplifying the pixel signal;
A determination unit that determines a magnitude relationship between the amplified output signal output from the amplification unit and a threshold;
An AD converter that converts the amplified output signal into a digital signal, and when the amplified output signal is determined to be equal to or less than the threshold value, performs first AD conversion, and the amplified output signal is greater than the threshold value; An AD converter that performs second AD conversion if determined,
With
The AD converter, when performing the second AD conversion, converts the amplified output signal into the digital signal in a range where the amplified output signal takes a value equal to or higher than a reference value based on the threshold value. It is an imaging device.

  According to the present invention, it is possible to provide an imaging apparatus that can suitably realize AD conversion with a large number of conversion bits.

Schematic diagram showing the imaging apparatus of Example 1 The figure which shows the drive timing of the basic process of Example 1. FIG. Another diagram showing the drive timing of the basic processing of the first embodiment AD conversion gain switching image of the first embodiment The figure which shows the process drive timing of Example 1. FIG. Another diagram showing processing drive timing of the first embodiment Another diagram showing processing drive timing of the first embodiment Schematic diagram illustrating the imaging apparatus of Example 2 The figure which shows the drive timing of the basic process of Example 2. FIG. Another diagram showing the drive timing of the basic processing of the second embodiment The figure which shows the process drive timing of Example 2. Another diagram showing processing drive timing of the second embodiment Another diagram showing processing drive timing of the second embodiment Schematic configuration diagram of pixels included in the pixel unit Schematic configuration block diagram of an imaging system using an imaging device The figure which shows the system and moving body using an imaging device

  Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings. However, the dimensions, materials, shapes, and relative arrangements of the components described below should be appropriately changed depending on the configuration of the apparatus to which the invention is applied and various conditions. Therefore, the scope of the present invention is not intended to be limited to the following description.

<Example 1>
(Device configuration)
Hereinafter, an imaging apparatus of the present invention will be described with reference to the drawings. FIG. 1 is a schematic diagram of an imaging apparatus assumed in the first embodiment. The imaging device 100 shown in FIG. 1 is configured on the same semiconductor substrate.

  The imaging apparatus 100 includes a pixel unit 10 in which pixels 1 are arranged in a plurality of rows and columns. Each pixel 1 outputs a signal charge based on the charge photoelectrically converted in accordance with the intensity of incident light to the amplifying unit 20 as a pixel signal in accordance with the scanning of the vertical scanning circuit 15. The pixel signal output from the pixel 1 may include a noise signal in addition to a signal charge (photoelectric conversion signal) based on the photoelectrically converted charge. The pixel 1 includes, for example, a photodiode that is a photoelectric conversion unit, a transfer transistor that reads signal charges, a charge detection unit that has a floating diffusion structure, an amplification transistor that has a source follower circuit, a row selection transistor, a reset transistor, and the like. .

The vertical scanning circuit 15 scans the pixels 1 for each row based on a signal output from a timing generator (hereinafter, TG) 70. The TG 70 can function as a control unit that outputs various control pulses. In addition, a processing circuit that functions as a control unit may be provided in the imaging apparatus separately from the TG 70 or in cooperation with the TG 70.
The amplification unit 20 amplifies the pixel signal by the amplification circuit 201 and outputs the pixel signal to the comparison circuit 301 included in the comparison unit 30. The amplification unit 20 is provided in an electrical path between the comparison unit 30 and the pixel 1.

The reference voltage supply unit 25 outputs a plurality of reference voltages to the selection circuit 302 in each column. The determination circuit 202 is a determination unit that compares the pixel signal after amplification (amplified output signal) output from the amplification unit 20 with the threshold voltage Vj and determines the magnitude relationship between the two. The threshold value may be set to the most significant bit of a signal when low luminance is processed, or may be set to a value slightly smaller (for example, about 5 to 10%) than the most significant bit. Further, the threshold value for determination may be variable according to user input or the like. The selection circuit 302 selects a reference voltage to be output to the comparison circuit 301 from a plurality of reference voltages based on the determination result signal Jdg indicating the result of comparison by the determination circuit 202. The comparison circuit 301 outputs a comparison result signal CMP indicating the result of comparing the signal output from the amplification unit 20 and the reference voltage to the memory unit 50. The reference voltage is a signal whose potential changes depending on time, and the maximum value of the pixel signal that can be processed within a unit time increases as the potential change rate per unit time increases.

The memory unit 50 includes a flag memory 501, a first memory 502, and a second memory 503. A determination result signal Jdg is written in the flag memory 501, a photoelectric conversion signal is written in the first memory 502, and a noise signal is written in the second memory 503.
The TG 70 outputs a signal F_En to the flag memory 501. The counter 40 outputs a count signal obtained by counting the clock signal CLK to the first memory 502 and the second memory 503. The TG 70 outputs M1_En and M2_En to the first memory 502 and the second memory 503, respectively.

The horizontal scanning circuit 60 causes the DSP 80 to sequentially output digital signals held in the flag memory 501, the first memory 502, and the second memory 503 of each column. The DSP 80 functions as a processing unit, processes signals output from the flag memory 501, the first memory 502, and the second memory 503 in each column and outputs them to the output circuit 90. The output circuit 90 outputs a signal to the outside of the imaging device based on the signal output from the TG 70. The DSP 80 may connect digital signals obtained with different gains according to the gain ratio. Any known method may be employed for the joining process.
In the imaging apparatus illustrated in FIG. 1, the AD conversion unit 110 includes a comparison unit 30 and a memory unit 50. In addition, each column of the AD conversion unit 110 is provided corresponding to each column of the pixels 1.

(Conventional basic operation flow)
First, prior to describing the first embodiment of the present invention, the conventional basic operation of the imaging apparatus assumed in the first embodiment will be described. The operation of the imaging device shown in FIG. 1 will be described with reference to the timing charts of FIGS. 2A and 2B. The difference between FIG. 2A and FIG. 2B is FIG. 2A when the level of the photoelectric conversion signal is lower than the threshold voltage Vj, and FIG. 2B when the level is higher than the threshold voltage Vj. At each timing, “a” is added to the end in FIG. 2A, and “b” is added to the end in FIG. 2B.

  2A and 2B, Out_Vline represents a pixel signal potential, Amp_Gain represents the gain of the amplifier circuit 201, and Out_Amp represents a signal (amplified output signal) output from the amplifier unit 20. Vr1 and Vr2 are reference voltages output from the reference voltage supply unit 25, respectively. The reference voltage Vr1 is a first reference voltage whose potential changes with a first change amount per unit time. The reference voltage Vr2 is a second reference voltage whose potential changes with a second change amount larger than the first change amount per unit time. The ratio of the amount of change between Vr1 and Vr2 corresponds to the gain ratio of conversion. 2A and 2B, the gain ratio is described as 4, but may be changed as appropriate. The reference voltage Vr1 corresponds to the first reference signal. The reference voltage Vr2 corresponds to the second reference signal.

At times t21a and t21b, a signal corresponding to a noise signal is output from the pixel 1.
From time t22a, t22b, the counter 40 starts counting and the reference voltage Vr1 is input.
At times t23a and t23b, the signal value of the comparison result signal CMP becomes High at the timing when the reference voltage Vr1 becomes higher than Out_Amp. The count signal at this time is written and held in the second memory 503.

Subsequently, a photoelectric conversion signal is output from the pixel 1 at times t24a and t24b.
At times t25a and t25b, the output level is determined for the threshold voltage Vj output from the TG 70. At this time, when the output signal Out_Amp of the amplification unit 20 is equal to or lower than the threshold voltage Vj, that is, when the output signal Out_Amp is equal to or lower than the threshold as shown in FIG. 2A, the determination circuit 202 outputs the determination result signal Jdg at the L level. L level is written. Further, Vr1 is selected by the selection circuit 302 as a reference voltage.
On the contrary, when the threshold voltage Vj is larger than the output signal Out_Amp of the amplification unit 20, that is, in the case of FIG. 2B, the determination circuit 202 outputs the determination result signal Jdg of H level, and the H level is output to the flag memory 501. Written. Further, Vr2 is selected by the selection circuit 302 as a reference voltage. Note that the terms “below” and “greater than” regarding the magnitude relationship between the threshold voltage Vj and the output signal Out_Amp may be replaced with “less than” and “more than”.

Regarding the subsequent operation, first, the case of FIG. 2A (when the determination result signal Jdg of the determination circuit 202 is at the L level) will be described. This process is also called first AD conversion. At time t26a, the counter 40 starts counting and the reference voltage Vr1 is input.
At time t27a, the signal value of the comparison result signal CMP becomes High at the timing when the reference voltage Vr1 becomes larger than Out_Amp. The count signal at this time is written and held in the first memory 502.
Further, at time t28a, the input of the reference voltage Vr1 is completed.

  Thereafter, the downstream DSP 80 subtracts the signal written in the second memory 503 from the signal written in the first memory 502 by the digital value. By performing the above processing, it is possible to accurately convert the output signal Out_Amp of the amplification unit 20 that is an analog signal into a digital signal while removing the noise signal from the photoelectric conversion signal.

Next, the case of FIG. 2B (when the determination result signal Jdg of the determination circuit 202 is at the H level) will be described. This process is also called second AD conversion. At this time, Vr2 is selected by the selection circuit 302 as a reference voltage. At time t26b, the counter 40 starts counting and the reference voltage Vr2 is input.
At time t27b, the signal value of the comparison result signal CMP becomes High at the timing when the reference voltage Vr2 becomes higher than Out_Amp. The count signal at this time is written and held in the first memory 502.
Further, at time t28b, the input of the reference voltage Vr2 is completed.

In the case of FIG. 2B, the DSP 80 at the subsequent stage does not simply subtract the signal written in the second memory 503 from the signal written in the first memory 502 in the digital value. Instead, the signal of the first memory 502 is first multiplied by 4 which is the gain ratio of the reference voltages Vr1 and Vr2. Thereafter, a subtraction process is performed.
By performing such processing, for example, even when 10-bit AD conversion is performed, an AD conversion result corresponding to 12 bits (4 times 10 bits) can be obtained. As a result, it is possible to accurately convert the output signal Out_Amp of the amplification unit 20 that is an analog signal into a digital signal while removing a noise signal from the photoelectric conversion signal. That is, the dynamic range of AD conversion can be expanded by switching the processing of FIGS. 2A and 2B according to the signal level.

FIG. 3 shows an output image of a digital signal obtained by performing the operations of FIGS. 2A and 2B. When 10-bit AD conversion is performed, the signal AD-converted using the reference voltage Vr1 in FIG. 2A takes a digitally continuous value from 0 to 1023.
On the other hand, a gain ratio of 4 is further multiplied to the signal AD-converted using the reference voltage Vr2 in FIG. 2B. As a result, the digital value ranges from 0 to 4092, but becomes a discrete value in increments of 4. In order to reduce the influence of the discrete values on the image quality, a digital value in which photon shot noise becomes dominant is considered. Since the photon shot noise corresponds to the square root of the signal amount, if it is a signal of 1000 electrons, about 30 electrons correspond to the photon shot noise, which can be said to be sufficiently large with respect to the signal of every 4 steps.
As described above, the operation described in FIG. 2A is used until the photoelectric conversion signal corresponding to 1023, and the operation described in FIG. 2B is used for the photoelectric conversion signal exceeding 1023, thereby reducing the influence of taking discrete values. When connecting the values obtained by the operation of FIG. 2A and the operation of FIG. 2B, an existing method such as Patent Document 2 may be used.

(Operation flow of this embodiment)
Next, Embodiment 1 of the present invention will be described with reference to operation timing charts of FIGS. 4A to 4C. 4A to 4C are drive timing diagrams of the image pickup apparatus of the present embodiment. 4A to 4C, the same parts as those in FIGS. 2A to 2B are denoted by the same reference numerals, and detailed description thereof is omitted. At each timing, “a” to “c” are appended to the end in FIGS. 4A to 4C. Any of these processes can be said to be a modification of the second AD conversion described above.

  As described above, among the signals AD-converted using the reference voltage Vr2, the portion of the small digital value that overlaps the signal AD-converted using the reference voltage Vr1 is the final output of the imaging device 100. Is not used. The threshold value for determining whether or not this is finally used corresponds to the threshold voltage Vj. When the reference voltage Vr2 is used, a signal equal to or lower than the threshold voltage Vj is not used as a final output. When a signal level equal to or lower than the threshold voltage Vj is input, the reference voltage Vr1 is selected in the first place. Therefore, in FIG. 2B, it is not necessary to perform conversion until the reference voltage Vr2 exceeds the threshold voltage Vj. In view of the above, in FIGS. 4A to 4C, when the reference voltage Vr2 is used, the reference voltage that starts as a reference is the threshold voltage Vj.

(Operation example of this embodiment)
The drive timing chart of FIG. 4A will be described. FIG. 4A corresponds to FIG. 2B and assumes a case where the output signal Out_Amp of the amplification unit 20 is larger than the threshold voltage Vj. The operation up to time t45a is AD conversion of the noise signal as in the case up to time t25b of FIG.

At time t45a, the output level is determined for the threshold voltage Vj output from the TG 70. At this time, since the output signal Out_Amp of the amplification unit 20 is larger than the threshold voltage Vj, the determination circuit 202 outputs the determination result signal Jdg of H level, and the H level is written in the flag memory 501. Furthermore, Vr2_1 is selected from the reference voltage supply unit 25 as the reference voltage. At this time, the reference voltage Vr2_1 is different from FIG. 2B in that it is a signal that changes with the threshold voltage Vj as a reference value. That is, the reference voltage Vr <b> 2 </ b> _ <b> 1 is a value at which the potential changes within a range of values that are equal to or greater than a threshold value (greater than a reference value).
Here, at a certain time during a period from t42a to t43a, the comparison unit outputs a value less than the reference value (both the first value) as a part of the changing potential of the reference voltage (reference signal) compared with the amplified output signal. Potential) is input.

At time t46a, the counter 40 starts counting and the reference voltage Vr2_1 changes.
At time t47a, the signal value of the comparison result signal CMP becomes High at the timing when the reference voltage Vr2_1 becomes higher than Out_Amp. The count signal at this time is written and held in the first memory 502.
Further, at time t48a, the input of the reference voltage Vr2_1 is completed.
Here, the time t47a and the time t48a are earlier than the time t27a of FIG. 2B by the offset corresponding to the threshold voltage Vj. Therefore, since the time during which the reference voltage has to be input can be shortened, the supply of the reference voltage can be stopped quickly, and the power consumption can be reduced accordingly. The power consumption can also be reduced by causing the supply start timing of the reference voltage to be sent more than before and the supply end timing to be the same as the conventional one. In addition, if the supply period of the reference voltage can be made shorter than before, power consumption can be reduced.

  Here, at a certain time during a period from t46a to t48a, a potential indicating a value equal to or greater than t (also referred to as a second value) is input to the reference as a part of the potential at which the reference voltage compared with the amplified output signal changes. The The reference voltage temporarily passes the first value at the time of rising immediately after t45a. However, immediately after the rise of the signal, the comparison process is invalidated by switching of Mj_en. Accordingly, at this time, the comparison unit does not compare the potential indicating the first value as the potential to be converted by the reference voltage with the amplified output signal.

  In this case, the DSP 80 at the subsequent stage does not simply subtract the signal written in the second memory 503 from the signal written in the first memory 502 in the digital value. Instead, the DSP 80 first adds a digital value corresponding to the offset of the threshold voltage Vj to the signal of the first memory 502, and then multiplies by 4 which is the gain ratio of the reference voltages Vr1 and Vr2_1. By performing such processing, the result of AD conversion equivalent to 12 bits (four times 10 bits) can be obtained even when, for example, 10-bit AD conversion is performed as in FIG. 2B. . As a result, it is possible to accurately convert the output signal Out_Amp of the amplification unit 20 that is an analog signal into a digital signal while removing a noise signal from the photoelectric conversion signal. By using the imaging apparatus and driving method of this embodiment, power consumption can be reduced.

(Modification 1-1)
Next, another embodiment of the first embodiment of the present invention will be described with reference to the operation timing chart of FIG. 4B. In FIG. 4B, the same parts as those in FIGS. 2A to 2B and 4A are denoted by the same reference numerals, and detailed description thereof is omitted. The operation up to time t47b is the same as that up to time t47a in FIG.

  FIG. 4B is different from FIG. 4A in the timing when the input of the reference voltage Vr2 ends. That is, the time t48b in FIG. 4B is extended from the time t48a in FIG. 4A and has the same timing as the time t28b in FIG. 2B.

  By extending the input of the reference voltage Vr2 to such timing and setting it to Vr2_2, it is possible to perform AD conversion up to a larger output signal Out_Amp. Therefore, AD conversion can be performed up to a final digital output value that is larger than 12 bits by the number of bits of the digital value of the threshold voltage Vj. That is, the dynamic range of signal output as the imaging apparatus 100 can be expanded by using the imaging apparatus and driving method of this modification.

  The time required for extending t48b can be secured by raising the start value at t46b to Vj and causing an offset. Therefore, even when a pixel signal is output from a pixel at a predetermined cycle, the dynamic range can be expanded without delaying the processing cycle. Further, the extension period of the comparison time in the AD conversion is set within the range of the processing time reduced by the present modification, that is, within the time range necessary for converting the pixel signal having a value equal to or lower than the threshold voltage Vj. It is preferable.

(Modification 1-2)
Next, still another embodiment of the first embodiment of the present invention will be described with reference to the operation timing chart of FIG. 4C. In FIG. 4C, parts similar to those in FIGS. 2A to 2B and FIGS. 4A to 4B are denoted by the same reference numerals, and detailed description thereof is omitted. The operation up to time t46c is the same as that up to time t46b of FIG.

  FIG. 4C differs from FIG. 4B in the amount of change per unit time of the reference voltage Vr2. The maximum voltage value at the time t48c of the reference voltage Vr2_3 in this embodiment is equal to the maximum voltage value at the time t28b in FIG. 2B. Therefore, the amount of change per unit time can be suppressed compared to FIG. 4B. Here, the change amount of the potential per unit time at the reference voltage Vr1 is set as a first change amount, and the change amount of the potential per unit time at the reference voltages Vr2, Vr2_1, Vr2_2 is set as the second change amount. . Then, the third change amount, which is the change amount of the potential per unit time of the reference voltage Vr2_3, is larger than the first change amount and smaller than the second change amount. As a result, the ratio of the change amounts of the reference voltages Vr1 and Vr2_3 is suppressed to be smaller than the change ratio in FIG. 2B. That is, the conversion gain ratio is small. For example, in FIG. 4C, the gain ratio is 3.

  As described above, when a signal is output as the imaging apparatus 100, the signal AD-converted using the reference voltage Vr2_3 is multiplied by the gain ratio (3 in this case). As a result, the digital value of the output signal is a value from 0 to 4092, and takes a discrete value in increments of 3. That is, by using the imaging apparatus and driving method of the present embodiment, it is possible to reduce quantization errors related to AD conversion of signal output as the imaging apparatus 100.

  The gain ratio may take a different value other than 3. For example, the gain ratio may be 3.5, and may be used in combination with the reduction in power consumption or the expansion of the dynamic range described above. By using the imaging apparatus and driving method of this modification, the performance of the imaging apparatus is further improved.

<Example 2>
(Device configuration)
FIG. 5 is a schematic diagram of the imaging apparatus 100 assumed in the second embodiment, and is configured on the same semiconductor substrate. The same parts as those in the first embodiment are denoted by the same reference numerals, and detailed description may be omitted.

  The imaging apparatus 100 includes a pixel unit 10 in which pixels 1 are arranged in a plurality of rows and columns. Each pixel 1 outputs a signal charge based on the charge photoelectrically converted in accordance with the intensity of incident light to the amplifying unit 20 as a pixel signal in accordance with the scanning of the vertical scanning circuit 15. The pixel signal output from the pixel 1 may include a noise signal in addition to a signal charge (photoelectric conversion signal) based on the photoelectrically converted charge.

  The vertical scanning circuit 15 scans the pixels 1 for each row based on a signal output from a timing generator (hereinafter referred to as TG) 70. The amplification unit 20 amplifies the pixel signal by the amplification circuit 201 and outputs the pixel signal to the comparison circuit 301 included in the comparison unit 30. In the present embodiment, the gain of the amplifier circuit 201 is selected based on a determination result signal Jdg indicating the result of comparing the signal output from the amplifier 20 and the threshold voltage Vj by the determination circuit 202. The amplification unit 20 is provided in an electrical path between the comparison unit 30 and the pixel 1.

  In this embodiment, the reference voltage supply unit 25 outputs the reference voltage Vr1 to the comparison circuit 301 in each column. The comparison circuit 301 outputs a comparison result signal CMP indicating the result of comparing the signal output from the amplification unit 20 and the reference voltage Vr1 to the memory unit 50.

  The memory unit 50 includes a flag memory 501, a first memory 502, and a second memory 503. A determination result signal Jdg is written in the flag memory 501, a photoelectric conversion signal is written in the first memory 502, and a noise signal is written in the second memory 503. The TG 70 outputs a signal F_En to the flag memory 501. The counter 40 outputs a count signal obtained by counting the clock signal CLK to the first memory 502 and the second memory 503. The TG 70 outputs M1_En and M2_En to the first memory 502 and the second memory 503, respectively.

The horizontal scanning circuit 60 causes the DSP 80 to sequentially output digital signals held in the flag memory 501, the first memory 502, and the second memory 503 of each column. The DSP 80 functions as a processing unit, processes signals output from the flag memory 501, the first memory 502, and the second memory 503 in each column and outputs them to the output circuit 90. The output circuit 90 outputs a signal to the outside of the imaging device based on the signal output from the TG 70. The DSP 80 may connect digital signals obtained with different gains according to the gain ratio. Any known method may be employed for the joining process.
In the imaging apparatus illustrated in FIG. 5, the AD conversion unit 110 includes a comparison unit 30 and a memory unit 50. In addition, each column of the AD conversion unit 110 is provided corresponding to each column of the pixels 1.

(Conventional basic operation flow)
First, prior to describing the second embodiment of the present invention, the conventional basic operation of the imaging apparatus assumed in the second embodiment will be described. The operation of the imaging apparatus shown in FIG. 5 will be described with reference to FIGS. 6A and 6B. The difference between FIG. 6A and FIG. 6B is FIG. 6A when the output level of the amplifier circuit 201 is lower than the threshold voltage Vj, and FIG. 6B when the output level is higher than the threshold voltage Vj. At each timing, “a” is appended to the end in FIG. 6A, and “b” is appended to the end in FIG. 6B. The process in FIG. 6A corresponds to the first AD conversion, and the process in FIG. 6B corresponds to the second AD conversion.

  6A and 6B, Out_Vline indicates the pixel signal potential, Amp_Gain indicates the gain of the amplifier circuit 201, and Out_Amp indicates the signal output by the amplifier unit 20. Vr1 is a reference voltage output by the reference voltage supply unit 25. The reference voltage Vr1 is a reference voltage whose potential changes with a certain amount of change per unit time. 6A and 6B, the gain of the amplifier circuit 201 is described as 4 or 1, but may be changed as appropriate.

At times t61a and t61b, a signal corresponding to a noise signal is output from the pixel 1.
At time t62a and t62b, the counter 40 starts counting and the reference voltage Vr1 is input.
At times t63a and t63b, the signal value of the comparison result signal CMP becomes High at the timing when the reference voltage Vr1 becomes larger than Out_Amp. The count signal at this time is written and held in the second memory 503.

Subsequently, a photoelectric conversion signal is output from the pixel 1 at times t64a and t64b.
At times t65a and t65b, the output level is determined for the threshold voltage Vj output from the TG 70. At this time, when the output signal Out_Amp of the amplification unit 20 is equal to or lower than the threshold voltage Vj, that is, when the output signal Out_Amp is equal to or lower than the threshold as shown in FIG. 6A, the determination circuit 202 outputs the L-level determination result signal Jdg and the flag memory 501 The L level is written, and the gain of the amplifier circuit 201 is not changed (maintains 4).
On the contrary, when the threshold voltage Vj is larger than the output signal Out_Amp of the amplifying unit 20, that is, in the case of FIG. 6B, the determination circuit 202 outputs the determination result signal Jdg of H level, and the H level is output to the flag memory 501. As a result, the gain of the amplifier circuit 201 is changed to 1.

The subsequent operation will be described with reference to FIG. 6A, assuming that the signal output from the comparison circuit 301 is at L level. At time t66a, the counter 40 starts counting and the reference voltage Vr1 is input.
At time t67a, the signal value of the comparison result signal CMP becomes High at the timing when the reference voltage Vr1 becomes higher than Out_Amp. The count signal at this time is written and held in the first memory 502.
Further, at time t68a, the input of the reference voltage Vr1 is completed.

  Thereafter, the downstream DSP 80 subtracts the signal written in the second memory 503 from the signal written in the first memory 502 by the digital value. By performing the above processing, it is possible to accurately convert the output signal Out_Amp of the amplification unit 20 that is an analog signal into a digital signal while removing the noise signal from the photoelectric conversion signal.

  Next, in the case of FIG. 6B (the operation when the determination result signal Jdg of the determination circuit 202 is at the H level will be described. At this time, the determination circuit 202 outputs the determination result signal Jdg of the H level at the time t65b, and the flag The H level is written in the memory 501 and the gain of the amplifier circuit 201 is changed to 1. With this gain change, Out_Amp once exceeds the threshold voltage Vj returns to a value equal to or lower than Vj.

At time t66b, the counter 40 starts counting and the reference voltage Vr1 is input.
At time t67b, the signal value of the comparison result signal CMP becomes High at the timing when the reference voltage Vr1 becomes higher than Out_Amp. The count signal at this time is written and held in the first memory 502.
Further, at time t68b, the input of the reference voltage Vr1 is completed.

In the case of FIG. 6B, the subsequent DSP 80 does not simply subtract the signal written in the second memory 503 from the signal written in the first memory 502 in the digital value. Instead, the signal of the first memory 502 is first multiplied by 4 which is the gain ratio of the amplifier circuit 201. Thereafter, a subtraction process is performed.
By performing such processing, for example, even when 10-bit AD conversion is performed, an AD conversion result corresponding to 12 bits (4 times 10 bits) can be obtained. As a result, it is possible to accurately convert the output signal Out_Amp of the amplification unit 20 that is an analog signal into a digital signal while removing a noise signal from the photoelectric conversion signal. That is, the dynamic range of AD conversion can be expanded by switching the processing of FIGS. 6A and 6B according to the signal level.

  The output image of the digital signal obtained by performing the operations of FIGS. 6A and 6B is the same as that of FIG. 3 of the first embodiment, and detailed description thereof is omitted.

(Operation flow of this embodiment)
Next, a second embodiment of the present invention will be described with reference to operation timing diagrams of FIGS. 7A to 7C. 7A to 7C are drive timing diagrams of the image pickup apparatus of the present embodiment. 7A to 7C, the same parts as those in FIGS. 6A to 6B are denoted by the same reference numerals, and detailed description thereof is omitted. At each timing, “a” to “c” are added to the end in FIGS. 7A to 7C. Any of these processes can be said to be a modification of the second AD conversion.

As described in the first embodiment, since the luminance is high when the determination result signal Jdg outputs an H level, AD conversion is performed in a portion having a luminance lower than the determination threshold voltage Vj / 4. There is no need to do. The difference from the first embodiment is that when the determination result signal Jdg is at the H level, the conversion gain of the amplifying unit 20 is switched to a low gain. The low gain is also called a first amplification gain, and the high gain is also called a second amplification gain. Therefore, it is preferable to use a reference voltage that starts with a value obtained by dividing the gain ratio (here, 4) based on the threshold voltage Vj. That is, the reference voltage is a value at which the potential changes in a range of a value equal to or greater than the value obtained by dividing the threshold by the gain ratio (greater than the reference value). In view of the above, in FIGS. 7A to 7C, the reference voltage Vr1 starts with the threshold voltage Vj / 4 as a reference.

(Operation example of this embodiment)
The drive timing chart of FIG. 7A will be described. FIG. 7A corresponds to FIG. 6B and assumes a case where the output signal Out_Amp of the amplification unit 20 is larger than the threshold voltage Vj. Since the operation up to time t75a is the same as that up to time t65b of FIG. 6B described above, description thereof is omitted.

  At time t75a, the output level is determined for the threshold voltage Vj output from the TG 70. At this time, since the output signal Out_Amp of the amplification unit 20 is larger than the threshold voltage Vj, the determination circuit 202 outputs the determination result signal Jdg of H level, and the H level is written in the flag memory 501. Further, the gain of the amplifier circuit 201 is changed to 1. At this time, the reference voltage Vr1-1 differs from FIG. 6B in that the reference voltage Vr1-1 is a signal that changes based on the threshold voltage Vj / 4.

At time t76a, the counter 40 starts counting and the reference voltage Vr1 changes.
At time t77a, the signal value of the comparison result signal CMP becomes High at the timing when the reference voltage Vr1 becomes higher than Out_Amp. The count signal at this time is written and held in the first memory 502.
Further, at time t78a, the input of the reference voltage Vr1 is completed. Here, the time t77a and the time t78a are earlier than the times t67a and t68a in FIG. 6B by the offset corresponding to the threshold voltage Vj / 4. Accordingly, the time during which the reference voltage must be input can be shortened, so that the supply of the reference voltage can be stopped quickly. As a result, power consumption can be reduced.

In the case of FIG. 7A, the DSP 80 at the subsequent stage does not simply subtract the signal written in the second memory 503 from the signal written in the first memory 502 in the digital value. Instead, a digital value corresponding to the offset of the threshold voltage Vj / 4 is first added to the signal in the first memory 502, and then multiplied by 4, which is the gain ratio between the reference voltages Vr1 and Vr1-1. Thereafter, a subtraction process is performed.
By performing such processing, as in the case of FIG. 6B, for example, even when 10-bit AD conversion is performed, an AD conversion result corresponding to 12 bits (4 times 10 bits) is obtained. It is done. As a result, it is possible to accurately convert the output signal Out_Amp of the amplification unit 20 that is an analog signal into a digital signal while removing a noise signal from the photoelectric conversion signal. As described above, power consumption can be reduced by using the imaging apparatus and driving method of this embodiment.

(Modification 2-1)
Next, another embodiment of the second embodiment of the present invention will be described using the operation timing chart of FIG. 7B. In FIG. 7B, the same reference numerals are given to the same parts as those in the second embodiment, and the detailed description is omitted. The operation up to time t77b is the same as that up to time t77a in FIG.

FIG. 7B differs from FIG. 7A in the timing at which the input of the reference voltage Vr1 ends. That is, time t78b is extended to the same timing as time t68b in FIG. 6B.
By extending the input of the reference voltage Vr1 to such timing and performing Vr1-2, AD conversion can be performed up to a larger output signal Out_Amp. Therefore, AD conversion can be performed up to a final digital output value that is larger than the 12-bit digital value by the number of bits of Vj / 4. That is, the dynamic range of signal output as the imaging apparatus 100 can be expanded by using the imaging apparatus and driving method of this modification.

  The time required for extending t78b can be secured by raising the start value at t76a to Vj / 4 and causing an offset. Therefore, even when a pixel signal is output from a pixel at a predetermined cycle, the dynamic range can be expanded without delaying the processing cycle. In addition, the extension period of the comparison time in the AD conversion is within the range of the processing time reduced by the present modification, that is, within the time range necessary for converting the pixel signal whose value is Vj / 4 or less. It is preferable.

(Modification 2-2)
Next, still another embodiment of the second embodiment of the present invention will be described with reference to the operation timing chart of FIG. 7C. In FIG. 7C, the same parts as those in the second embodiment and the first modification are denoted by the same reference numerals, and detailed description thereof is omitted. The operation up to time t76c is the same as that up to time t76b of FIG.

  7C differs from FIG. 7B in the amount of change per unit time of the reference voltage. The reference voltage for the photoelectric conversion signal of this modification is Vr1-3. The maximum voltage value of the reference voltage Vr1-3 at time t78c is equivalent to the maximum voltage value of the reference voltage Vr1 at time t68b in FIG. 6B. Therefore, the amount of change per unit time can be suppressed compared to FIG. 7B. As a result, the ratio of the amount of change between the reference voltages Vr1 and Vr1-3 is suppressed to be smaller than the gain ratio of the amplifier circuit 201. That is, the conversion gain ratio is reduced. For example, in FIG. 7C, the gain ratio is 3/4.

  When a signal is output as the imaging apparatus 100, a gain ratio (in this case, 3) is further multiplied to the signal AD-converted using the reference voltage Vr1-3. As a result, the digital value becomes a value from 0 to 4092, and takes a discrete value in increments of 3. That is, by using the imaging apparatus and driving method of the present embodiment, it is possible to reduce quantization errors related to AD conversion of signal output as the imaging apparatus 100.

  The gain ratio may take a different value other than 3. For example, the gain ratio may be 3.5, and may be used in combination with the reduction in power consumption or the expansion of the dynamic range described above. By using the imaging apparatus and driving method of this modification, the performance of the imaging apparatus is further improved.

  As described above, the dynamic range can be expanded while reducing the power consumption of the imaging device by using the imaging device and the driving method according to each embodiment of the present invention. Further, suitable AD conversion can be performed without increasing the scale of the circuit and memory.

<Another embodiment>
The present invention has been described with reference to specific examples. However, the present invention is not limited to the above embodiments, and various modifications and changes can be made without departing from the object and scope of the present invention. Combinations are possible. Hereinafter, various application examples and modification examples of the present invention will be described.

  For example, the present invention is not limited to the case where the imaging device 100 is formed on the same substrate. That is, the present invention may be applied to a configuration in which an imaging device is formed using a plurality of substrates. For example, the pixel unit 10 and the vertical scanning circuit 15 may be formed on different semiconductor substrates and connected by some means as appropriate.

  Further, the gain of the amplifier circuit, the threshold voltage, the conversion amount of the reference voltage, etc. are fixed for the sake of simplification, and the description is made using the same value, but the present invention is not limited to this, and can be changed as appropriate It is. Further, the value may be appropriately changed in the solid-state imaging device, or may be designated from a system provided separately from the solid-state imaging device.

Further, in the embodiments, the mode in which the reference voltage is offset has been described. However, for example, a signal corresponding to the offset of the reference voltage may be subtracted from the output of the amplifier circuit 201.
In this example, the offsets are described as the threshold voltage Vj. However, it is not always necessary to make them coincide with each other. For example, it is conceivable to perform processing while setting Vj to a predetermined value or a small ratio.

  In each of the embodiments described above, if Out_Amp is larger than Vj, a reference voltage having a large slope (a relatively large change amount per unit time) is applied as a reference signal, or a gain applied to Out_Amp is reduced. . In this way, the process of connecting signals having different gains may be applied to three or more signals. For example, two types of threshold values for comparing Out_Amp, Vj_1 and Vj_2 higher than Vj_1, may be set. In that case, a reference voltage with a small slope is used if Out_Amp is Vj_1 or less, a reference voltage with a medium slope is used if Out_Amp is greater than Vj_1 and less than Vj_2, and a reference voltage having a maximum slope is used if Out_Amp is greater than Vj_2. To do. The comparison start value is set to Vj_1 when the reference voltage having a medium slope is used, and is set to Vj_2 when the reference voltage has the maximum slope. At this time, as in FIGS. 4B and 4C, the dynamic range may be expanded and the quantization error may be reduced.

  Further, the gain may be changed as in the second embodiment according to the comparison result between Out_Amp and a plurality of threshold values. For example, if Out_Amp is Vj_1 or less, the gain is 8 times, if Out_Amp is greater than Vj_1 and less than Vj_2, the gain is 4 times, and if Out_Amp is greater than Vj_2, the gain is 1 time. Then, the comparison start value is raised according to Out_Amp. At this time, as in the case of FIGS. 7B and 7C, the dynamic range may be expanded and the quantization error may be reduced.

  Further, the selective use of the reference signal as shown in the first embodiment and the gain change as shown in the second embodiment may be used in combination. In this way, it is possible to further expand the dynamic range by using an appropriate combination of the reference signal and the gain according to the comparison result with the threshold value.

  1 and 5, the amplifier circuit is provided between the pixel and the comparison circuit, but the present invention is not limited to this. For example, the gain may be switched within the pixel by switching the floating diffusion capacitance.

In addition, the imaging apparatus may include a variation correction unit for correcting gain variation of the amplifier circuit, threshold signal variation, reference voltage variation, and the like that occur between columns. By having a means for correcting various variations, the image quality is further improved.
Further, the processing may be performed in units of blocks of a certain pixel circuit instead of each column. Although the circuit scale increases, processing may be performed on each pixel.
Furthermore, in this example, the ramp method AD conversion using the reference voltage Vr (ramp signal), the comparison circuit, and the counter is adopted as the AD conversion method. However, the present invention is not limited to this. For example, other AD conversion methods such as a successive approximation AD conversion method can be applied.

(Configuration example of pixel unit)
The configuration of the pixel 1 will be described with reference to FIG. FIG. 8A is a schematic diagram when one pixel 1 is viewed from the direction facing the main surface of the substrate of the imaging apparatus. One pixel includes one microlens 102. For example, the microlens can be formed by photolithography using a gray tone mask. A pixel portion is formed by arranging the pixels 1 in an array.
FIG. 8B is a partial cross-sectional view of the pixel portion. In one pixel 1, a color filter 104 and a microlens 102 are provided above a photodiode PD which is a photoelectric conversion unit provided on the substrate. For the color filter 104, for example, a pattern in which three colors of green, blue, and red are arranged in a Bayer array can be used. As the color material of the color filter, pigments, dyes, or hybrids thereof can be used.

(Application example to imaging system)
An example of application of the present invention to an imaging system will be described with reference to the schematic block diagram of FIG.
The solid-state imaging device described in the above embodiments (hereinafter collectively referred to as the imaging device 1000) can be applied to various imaging systems. Applicable imaging systems are not particularly limited, and examples include a digital still camera, a digital camcorder, a surveillance camera, a copying machine, a fax machine, a mobile phone, an in-vehicle camera, and an observation satellite. A camera module including an optical system such as a lens and an imaging device is also included in the imaging system. In the figure, as an example of these, a block diagram of a digital still camera is illustrated.

The imaging system 3000 includes an imaging optical system 3020, a CPU 3100, a lens control unit 3120, an imaging device control unit 3140, an image processing unit 3160, an aperture shutter control unit 3180, a display unit 3200, an operation switch 3220, and a recording medium 3240.
The imaging optical system 3020 is an optical system for forming an optical image of a subject, and includes a lens group, a diaphragm 3040, and the like. The diaphragm 3040 has a function of adjusting the amount of light at the time of shooting by adjusting the aperture diameter, and also has a function as a shutter for adjusting the exposure time when shooting a still image. The lens group and the diaphragm 3040 are held so as to be able to advance and retreat along the optical axis direction, and realize a zoom function and a focus adjustment function by their interlocking operations. The imaging optical system 3020 may be integrated with the imaging system or may be an imaging lens that can be attached to the imaging system.

  The imaging device 1000 is arranged in the image space of the imaging optical system 3020 so that the imaging surface is located. The imaging device 1000 corresponds to the imaging device described in the above embodiment, and includes a CMOS sensor (pixel region) and its peripheral circuit (peripheral circuit region). In the imaging apparatus 1000, pixels having a plurality of photoelectric conversion units are two-dimensionally arranged, and a color filter is arranged for these pixels, thereby forming a two-dimensional single-plate color sensor. The imaging apparatus 1000 photoelectrically converts the subject image formed by the imaging optical system 3020 and outputs it as an image signal or a focus detection signal.

  The lens control unit 3120 is for performing zooming operation and focus adjustment by controlling the forward / backward drive of the lens group of the imaging optical system 3020, and is configured by a circuit and a processing device configured to realize the function. Has been. The aperture shutter control unit 3180 is for adjusting the photographing light quantity by changing the aperture diameter of the aperture 3040 (with the aperture value being variable), and is configured by a circuit or a processing device configured to realize the function. Is done.

The CPU 3100 is a control device in the camera that controls various controls of the camera body, and includes a calculation unit, a ROM, a RAM, an A / D converter, a D / A converter, a communication interface circuit, and the like. The CPU 3100 controls the operation of each part in the camera according to a computer program stored in a ROM or the like, and includes detection of the focus state (focus detection) of the imaging optical system 3020.
A series of photographing operations such as F, imaging, image processing, and recording are executed. The CPU 3100 is also a signal processing unit.

  The imaging device control unit 3140 controls the operation of the imaging device 1000, A / D converts a signal output from the imaging device 1000, and transmits the signal to the CPU 3100. The imaging device control unit 3140 is configured to implement these functions. It is comprised by the circuit and control apparatus which were made. The A / D conversion function may be included in the imaging apparatus 1000. The image processing unit 3160 is for performing image processing such as γ conversion and color interpolation on an A / D converted signal to generate an image signal, and a circuit configured to realize the function And a control device. The display unit 3200 is a display device such as a liquid crystal display (LCD), and displays information related to the shooting mode of the camera, a preview image before shooting, a confirmation image after shooting, a focus state at the time of focus detection, and the like. The operation switch 3220 includes a power switch, a release (shooting trigger) switch, a zoom operation switch, a shooting mode selection switch, and the like. The recording medium 3240 is for recording a captured image or the like, and may be built in the imaging system, or may be a removable one such as a memory card.

  In this way, by configuring the imaging system 3000 to which the imaging apparatus 1000 according to each embodiment is applied, a high-performance imaging system that can perform high-precision focus adjustment and acquire an image with a deep depth of field. Can be realized.

(Application example to mobile objects)
The imaging system and moving body of the present invention will be described with reference to the block diagram of FIG. FIG. 10A shows an example of an imaging system 4000 related to an in-vehicle camera. The imaging system 4000 includes an imaging device 4100. The imaging device 4100 is any of the solid-state imaging devices described in the above embodiments. The imaging system 4000 includes an image processing unit 4120 that performs image processing on a plurality of image data acquired by the imaging device 4100, and parallax (phase difference of parallax images) from the plurality of image data acquired by the imaging device 4100. A parallax acquisition unit 4140 that performs calculation is included. The imaging system 4000 also calculates a distance acquisition unit 4160 that calculates the distance to the object based on the calculated parallax, and a collision determination unit 4180 that determines whether there is a collision possibility based on the calculated distance. And having. Here, the parallax acquisition unit 4140 and the distance acquisition unit 4160 are examples of a distance information acquisition unit that acquires distance information to the object. That is, the distance information is information related to the parallax, the defocus amount, the distance to the object, and the like. The collision determination unit 4180 may determine the possibility of collision using any of these distance information. The distance information acquisition unit may be realized by hardware designed exclusively, or may be realized by a software module. Further, it may be realized by an FPGA (Field Programmable Gate Array), an ASIC (Application Specific Integrated Circuit), or a combination of these.

  The imaging system 4000 is connected to a vehicle information acquisition device 4200 and can acquire vehicle information such as a vehicle speed, a yaw rate, and a steering angle. In addition, the imaging system 4000 is connected to a control ECU 4300 that is a control device that outputs a control signal for generating a braking force for the vehicle based on a determination result in the collision determination unit 4180. That is, the control ECU 4300 is an example of a moving body control unit that controls the moving body based on the distance information. The imaging system 4000 is also connected to an alarm device 4400 that issues an alarm to the driver based on the determination result of the collision determination unit 4180. For example, when the possibility of a collision is high as a determination result of the collision determination unit 4180, the control ECU 4300 performs vehicle control to avoid a collision and reduce damage by applying a brake, returning an accelerator, or suppressing an engine output. The alarm device 4400 warns the user by sounding an alarm such as a sound, displaying alarm information on a screen of a car navigation system, or applying vibration to the seat belt or steering.

  In the present embodiment, the imaging system 4000 images the periphery of the vehicle, for example, the front or rear. FIG. 10B shows an imaging system 4000 when imaging the front of the vehicle (imaging range 4500). The vehicle information acquisition device 4200 sends an instruction to operate the imaging system 4000 to execute imaging. By using the solid-state imaging device of each of the embodiments described above as the imaging device 4100, the imaging system 4000 further improves the accuracy of distance measurement.

  In the above description, an example of controlling so as not to collide with other vehicles has been described, but it can also be applied to control for automatically driving following other vehicles, control for automatically driving so as not to protrude from the lane, and the like. is there. Furthermore, the imaging system is not limited to a vehicle such as an automobile, and can be applied to a moving body (moving device) such as a ship, an aircraft, or an industrial robot. In addition, the present invention is not limited to moving objects, and can be applied to devices that widely use object recognition, such as intelligent road traffic systems (ITS).

  Further, the present invention can be used in various fields such as an image sensor applied to a medical image acquisition apparatus, an image sensor used in a precision component inspection apparatus, and an image sensor used in a surveillance camera.

  1: Pixel, 20: Amplifier, 100: Imaging device, 110: AD converter, 202: Determination circuit

Claims (12)

A pixel that outputs a pixel signal;
An amplifying unit for amplifying the pixel signal;
A determination unit that determines a magnitude relationship between the amplified output signal output from the amplification unit and a threshold;
An AD converter that converts the amplified output signal into a digital signal, and when the amplified output signal is determined to be equal to or less than the threshold value, performs first AD conversion, and the amplified output signal is greater than the threshold value; An AD converter that performs second AD conversion if determined,
With
The AD converter, when performing the second AD conversion, converts the amplified output signal into the digital signal in a range where the amplified output signal takes a value equal to or higher than a reference value based on the threshold value. An imaging device. The AD conversion unit converts the amplified output signal into the digital signal by using a comparison unit that compares the amplified output signal with a reference signal whose potential changes with time. Imaging device. The AD converter is
In the first AD conversion, the amplified output signal is compared with a first reference signal whose amount of change in potential per unit time is the first change amount,
In the second AD conversion, the amount of change in potential per unit time is greater than the first amount of change in a range where the threshold value is the reference value and the amplified output signal takes a value equal to or greater than the reference value. The imaging apparatus according to claim 2, wherein a second reference signal that is a large second change amount is compared with the amplified output signal. In the second AD conversion, the AD conversion unit extends a comparison time between the second reference signal and the amplified output signal within a range of an offset generated by setting the threshold as the reference value. The imaging apparatus according to claim 3. When the comparison time is extended in the second AD conversion, the AD conversion unit has a potential change amount per unit time larger than the first change amount with respect to the second reference signal. The imaging apparatus according to claim 4, wherein a third change amount smaller than the second change amount is applied. The amplifying unit can amplify the pixel signal with a first amplification gain or a second amplification gain higher than the first amplification gain,
The determination unit determines a magnitude relationship between the amplified output signal amplified by the second amplification gain and the threshold;
The AD converter is
In the first AD conversion, the amplified output signal amplified by the second amplification gain is compared with the reference signal,
In the second AD conversion, a value obtained by dividing the threshold value by a gain ratio between the first amplification gain and the second amplification gain is set as the reference value, and the range in which the amplified output signal takes a value equal to or larger than the reference value. The imaging apparatus according to claim 2, wherein the amplified output signal amplified with the first amplification gain is compared with the reference signal. In the second AD conversion, the AD conversion unit compares the reference signal and the amplified output signal within a range of an offset generated by setting a value obtained by dividing the threshold by the gain ratio as the reference value. The imaging apparatus according to claim 6, wherein the time is extended. 8. The AD converter according to claim 7, wherein when the comparison time is extended in the second AD conversion, the change amount of the potential per unit time is reduced with respect to the reference signal. Imaging device. In the first AD conversion, a potential indicating a first value less than the reference value is input to the comparison unit as a part of a changing potential of the reference signal compared with the amplified output signal.
In the second AD conversion, the comparison unit does not compare the amplified output signal with the potential indicating the first value as the changing potential of the reference signal, and the comparison unit compares the amplified output signal with the amplified output signal. The imaging apparatus according to claim 2, wherein a potential indicating a second value equal to or greater than the reference value is input as a part of the potential that changes in the reference signal. 10. The processing apparatus according to claim 1, further comprising a processing unit that performs a splicing process on the digital signal obtained by each of the first AD conversion and the second AD conversion and outputs the result. The imaging apparatus of Claim 1. An imaging device according to any one of claims 1 to 10,
A signal processing unit for processing a signal output from the imaging device;
An imaging system comprising: An imaging device according to any one of claims 1 to 10,
And a moving body control unit that controls the moving body based on signals output from the pixels of the imaging device.

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