JP2019039941A - Optical computing unit - Google Patents

Abstract

To provide an optical calculation device capable of performing optical arithmetic at a higher speed.SOLUTION: The optical calculation device has S (S is a natural number) arithmetic elements 102 which are configured to output a single optical signal to an input signal and are connected to each other in series. Multiple operation units 101 are cascade-connected to each other in which a single optical signal is calculated and output using S input signals. A signal which is output from S operation units 101 in a front stage is input to a single operation unit 101 in a subsequent stage.SELECTED DRAWING: Figure 1

Description

  The present invention relates to an optical computing unit including a photoelectric fusion type arithmetic circuit.

  The current electronic arithmetic circuit has been devised to reduce the chip size and element size to the limit in order to improve the processing speed of the arithmetic operation. This is because the resistance (R) and capacitance (C) in the circuit greatly limit the propagation of signals, and the only way to increase the calculation speed is to reduce the chip size and element size. For this reason, devices such as multi-core and many-core have been devised by packing elements in a small area logic block or core, but the wiring to connect them creates a new "delay", and there is a limit to speeding up operations I am seeing.

  On the other hand, an optical wiring or an optical pass gate used in optical communication or the like can propagate an optical signal independent of C and R in the wiring path. In addition, with the progress of nanophotonics, the energy consumption of the optical gate has been dramatically improved, and the energy cost [J / bit] is about the same level between the CMOS gate and the optical pass gate. For this reason, various studies have been made to opticalize communication within and between chips.

  Here, a connection form in which a signal is input from the electrical control port side of the optical gate is defined as a cascade connection, and a form in which the optical propagation paths of the switches are continuously connected is defined as a serial connection. For example, when a photoelectric fusion type circuit in which serial connection and cascade connection are mixed is assumed, the cascade connection part becomes a boundary between light and electricity. At this boundary, the optical signal propagating in the circuit is once converted into electricity (OE conversion). Since this conversion is rate-controlled by an electric circuit, a circuit frequently used for OE conversion has a small merit of using light. For this reason, the boundary between light and electricity, that is, the location and number of cascade connections are important points in the circuit configuration.

  Here, an N-input AND circuit is taken as an example. In the case of a CMOS circuit, an S input element is formed by serially connected pass block gates, and this is cascade-connected in a tree structure to form an N input function. In this case, the delay time of the N input function is as follows.

  In this case, since the electric signal propagation delay of the serial connection portion is affected by the resistance and capacitance corresponding to the number of gates, there is a problem that it increases in proportion to the square of the number S of serial connection. If the operating voltage is increased to solve this problem, the power consumption also increases, so that the S of the CMOS circuit remains at most 2. Further, in order to use a small S, it is necessary to increase the number of cascade stages M, resulting in a problem of increasing the delay of the N input function.

  In the case of an optical circuit, it is known that an operation with a small delay is possible only by serial connection (Non-Patent Documents 1 and 2). This is because the optical signal propagation delay of the serial portion depends only on the gate length, that is, the delay has a characteristic proportional to S, and the above-described problem of the electrical signal propagation delay can be alleviated. It is.

J. Hardy et al., "Optics inspired logic architecture", Optics Express, vol. 15, no. 1, pp. 150-165, 2007. Tetsuya Asai et al. “Photonic crystal integrated device based on binary decision graph”, Proceedings of the 2000 IEICE General Conference, 386-387, 2000. Q. Xu et al., "Reconfigurable optical directed-logic circuits using microresonator-based optical switches", Optics Express, vol. 19, no. 6, pp. 5244-5259, 2011. Satoshi Ishihara et al., “Proposal of Parallel Adder Circuit Based on Optical Passgate Logic and Operational Verification by Photoelectric Hybrid Circuit Simulator”, IEICE Technical Report, vol. 116, no. 94, pp. 109-114, 2016.

  However, since the light intensity loss is proportional to S, it is possible to handle S larger than electricity. However, when handling too large S, it is necessary to take measures against signal degradation.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to enable optical calculation at higher speed.

  The optical computing unit according to the present invention is configured by serially connecting S computing elements (S is a natural number) that outputs one optical signal with respect to an input signal, and one optical signal is generated by the S input signals. The arithmetic units are connected in cascade, and the signals output from the S arithmetic units in the previous stage are input to one arithmetic unit in the subsequent stage.

  In the optical computing unit, the input signal is an electrical signal, and each of the plurality of computing units includes a conversion element that photoelectrically converts the optical signal output from the serially connected final stage computing element.

  In the optical arithmetic unit, the input signal is an optical signal, and each of the plurality of arithmetic units outputs a value of 1 when an optical signal is output from the S arithmetic elements, and outputs light from the S arithmetic elements. A conversion element that outputs a value 0 is provided except when a signal is output.

In the optical computing unit, the number M of cascade-connected stages and the number S of computing elements are calculated from the number N of input signals, the computing time τ _gate in the computing element, and the processing time τ _OEO in the converting element by the equation (A). It is determined.

  In the optical computing unit, the computing elements in the first stage are configured by a Mach-Zehnder interferometer, and the computing elements in the computing elements in the second and subsequent stages are converted into one input signal that is an electrical signal. Alternatively, one optical signal may be output.

  As described above, according to the present invention, it is possible to obtain an excellent effect that optical calculation can be performed at higher speed.

FIG. 1 is a configuration diagram showing the configuration of the optical computing unit according to Embodiment 1 of the present invention. FIG. 2 is a configuration diagram showing the configuration of the arithmetic unit 101 of the optical arithmetic unit according to the first embodiment of the present invention. FIG. 3 is an explanatory diagram for explaining an operation delay of an arithmetic unit (arithmetic circuit) that performs an AND operation. FIG. 4 is a configuration diagram showing a partial configuration of the optical computing unit according to the first embodiment of the present invention. FIG. 5 is a configuration diagram showing the configuration of the arithmetic unit 101 of the optical arithmetic unit according to the second embodiment of the present invention. FIG. 6 is a configuration diagram showing the configuration of the optical computing unit in the third embodiment of the present invention. FIG. 7 is a configuration diagram showing the configuration of the optical computing unit in the fourth embodiment of the present invention. FIG. 8 is a block diagram showing the configuration of a 2-input 2-output XOR / XNOR arithmetic element and an XNOR-AND / XOR-OR arithmetic unit by a combination thereof in the present invention.

  Embodiments of the present invention will be described below.

[Embodiment 1]
First, an optical computing unit according to Embodiment 1 of the present invention will be described with reference to FIG. This optical arithmetic unit includes a plurality of arithmetic units 101 connected in cascade. The arithmetic unit 101 is configured by serially connecting S (S is a natural number) arithmetic elements 102 that output one optical signal with respect to an input signal. The computing unit 101 computes and outputs one optical signal based on S input signals. In addition, signals output from the S calculation units 101 in the previous stage are input to one calculation unit 101 in the subsequent stage. In addition, in FIG. 1, the case where S = 2 is illustrated. Further, FIG. 1 illustrates a case where the cascade connection stage number M is three.

Here, in Embodiment 1, the input signal is an electrical signal, and the arithmetic unit 101 includes a conversion element 103 that photoelectrically converts the optical signal output from the final-stage arithmetic element 102 connected in series. For example, as illustrated in FIG. 2, the calculation unit 101 may be configured by a light source 111, a 1 × 1 optical pass gate 102 a, and a conversion element 103. The two 1 × 1 optical pass gates 102a are serially connected. In this configuration, the electrical control input to the preceding 1 × 1 optical pass gate 102a is x _i, and the electrical control input to the subsequent 1 × 1 optical pass gate 102a is y _i . If the signal is set to be transmitted only when the electrical control input is 1, a combination of electrical signals in which both the preceding 1 × 1 optical pass gate 102a and the succeeding 1 × 1 optical pass gate 102a are transmitted, that is, x Only when _i y _j = 1, the AND operation outputs light.

  In the present invention, as described above, the optical computation is speeded up by the cascade connection of the optical serial connection circuits. In the first embodiment, the conversion element 103 is used to input the optical output from the serial connection circuit by the 1 × 1 optical pass gate 102a to the electric control side of the 1 × 1 optical pass gate 102a. The calculation delay time in this configuration is represented by the following equation.

Here, in order to simplify the calculation, the number of all serial stages is uniform, and the propagation time of light propagating through the arithmetic element 102 is uniform at τ _gate in all the 1 × 1 optical pass _gates 102a (the arithmetic element 102). The OE conversion time in all conversion elements 103 is assumed to be uniform with τ _OEO , and the operation delay characteristic is handled. The calculation delay under this condition is expressed by the following equation (3).

In the electric circuit, since the conversion element 103 is not required in the cascade connection portion, τ _OEO = 0, and when the number of serial stages is large, the response becomes slow, so the value of S is up to about 2. On the other hand, the optical computing unit according to the first embodiment needs to pass the output of the serially connected computing element 102 through the conversion element 103 and can handle S larger than 2. In these points, the configurations of the electric circuit and the optical computing unit in the first embodiment are greatly different.

  As shown in FIG. 3, the delay amount of the M-stage cascade and the M + 1-stage cascade is reversed by a certain number of inputs N, and the M + 1-stage cascade delay is smaller than the M-stage cascade in the case of more inputs. Become.

In other words, if N = N ₀ satisfying F (N ₀ , M) = F (N ₀ , M + 1) is defined as the break-even point, the number of cascade stages is M + 1 for the number of inputs exceeding this and M for the number of inputs not exceeding this. By adopting, the delay can be kept small. Further, when N = N ₀ , by adopting the number of cascade stages of M + 1 stages, a smaller S can be adopted and the problem of optical serial circuit loss can be solved.

Next, attention is paid to delay characteristics when N is fixed to a specific value and S, M = log _S (N) is used as a parameter. In the optical computing unit in the first embodiment, M and S need to be handled as natural numbers, but here, the range is expanded to a real number range, and the computation delay is expressed by equation (4).

The delays of the electric circuit and the optical circuit are expressed by equations (6) and (7), respectively. Here, in the electric circuit, τ _OEO = 0 is set because no OE conversion element is required in the cascade connection portion, and τ _gate = τ _CMOS is set so as to distinguish it from the optical computing unit in the embodiment.

  Now, the maximum value of the right side of equation (8) is expressed by the following equation, and under the condition that it is smaller than 1, the delay of the optical computing unit in the first embodiment is smaller than that of the electric circuit.

That is, using the light pass gate having a smaller propagation delay than e ^1-p times the CMOS switching time (arithmetic element 102), constitute a serial connection of S ₀ = e ^p stage, the light output from the serial connection circuit By passing the signal through a photoelectric conversion element (conversion element 103) whose response speed is smaller than e (p-1) times the switching time of CMOS and cascading M ₀ = log _S0 (N) stages, an electric circuit is obtained. It is possible to configure an optical circuit with a smaller delay.

In other words, the number M of cascade-connected stages and the number S of the arithmetic elements 102 are calculated from the number N of input signals, the arithmetic time τ _gate in the arithmetic element 102, and the processing time τ _OEO in the conversion element 103 by the equation (4). Can be determined.

  Here, the response speed of the conversion element 103 is about the same as that of an electric circuit, but the propagation delay of the arithmetic element 102 must be smaller than the response speed of the CMOS. Regarding this, in consideration of the fact that the propagation speed of light is about 100 μm / ps in a semiconductor, this condition is achieved by realizing an optical pass gate (arithmetic element 102) having an element length of 1000 μm or less with nanophotonics. .

Now, S ₀ and M ₀ described above are real values, but in an actual circuit, these must be treated as natural numbers. For this reason, the following natural numbers S and M are adopted as these values.

First, the cascade stage number M is a candidate for adopting a value obtained by rounding up or rounding down the decimal point of the real value M ₀ = log _S0 (N). It is clear from equation (3) that the lowest value appears in the operation delay between two natural numbers sandwiching the real value M ₀ . The number S of serial connection stages is obtained by substituting M candidates to be adopted into the equation (3). By substituting two S and M candidates into equation (3) and adopting S and M with smaller F (N, M), the minimum computation delay can be obtained.

When the values of F (N, M) are the same, a value obtained by rounding up the decimal point of M ₀ may be adopted as M for the reason described above. The setting method of M is the same as the method when considering the breakeven point N ₀ .

As for the characteristic that the break-even point N ₀ exists and the delay takes the minimum value at S ₀ , the serial connection portion in which the operation delay increases in proportion to S and the cascade connection portion in which the delay decreases with the increase of S are mixed. Because of this, the same tendency appears even in the case where S, τ _gate , and τ _OEO are not uniform in the circuit.

In such a case, when the natural number S that minimizes the expression (2) is S (N, M) and the value of the natural number M is gradually increased from 1, F (N, M) <F (N , M + 1), and M and S (N, M) are adopted. However, if the value of S is larger than the maximum value S _max (natural number) allowed, the value of M is increased until S ≦ S _max is satisfied. Thereby, the minimum delay can be obtained.

  As described above, according to the first embodiment, the arithmetic unit 101 is connected by a multi-stage serial connection circuit that is impossible in an electric circuit by the arithmetic element 102 (for example, an optical pass gate) having a propagation delay smaller than the switching time of the CMOS. An optical circuit having a smaller delay than the electric circuit is configured by photoelectrically converting the optical signal output from the serial connection circuit of the arithmetic element 102 by the conversion element 103 and connecting (input) to the arithmetic element 102 in the subsequent stage. can do.

FIG. 3 shows a comparison of arithmetic delays between the CMOS circuit and the optical arithmetic unit according to the first embodiment in the above-described multi-input AND operation. The delay of the optical circuit is calculated using the equation (3) with τ _gate = 0.2 ps and τ _OEO = 25 ps, and is shown by a curve of M = 1 to 3. In this case, S ₀ = 44.7, and the characteristic curve expressed by the equation (4) is a straight line that is in contact with the curve expressed by the equation (3) at N = S ₀ ^M. Further, the delay of the CMOS circuit is calculated using the equation (4) with τ _gate = 10 ps, τ _OEO = 0 ps, and S = 2.

This result shows that it is possible to realize an operation with a much lower delay than that of a CMOS circuit only by adopting cascade connection of at most one or two stages. For example, when N = 1000, M ₀ = 1.82 from the expressions (3) and (5), and F (1000,1) _{S = 1000} > F (1000,2) _{S = 32} from the expression (3). Therefore, M = 2 and S = 32 are adopted. In this case, as shown in FIG. 4, the circuit is a square circuit composed of 32 × 32 1 × 1 optical pass gates 102a, and 1 × 1 optical pass gates 102a (calculations) serially connected after light is input. All times passing through the element 102) are equal. However, since 32 ² = 1024> 1000, there is a useless gate.

[Embodiment 2]
Next, an optical computing unit according to Embodiment 2 of the present invention will be described with reference to FIG. Note that the second embodiment also includes a plurality of arithmetic units 101 connected in cascade as described with reference to FIG. As shown in FIG. 5, the calculation unit 101 is configured by serially connecting S (S is a natural number) calculation elements 102 b that output one optical signal with respect to an input optical signal.

In the second embodiment, for example, the first arithmetic element 102b to be serially connected optically couples the optical signal λ ₁ to the waveguide connected to the conversion element 103b. The next arithmetic element 102b connected in series multiplexes the light signal λ ₂ with the light output from the first arithmetic element 102b. The arithmetic element 102b is, for example, a multiplexer configured from a ring resonator.

  In the second embodiment, the arithmetic unit 101 outputs an optical signal having a value of 1 when an optical signal is output from the S arithmetic elements 102b, and an optical signal is output from the S arithmetic elements 102b. A conversion element 103b that outputs an optical signal having a value of 0 is provided. In this configuration, a multi-input OR operation circuit is obtained.

  In the second embodiment, when the power coupling efficiency of multiplexing in each arithmetic element 102b is α and the number of inputs is N and M = 1, that is, S = N, (only one input is multiplexed) / ( The intensity ratio of the case where all inputs are not combined is {α + (1−α) × (N−1)} / {(1−α) × N}. This value is the contrast ratio when the difference between “0” and “1” of the OR operation output is the smallest.

  The contrast ratio when α = 0.9 is 0.33 dB and 2.6 dB when N = 100 and 10, respectively, and the larger N is, the more the contrast deteriorates.

Here, S _max = 10 is the maximum value of the number of serial connection stages at which contrast can be detected on the optical receiving side of the conversion element 103b, and N = 100 when the circuit characteristics of the optical computing unit are the same as those in the first embodiment. Consider the OR operation.

In this case, S ₀ = 44.7 and M ₀ = 1.2 from the equations (3) and (5), and F ₌ (100,1) _{S = 100} <F (100,2) 1 However, since S = 100 and S _max = 10 is exceeded, M = 2 and S = 10 are adopted. As a result, a minimum delay can be realized while ensuring suppression of a decrease in contrast.

[Embodiment 3]
Next, an optical computing unit according to Embodiment 3 of the present invention will be described with reference to FIG. In the third embodiment, a plurality of arithmetic units 101a in the k = 1 stage cascaded in multiple stages are configured by an arithmetic element 102c and a conversion element 103c that are configured by a 1-input 1-output Mach-Zehnder interferometer. . An input signal X and an input signal Y are input to the electric control units provided in the two arms of the Mach-Zehnder interferometer. Note that the arithmetic unit 101 after the k = 2nd stage includes the arithmetic element 102 and the conversion element 103 that are the same as those in the first embodiment. In the third embodiment, the composite function XNOR-AND is calculated.

Here, the conversion element 103c is the same as the conversion element 103 of the first embodiment. The electrical signals output from the conversion element 103c are the input signals x ( _{N 1} binary signals of x _{1 to} x _N ) and input signals y (y ₁ to y ₁ ) of the N arithmetic elements 102c connected in series. y _N N-digit binary signal) is the result of ANDing each digit, and is 1 when all digits match, and 0 otherwise. In other words, the composite function XNOR-AND can be calculated even in the first stage only (M = 1).

However, in the case of k = 1 stage only (M = 1), the match output for each digit is output as AND _M (A ₁ ,..., A _N ), A _j = XNOR (X _j , Y _j ), A _j = XNOR (X _j , Y _j ) is an electronic signal (X _j , Y _j ) at the two input terminals of the arithmetic element 102c, which is a Mach-Zehnder interferometer type intensity modulator. AND _M (A ₁ ,..., A _N ) is executed by serially connecting the arithmetic elements 102c that execute the above-described arithmetic operations. Since AND _M is generally larger in structure than the AND of the arithmetic element 102a in the first embodiment, the delay in the AND operation becomes large.

In order to solve this problem, here, it is considered to adopt a cascade connection in the AND operation part. That is, in Equation (2), k = 1 stage is configured by AND _M having a large τ _gate , and k ≧ 2 stages is configured by AND by the calculation unit 101 in Embodiment 1 having a small τ _gate . In this case, Equation (3) is rewritten as Equation (12). Here, S ₁ and τ _gate1 are k = the number of serial connection stages of the first stage and the propagation delay of one arithmetic element 102c, and S ₂ and τ _gate2 are the number of serial connection stages after the second stage of k = 2 and the propagation of one arithmetic element 102. Delay, L is the total number of inputs to the k = 2 stage, and M is the number of cascade stages after the k = 2 stage. However, the equation (12) holds only if M is a natural number, in the case of M = 0 is set to F (N, M) = βS1τ gate2.

For example, when N = 10000, α = 125, and β = 100, M = 3, S ₁ = 1, and S ₂ = 22 are adopted as follows.

When M = 0, F (10000,0) = (10 ⁶ ) τ _gate2 ,
When M = 1, S ₁ = 10 ¹ , S ₂ = 10 ³ , F (10000,1) = (2125) τ _gate2 ,
When M = 2, S ₁ = 10 ⁰ , S ₂ = 10 ² , F (10000,2) = (550) τ _gate2 ,
When M = 3, S ₁ = 10 ⁰ , S ₂ = 22, F (10000,3) = (541) τ _gate2 ,
When M = 4, S ₁ = 10 ⁰ , S ₂ = 10 ¹ , F (10000,4) = (640) τ _gate2 ,

For example, when N = 100, α = 125, and β = 100, M = 1, S ₁ = 1, and S ₂ = 100 are adopted as follows.

When M = 0, F (10000,0) = (10 ⁴ ) τ _gate2 ,
When M = 1, S ₁ = 10 ⁰ , S ₂ = 10 ² , F (10000,1) = (325) τ _gate2 ,
When M = 2, S ₁ = 10 ⁰ , S ₂ = 10 ¹ , F (10000,2) = (370) τ _gate2 .

[Embodiment 4]
Next, an optical computing unit according to Embodiment 4 of the present invention will be described with reference to FIG. In the fourth embodiment, a plurality of arithmetic units 101a in the k = 1 stage cascaded in multiple stages are configured from arithmetic elements 102d in which Mach-Zehnder interferometers with two inputs and two outputs are serially connected in two stages. In this configuration, an electric control input to the preceding Mach-Zehnder interferometer of the arithmetic element 102d is X _i, and an electric control input to the latter-stage Mach-Zehnder interferometer is Y _i . Note that the arithmetic unit 101 after the k = 2nd stage includes the arithmetic element 102b and the conversion element 103b similar to those of the second embodiment described above. In the fourth embodiment, the composite function XOR-OR is calculated.

In the k = 1 stage of this configuration, an element corresponding to the conversion element 103c in Embodiment 3 is not required, and an optical signal output from the calculation unit 101a is obtained from N serially connected calculation elements 102d. For each input signal x ( _{N 1-} digit binary signal of x _{1 to} x _N ) and input signal y ( _{N 1-} digit binary signal of y _{1 to} y _N ), the XOR operation result in each digit is represented by all the digits. As a result of ORing, the result is 0 when all digits are matched, and 1 otherwise. In other words, the composite function XOR-OR can be calculated even when only k = 1 stage (M = 1).

However, the output of only k = 1 stage (M = 1) is expressed as OR _M (A ₁ ,..., A _N ), A _j = XOR (X _j , Y _j ). An electronic signal (X _j , Y _j ) is input to the two input terminals of an arithmetic element 102d in which two Mach-Zehnder interferometers are serially connected, and a signal from a cross-side port is output from the light source connected to 102d. Thus, A _j = XOR (X _j , Y _j ) is executed, and OR _M (A ₁ ,..., A is established by connecting the output signal from the preceding stage 102d to an input port different from the port connected to the light source. _N ). Since this OR _M is realized by using a Mach-Zehnder interferometer, in general, the OR _M has a larger structure than the OR by the arithmetic element 102b in the second embodiment, and the delay in the OR operation becomes large.

In order to solve this problem, it is considered here that a cascade connection is adopted in the OR operation part. That is, in Equation (2), k = 1 stage is configured with OR _M having a large τ _gate , and k ≧ 2 stages is configured with OR by the arithmetic unit 101 in Embodiment 2 having a small τ _gate . In this case, Equation (3) is rewritten as Equation (14). Here, S ₁ and τ _gate1 are k = 1 number of serial connection stages and one arithmetic element 102d propagation delay, and S ₂ and τ _gate2 are k = 2 and subsequent serial connection stages and propagation of one arithmetic element 102. Delay, L is the total number of inputs to the k = 2 stage, and M is the number of cascade stages after the k = 2 stage. However, the equation (14) holds only when M is a natural number, and when M = 0, F (N, M) = βS ₁ τ _{gate 2} .

  Other configurations are the same as those of the third embodiment described above, and a description thereof will be omitted.

  The result of inverting 0 and 1 of the output of XNOR-AND of the third embodiment is the same as the output result of XOR-OR of the fourth embodiment. In some cases, the multi-input OR in the second embodiment can implement a circuit faster than the multi-input AND in the first embodiment. For example, in Embodiment 2, the arithmetic element 102b connected in serial is connected to the conversion element 103b, but the same effect as in Embodiment 2 can be obtained by connecting the arithmetic element 102b connected in parallel to the conversion element 103b. .

  In this case, since the output from the plurality of conversion elements 102b is collectively connected to the conversion element 103b, the configuration of the calculation unit 101 is large. However, since the calculation of the operator 102b is processed in parallel, it is serially connected. There is a possibility that the delay becomes smaller than that. In other words, the calculation using the XOR-OR according to the fourth embodiment instead of the XNOR-AND according to the third embodiment may be performed at high speed. Note that multi-bit pattern matching can be implemented using either XNOR-AND or XOR-OR, so that a circuit configuration that meets the needs can be selected.

Now, the calculation unit at the k = 1 stage in this embodiment is obtained by serially connecting (a) of FIG. 8 to the configuration of (c) of FIG. Here in FIG. 8 (a) shows the configuration of the arithmetic elements of the two inputs and two outputs, an electrical control signal X _i, to Y _i, the output port is switched when the X _i and Y _i does not match the time matching Any arithmetic element may be used. In the configuration of FIG. 8C, the light source is connected to one of the input ports of the first stage arithmetic element, and the output port when X _i and Y _i do not match (XOR) is the input port of the next stage arithmetic element. The light source may be connected to the input port opposite to the port used for this connection [Description 1]. As a result, the XOR-OR operation can be realized only with k = 1 stage (M = 1). Further, it is obvious that the XOR-OR operation with a smaller delay can be obtained by employing the configuration of the fourth embodiment after the k = 2 stage.

Further, when the calculation unit at the k = 1 stage in the present embodiment is changed to a configuration in which FIG. 8A is serially connected to the configuration of FIG. 8D, XNOR-AND calculation is possible. Here, in FIG. 8D, the light source is connected to one of the input ports of the first stage arithmetic element, and the output port when X _i and Y _i match (XNOR) is connected to the input port of the next stage arithmetic element. [Explanation 2] As a result, the XNOR-AND operation can be realized only at k = 1 stage (M = 1). In addition, it is obvious that an XNOR-AND operation with a smaller delay can be obtained by adopting the configuration of the third embodiment after k = 2.

Here, FIG. 8A is composed of a combination of two 2-input 2-output Mach-Zehnder interferometers, and electric control signals X _i , Y _i are applied to one arm of each Mach-Zehnder interferometer. give. The arm on the side to which the electric control signal is given is set to shift the phase of the light propagating there by π, and in the case of this configuration in which one of the two arms is electrically controlled, the two-input two-output Mach The zender interferometer outputs an optical signal from the bar side / cross side output port with respect to the input port to which the light source is connected when the electrical control input is present or absent. 8A outputs XOR (X _i , Y _i ) from the output port on the cross side of the light source, and outputs XNOR (X _i , Y _i ) from the opposite bar port.

Therefore, the function of the arithmetic element in FIG. 8A is that the electric control signals X _i and Y _i are respectively applied to both arms of one 2-input 2-output Mach-Zehnder interferometer 102e shown in FIG. 8B. This can also be realized by giving In other words, the phase difference is π when an electrical control signal is applied to one arm, and the phase difference is zero when an electrical signal is applied to both arms or not applied to both arms. To do. At this time, the positional relationship between XNOR and XOR at the output port is opposite to that of FIG. 8A, but in accordance with [Description 1] and [Description 2] described above, the XOR-OR output port is set as follows for the XOR-OR operation. It is only necessary to connect the output port of XNOR to the next stage for XNOR-AND operation. The length (element length) of the element shown in FIG. 8B is half of the element length shown in FIG. 8A. Therefore, the configuration shown in FIG. By substituting for the configuration shown in (1), a smaller calculation delay can be obtained.

  Further, the 2-input 2-output Mach-Zehnder interferometer used in FIG. 8A can be replaced by a 2-input 2-output directional coupler. That is, the coupling state of the two-input / two-output directional coupler is controlled by an electric control signal, and the optical signal is output from the output port on the cross side with respect to the port to which the optical signal is input, and the optical signal. The state in which the optical signal is output from the output port on the bar side is switched with respect to the port to which is input. Because the directional coupler can be smaller in size than the Mach-Zehnder interferometer, this alternative can provide a smaller computational delay.

  Furthermore, the 2-input 2-output Mach-Zehnder interferometer used in FIG. 8A can be replaced by a 2-input 2-output XOR or XNOR arithmetic element (non-patent document 3) using a ring resonator or the like. . In other words, in a 2-input 2-output computing element in which two waveguides are coupled via a ring resonator, the resonance state of the resonator is controlled by an electric control signal, and the optical signal is input to the port. The resonance state in which the optical signal is output from the output port on the cross side and the non-resonance state in which the optical signal is output from the output port on the bar side are switched with respect to the port to which the optical signal is input. Since the ring resonator can be smaller in size than the Mach-Zehnder interferometer, this alternative provides a smaller computational delay.

  As described above, a plurality of S (S is a natural number) arithmetic elements that output one optical signal with respect to an input signal are serially connected to calculate and output one optical signal based on the S input signals. Since the calculation units are connected in cascade, optical calculation can be performed at higher speed.

  The present invention is not limited to the embodiment described above, and many modifications and combinations can be implemented by those having ordinary knowledge in the art within the technical idea of the present invention. It is obvious.

  101: arithmetic unit, 102: arithmetic element, 103: conversion element.

Claims (5)

A plurality of arithmetic units that are configured by serially connecting S arithmetic elements (S is a natural number) that outputs one optical signal with respect to an input signal, and that outputs one optical signal based on the S input signals. With
The plurality of arithmetic units are cascade-connected,
An optical computing unit, wherein the signal output from the S computing units at the preceding stage is inputted to one computing unit at the succeeding stage. The optical computing unit according to claim 1,
The input signal is an electrical signal;
Each of the plurality of calculation units includes a conversion element that photoelectrically converts an optical signal output from the final-stage calculation element that is serially connected. The optical computing unit according to claim 1,
The input signal is an optical signal;
Each of the plurality of arithmetic units outputs a value of 1 when an optical signal is output from the S arithmetic elements, and outputs a value of 0 except when an optical signal is output from the S arithmetic elements. An optical computing unit comprising: a conversion element that performs the operation. The optical computing unit according to claim 2 or 3,
The number M of cascaded stages and the number S of arithmetic elements are determined by the equation (A) from the number N of the input signals, the arithmetic time τ _gate in the arithmetic elements, and the processing time τ _OEO in the conversion element. An optical computing unit.

The optical computing unit according to claim 1,
In the plurality of calculation units in the first stage, the calculation element includes a Mach-Zehnder interferometer,
The arithmetic unit in the plurality of arithmetic units in the second and subsequent stages outputs one optical signal for one input signal that is an electric sign.

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