JP2019036586A - Semiconductor device, power supply device, amplifier, and semiconductor device manufacturing method - Google Patents

Abstract

To provide a semiconductor device having high breakdown voltage and high reliability even when carrying out heat treatment for ohmic-contacting with an electrode.SOLUTION: The semiconductor device comprises: a first semiconductor layer formed of a compound semiconductor on a substrate; a second semiconductor layer formed of the compound semiconductor on the first semiconductor layer; a source electrode and a drain electrode formed on the second semiconductor layer; a Ta film covering the source electrode and the drain electrode; and a gate electrode formed on the second semiconductor layer, therein the Ta film is formed of α-Ta, or the Ta film contains more α-Ta than β-Ta.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a semiconductor device, a power supply device, an amplifier, and a method for manufacturing the semiconductor device.

  A nitride semiconductor such as GaN, AlN, InN, or a mixed crystal material thereof has a wide band gap, and is used as a high-power electronic device, a short wavelength light-emitting device, or the like. Among these, as a high-power device, a technique related to a field-effect transistor (FET), in particular, a high electron mobility transistor (HEMT) has been developed (for example, Patent Document 1). ). HEMTs using such nitride semiconductors are used in high power / high efficiency amplifiers, high power switching devices, and the like.

  As a field effect transistor using a nitride semiconductor, there is a HEMT using GaN as an electron transit layer and AlGaN as an electron supply layer, and 2DEG (Two- Dimensional Electron Gas) is generated. Thus, the HEMT using GaN for the electron transit layer may be called GaN-HEMT.

JP 2002-359256 A JP 2014-232788 A JP2015-41651A

  In the GaN-HEMT as described above, a source electrode and a drain electrode formed on an electron supply layer or the like are brought into ohmic contact to reduce contact resistance. ) Is performed. By performing the heat treatment in this manner, the contact resistance at the source electrode and the drain electrode can be lowered, and the drain current can be increased.

  In general, a source electrode and a drain electrode contain Al (aluminum), but Al has a low melting point, and Al is contained in the source electrode and the drain electrode when heat treatment for ohmic contact is performed. May spread. Thus, when Al contained in the source electrode and the drain electrode is diffused, the distance between the gate and the source (Lgs) and between the gate and the drain (Lgd) is effectively shortened, and the breakdown voltage is reduced and the reliability is increased. It will cause a decline in sex. This is particularly noticeable in a GaN-HEMT in the millimeter wave band where the distance between the gate and the source (Lgs) and the distance between the gate and the drain (Lgd) are relatively short.

  Therefore, in a semiconductor device using a nitride semiconductor, there is a demand for a highly reliable semiconductor device with low Al diffusion, high withstand voltage, even when heat treatment is performed to make ohmic contact between the source electrode and the drain electrode. Yes.

  According to one aspect of the present embodiment, a first semiconductor layer formed of a compound semiconductor on a substrate and a second semiconductor layer formed of a compound semiconductor on the first semiconductor layer. A source electrode and a drain electrode formed on the second semiconductor layer, a Ta film covering the source electrode and the drain electrode, a gate electrode formed on the second semiconductor layer, The Ta film is made of α-Ta, or the Ta film contains more α-Ta than β-Ta.

  According to the disclosed semiconductor device, a semiconductor device with high withstand voltage and high reliability can be obtained even when heat treatment for ohmic contact of electrodes is performed.

Structure diagram of semiconductor device Structure diagram of the semiconductor device in the first embodiment Process drawing (1) of the manufacturing method of the semiconductor device in 1st Embodiment Process drawing (2) of the manufacturing method of the semiconductor device in the first embodiment Process drawing (3) of the manufacturing method of the semiconductor device in the first embodiment Process drawing (4) of the manufacturing method of the semiconductor device in the first embodiment Structure diagram of semiconductor device according to second embodiment Process drawing (1) of the manufacturing method of the semiconductor device in 2nd Embodiment Process drawing (2) of the manufacturing method of the semiconductor device in 2nd Embodiment Process drawing of the manufacturing method of the semiconductor device in 2nd Embodiment (3) Process drawing (4) of the manufacturing method of the semiconductor device in 2nd Embodiment Structure diagram of semiconductor device according to third embodiment Explanatory diagram of a discretely packaged semiconductor device according to the fourth embodiment Circuit diagram of power supply device according to fourth embodiment Structure diagram of high-frequency amplifier in fourth embodiment

  The form for implementing is demonstrated below. In addition, about the same member etc., the same code | symbol is attached | subjected and description is abbreviate | omitted.

[First Embodiment]
As a method for suppressing the diffusion of Al from the source electrode and the drain electrode when the above heat treatment is performed, as shown in FIG. 1, the source electrode 932 and the drain electrode 933 containing Al are covered. In addition, there is a method of forming the electrode protective film 940 from a material such as Ti. Specifically, the semiconductor device shown in FIG. 1 is formed by stacking a buffer layer 911, an electron transit layer 921, an electron supply layer 922, and a cap layer 923 on a substrate 910 by epitaxial growth of a nitride semiconductor. ing. A source electrode 932 and a drain electrode 933 are formed on the electron supply layer 922. A gate electrode 931 is formed on the cap layer 923, and an insulating film 951 is formed on the cap layer 923 between the gate electrode 931 and the source electrode 932 and between the gate electrode 931 and the drain electrode 933. Is formed.

  An electrode protective film 940 is formed on part of the side surface and upper surface of the source electrode 932 and part of the side surface and upper surface of the drain electrode 933. The electrode protective film 940 is made of a metal material such as Ti (titanium). Further, an interlayer insulating film 952 is formed over the gate electrode 931, the electrode protection film 940, and the insulating film 951. In the interlayer insulating film 952, openings are formed over the source electrode 932 and the drain electrode 933. By filling the openings with a metal material, the source wiring 962 and the drain electrode 933 connected to the source electrode 932 are formed. A drain wiring 963 to be connected is formed.

  The substrate 910 is made of a semiconductor material such as SiC. The buffer layer 911 is made of AlN, GaN or the like, the electron transit layer 921 is made of i-GaN, the electron supply layer 922 is made of n-AlGaN, and the cap layer 923 is made of n- It is made of GaN. As a result, in the electron transit layer 921, 2DEG 921a is generated in the vicinity of the interface between the electron transit layer 921 and the electron supply layer 922.

  When the semiconductor device having the structure shown in FIG. 1 is manufactured, a source electrode 932 and a drain electrode 933 containing Al are formed on the electron supply layer 922, and the electrodes are formed so as to cover the source electrode 932 and the drain electrode 933. The protective film 940 is formed of a metal material such as Ti. Thereafter, heat treatment is performed to make ohmic contact between the source electrode 932 and the drain electrode 933. The electrode protection film 940 prevents Al contained in the source electrode 932 and the drain electrode 933 from diffusing during the heat treatment. It is formed for the purpose.

  However, the temperature of this heat treatment is about 800 ° C., and the surface of the electrode protection film 940 is oxidized by this heat treatment. When Ti or the like is oxidized, the volume expands, the density of the film decreases, and the function of barriering Al diffusion decreases, so that the Al contained in the source electrode 932 and the drain electrode 933 diffuses during the heat treatment. End up. The melting point of Al is 660 ° C., which is lower than the temperature of this heat treatment.

(Semiconductor device)
Next, the semiconductor device in the first embodiment will be described. In the semiconductor device according to the present embodiment, as shown in FIG. 2, a buffer layer 11, an electron transit layer 21, an electron supply layer 22, and a cap layer 23 are stacked on a substrate 10 by epitaxial growth of a nitride semiconductor. Is formed. A source electrode 32 and a drain electrode 33 are formed on the electron supply layer 22. A gate electrode 31 is formed on the cap layer 23 between the source electrode 32 and the drain electrode 33. In the present embodiment, the electron transit layer 21 may be referred to as a first semiconductor layer, and the electron supply layer 22 may be referred to as a second semiconductor layer.

  An α-Ta film 41 is formed on a part of the side surface and upper surface of the source electrode 32 and a part of the side surface and upper surface of the drain electrode 33 so as to cover the source electrode 32 and the drain electrode 33. A metal nitride film 42 is formed on 41 so as to cover the α-Ta film 41. That is, the α-Ta film 41 and the metal nitride film 42 are sequentially stacked on the side surface and part of the upper surface of the source electrode 32 and on the side surface and part of the upper surface of the drain electrode 33. The metal nitride film 42 is formed of a metal nitride such as Ta (tantalum), Ti (titanium), Al (aluminum), W (tungsten), that is, TaN, TiN, AlN, WN, or the like.

  An insulating film 51 is formed of SiN or the like on the metal nitride film 42 and the cap layer 23, and an interlayer insulating film 52 is formed on the gate electrode 31 and the insulating film 51. In addition, an opening is formed in the interlayer insulating film 52, the insulating film 51, the metal nitride film 42, and the α-Ta film 41, and the opening is filled with a metal material, whereby the source wiring 62 connected to the source electrode 32. A drain wiring 63 connected to the drain electrode 33 is formed.

  The substrate 10 is made of a semiconductor material such as SiC. The buffer layer 11 is made of AlN, GaN or the like, the electron transit layer 21 is made of i-GaN, the electron supply layer 22 is made of n-AlGaN, and the cap layer 23 is made of n- It is made of GaN. Thereby, in the electron transit layer 21, 2DEG 21 a is generated in the vicinity of the interface between the electron transit layer 21 and the electron supply layer 22. The source electrode 32 and the drain electrode 33 are formed by a metal laminated film in which an Al layer is formed on a Ti layer.

  By the way, the Ta crystal has an α phase and a β phase. α-phase tantalum (α-Ta) is a tantalum having a body-centered cubic crystal structure and a resistivity of 12 to 20 μΩ · cm. On the other hand, β-phase tantalum (β-Ta) is a tetragonal system tantalum and has a resistivity of about 200 μΩ · cm, which is one digit higher than α-Ta. Further, α-Ta is denser than β-Ta and is considered to have a high function as a barrier.

  The α-Ta film and the β-Ta film can be separately formed by a film forming method or the like. In general, the Ta film becomes β-Ta when the substrate temperature is formed by sputtering at room temperature, and becomes α-Ta when the film is formed by sputtering at a relatively high substrate temperature. Specifically, when a film is formed by sputtering at a substrate temperature of 200 ° C. or higher and 300 ° C. or lower, α-Ta or a film containing more α-Ta than β-Ta may be formed. Obtained as knowledge. In addition, when a Ta film is formed by vacuum deposition, a film in which α-Ta and β-Ta are mixed is obtained.

  In the semiconductor device in the present embodiment, an α-Ta film 41 is formed so as to cover the source electrode 32 and the drain electrode 33, and the α-Ta film 41 is further formed on the α-Ta film 41. A metal nitride film 42 is formed so as to cover the surface. For this reason, even if heat treatment for making ohmic contact between the source electrode 32 and the drain electrode 33 is performed, the α-Ta film 41 is dense and has a high function as a barrier. It can be prevented from spreading.

  Moreover, even if it is (alpha) -Ta, when it oxidizes, the volume expands, the density of a film | membrane falls, and the function as a barrier may fall. Therefore, in the present embodiment, a metal nitride film 42 made of TaN, TiN, AlN, WN or the like is formed on the α-Ta film 41. Since these metal nitrides have a high function as a barrier against oxygen, it is possible to prevent the α-Ta film 41 from being oxidized even when heat treatment is performed to bring the source electrode 32 and the drain electrode 33 into ohmic contact. it can.

  Therefore, since the source electrode 32 and the drain electrode 33 are covered with the α-Ta film 41 and the metal nitride film 42, even if a heat treatment for ohmic contact is performed, Al is generated from the source electrode 32 and the drain electrode 33. It can be prevented from spreading. The α-Ta film 41 may be a film containing more α-Ta than β-Ta. This is because the above effect can be obtained also in this case. However, the α-Ta film 41 is more preferably a film formed of only α-Ta from the viewpoint of denseness.

(Method for manufacturing semiconductor device)
Next, a method for manufacturing the semiconductor device in the first embodiment will be described.

  First, as shown in FIG. 3A, the buffer semiconductor layer 11, the electron transit layer 21, the electron supply layer 22, and the cap layer 23 are formed on the substrate 10 by epitaxially growing a nitride semiconductor layer. Thereby, in the electron transit layer 21, 2DEG 21 a is generated in the vicinity of the interface between the electron transit layer 21 and the electron supply layer 22. The nitride semiconductor layer is formed by epitaxial growth by MOVPE (Metal Organic Vapor Phase Epitaxy). These nitride semiconductor layers may be formed by MBE (Molecular Beam Epitaxy) instead of MOVPE.

  As the substrate 10, for example, a sapphire substrate, a Si substrate, a SiC substrate, or a GaN substrate can be used. In the present embodiment, a SiC substrate is used as the substrate 10. The buffer layer 11 is made of AlGaN or the like, the electron transit layer 21 is made of i-GaN, the electron supply layer 22 is made of n-AlGaN, and the cap layer 23 is made of n-GaN. ing.

When these nitride semiconductor layers are formed by MOVPE, TMA (trimethylaluminum) is used as the Al source gas, and TMG (trimethylgallium) is used as the Ga source gas. Further, NH ₃ (ammonia) is used as the N source gas. In addition, SiH ₄ (monosilane) is used when doping Si as an n-type impurity element. These source gases are supplied to the reactor of the MOVPE apparatus using hydrogen (H ₂ ) as a carrier gas.

  Thereafter, although not shown, an element isolation region for isolating elements is formed. Specifically, a photoresist is applied on the cap layer 23, and exposure and development are performed by an exposure apparatus, thereby forming a resist pattern having an opening in a region where an element isolation region is formed. Thereafter, an element isolation region is formed by implanting argon (Ar) ions into the nitride semiconductor layer in the region where the resist pattern is not formed. The element isolation region may be formed by removing a part of the nitride semiconductor layer in a region where the resist pattern is not formed by dry etching such as RIE (Reactive Ion Etching). After forming the element isolation region, the resist pattern is removed with an organic solvent or the like.

Next, as shown in FIG. 3B, the source electrode 32 and the drain electrode 33 are formed. Specifically, by applying a photoresist on the cap layer 23 and performing exposure and development by an exposure apparatus, a resist pattern (not shown) having openings in regions where the source electrode 32 and the drain electrode 33 are formed is formed. Form. Thereafter, the cap layer 23 in the region where the resist pattern is not formed is removed by dry etching using a chlorine-based gas as an etching gas to expose the electron supply layer 22. At this time, part of the electron supply layer 22 in the region where the source electrode 32 and the drain electrode 33 are formed may be removed by dry etching. Thereafter, the resist pattern is removed with an organic solvent or the like to expose exposed electrons. A source electrode 32 and a drain electrode 33 are formed on the supply layer 22. Specifically, a photoresist (not shown) having openings in regions where the source electrode 32 and the drain electrode 33 are formed by applying a photoresist on the cap layer 23 and performing exposure and development with an exposure apparatus. Form a pattern. Thereafter, a metal laminated film formed of Ti / Al (a metal laminated film formed in the order of Ti layer and Al layer) is formed by vacuum vapor deposition, and then immersed in an organic solvent, so that the top of the resist pattern The metal laminated film is removed together with the resist pattern by lift-off. Thereby, the source electrode 32 and the drain electrode 33 are formed by the metal laminated film remaining on the electron supply layer 22.

  Next, as shown in FIG. 4A, an α-Ta film 41 and a metal nitride film 42 that cover the side surfaces and the upper surface of the source electrode 32 and the drain electrode 33 are stacked. Specifically, the α-Ta film 41 is formed by forming a Ta film by sputtering at a substrate temperature of 250 ° C. Thus, the α-Ta film 41 can be formed by forming the Ta film by sputtering at a substrate temperature of 250 ° C. The film thickness of the α-Ta film 41 formed at this time is about 5 nm. Thereafter, the metal nitride film 42 is formed by nitriding the surface of the α-Ta film 41. Specifically, the metal nitride film 42 is formed by nitriding the surface of the α-Ta film 41 with nitrogen plasma generated using ammonia or nitrogen. In addition to this method, the metal nitride film 42 may be formed by forming a TaN film, a TiN film, or the like on the α-Ta film 41 by sputtering. Note that the film thickness of the α-Ta film 41 formed by sputtering is preferably 5 nm or more and 10 nm or less. This is because, in order for the α-Ta film 41 to function as a barrier, a thickness of several atomic layers is necessary. If it is too thick, it will take time and the like in the etching described later, leading to a decrease in throughput. .

  Thereafter, the α-Ta film 41 and the metal nitride film 42 between the source electrode 32 and the drain electrode 33 are removed. Specifically, a photoresist is applied on the metal nitride film 42, and exposure and development are performed by an exposure apparatus, whereby a resist pattern (not shown) is formed in a region where the source electrode 32 and the drain electrode 33 are formed. Form. This resist pattern has an opening between the source electrode 32 and the drain electrode 33. Thereafter, the α-Ta film 41 and the metal nitride film 42 in a region where the resist pattern is not formed are removed by dry etching using a fluorine-based gas, and the cap layer 23 is exposed. Thereafter, the resist pattern is removed with an organic solvent or the like, and heat treatment is performed at a temperature of 400 ° C. or higher and 1000 ° C. or lower, for example, about 800 ° C. in a nitrogen atmosphere. Let

  Next, as illustrated in FIG. 4B, the insulating film 51 is formed on the cap layer 23 and the metal nitride film 42. The insulating film 51 is formed by forming a silicon nitride (SiN) film having a thickness of 10 to 100 nm, for example, 40 nm on the cap layer 23 and the metal nitride film 42 by plasma CVD (chemical vapor deposition). To form. The insulating film 51 may be formed of silicon oxide (SiO), silicon oxynitride (SiON), aluminum nitride (AlN), aluminum oxide (AlO), or the like other than silicon nitride, and two of these materials You may form by the laminated film of. When the insulating film 51 is formed of a nitride such as silicon nitride or aluminum nitride, the cap layer 23 and the metal nitride film 42 are preferably the same nitride and have strong adhesion, which is preferable.

  Next, as shown in FIG. 5A, the gate electrode 31 is formed on the cap layer 23. Specifically, a photoresist is applied on the insulating film 51, and exposure and development are performed by an exposure apparatus, thereby forming a resist pattern (not shown) having an opening in a region where the gate electrode 31 is formed. Thereafter, the insulating film 51 in the opening of the resist pattern is removed by dry etching using a fluorine-based gas, and the surface of the cap layer 23 is exposed. Thereafter, the resist pattern is removed with an organic solvent or the like, a photoresist is applied again on the insulating film 51 and the cap layer 23, and exposure and development are performed by an exposure apparatus, whereby the gate electrode 31 is formed. A resist pattern (not shown) having an opening in a region to be formed is formed. Thereafter, a metal laminated film formed of Ni / Au (a metal laminated film formed in the order of Ni layer and Au layer) is formed by vacuum vapor deposition, and immersed in an organic solvent, whereby the metal on the resist pattern is formed. The laminated film is removed together with the resist pattern by lift-off. Thereby, the gate electrode 31 is formed by the metal laminated film remaining on the cap layer 23.

  Next, as shown in FIG. 5B, an interlayer insulating film 52 is formed on the insulating film 51 and the gate electrode 31, and openings 52 a and 52 b are formed on the source electrode 32 and the drain electrode 33. Form. Specifically, the interlayer insulating film 52 is formed on the insulating film 51 and the gate electrode 31 by applying methylsilsesquioxane by spin coating. Thereafter, a photoresist is applied on the interlayer insulating film 52, and exposure and development are performed by an exposure apparatus, whereby a resist pattern (not shown) having openings in regions where the source wiring 62 and the drain wiring 63 are formed. Form. Thereafter, the interlayer insulating film 52, the insulating film 51, the metal nitride film 42, and the α-Ta film 41 in the resist pattern opening are removed by dry etching to expose the surfaces of the source electrode 32 and the drain electrode 33. Openings 52a and 52b are formed. Although not shown, an opening where the surface of the gate electrode 31 is exposed is formed in the same step in the region where the gate electrode 31 is formed.

  Next, as shown in FIG. 6, the source wiring 62 connected to the source electrode 32 and the drain wiring 63 connected to the drain electrode 33 are formed in the openings 52 a and 52 b. Specifically, a metal laminated film such as Ti / Pt / Au serving as a barrier metal and a seed metal is formed on the surface of the interlayer insulating film 52 and the surfaces of the openings 52a and 52b by sputtering. Thereafter, a photoresist is applied onto the metal laminated film, and exposure and development are performed by an exposure apparatus, whereby a resist pattern (not shown) having openings in regions where the source wiring 62 and the drain wiring 63 are formed. Form. Thereafter, a film of Au or the like is formed by plating. Specifically, a source wiring 62 connected to the source electrode 32 and a drain wiring 63 connected to the drain electrode 33 are formed by forming a film of Au or the like by plating in a region where the metal laminated film is exposed. It is formed. Thereafter, the resist pattern is removed with an organic solvent or the like, and the metal laminated film such as Ti / Pt / Au is further removed by dry etching or the like. Although not shown, the gate wiring connected to the gate electrode 31 is also formed in the same process.

  As described above, the semiconductor device in this embodiment can be manufactured. In this embodiment, since the α-Ta film 41 and the metal nitride film 42 that cover the source electrode 32 and the drain electrode 33 are formed, the source electrode 32 and the drain electrode can be obtained even if heat treatment for ohmic contact is performed. Al contained in 33 can be prevented from diffusing.

  In the above description, the case where the electron supply layer 22 is AlGaN has been described. However, the electron supply layer 22 may be formed of InAlN or InAlGaN. The present embodiment can also be applied to the case where the electron transit layer 21, the electron supply layer 22, and the cap layer 23 are a compound semiconductor other than a nitride semiconductor, such as GaAs. However, since nitride semiconductors can be used for applications such as high breakdown voltage, it is more preferable to use this embodiment for nitride semiconductors.

[Second Embodiment]
(Semiconductor device)
Next, a second embodiment will be described. In the semiconductor device according to the present embodiment, the metal nitride film 42 is formed of a highly insulating material such as AlN, and metal nitridation is provided between the source electrode 32 and the drain electrode 33 as shown in FIG. The physical film 42 is formed, but the α-Ta film 41 is not formed. In the present embodiment, the surface of the cap layer 23 can be prevented from being oxidized by the metal nitride film 42 in the heat treatment for making ohmic contact between the source electrode 32 and the drain electrode 33. Since the metal nitride film 42 is formed of a highly insulating material, there is a problem even if the metal nitride film 42 is formed on the cap layer 23 between the source electrode 32 and the drain electrode 33. It will not be.

(Method for manufacturing semiconductor device)
Next, a method for manufacturing a semiconductor device in the second embodiment will be described.

  First, as shown in FIG. 8A, the nitride semiconductor layer is epitaxially grown on the substrate 10 to form the buffer layer 11, the electron transit layer 21, the electron supply layer 22, and the cap layer 23.

  Next, as shown in FIG. 8B, the source electrode 32 and the drain electrode 33 are formed.

  Next, as shown in FIG. 9A, an α-Ta film 41 that covers the side surfaces and the upper surface of the source electrode 32 and the drain electrode 33 is formed, and further, a metal that covers the α-Ta film 41 and the cap layer 23. A nitride film 42 is stacked. Specifically, the α-Ta film 41 is formed by forming a Ta film by sputtering at a substrate temperature of 250 ° C. The film thickness of the α-Ta film 41 formed at this time is about 5 nm.

  Thereafter, the α-Ta film 41 between the source electrode 32 and the drain electrode 33 is removed. Specifically, a photoresist is applied on the metal nitride film 42, and exposure and development are performed by an exposure apparatus, whereby a resist pattern (not shown) is formed in a region where the source electrode 32 and the drain electrode 33 are formed. Form. This resist pattern has an opening between the source electrode 32 and the drain electrode 33. Thereafter, the α-Ta film 41 in the opening of the resist pattern is removed by dry etching using a fluorine-based gas, and the cap layer 23 is exposed. Thereafter, the resist pattern is removed with an organic solvent or the like.

  Thereafter, an AlN film or the like is formed by sputtering or the like, thereby forming a metal nitride film 42 on the α-Ta film 41 and the cap layer 23. Thereafter, the source electrode 32 and the drain electrode 33 are brought into ohmic contact by heat treatment in a nitrogen atmosphere at a temperature of 400 ° C. or higher and 1000 ° C. or lower, for example, about 800 ° C.

  Next, as shown in FIG. 9B, an insulating film 51 is formed on the metal nitride film 42. The insulating film 51 is formed by forming a silicon nitride film having a thickness of 10 to 100 nm, for example, 40 nm on the metal nitride film 42 by plasma CVD.

  Next, as shown in FIG. 10A, the gate electrode 31 is formed on the cap layer 23. Specifically, a photoresist is applied on the insulating film 51, and exposure and development are performed by an exposure apparatus, thereby forming a resist pattern (not shown) having an opening in a region where the gate electrode 31 is formed. Thereafter, the insulating film 51 and the metal nitride film 42 in the opening of the resist pattern are removed by dry etching using a fluorine-based gas, and the surface of the cap layer 23 is exposed. Thereafter, the resist pattern is removed with an organic solvent or the like, a photoresist is applied again on the insulating film 51 and the cap layer 23, and exposure and development are performed by an exposure apparatus, whereby the gate electrode 31 is formed. A resist pattern (not shown) having an opening in a region to be formed is formed. Thereafter, a metal laminated film formed of Ni / Au is formed by vacuum deposition and immersed in an organic solvent, whereby the metal laminated film on the resist pattern is removed together with the resist pattern by lift-off. Thereby, the gate electrode 31 is formed by the metal laminated film remaining on the cap layer 23.

  Next, as shown in FIG. 10B, an interlayer insulating film 52 is formed on the insulating film 51 and the gate electrode 31, and openings 52 a and 52 b are formed on the source electrode 32 and the drain electrode 33. Form. Although not shown, the gate electrode 31 is similarly formed with an opening through which the surface of the gate electrode 31 is exposed.

  Next, as shown in FIG. 11, the source wiring 62 connected to the source electrode 32 and the drain wiring 63 connected to the drain electrode 33 are formed in the openings 52a and 52b. Although not shown, the gate wiring connected to the gate electrode 31 is formed in the same manner.

  Through the above steps, the semiconductor device in this embodiment can be manufactured. In this embodiment, since the cap layer 23 is covered with the metal nitride film 42, the surface of the cap layer 23 is oxidized even if heat treatment for ohmic contact is performed on the source electrode 32 and the drain electrode 33. There is nothing. Thus, reliability and yield in the semiconductor device can be improved.

  The contents other than the above are the same as in the first embodiment.

[Third Embodiment]
Next, a third embodiment will be described. The semiconductor device in the present embodiment has a structure in which the metal nitride film 42 is not formed, as shown in FIG. For example, even if a heat treatment for making ohmic contact between the source electrode 32 and the drain electrode 33 is performed, it is not necessary to form the metal nitride film 42 unless the α-Ta film 41 is oxidized. Specifically, a case where heat treatment is performed in a high vacuum not containing oxygen or the like is assumed.

  The manufacturing method of the semiconductor device in the present embodiment is the same as that of the first embodiment except that the metal nitride film 42 is not formed. The contents other than those described above are the same as those in the first embodiment.

[Fourth Embodiment]
Next, a fourth embodiment will be described. The present embodiment is a semiconductor device, a power supply device, and a high-frequency amplifier.

  The semiconductor device according to the present embodiment is a discrete package of the semiconductor device according to the first to third embodiments. The discretely packaged semiconductor device will be described with reference to FIG. FIG. 13 schematically shows the inside of a discretely packaged semiconductor device. The arrangement of electrodes and the like are different from those shown in the first to third embodiments. .

  First, the semiconductor device manufactured in the first to third embodiments is cut by dicing or the like, thereby forming a semiconductor chip 410 such as a HEMT made of a GaN-based semiconductor material. The semiconductor chip 410 is fixed on the lead frame 420 with a die attach agent 430 such as solder. The semiconductor chip 410 corresponds to any one of the semiconductor devices according to the first to third embodiments.

  Next, the gate electrode 411 is connected to the gate lead 421 by a bonding wire 431, the source electrode 412 is connected to the source lead 422 by a bonding wire 432, and the drain electrode 413 is connected to the drain lead 423 by a bonding wire 433. The bonding wires 431, 432, and 433 are made of a metal material such as Al. In the present embodiment, the gate electrode 411 is a gate electrode pad and is connected to the gate electrode 31 of the semiconductor device in the first to third embodiments. The source electrode 412 is a source electrode pad, and is connected to the source electrode 32 of the semiconductor device according to the first to third embodiments. The drain electrode 413 is a drain electrode pad, and is connected to the drain electrode 33 of the semiconductor device according to the first to third embodiments.

  Next, resin sealing with a mold resin 440 is performed by a transfer molding method. In this manner, a discrete device such as HEMT using a GaN-based semiconductor material can be manufactured.

  Next, a power supply device and a high frequency amplifier in the present embodiment will be described. The power supply device and the high-frequency amplifier in the present embodiment are a power supply device and a high-frequency amplifier using any one of the semiconductor devices in the first to third embodiments.

  First, the power supply apparatus according to the present embodiment will be described with reference to FIG. The power supply device 460 in this embodiment includes a high-voltage primary circuit 461, a low-voltage secondary circuit 462, and a transformer 463 disposed between the primary circuit 461 and the secondary circuit 462. The primary circuit 461 includes an AC power supply 464, a so-called bridge rectifier circuit 465, a plurality of switching elements (four in the example shown in FIG. 14) 466, a switching element 467, and the like. The secondary side circuit 462 includes a plurality of switching elements (three in the example shown in FIG. 14) 468. In the example shown in FIG. 14, the semiconductor device according to the first to third embodiments is used as the switching elements 466 and 467 of the primary circuit 461. Note that the switching elements 466 and 467 of the primary circuit 461 are preferably normally-off semiconductor devices. The switching element 468 used in the secondary circuit 462 uses a normal MISFET (metal insulator semiconductor field effect transistor) formed of silicon.

  Next, the high frequency amplifier in the present embodiment will be described with reference to FIG. The high frequency amplifier 470 in the present embodiment may be applied to, for example, a power amplifier for a base station of a mobile phone. The high frequency amplifier 470 includes a digital predistortion circuit 471, a mixer 472, a power amplifier 473, and a directional coupler 474. The digital predistortion circuit 471 compensates for nonlinear distortion of the input signal. The mixer 472 mixes the input signal compensated for nonlinear distortion and the AC signal. The power amplifier 473 amplifies the input signal mixed with the AC signal. In the example illustrated in FIG. 15, the power amplifier 473 includes the semiconductor device according to the first to third embodiments. The directional coupler 474 performs monitoring of input signals and output signals. In the circuit shown in FIG. 15, for example, the output signal can be mixed with the AC signal by the mixer 472 and sent to the digital predistortion circuit 471 by switching the switch.

  Although the embodiment has been described in detail above, it is not limited to the specific embodiment, and various modifications and changes can be made within the scope described in the claims.

In addition to the above description, the following additional notes are disclosed.
(Appendix 1)
A first semiconductor layer formed of a compound semiconductor on a substrate;
A second semiconductor layer formed of a compound semiconductor on the first semiconductor layer;
A source electrode and a drain electrode formed on the second semiconductor layer;
A Ta film covering the source electrode and the drain electrode;
A gate electrode formed on the second semiconductor layer;
Have
The Ta film is formed of α-Ta, or the Ta film contains more α-Ta than β-Ta.
(Appendix 2)
The semiconductor device according to appendix 1, wherein a metal nitride film is formed of metal nitride on the Ta film.
(Appendix 3)
The semiconductor device according to appendix 2, wherein the metal nitride film is a nitride containing any one of tantalum, titanium, aluminum, and tungsten.
(Appendix 4)
4. The semiconductor device according to any one of appendices 1 to 3, wherein the compound semiconductor is a nitride semiconductor.
(Appendix 5)
The first semiconductor layer is made of a material containing GaN,
The semiconductor device according to any one of appendices 1 to 4, wherein the second semiconductor layer is made of a material containing any one of AlGaN, InAlN, and InAlGaN.
(Appendix 6)
A cap layer is formed of a material containing GaN on the second semiconductor layer,
6. The semiconductor device according to any one of appendices 1 to 5, wherein the gate electrode is formed on the cap layer.
(Appendix 7)
7. The semiconductor device according to any one of appendices 1 to 6, wherein the source electrode and the drain electrode are made of aluminum.
(Appendix 8)
A power supply device comprising the semiconductor device according to any one of appendices 1 to 7.
(Appendix 9)
An amplifier comprising the semiconductor device according to any one of appendices 1 to 7.
(Appendix 10)
Forming a first semiconductor layer from a compound semiconductor on a substrate;
Forming a second semiconductor layer from a compound semiconductor on the first semiconductor layer;
Forming a source electrode and a drain electrode on the second semiconductor layer;
Forming the Ta film covering the source and drain electrodes;
A step of performing a heat treatment after forming the Ta film;
After the heat treatment, forming a gate electrode on the second semiconductor layer;
Have
The method for manufacturing a semiconductor device, wherein the Ta film is formed of α-Ta or contains more α-Ta than β-Ta.
(Appendix 11)
Forming a metal nitride film on the Ta film after forming the Ta film;
The method of manufacturing a semiconductor device according to appendix 10, wherein the heat treatment is performed after the metal nitride film is formed.
(Appendix 12)
12. The method of manufacturing a semiconductor device according to appendix 11, wherein the metal nitride film is a nitride containing any one of tantalum, titanium, aluminum, and tungsten.
(Appendix 13)
The method of manufacturing a semiconductor device according to appendix 11, wherein the metal nitride film is formed by nitriding the surface of the Ta film.
(Appendix 14)
14. The method of manufacturing a semiconductor device according to appendix 13, wherein the nitriding of the Ta film is performed using nitrogen plasma.
(Appendix 15)
15. The method of manufacturing a semiconductor device according to any one of appendices 10 to 14, wherein the Ta film is a film formed by sputtering.
(Appendix 16)
The method of manufacturing a semiconductor device according to appendix 15, wherein a substrate temperature when the Ta film is formed by sputtering is 200 ° C. or higher and 300 ° C. or lower.
(Appendix 17)
17. The method of manufacturing a semiconductor device according to any one of appendices 10 to 16, wherein the thickness of the Ta film is 5 nm or more and 10 nm or less.
(Appendix 18)
18. The method of manufacturing a semiconductor device according to any one of appendices 10 to 17, wherein the heat treatment is for making ohmic contact between the source electrode and the drain electrode.
(Appendix 19)
The method for manufacturing a semiconductor device according to any one of appendices 10 to 18, wherein the temperature of the heat treatment is 400 ° C. or higher and 1000 ° C. or lower.
(Appendix 20)
20. The method of manufacturing a semiconductor device according to any one of appendices 10 to 19, wherein the source electrode and the drain electrode are formed of an aluminum-containing material.
(Appendix 21)
The method of manufacturing a semiconductor device according to appendix 20, wherein the temperature of the heat treatment is equal to or higher than a melting point of aluminum.
(Appendix 22)
22. The method for manufacturing a semiconductor device according to any one of appendices 10 to 21, wherein the compound semiconductor is a nitride semiconductor.
(Appendix 23)
The first semiconductor layer is made of a material containing GaN,
23. The method for manufacturing a semiconductor device according to any one of appendices 10 to 22, wherein the second semiconductor layer is formed of a material containing any one of AlGaN, InAlN, and InAlGaN.

10 substrate 11 buffer layer 21 electron transit layer (first semiconductor layer)
21a 2DEG
22 Electron supply layer (second semiconductor layer)
23 Cap layer 31 Gate electrode 32 Source electrode 33 Drain electrode 41 α-Ta film 42 Metal nitride film 51 Insulating film 52 Interlayer insulating film 62 Source wiring 63 Drain wiring

Claims (11)

A first semiconductor layer formed of a compound semiconductor on a substrate;
A second semiconductor layer formed of a compound semiconductor on the first semiconductor layer;
A source electrode and a drain electrode formed on the second semiconductor layer;
A Ta film covering the source electrode and the drain electrode;
A gate electrode formed on the second semiconductor layer;
Have
The Ta film is formed of α-Ta, or the Ta film contains more α-Ta than β-Ta.   The semiconductor device according to claim 1, wherein a metal nitride film is formed of metal nitride on the Ta film.   The semiconductor device according to claim 2, wherein the metal nitride film is a nitride containing any one of tantalum, titanium, aluminum, and tungsten.   A power supply device comprising the semiconductor device according to claim 1.   An amplifier comprising the semiconductor device according to claim 1. Forming a first semiconductor layer from a compound semiconductor on a substrate;
Forming a second semiconductor layer from a compound semiconductor on the first semiconductor layer;
Forming a source electrode and a drain electrode on the second semiconductor layer;
Forming the Ta film covering the source and drain electrodes;
A step of performing a heat treatment after forming the Ta film;
After the heat treatment, forming a gate electrode on the second semiconductor layer;
Have
The method for manufacturing a semiconductor device, wherein the Ta film is formed of α-Ta or contains more α-Ta than β-Ta. Forming a metal nitride film on the Ta film after forming the Ta film;
The method of manufacturing a semiconductor device according to claim 6, wherein the heat treatment is performed after the metal nitride film is formed.   8. The method of manufacturing a semiconductor device according to claim 7, wherein the metal nitride film is formed by nitriding the surface of the Ta film.   9. The method of manufacturing a semiconductor device according to claim 8, wherein the nitriding of the Ta film is performed using nitrogen plasma.   The method of manufacturing a semiconductor device according to claim 6, wherein the Ta film is a film formed by sputtering. The method of manufacturing a semiconductor device according to claim 10, wherein a substrate temperature when the Ta film is formed by sputtering is 200 ° C. or more and 300 ° C. or less.

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