JP2019028651A - Synchronous reset circuit and control method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To supply a clock having an appropriate frequency during a fixed reset period to a functional block to be reset without affecting system performance in a semiconductor integrated circuit that performs synchronous reset individually on a plurality of functional blocks. A synchronous reset circuit according to the present invention includes a reset generation unit that individually enables reset signals of individual reset target circuits in a chip for a fixed period, and individually supplies a clock signal to the individual reset target circuits. The clock signal corresponding to the reset target circuit connected to the valid reset signal outputs a pulse number appropriate for resetting the reset target circuit during the fixed period in which the reset signal is valid. And clock supply means for changing the frequency. [Selection] Figure 1

Description

  The present invention relates to clock control during execution of synchronous reset in a synchronous reset circuit.

  In recent years, high-performance and high-functionality mobile terminal devices such as digital cameras and smartphones have progressed, and the power consumption of LSIs has increased, and power reduction measures are urgently needed.

  Power consumption is classified into dynamic power and leak power. Dynamic power is the power consumed during the circuit operation, and the leak power is steady when the power is on regardless of whether the circuit is operating. Power consumption.

  Methods for reducing dynamic power include clock cutoff (clock gating) and clock frequency reduction. In a synchronous reset circuit adopting a synchronous reset method, initialization is performed by supplying a clock to a storage element such as a flip-flop of a reset target circuit during a reset operation. It is known that the dynamic power of the chip during the reset operation becomes larger than that during the normal operation because the clock is simultaneously supplied to all the reset target circuit elements during the reset operation. There has been proposed a technique for reducing dynamic power by switching a clock supplied to a reset target circuit to a low frequency clock during a power-on reset period after power-on (for example, Patent Document 1).

  On the other hand, as a typical method for reducing leakage power, each function block that realizes each function of the system of the semiconductor integrated circuit is divided into power-off blocks, and this function is used during a period when the function that each function block is in charge of is not used. There is a “power shutdown” that shuts off the power to the functional block.

  In the case of this “power shutdown”, unlike the case of clock shutdown for reducing dynamic power, the power switch control, clock control, reset control, isolation control, etc. Need control of the signal.

  The power shutdown sequence and the power recovery sequence are necessary to suppress the influence on the peripheral blocks where the power is not shut off, and to prevent the functional block targeted for power shutdown from restarting the process from an unstable state. It is desirable to switch to a low frequency clock from the viewpoint of dynamic power even during reset control of this power recovery sequence.

  Conventionally, the power shutdown sequence and the power recovery sequence have been realized by software controlled implementation. The hardware is mounted so that the polarity of a control signal such as a power switch and reset can be controlled, and the polarity and timing are all controlled by software. Switching to a low frequency clock was also controlled by software.

  As a means for realizing the above clock control, a configuration is conceivable in which a low frequency clock is generated by an oscillator, a high frequency clock used during normal operation of the system is generated by a PLL (Phase Lock Loop), and switched according to the operation mode of the chip. . From the viewpoint of chip size and power consumption, it is preferable that the number of PLLs is small. A plurality of functional blocks share one PLL as a clock source. Furthermore, from the viewpoint of physical timing convergence, the low-frequency clock and the high-frequency clock are switched in the vicinity of the PLL, branched to a clock for each functional block, and the clock is supplied via a frequency divider arranged in the vicinity of each functional block. A distributed clock configuration is taken.

  In the case of this clock configuration, at the time of power-on reset, the low-frequency clock of the oscillator is supplied to the entire system to execute the power-on reset, and the high-frequency clock of the PLL is switched during normal operation. When resetting the target functional block to restore power during normal operation, switching the PLL clock to the oscillator low-frequency clock slows down the entire system, affecting system performance. End up. Therefore, the frequency of only the clock supplied to the function block to be reset is lowered by the frequency divider near each functional block.

Japanese Patent No. 3119628

  In recent years, due to an increase in the number of signals to be controlled during a reset sequence, timing restrictions between signals, and the like, complicated reset sequence control is required, and control by software has become difficult. Furthermore, in order to improve the required performance, it is required to complete the reset sequence in a shorter period. In order to solve such a problem, it is conceivable to automate the reset sequence executed when the power is restored by hardware.

  When the reset sequence is implemented by fixing the control timing of the reset related signal by hardware, it is necessary to supply a clock for synchronous reset within a fixed period in which the reset is valid. Here, if the clock frequency to be supplied is too high, power consumption will increase. Conversely, if the frequency is too low, the number of pulses required for synchronous reset cannot be supplied within the reset period and initialization will not be performed normally. Will occur. Whether the entire system is operating with a high-frequency clock or a low-frequency clock when executing power recovery depends on the product and system. It is necessary to supply a clock having an appropriate frequency to the function block to be reset in accordance with the operation mode of the system.

  The present invention has been made to solve the above-described problem, and is a hardware that automatically supplies a clock having an appropriate frequency to a functional block to be reset during a fixed reset period without affecting system performance. An object is to provide a wear sequencer.

  A synchronous reset circuit according to the present invention includes: a reset supply unit that individually enables a reset signal of each reset target circuit in a chip to be valid for a fixed period; and a clock signal is individually supplied to each of the reset target circuits, and the reset During a fixed period in which the signal is valid, the frequency is changed so that the clock signal corresponding to the reset target circuit to which the valid reset signal is connected outputs an appropriate number of pulses to reset the reset target circuit. And a clock supply unit.

  According to the present invention, it is possible to reliably perform a reset while suppressing power consumption without affecting the performance of a circuit other than the reset target and without depending on the operation mode of the system.

Block diagram showing a configuration example of an information processing apparatus Block diagram showing a configuration example of the reset supply unit Block diagram showing a configuration example of the clock supply unit Diagram showing an example of the configuration of the reset synchronizer Flow chart explaining the power recovery sequence Flow chart explaining power-off sequence A flowchart for explaining a reset sequence in the power recovery sequence The figure explaining operation of a reset supply part and a clock supply part at the time of a power-on reset sequence The figure explaining operation | movement of the reset supply part and clock supply part at the time of the reset sequence with respect to the subsystem 106 at the time of operate | moving with a high frequency clock. The figure explaining operation | movement of the reset supply part and clock supply part at the time of the reset sequence with respect to the subsystem 106 at the time of operate | moving with a low frequency clock.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings. The following embodiments are merely examples, and are not intended to limit the scope of the present invention.

[Example 1]
A configuration example of the information processing apparatus 10 is shown in the block diagram of FIG. The information processing apparatus 10 is an information processing apparatus for a digital camera system, for example, and has a configuration represented by a semiconductor device called a system-on-chip. A synchronous reset circuit for performing synchronous reset is included.

  The information processing apparatus 10 includes a reset supply unit 101 that generates a reset signal to be supplied to each block in the information processing apparatus 10 and a clock supply unit 102 that generates a clock signal. Furthermore, it has the power supply control part 103 which produces | generates the power supply control signal with respect to each power supply interruption | blocking block.

  The information processing apparatus 10 includes a bus system 104 that controls data transfer, and is called an interconnect, a fabric, an on-chip network, or a network on chip. The bus system 104 is connected to a CPU 105 that performs processing of the entire information processing apparatus. Further, a video input processing unit that receives digital data from a sensor outside the semiconductor device 10 (not shown) and transfers the video data to the DRAM 20 is connected. Further, an image processing unit that processes the video data stored in the DRAM 20 and a video output processing unit that transfers the video data to the outside of the information processing apparatus 10 are connected. It is assumed that the subsystem 106 and the subsystem 107 are responsible for these processing units.

  On the other hand, a memory controller 108 for transferring data to the DRAM 20 is connected to the bus system 104. The CPU 105 executes a program stored in a ROM (not shown) using the DRAM 20 as a work memory.

  Although not shown in the figure, the reset supply unit 101 is supplied with a clock from the clock supply unit 102 and operates in synchronization with the clock. The reset supply unit 101 generates a clock enable 109 for the clock supply unit 102 together with the reset signal. In this embodiment, the clock enable signal is controlled individually for each clock signal, and the clock enable 109 is expressed by bundling a total of five signals corresponding to clocks 1 to 5. Details of the operation of the reset supply unit 101 will be described later with reference to FIG.

  When the clock enable 109 becomes valid, the clock supply unit 102 outputs a corresponding clock. Further, the frequency of the clock signal can be individually controlled. Details of the operation of the clock supply unit 102 will be described later with reference to FIG.

  The power control unit 103 performs power supply control and isolation control of the power shut-off block inside the information processing apparatus 10. Power supply control and isolation control are generally controlled by separate signals. In this embodiment, the power supply control signal and the isolation control signal are bundled and expressed as a power control signal. Here, the isolation control refers to mask control for preventing a circuit whose power is cut off from affecting other uncut circuits.

  The reset supply unit 101, the clock supply unit 102, and the power supply control unit 103 are interconnected by a sequence state notification interface. The sequence status notification interface is used to notify each other of the sequence execution status when executing the power shutdown sequence and the power recovery sequence.

  The subsystem 106 and the subsystem 107 are power shut-off blocks, and each power supply and isolation are individually controlled by the power control unit 103 via the power control signal 1 and the power control signal 2. Other functional blocks are not subject to power shut-off, and are always supplied with power.

  The bus system 104, the CPU 105, the subsystem 106, the subsystem 107, and the memory controller 108 are synchronous reset type functional blocks, and at least three cycles of clock pulses are required to execute the reset. One of the factors that require multiple clock pulses for reset execution in synchronous reset is a reset synchronizer. Details of the reset synchronizer will be described later with reference to FIG.

  An example of the configuration of the reset supply unit 101 is shown in the block diagram of FIG. The reset supply unit 101 includes a power-on reset reset sequencer 1011 and a power-off reset sequencer 1012. Further, reset control signal selection units 1013 and 1014 and clock enable selection units 1015 and 1016 for selecting a reset control signal and a clock enable signal output from each reset sequencer are provided. And it has the reset holding | maintenance part 1017 which hold | maintains the signal level of a reset according to a reset control signal.

  The power-on-reset reset sequencer 1011 is a reset sequencer that operates when the chip is activated, and is activated using an external reset signal input from outside the information processing apparatus 10 as a trigger.

  The power-on reset reset sequencer 1011 generates power-on reset reset control signals 1 and 2. The reset control signal 1 for power-on reset is a signal for controlling the reset 4 supplied to the CPU 105, and the reset control signal 2 for power-on reset is a signal for controlling the reset signal supplied to other functional blocks. Reset control information indicating whether the reset signal is set to L level or H level is transmitted to the reset holding unit 1017 by the reset control signals 1 and 2 for power-on reset. The reset signal is active at the L level (low active). When the reset control information is transmitted, the reset holding unit 1017 changes the signal level of the reset signal to the level indicated by the transmitted reset control information, and holds the signal level until the reset control information is transmitted again. The power-on-reset reset sequencer 1011 starts a power-on reset sequence with an external reset signal as a trigger. Details of the power-on reset sequence will be described later with reference to FIG. The power-on-reset reset sequencer 1011 also generates a power-on-reset clock enable 1 that is a clock enable signal dedicated to the clock signal of the CPU 105 and a power-on-reset clock enable 2 for other clock signals.

  The power shutdown reset sequencer 1012 is a reset sequencer that operates during a power shutdown recovery sequence, and is activated by using a sequence status notified from the power control unit 103 via a sequence status notification interface as a trigger. The power shutdown reset sequencer 1012 duplicates the power-on reset reset sequencer 1011 and performs an equivalent operation. The power-on reset control signals 1 and 2 and the power-off reset control signals 1 and 2 correspond to the power-on reset clock enables 1 and 2 and the power-off clock enables 1 and 2, respectively.

  The power shutdown reset sequencer 1012 generates power shutdown reset control signals 1 and 2. The power cutoff reset control signal 1 is a signal for controlling a reset signal dedicated to the CPU 105, but in this embodiment, the CPU 105 is not connected to the power cutoff because it is not a target for power cutoff. The power cutoff reset control signal 2 is a signal for controlling a reset signal supplied to other functional blocks. Further, the power shutdown reset sequencer 1012 generates a power cutoff clock enable 1 which is a clock enable signal dedicated to the clock signal of the CPU 105 and a power cutoff clock enable 2 for other clock signals. Similarly, since the CPU 105 is not a power cutoff block, the power cutoff clock enable 2 is not connected.

  The power shutdown reset sequencer 1012 notifies the status of the reset sequence to the clock supply unit 102 and the power supply control unit 103 via the status notification interface.

  The reset control signal selection unit 1013 selects the power-on reset reset control signal 2 and the power-off reset control signal 2 and outputs the reset control signal 1. The reset control signal selection unit 1013 selects the power shutdown reset control signal 2 when the subsystem 106 is the target based on the power shutdown target block information of the power shutdown return sequence notified via the sequence state notification interface. . During other periods, the power-on reset reset control signal 2 is selected. Similarly, the reset control signal selection unit 1014 and the clock enable selection units 1015 and 1016 operate to select a signal output by the power shutdown reset sequencer 1012 during the power shutdown return sequence for the corresponding power shutdown block. From the above, during power-on reset, the signal output by the power-on reset reset sequencer is valid, and during the power-off reset sequence, the signal output by the power-off reset sequencer only for the power-off target block in the power-off reset sequence Becomes effective.

  The reset supply unit individually enables reset signals of individual reset target circuits in the chip for a fixed period.

  A configuration example of the clock supply unit 102 is shown in the block diagram of FIG. An OSC (oscillator) 1021 is an oscillation circuit that generates a low-frequency clock. A PLL (Phase Lock Loop) 1022 is a phase synchronization circuit that generates a clock faster than the clock generated by the OSC 1021. The present invention is not limited to the oscillator and the PLL, and any form may be used as long as it is a clock source source.

  The clock MUX 1023 selects one of the clocks output from the OSC 1021 and the PLL 1022 and outputs it as the clock 6. The clock control unit 1024 generates a select signal for controlling the clock MUX1023. After the clock 6 branches, it is output from the clock supply unit 102 as the clock 1 to the clock 5 through the respective clock frequency dividing units 1026 and the clock gating unit 1028.

  In the initial state of the power-on reset period at the time of chip activation, the clock MUX 1023 selects the low frequency clock output from the OSC 1021 and outputs it as the clock 6. On the other hand, after the power-on reset is completed, the information processing apparatus 10 as a whole can execute processing at high speed by switching the high-frequency clock output from the PLL 1022 to be selected by the clock MUX 1023. When the low frequency clock is selected, the low speed operation mode is called, and when the high frequency clock is selected, the normal operation mode is called.

  As described above, the clock control unit 1024 generates the select signal of the clock MUX1023. Further, the clock control unit 1024 generates the clock enable 11 from the clock enable 7 supplied to the clock gating unit 1028. The clock control unit 1024 may include a register interface (not shown) and may control an output signal by register access from the CPU 105 via the bus system 104. Alternatively, the clock control unit 1024 may include a hardware sequencer and automatically control the output signal in accordance with the state of the reset signal and other signals indicating the state of the chip.

  The clock frequency division setting unit 1025 outputs a frequency division setting value to the clock frequency division unit, triggered by the sequence state notified from the power shutdown reset sequencer 1012 via the sequence state notification interface. The clock frequency division setting unit 1025 can individually control the frequency division setting values for the clock frequency division unit 1026 corresponding to each of the clocks 1 to 5. By notifying the power-off target block information of the power-off return sequence being executed from the sequence state notification interface, only the frequency division setting value for the clock signal corresponding to the power-off target block is controlled. Further, the clock frequency division setting unit 1025 monitors which clock is selected by the clock MUX 1023 and determines a frequency division ratio suitable for reset execution according to the frequency of the clock 6. The frequency division ratio is a ratio that the clock signal has the number of pulses necessary for resetting the reset target circuit in a fixed period in which the reset signal is valid.

  The clock divider 1026 divides the clock 6 based on the signal notified from the clock divider setting unit 1025 and outputs the clock to the clock gating unit 1028.

  Clock enable signals corresponding to the clocks output from the reset supply unit 101 and the clock control unit 1024 are logically ORed by the OR circuit 1027 and input to the clock gating unit 1028. The clock enable signal is active at the H level (high active).

  The clock gating unit 1028 performs a clock ON / OFF operation based on the input clock gating signal. Specifically, the clock is passed during the period when the clock gating signal is at the H level, and the clock is shut off during the period when the clock gating signal is at the L level. Accordingly, a clock corresponding to the clock enable signal output from the reset supply unit 101 or the clock control unit 1024 is output from the clock supply unit 102 while the clock enable signal is at the H level. As a typical circuit of the clock gating unit 1028, a GCB (clock gating buffer) is widely known.

  The reset signal synchronizer in the synchronous reset method will be described with reference to the circuit diagram of FIG. The two flip-flops 301 and 302 of the reset synchronizer 30 receive the reset signal in synchronization with the clock. When the reset signal becomes valid (L level), the L level propagates from the reset synchronizer 30 after two cycles. FIG. 4 shows a case where the initial value of the flip-flop 31 existing at the end is 0, and the reset signal reaches the D terminal of the flip-flop 31 via the AND circuit 32. In the next cycle in which the reset signal is synchronized, the flip-flop 31 latches the L level, and the reset state is entered. Although the other input of the AND circuit 32 is not shown in the figure, an input signal latched by the flip-flop 31 when the reset signal is invalid (H level) is connected.

  If one reset synchronizer exists in the reset target block from the above operation, a total of three cycles are required until the terminal flip-flop is in the reset state. The same is true at the time of reset cancellation, and three cycles are required until the reset signal becomes invalid (H level) and reflected in the terminal flip-flop 31. If reset synchronizers are arranged in multiple stages in the reset target block, the number of clock pulses necessary for the synchronous reset increases according to the number of reset synchronizers.

  The power recovery sequence operation of the power shutoff block will be described with reference to the flowchart shown in FIG. Note that the power recovery sequence shown in FIG. 5 is a sequence for individually recovering the power of each power shut-off block, and the power shut-off blocks are sequentially controlled exclusively. For ease of explanation, the case where the power supply of the subsystem 106 is restored will be described below.

  The subsystem 106 is in a power-off state at the start of the power recovery sequence, and no power is supplied (S0). Furthermore, the clock 1 is stopped and the isolation function is enabled. When the CPU 105 notifies the power control unit 103 of the start of the power recovery sequence, the power control unit 103 enables the power switch of the subsystem 106 via the power control signal 1 and supplies power (S1). As an example of a method for notifying the power supply control unit 103 of starting the power recovery sequence, a register interface is provided in the power supply control unit 103, and the CPU 105 rewrites the sequence activation register possessed by the power control unit 103 via the bus system 104. Conceivable. However, the data transfer interface from the bus system 104 to the power supply control unit 103 is not shown in the figure.

  When power is supplied to the subsystem 106, the power control unit 103 notifies the reset supply unit 101 that the power supply has been completed via the sequence state notification interface. The reset supply unit 101 executes a reset sequence for the subsystem 106 (S2). Details of the reset sequence when power is restored will be described later with reference to FIGS. In addition, the sequence state notification interface notifies that the power cutoff target block is the subsystem 106 together with the power supply completion state.

  When the reset sequence is completed, the reset supply unit 101 notifies the power supply control unit 103 of the completion of the reset sequence, and the power supply control unit 103 performs control to invalidate the isolation of the subsystem 106 via the power supply control signal 1 (S3). ).

  When the isolation invalidation is completed, the power control unit 103 notifies the CPU 105 of the completion of the power recovery sequence (S4). An interrupt signal shown in FIG. 1 may be used as a method for notifying the CPU 105 of the completion of the power recovery sequence. Alternatively, a status register may be provided in the power supply control unit 103, and the CPU 105 may notify by a method of polling the register.

  Thus, the power recovery sequence of the subsystem 106 is completed, and the subsystem 106 becomes operable (S5).

  The power shutdown sequence operation of the power shutdown block will be described with reference to the flowchart shown in FIG. Note that the power shut-off sequence shown in FIG. 6 is a sequence for powering off each power shut-off block individually, and each power shut-off block is controlled sequentially and exclusively. For ease of explanation, the case where the subsystem 106 is powered off will be described below.

  The subsystem 106 is in a power-on state at the start of the power shutdown sequence, and power is supplied (S5). Furthermore, the clock is stopped and the isolation function is disabled. When the CPU 105 notifies the power control unit 103 of the start of the power shutoff sequence, the power control unit 103 performs control for enabling the isolation to the subsystem 106 via the power control signal 1 (S6). As an example of a method for notifying the power supply control unit 103 of the start of the power shutdown sequence, the register interface described above can be considered as in the power recovery sequence.

  When the isolation activation is completed, the power supply control unit 103 notifies the reset supply unit 101 of the completion of the isolation activation via the sequence state notification interface, and the reset supply unit 101 enables the reset 1 for the subsystem 106 ( S7).

  When the reset 1 validation is completed, the reset supply unit 101 notifies the power control unit 103 of the completion of the reset 1 validation, and the power control unit 103 disables the power switch for the subsystem 106 via the power control signal 1. Then, the power is shut off (S8).

  When the power of the subsystem 106 is cut off, the power supply control unit 103 notifies the CPU 105 of the completion of the power cut-off sequence (S9). As a method for notifying the CPU 105 of the completion of the power shutdown sequence, the method using the above-described interrupt signal or the method of polling the status register provided in the power control unit 103 may be used.

  Thus, the power-off sequence of the sub-system 106 is completed, and the sub-system 106 enters a state where the power is cut-off (S0).

  Note that the sequences described with reference to FIGS. 5 and 6 are examples, and the execution order of the steps may be switched within a range in which the power-off recovery can be realized without destabilizing the circuit operation.

  A detailed sequence of the reset sequence (S2) upon power recovery will be described with reference to the flowchart shown in FIG. For ease of explanation, the case where the subsystem 106 is reset will be described below.

  The power supply control unit 103 notifies the reset supply unit 101 that power supply to the subsystem 106 has been completed via the sequence state notification interface (S20). The reset supply unit 101 validates the reset 1 supplied to the subsystem 106 (S21). However, if the reset 1 is already in a valid state at the start of the reset sequence, an operation for maintaining the valid state is performed in S21. The clock supply unit 102 is notified by the reset supply unit 101 that the reset sequence has started, and changes the frequency division ratio so that the frequency of the clock 1 of the subsystem 106 that is the power return target is appropriate for reset execution (S22). ). The reset supply unit 101 validates the clock enable for the clock 1, and the clock supply unit 102 outputs the clock 1 for a period during which the clock enable is valid (S23). When the clock supply is completed and the subsystem 106 is reset, the reset supply unit 101 invalidates the reset 1 (S24). After the reset 1 becomes invalid, the reset supply unit 101 enables the clock enable for the clock 1 again, and the clock supply unit 102 outputs the clock 1 while the clock enable is valid (S25). The clock supply is completed, and all the circuits inside the subsystem 106 are in a reset release state. The clock supply unit 102 is notified by the reset supply unit 101 that the reset release has been completed, and restores the division ratio of the clock 1 to the state before the start of the reset sequence (S26). The reset supply unit 101 notifies the power supply control unit 103 that the reset sequence has been completed via the sequence state notification interface (S27). The reset sequence execution (S2) is thus completed.

  The detailed operations of the reset supply unit 101 and the clock supply unit 102 during power-on reset will be described with reference to FIG.

  At time T0, the external reset transitions from the L level to the H level. Here, the external reset is an L level active (low active) signal. In the initial state, it is assumed that the low frequency clock of the OSC 1021 is selected and output from the clock MUX 1023 to the clock 6. At time T1, the power-on reset reset sequencer 1011 starts a power-on reset sequence triggered by the transition of the external reset to the H level. A preset count value is set in a reset counter included in the power-on reset reset sequencer 1011 to start down-counting. The power-on reset reset sequencer 1011 controls the reset signal and the clock enable signal based on the count value of the reset counter. In this embodiment, the reset signal, the clock enable signal, and the clock signal are controlled in the reset sequence. However, the present invention is not limited to these signals. In recent years, it has become necessary to perform a repair operation on a failed SRAM in order to improve chip yield. Since this repair operation is performed as part of the reset sequence, a signal related to the repair operation is also a target signal.

  When the power-on reset sequence is started, the power-on-reset reset sequencer 1011 indicates L level in the power-on-reset reset control signals 1 and 2. Since the reset control signal selection units 1013 and 1014 are not in the power shutdown return sequence, they select the power-on reset reset control signals 1 and 2 and output them to the reset control signals 1 and 2. However, since all the reset signals are at the L level in the initial state, the reset control signals 1 and 2 for power-on reset do not affect the reset signal at time T1.

  From time T6 to T10, the power-on-reset reset sequencer 1011 enables the power-on-reset clock enables 1 and 2 for a fixed period. All are enabled from clock enable 1 to clock enable 5, all clocks pass through the clock gating unit 1028, and clocks 1 to 5 are output. During this period, all clocks output 3 pulse clocks, and the reset target circuit is in a reset state.

  At time T11, the power-on-reset reset sequencer 1011 indicates the power-on-reset reset control signal 2 at H level. At this time, the power-on reset reset control signal 1 does not indicate H level. At time T12, all resets other than reset 4 are disabled. However, at this time, the reset release state does not reach all the circuits within the reset target block.

  From time T13 to T17, the power-on-reset reset sequencer 1011 enables the power-on-reset clock enable 2 for a fixed period. All clock enables other than clock enable 4 are valid, and all clocks other than clock 4 pass through clock gating unit 1028 and are output. During this period, all the clocks other than the clock 4 output 3 pulse clocks, and all the functional blocks other than the CPU 105 are in the reset release state.

  At time T18, the power-on reset reset sequencer 1011 indicates the power-on reset reset control signal 1 at H level. At time T19, the reset 4 is disabled. When the reset 4 becomes invalid, the clock control unit 1024 enables the clock enable 10 so that the clock supply unit 102 outputs the clock 4 and the CPU 105 can operate.

  The detailed operation of the reset supply unit 101 and the clock supply unit 102 in the reset sequence execution (S2) in the normal operation mode in which the clock MUX 1023 selects the output clock of the PLL 1022 will be described with reference to FIG. In FIG. 9, a case where a reset sequence is executed for the subsystem 106 will be described.

  The subsystem 106 is in a state where power is supplied from the power-off state at time T0. At the start of the reset sequence, the reset 1 supplied to the subsystem 106 is valid, the clock 1 is stopped, and the clock enable 1 is invalid. The clock MUX 1023 selects the high frequency clock output from the PLL 1022 and outputs it to the clock 6. At time T0, the power supply control unit 103 notifies the reset supply unit 101 that power supply to the subsystem 106 has been completed via the sequence state notification interface. At time T1, the reset supply unit 101 starts a reset sequence for the subsystem 106. A preset count value is set in a reset counter included in the power shut-off reset sequencer 1012 to start down-counting. The power shutdown reset sequencer 1012 controls the reset signal and the clock enable signal based on the count value of the reset counter. When the reset sequence is started, the power shutdown reset sequencer 1012 indicates the L level in the power shutdown reset control signals 1 and 2. The reset control signal selection unit 1013 selects the power cutoff reset control signal 2 and outputs it to the reset control signal 1 because the subsystem 106 is a block for power cutoff in the power recovery sequence. However, since reset 1 is already in the valid state, reset 1 maintains the valid state. On the other hand, the reset control signal selection unit 1014 selects the power-on reset reset control signal 2 and outputs it to the reset control signal 2 because the subsystem 107 is not a power-off block, and the reset 2 remains invalid. Become. Further, although the power cutoff reset control signal 1 also shows an L level, the power cutoff reset control signal 1 is an unconnected signal and does not affect any other signals.

  The clock division setting unit 1025 is notified from the power shutdown reset sequencer 1012 that the reset sequence has been started via the sequence state notification interface, and changes the clock division ratio at time T5. The clock frequency division setting unit 1025 determines the frequency division ratio so that the clock 1 has an optimum number of pulses for executing the synchronous reset during the period when the clock enable 1 is valid. In the clock MUX 1023, since the high frequency clock of the PLL 1022 is selected, in this embodiment, the division by 4 is selected to supply 3 pulses during the clock enable valid period, and the frequency is divided by 4 from the clock dividing unit 1026 for the clock 1. Clock is output.

  From time T6 to T10, the power shutdown reset sequencer 1012 enables the clock enable 1 for a fixed period. The clock enable 1 passes through the clock gating unit 1028 for the clock 1 during the valid period, and the clock 1 is output. During this period, the clock 1 outputs a three-pulse clock, and the subsystem 106 is reset. Rather than outputting the PLL 1022 high-frequency clock as it is, by outputting the clock divided by 4 as the clock 1, an effect of power saving can be obtained. Furthermore, it is possible to avoid impairing the processing performance of the information processing apparatus 10 as a whole by not affecting the clocks 2 to 5.

  At time T11, the power shutdown reset sequencer 1012 indicates the H level by the power shutdown reset control signal 2. Reset 1 is disabled at time T12. However, at this time, the reset release state does not reach all the circuits in the subsystem 106. In this embodiment, it is assumed that a clock of three pulses or more is required after the reset becomes invalid until all the circuits are in the reset release state.

  From time T13 to T17, the power shutdown reset sequencer 1012 enables the clock enable 1 again for a fixed period. The clock enable 1 passes through the clock gating unit 1028 for the clock 1 during the valid period, and the clock 1 is output. During this period, the clock 1 outputs a 3-pulse clock, and all the circuits of the subsystem 106 are in a reset release state.

  The clock frequency division setting unit 1025 is notified from the power shutdown reset sequencer 1012 that the reset release has been completed via the sequence state notification interface, and restores the clock frequency division ratio at time T18. At time T20, the power shutdown reset sequencer 1012 notifies the power control unit 103 of the completion of the reset sequence via the sequence state notification interface, and the reset sequence execution (S2) is completed.

  The detailed operations of the reset supply unit 101 and the clock supply unit 102 in the reset sequence execution (S2) in the low-speed operation mode in which the clock MUX 1023 selects the output clock of the OSC 1021 will be described with reference to FIG. In FIG. 10, the same operation as in FIG. 9 is performed except for the initial state of the clock 6 and the operation of changing the frequency division ratio at time T5.

  At time T0, the clock MUX 1023 selects the low frequency clock output from the OSC 1021 and outputs it to the clock 6.

  At time T5, the clock frequency division setting unit 1025 is notified from the power shutdown reset sequencer 1012 that the reset sequence has been started via the sequence state notification interface, and changes the clock frequency division ratio. Since the low-frequency clock of the OSC 1021 is selected in the clock MUX 1023, the clock divider 1026 outputs the clock 6 without dividing the clock 6 before the clock gating (divided by 1). When the low frequency clock of the OSC 1021 is selected, the clock 1 is generated without frequency division, so that 3 pulses necessary for the synchronous reset can be secured during the period when the reset 1 is valid, and the reset is executed reliably. Is possible.

  At time T18, the clock frequency division setting unit 1025 is notified from the power shutdown reset sequencer 1012 that the reset release has been completed via the sequence state notification interface, and restores the clock frequency division ratio. However, since the frequency division ratio was not changed at time T5, the frequency division ratio is maintained at 1 at the time T18 as it is.

  The described embodiments are provided in order to briefly explain the principle and actual application examples of the present invention so that others skilled in the art can understand the present invention. Other embodiments with various modifications may be suitable for a particular application, but are within the scope of the present invention.

  For example, in this embodiment, the clock frequency division setting unit 1025 monitors the selection signal to the clock MUX 1023, but the setting value of the PLL 1022 may also be monitored. By monitoring the setting value of the PLL 1022, it is possible to set an optimum frequency dividing ratio following the change in the frequency of the PLL 1022.

  As described above, according to the present embodiment, the automatic clock division ratio is set according to the operation mode of the system without affecting the performance of the circuits other than the reset target, and the reset is performed while suppressing the power consumption. It is possible to reliably reset the target circuit.

10 Information processing device 20 DRAM
DESCRIPTION OF SYMBOLS 30 Reset synchronizer 31 Flip-flop 32 AND circuit 101 Reset supply part 102 Clock supply part 103 Power supply control part 104 Bus system 105 CPU
106 subsystem 107 subsystem 108 memory controller 109 clock enable 301 flip-flop 302 flip-flop 1011 power-on reset reset sequencer 1012 power-off reset sequencer 1013 reset control signal selection unit 1014 reset control signal selection unit 1015 clock enable selection unit 1016 clock Enable selection unit 1017 Reset holding unit 1021 OSC
1022 PLL
1023 Clock MUX
1024 clock control unit 1025 clock division setting unit 1026 clock division unit 1027 OR circuit 1028 clock gating unit

Claims (8)

A synchronous reset circuit that generates a clock and a reset signal and resets a target circuit to an initial state,
Reset supply means for individually enabling reset signals of individual reset target circuits in the chip for a fixed period; and
The clock signal corresponding to the reset target circuit to which the valid reset signal is connected is supplied to the individual reset target circuit, and the reset target circuit is connected to the reset target circuit during a fixed period in which the reset signal is valid. A clock supply means for changing the frequency so as to output an appropriate number of pulses for resetting,
A synchronous reset circuit comprising: The clock supply means includes
Clock selection means for selecting one from a plurality of clock sources;
Clock dividing means for individually dividing the clock source selected by the clock selecting means and outputting it as the clock signal supplied to the individual reset target circuits;
The synchronous reset circuit according to claim 1, comprising:   3. The synchronous reset circuit according to claim 2, wherein the frequency of the clock signal corresponding to a reset target circuit for which the reset signal is not valid is maintained. The clock supply means has a fixed period during which the reset signal is valid.
A frequency dividing ratio of the clock frequency dividing means for dividing the clock signal corresponding to the reset target circuit to which the valid reset signal is connected is determined according to the frequency of the clock source selected by the clock selecting means. 4. The synchronous reset circuit according to claim 3, wherein:   5. The synchronous reset circuit according to claim 4, wherein the frequency division ratio is a ratio that the clock signal has a pulse number necessary for resetting the reset target circuit during a fixed period in which the reset signal is valid. The reset supply means generates a clock enable signal corresponding to the individual clock signals, enables the clock enable signal for a fixed period during a period when the reset signal is valid,
The synchronous reset circuit according to claim 4, wherein the clock supply unit validates the clock signal corresponding to a fixed period in which the clock enable signal is valid.   7. The synchronous reset circuit according to claim 6, wherein the division ratio is a ratio that the clock signal has a pulse number necessary for resetting the reset target circuit during a fixed period in which the clock enable signal is valid. A method of controlling a synchronous reset circuit that generates a clock and a reset signal to reset a target circuit to an initial state,
A reset supply step for individually enabling reset signals of individual reset target circuits in the chip for a fixed period; and
The clock signal corresponding to the reset target circuit to which the valid reset signal is connected is supplied to the individual reset target circuit, and the reset target circuit is connected to the reset target circuit during a fixed period in which the reset signal is valid. And a clock supply step for changing the frequency so as to output a pulse number appropriate for resetting the signal.

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