JP2019022049A - Signal processor - Google Patents

Abstract

To finely adjust the position on the time axis of sound data without deteriorating the sound quality.SOLUTION: A signal processor 12 includes a parallel/serial conversion circuit 22_n for converting first parallel sound data Ya_n (n=1 to N) including sample data composed of a plurality of bits for each first period into second serial sound data Yb_n in which each of the plurality of bits is arranged for each second period shorter than the first period, a delay circuit 23_n for delaying the second sound data Yb_n by a delay time in a unit of the second period, and a D/A conversion circuit 24_n for converting the second sound data Yb_n delayed by the delay circuit 23_n into an analog acoustic signal Z_n.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a technique for processing digital data representing sound (hereinafter referred to as “sound data”).

  2. Description of the Related Art Conventionally, signal processing apparatuses that process sound data representing various sounds such as voice or musical sound have been proposed. For example, in the sound signal processing apparatus disclosed in Patent Document 1, a word clock that defines the period of each sample data constituting sound data is transmitted together with the sound data.

JP 2017-17368 A

  For example, in an acoustic system installed in an acoustic hall or the like, it is important to finely adjust the phase of sound data between a plurality of channels. In the prior art including Patent Document 1, the delay time given to the sound data is limited to the time length in units of the word clock cycle. Therefore, it is difficult to finely adjust the phase (ie, delay time) of the sound data. In addition, the structure which delays sound data only for the time shorter than the period of a word clock by performing the interpolation process (resampling) between the several sample data succeeding in sound data is also assumed. However, there is a problem that sound quality deteriorates due to the interpolation processing. In view of the above circumstances, a preferred aspect of the present invention aims to finely adjust the position of sound data on the time axis without deteriorating sound quality.

In order to solve the above-described problems, a signal processing device according to a preferred aspect of the present invention provides parallel-format first sound data including sample data composed of a plurality of bits for each first period. A parallel / serial conversion circuit for converting each bit into second sound data in a serial format arranged every second period shorter than the first period, and the second sound data for a delay time in units of the second period And a D / A conversion circuit that converts the second sound data delayed by the delay circuit into an analog acoustic signal. In the above aspect, the first sound data in the parallel format is converted into the second sound data in the serial format, and the second time is the delay time in units of the second period in which the respective bits of the converted second sound data are arranged. Sound data is delayed. That is, the position of the second sound data on the time axis is adjusted in units of time shorter than the first period without executing interpolation processing (resampling). Therefore, it is possible to finely adjust the position of the second sound data on the time axis without deteriorating the sound quality of the reproduced sound.
A signal processing device according to another aspect of the present invention provides first sound data in parallel format including sample data composed of a plurality of bits for each first period, and each of the plurality of bits is more than in the first period. An output device including a parallel / serial conversion circuit for converting the second sound data in the serial format arranged every short second period, and a delay circuit for delaying the second sound data, to the output device after the conversion by the parallel / serial conversion circuit. A connection terminal for outputting second sound data; and a control unit for instructing the delay circuit of a variable delay time in units of the second period. In the above aspect, the first sound data in the parallel format is converted into the second sound data in the serial format, and the second time is the delay time in units of the second period in which the respective bits of the converted second sound data are arranged. Sound data is delayed. That is, the position of the second sound data on the time axis is adjusted in units of time shorter than the first period without executing interpolation processing (resampling). Therefore, it is possible to finely adjust the position of the second sound data on the time axis without deteriorating the sound quality of the reproduced sound.

1 is a block diagram showing a configuration of an acoustic system according to a first embodiment of the present invention. It is explanatory drawing of operation | movement of a parallel / serial conversion circuit and a delay circuit. It is a block diagram which shows the structure of a delay circuit. It is a schematic diagram of a reference table. It is a flowchart of a delay control process. It is a flowchart of a prior measurement process. It is a block diagram which shows the scene which performs a prior measurement process. It is a block diagram which shows the structure of the acoustic system which concerns on 2nd Embodiment. It is a schematic diagram of the reference table in 3rd Embodiment. It is a flowchart of the prior measurement process in 3rd Embodiment. It is a block diagram which shows the scene which performs the prior measurement process of 3rd Embodiment. It is a block diagram which shows the structure of the acoustic system in a modification. It is a block diagram which shows the aspect of the connection of the output device in a modification.

<First Embodiment>
FIG. 1 is a block diagram showing a configuration of an acoustic system 100 according to the first embodiment of the present invention. The acoustic system 100 of the first embodiment is a multi-channel audio system that reproduces various sounds such as musical sounds or voices. As illustrated in FIG. 1, the acoustic system 100 includes a signal supply device 11, a signal processing device 12, and N output devices 13_1 to 13_N (N is a natural number of 2 or more). Any two or more elements of the acoustic system 100 may be integrally configured. For example, the signal supply device 11 and the signal processing device 12 may be configured integrally.

  The signal supply device 11 is a signal source that supplies M-channel sound data X_1 to X_M representing various sounds such as voice or music to the signal processing device 12 (M is a natural number). For example, a reproduction apparatus that reads out sound data X_1 to X_M from a portable or built-in recording medium is a suitable example of the signal supply apparatus 11. Further, a communication device that receives sound data X_1 to X_M from another device such as a music distribution server via a communication network may be used as the signal supply device 11.

  The signal processing device 12 generates N-channel analog acoustic signals Z_1 to Z_N from the M-channel sound data X_1 to X_M supplied from the signal supply device 11. The signal processing device 12 includes N connection terminals C_1 to C_N corresponding to different channels. The output device 13_n is detachably connected to each connection terminal_n (n = 1 to N). An arbitrary one-channel acoustic signal Z_n generated by the signal processing device 12 is supplied to the output device 13_n via the connection terminal C_n. The difference between the number M of input channels and the number N of output channels of the signal processing device 12 is not questioned.

  Each output device 13_n of the first embodiment includes an amplifying device 14_n and a sound emitting device 15_n. Each amplification device 14_n amplifies and outputs the acoustic signal Z_n. For example, an amplifier having an arbitrary configuration such as a class A amplifier, a class B amplifier, or a class D amplifier is used as the amplification device 14_n. The sound emitting device 15_n is, for example, a speaker or a headphone, and reproduces the sound represented by the acoustic signal Z_n after being amplified by the amplifying device 14_n. The amplifying device 14_n and the sound emitting device 15_n may be configured integrally or may be configured separately. A line array speaker installed in an acoustic space such as an acoustic hall is constituted by the N sound emitting devices 15_1 to 15_N.

  As illustrated in FIG. 1, the signal processing device 12 includes an acoustic processing device 20 and a control unit 30. The acoustic processing device 20 generates N-channel acoustic signals Z_1 to Z_N from the M-channel sound data X_1 to X_M supplied from the signal supply device 11. The sound processing device 20 according to the first embodiment includes a processing circuit 21 and N unit circuits U_1 to U_N. Note that the processing circuit 21 and the N unit circuits U_1 to U_N may be configured separately.

  The processing circuit 21 is a digital signal processing circuit (DSP) that generates N-channel digital sound data Ya_1 to Ya_N from M-channel sound data X_1 to X_M. Specifically, the processing circuit 21 executes various acoustic processes such as a process for adjusting the localization of the sound image of the reproduced sound and a process for adjusting the frequency characteristic of the reproduced sound, whereby the M-channel sound data X_1. N channel sound data Ya_1 to Ya_N are generated from .about.X_M. An arbitrary unit circuit U_n is supplied with sound data Ya_n of the nth channel generated by the processing circuit 21.

  Each unit circuit U_n generates an analog acoustic signal Z_n from the sound data Ya_n. As illustrated in FIG. 1, the unit circuit U_n of the first embodiment includes a parallel / serial conversion circuit 22_n (PSC: Parallel-to-Serial Converter), a delay circuit 23_n, and a D / A conversion circuit 24_n (DAC: Digital- to-Analog Converter).

  The parallel / serial conversion circuit 22_n converts the sound data Ya_n (example of the first sound data) supplied from the processing circuit 21 in a parallel format into sound data Yb_n (example of the second sound data) in the serial format. As illustrated in FIG. 2, the sound data Ya_n is digital data in parallel format including sample data S composed of K bits B_1 to B_K for each period T1 (illustrated in the first period). In other words, K bits B_1 to B_K constituting one sample data S of the sound data Ya_n are supplied in parallel to the parallel / serial conversion circuit 22_n of the unit circuit U_n in every cycle T1. The period T1 corresponds to one period of the word clock. A plurality of sample data S may be included in the cycle T1.

  As illustrated in FIG. 2, the sound data Yb_n is a bit string in which each of the K bits B_1 to B_K of the sample data S is arranged in time series for each period T2. The period T2 is shorter than the period T1. Specifically, the period T2 is a time length corresponding to 1 / N of the period T1 (that is, one period of the bit clock). The sound data Yb_n output from the parallel / serial conversion circuit 22_n of each unit circuit U_n is supplied to the delay circuit 23_n of the unit circuit U_n.

  The delay circuit 23_n of FIG. 1 delays the sound data Yb_n supplied from the parallel / serial conversion circuit 22_n by a delay time τ_n. As illustrated in FIG. 2, the delay time τ_n is set to a time length with the period T2 as a unit. That is, the delay time τ_n is a time length that is an integral multiple of the period T2. The delay time τ_n is set to a time length shorter than the period T1. Note that the delay time τ_n may be the sum of a time length that is an integral multiple of the period T1 and a time length that is an integral multiple of the period T2.

  FIG. 3 is a block diagram showing a specific configuration of the delay circuit 23_n. As illustrated in FIG. 3, the delay circuit 23 — n according to the first embodiment includes a plurality of delay devices D and a selection circuit 231. The plurality of delay devices D are connected to each other in series. Each bit B_k (k = 1 to K) of the sound data Yb_n output from the parallel / serial conversion circuit 22_n is sequentially supplied to the first-stage delay device D in the cycle T2, and the second and subsequent stages are supplied. Each delay unit D is supplied with a bit B_k delayed by the preceding stage delay unit D. Each delay unit D delays the sequentially supplied bits B_k by a time corresponding to the period T2, and outputs the result.

  The selection circuit 231 selects one of the plurality of delay devices D. A time series of bits B_k sequentially output from one delay device D selected by the selection circuit 231 is output to the D / A conversion circuit 24_n as delayed sound data Yb_n. Therefore, the delay time τ_n given to the sound data Yb_n is variably controlled according to which delay device D the selection circuit 231 selects. As described above, the delay time of one delay device D corresponds to the period T2. Therefore, the variable delay time τ_n with the period T2 as a unit is given to the sound data Yb_n by the delay circuit 23_n. FIG. 2 illustrates a case where the delay circuit 23_n delays the sound data Yb_n by a delay time τ_n corresponding to two periods T2.

  The D / A conversion circuit 24 in FIG. 1 converts the sound data Yb_n delayed by the delay circuit 23_n into an analog acoustic signal Z_n. The acoustic signal Z_n converted by the D / A conversion circuit 24_n is supplied to the amplifying device 14_n through the connection terminal C_n. Various types of output devices can be selectively connected to each connection terminal C_n.

  A control unit 30 (an example of a control unit) in FIG. 1 is a controller that controls the sound processing device 20, and includes a control device 31 and a storage device 32. The control device 31 is an arithmetic processing circuit such as a CPU (Central Processing Unit), for example, and controls each element of the sound processing device 20 by executing a program stored in the storage device 32. The storage device 32 stores a program executed by the control device 31 and various data used by the control device 31. For example, a known recording medium such as a semiconductor recording medium or a magnetic recording medium, or a combination of a plurality of types of recording media is a suitable example of the storage device 32.

  The control device 31 of the first embodiment instructs the delay time τ_n (τ_1 to τ_N) to each of the plurality of delay circuits 23_n of the sound processing device 20. The delay circuit 23_n of each unit circuit U_n delays the sound data Yb_n by the delay time τ_n instructed from the control device 31. For the setting of each delay time τ_n by the control device 31, the reference table R of FIG. 4 stored in the storage device 32 is used.

  As illustrated in FIG. 4, the reference table R of the first embodiment is a data table in which delay times t0 (t0_a, t0_b,...) Are registered for each type of output device that can be connected to the connection terminal C_n. Specifically, the delay time t0 is stored for each combination of the type of the amplifying device and the type of the sound emitting device. The delay time t0 is a time length that is a candidate for the delay time τ_n given to the sound data Yb_n. Accordingly, the delay time t0 is set to a time length with the period T2 as a unit (that is, a time length that is an integral multiple of the period T2). The control device 31 searches the reference table R for a delay time t0 corresponding to the type of the output device 13 actually connected to the connection terminal C_n, and sets the delay time t0 as the delay time τ_n to the delay circuit 23_n of the unit circuit U_n. Instruct. The delay circuit 23_n delays the sound data Yb_n by the delay time τ_n instructed from the control device 31.

  The delay time from when the supply of the acoustic signal Z_n to the output device 13_n is started until the output device 13_n actually starts sound emission according to the acoustic signal Z_n depends on the type (configuration or type) of the output device 13_n. Can be different. Therefore, in the reference table R of the first embodiment, the delay time from the start of the supply of the sound data Ya_n to the unit circuit U_n until the output device 13_n starts emitting sound according to the sound data Ya_n is a predetermined target value. Delay time t0 is set for each type of output device. For example, the longer the delay time, the shorter the delay time t0 is set. Therefore, it is possible to match the timing of sound emission by each output device 13_n with high accuracy for the N channel.

  FIG. 5 is a flowchart of a process in which the control device 31 controls the delay time τ_n of each unit circuit U_n (hereinafter referred to as “delay control process”). For example, the delay control process of FIG. 5 is started when the signal processing device 12 is turned on or instructed by the user.

  When the delay control process is started, the control device 31 specifies the type of the output device 13_n (specifically, the type of the amplification device 14_n and the type of the sound emitting device 15_n) for each of the N channels (Sa1). The method for specifying the type of the output device 13_n is arbitrary. For example, a method for acquiring information on the type of the output device 13_n through communication with the output device 13_n (each of the amplifier device 14_n and the sound emitting device 15_n), or A method of specifying the type of the output device 13_n from information input by the user can be employed.

  The control device 31 searches the reference table R for each of the N channels for the delay time t0 corresponding to the type specified for the output device 13_n (Sa2). Then, the control device 31 instructs each delay circuit 23_n as the delay time τ_n of the channel, using the delay time t0 searched for each channel from the reference table R (Sa3). Each delay circuit 23_n delays the sound data Yb_n by the delay time τ_n instructed from the control device 31.

  Prior to the delay control process described above, the control device 31 executes a process of creating a reference table R (hereinafter referred to as “preliminary measurement process”). FIG. 6 is a flowchart of the preliminary measurement process, and FIG. 7 is an explanatory diagram of the preliminary measurement process. As illustrated in FIG. 7, the pre-measurement process is executed in a state where N sound collection devices 18_1 to 18_N corresponding to the N sound emission devices 15_1 to 15_N are installed. The distance δ between the output device 13_n (sound emitting device 15_n) and the sound collecting device 18_n is common to the N channels.

  In the state of FIG. 7, the control device 31 supplies digital data (hereinafter referred to as “measurement data”) Q representing sound for pre-measurement to the N unit circuits U_1 to U_N of the sound processing device 20 in common. (Sb1). The unit circuit U_n generates and outputs an acoustic signal Z_n from the measurement data Q, and the output device 13_n reproduces a sound corresponding to the acoustic signal Z_n. Each sound collection device 18_n collects the reproduced sound from the output device 13_n, and generates a sound collection signal P_n representing the reproduced sound. The control device 31 acquires N channel sound pickup signals P_1 to P_N via the unit circuit U_n and the output device 13_n (Sb2).

  The control device 31 compares the phases of the N channel sound pickup signals P_1 to P_N with each other, so that the delay time from the supply of the sound data Ya_n to the unit circuit U_n to the sound emission by the output device 13_n is predetermined over the N channel. The delay time t0 is set for each channel so as to be the target value (Sb3). That is, the delay time t0 of each channel is set so that the difference in delay time over N channels is reduced. The control device 31 identifies the type of the output device 13_n connected to each connection terminal C_n of the sound processing device 20, and registers the correspondence between the type of the output device 13_n and the delay time t0 in the reference table R for each of the N channels. (Sb4). Note that the type of each output device 13_n is specified from, for example, information obtainable from the output device 13_n or information input by the user.

  As understood from the above description, in the first embodiment, the unit of the cycle T2 in which the parallel-format sound data Ya_n is converted into the serial-format sound data Yb_n and the bits B_k of the converted sound data Yb_n are arranged. The sound data Yb_n is delayed by the delay time τ_n. That is, the position on the time axis of the sound data Yb_n is adjusted in units of time shorter than the cycle T1 without executing interpolation processing (resampling). Therefore, the position of the sound data Yb_n on the time axis can be finely adjusted without deteriorating the sound quality of the reproduced sound.

  Particularly in the first embodiment, the delay time τ_n of the delay circuit 23_n is changed according to an instruction from the control device 31. Therefore, there is an advantage that the influence of the delay characteristic (latency) of the output device 13_n connected to the connection terminal C_n can be reduced. For example, as illustrated in the first embodiment, it is possible to match the timing of the reproduced sound of each acoustic signal Z_n over N channels.

Second Embodiment
A second embodiment of the present invention will be described. In addition, about the element which an effect | action or function is the same as that of 1st Embodiment in each form illustrated below, the code | symbol used by description of 1st Embodiment is diverted, and each detailed description is abbreviate | omitted suitably.

  FIG. 8 is a block diagram illustrating a configuration of the acoustic system 100 according to the second embodiment. The acoustic system 100 according to the second embodiment is different from the first embodiment in the configuration of the unit circuit U_n and the output device 13_n.

  As illustrated in FIG. 8, each of the N unit circuits U_1 to U_N in the second embodiment includes a parallel / serial conversion circuit 22_n (PSC). The delay circuit 23_n and the D / A conversion circuit 24_n exemplified in the first embodiment are not included in the unit circuit U_n of the second embodiment. Similarly to the first embodiment, the parallel / serial conversion circuit 22_n converts the sound data Ya_n (example of the first sound data) supplied from the processing circuit 21 in the parallel format into the serial format sound data Yb_n (the second sound data). To (example). The sound data Yb_n converted by the parallel / serial conversion circuit 22_n is supplied to the output device 13_n through the connection terminal C_n.

  As illustrated in FIG. 8, each of the N output devices 13_1 to 13_N in the second embodiment includes a delay circuit 23_n, a D / A conversion circuit 24_n, an amplifier device 14_n, and a sound emitting device 15_n. Note that two or more elements of the output device 13_n may be configured integrally. For example, the delay circuit 23_n, the D / A conversion circuit 24_n, and the amplification device 14_n are configured as an integrated device (signal receiver).

  Similarly to the first embodiment, the delay circuit 23_n delays the sound data Yb_n supplied from the connection terminal C_n by the delay time τ_n. The specific configuration of the delay circuit 23_n is, for example, the configuration described above with reference to FIG. Also in the second embodiment, the delay time τ_n of the delay circuit 23_n is set to a time length in units of the cycle T2 (that is, a time length that is an integral multiple of the cycle T2). Therefore, in the second embodiment, as in the first embodiment, the position of the sound data Yb_n on the time axis can be finely adjusted without deteriorating the sound quality of the reproduced sound.

  Similarly to the first embodiment, the D / A conversion circuit 24_n converts the sound data Yb_n delayed by the delay circuit 23_n into an analog acoustic signal Z_n. Similarly to the first embodiment, the amplifying device 14_n amplifies the acoustic signal Z_n, and the sound emitting device 15_n reproduces the sound represented by the amplified acoustic signal Z_n.

  As in the first embodiment, the control device 31 according to the second embodiment includes an arithmetic processing circuit 21 such as a CPU. The control device 31 of the second embodiment instructs the delay time τ_n to the delay circuit 23_n in each of the N output devices 13_1 to 13_N. Each delay circuit 23_n delays the sound data Yb_n by the delay time τ_n instructed from the control device 31. Therefore, the second embodiment also has an advantage that the influence of the delay characteristic of the output device 13_n connected to the connection terminal C_n can be reduced as in the first embodiment.

  As in the first embodiment, the reference table R of FIG. 4 stored in the storage device 32 is used for setting each delay time τ_n by the control device 31. The contents of the delay control process (FIG. 5) in which the control device 31 sets the delay time τ_n of each delay circuit 23_n and the pre-measurement process (FIG. 6) in which the control device 31 creates the reference table R are the first embodiment. It is the same.

<Third Embodiment>
FIG. 9 is a schematic diagram of a reference table R used by the control device 31 of the third embodiment for setting the delay time τ_n (delay control process). In the third embodiment, a delay time from when the supply of the acoustic signal Z_n to the sound emitting device 15_n is started until the sound emitting device 15_n actually starts sound emission according to the sound signal Z_n (that is, the sound emitting device). 15_n delay time) is assumed to be the same over N sound emitting devices 15_1 to 15_N. On the other hand, the delay time of amplification by the amplification device 14_n may be different for each of the N amplification devices 14_1 to 14_N. Considering the above circumstances, the reference table R of the third embodiment has a delay time t0 (t0_a, t0_b,...) For each type of amplifier that can be connected between the connection terminal C_n and the sound emitting device 15_n. It is a registered data table. Similarly to the first embodiment, the delay time t0 is a time length that is a candidate for the delay time τ_n, and is set to a time length with the period T2 as a unit (that is, a time length that is an integral multiple of the period T2).

  The configuration of each unit circuit U_n and each output device 13_n of the third embodiment is the same as that of the first embodiment or the second embodiment. The control device 31 according to the third embodiment searches the reference table R for the delay time t0 corresponding to the type of the amplification device 14_n, and sets the delay time t0 as the delay time τ_n in the delay circuit 23_n.

  FIG. 10 is a flowchart of a pre-measurement process in which the control device 31 of the third embodiment creates the reference table R, and FIG. 11 is an explanatory diagram of the pre-measurement process. As illustrated in FIG. 11, the pre-measurement process is executed in a state where the output terminals of the N amplifiers 14 </ b> _ <b> 1 to 14 </ b> _N are connected to the control unit 30.

  In the state of FIG. 11, as illustrated in FIG. 10, the control device 31 supplies the measurement data Q representing the pre-measurement sound to the N unit circuits U_1 to U_N of the sound processing device 20 in common. (Sc1). By supplying the measurement data Q, the acoustic signal Z_n is output from each unit circuit U_n to the amplification device 14_n, and the amplified acoustic signal Z_n is output from each amplification device 14_n. The control device 31 acquires the N-channel acoustic signals Z_1 to Z_N output from the amplification device 14_n (Sc2).

  The control device 31 compares the phases of the N-channel acoustic signals Z_1 to Z_N with each other, so that the delay time from the supply of the sound data Ya_n to the unit circuit U_n to the output of the acoustic signal Z_n by the amplifying device 14_n extends over the N channels. A delay time t0 is set for each channel so as to be a predetermined target value (Sc3). Then, the control device 31 specifies the type of each amplification device 14_n, and registers the correspondence between the type of the amplification device 14_n and the delay time t0 in the reference table R for each of the N channels (Sc4). Note that the type of each amplifying device 14_n is specified from, for example, information obtainable from the amplifying device 14_n or information input by the user.

<Modification>
The embodiment illustrated above can be variously modified. Specific modifications are exemplified below. Two or more aspects arbitrarily selected from the following examples may be merged.

(1) In the first embodiment, the unit circuit U_n exemplifies a configuration including the delay circuit 23_n and the D / A conversion circuit 24_n. In the second embodiment, the output device 13_n includes the delay circuit 23_n and the D / A conversion. Although the configuration including the circuit 24_n has been illustrated, the first embodiment and the second embodiment may be merged. Specifically, as illustrated in FIG. 12, for the N1 channel (N1 <N) of the N channels, the delay circuit 23_n and the D / A conversion circuit 24_n are connected to the unit circuit U_n as in the first embodiment. Mounted on. On the other hand, for the remaining N2 channels (N2 = N−N1) among the N channels, the delay circuit 23_n and the D / A conversion circuit 24_n are mounted on the output device 13_n, as in the second embodiment. Also in the above configuration, the same effect as that of the first embodiment or the second embodiment is realized.

(2) In the pre-measurement process of the first embodiment, N sound collecting devices 18_1 to 18_N respectively corresponding to the N sound emitting devices 15_1 to 15_N are installed. The method of recording the signals P_1 to P_N is not limited to the above examples. For example, the N channel sound collecting signals P_1 to P_N may be recorded by sequentially moving one sound collecting device 18 to a position corresponding to each of the N sound emitting devices 15_1 to 15_N. That is, the process of arranging the sound collection device 18 at a position δ from the sound emission device 15_n and recording the sound collection signal P_n is sequentially executed in a time division manner for each of the N sound emission devices 15_1 to 15_N. .

(3) In each of the above-described embodiments, the case where the timing of sound emission by each output device 13_n is matched by adjusting the delay time τ_n is exemplified, but the relationship of the timing of sound emission by each output device 13_n is illustrated above. It is not limited to. For example, the delay time τ_n of the delay circuit 23_n may be set for each channel so that the sound emission timings of the N output devices 13_1 to 13_N are different by a predetermined time. According to the above configuration, by adjusting the delay time τ_n of each delay circuit 23_n, for example, the direction in which sound waves radiated from the entire N output devices 13_1 to 13_N are propagated (that is, in the acoustic space). Sound field control).

(4) In each of the above-described embodiments, one output device 13_n is connected to the connection terminal C_n for each channel, but a plurality of output devices 13_n can be installed for each channel. For example, as illustrated in FIG. 13, three output devices 13_n (13_n1, 13_n2, 13_n3) are connected to the connection terminal C_n. Each output device 13_n of FIG. 13 includes a delay circuit 23_n, a D / A conversion circuit 24_n, an amplifier device 14_n, and a sound emitting device 15_n, as illustrated in the second embodiment. The input terminal of the delay circuit 23_n1 of the output device 13_n1 is connected to the connection terminal C_n. The input terminal of the delay circuit 23_n2 of the output device 13_n2 is connected to, for example, the output terminal of the delay circuit 23_n1 of the output device 13_n1, and the input terminal of the delay circuit 23_n3 of the output device 13_n3 is, for example, the output terminal of the delay circuit 23_n2 of the output device 13_n2 Connected to. The delay time τ_n of each delay circuit 23_n (13_n1, 13_n2, 13_n3) is variably set according to an instruction from the control device 31. In the configuration of FIG. 13, the same effects as those of the above-described embodiments are realized.

DESCRIPTION OF SYMBOLS 100 ... Acoustic system, 11 ... Signal supply apparatus, 12 ... Signal processing apparatus, 13_n (13_1-13_N) ... Output apparatus, 14_n (14_1-14_N) ... Amplification apparatus, 15_n (15_1-15_N) ... Sound emission apparatus, 21 ... Processing circuit, U_n (U_1 to U_N) ... Unit circuit, 22_n (22_1 to 22_N) ... Parallel / serial conversion circuit, 23_n (23_1 to 23_N) ... Delay circuit, 24_n (24_1 to 24_N) ... D / A conversion circuit, 30 ... Control unit, 31 ... Control device, 32 ... Storage device.

Claims (5)

A second serial-type sound data in which sample data composed of a plurality of bits is included in each first period, and each of the plurality of bits is arranged in a second period shorter than the first period. A parallel / serial conversion circuit for converting to sound data;
A delay circuit for delaying the second sound data by a delay time in units of the second period;
A signal processing apparatus comprising: a D / A conversion circuit that converts the second sound data delayed by the delay circuit into an analog acoustic signal. The signal processing apparatus according to claim 1, further comprising: a control unit that instructs the delay circuit of a variable delay time in units of the second period. The signal processing device according to claim 1, further comprising: a connection terminal for outputting an acoustic signal converted by the D / A conversion circuit to an output device. A second serial-type sound data in which sample data composed of a plurality of bits is included in each first period, and each of the plurality of bits is arranged in a second period shorter than the first period. A parallel / serial conversion circuit for converting to sound data;
A connection terminal for outputting the second sound data converted by the parallel / serial conversion circuit to an output device including a delay circuit for delaying the second sound data;
And a control unit that instructs the delay circuit of a variable delay time in units of the second period. 5. The signal processing device according to claim 3, wherein the control unit instructs the delay circuit of a delay time corresponding to a type of the output device.

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