JP2019021680A - Semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress damage to a semiconductor element due to thermal expansion. A method for manufacturing a semiconductor device includes a step of joining a first conductor plate to a lower surface electrode of a semiconductor element via a first bonding material and a second conductor to the upper surface electrode of the semiconductor element via a second bonding material. It includes a step of joining the plates. The area of the first bonding region where the first conductor plate is bonded to the bottom electrode via the first bonding material is the second bonding region where the second conductor plate is bonded to the second conductor plate via the second bonding material. Greater than The semiconductor element is subjected to an annealing step of irradiating the bottom electrode with a laser. In the annealing step, the first region of the semiconductor element is irradiated with a laser having the first intensity, while the second region surrounding the first region of the semiconductor element is subjected to a second intensity weaker than the first intensity. Irradiate the laser to have. Alternatively, the second region is not irradiated with the laser. The boundary between the first region and the second region is located closer to the center than the outer peripheral edge of the second junction region in a plan view. [Selection diagram] Fig. 4

Description

  The technology disclosed in this specification relates to a method for manufacturing a semiconductor device.

  Patent Document 1 discloses a semiconductor device. This semiconductor device includes a semiconductor element having an upper surface electrode and a lower surface electrode, a first conductor plate bonded to the lower surface electrode via a first bonding material, and a second bonded to the upper surface electrode via a second bonding material. A conductor plate is provided. This type of semiconductor device is used in combination with a cooler in order to suppress the temperature rise of the semiconductor device because the semiconductor elements and the like generate heat when energized. Therefore, when energization and interruption of the semiconductor device are repeated, the temperature of the semiconductor device also fluctuates up and down in synchronization with it, and the semiconductor device alternately repeats thermal expansion and thermal contraction.

JP 2016-46497 A

  In the semiconductor device described above, the area of the first bonding region where the first conductor plate is bonded to the lower surface electrode via the first bonding material is equal to the area of the first bonding region where the second conductor plate is bonded to the upper surface electrode via the second bonding material. The area is larger than the area of the second junction region, and the structure is asymmetrical above and below the semiconductor element. With such a structure, the thermal expansion occurring in the semiconductor device is also asymmetrical above and below the semiconductor element, so that when the temperature of the semiconductor device fluctuates, the semiconductor element may be deformed to warp. Such deformation locally increases the stress generated in the semiconductor element, and can cause damage to the semiconductor element such as generation of cracks.

  In view of the above, this specification provides a technique capable of suppressing damage to a semiconductor element due to thermal expansion of a semiconductor device.

  The inventor has analyzed the deformation and stress generated in the semiconductor element, and obtained the following knowledge. When a current flows through the semiconductor device, each component of the semiconductor device including each conductor plate is thermally expanded, and each bonding material positioned above and below the semiconductor element moves toward the outer periphery. When such thermal expansion is repeated, the movement of the second bonding material positioned on the upper side of the semiconductor element is restricted by the molding resin or the like positioned around the semiconductor element. Move downwards. As a result, the outer peripheral portion of the semiconductor element is pressed downward by the second bonding material and displaced downward. Under the influence, in the first bonding material located on the lower side of the semiconductor element, the movement toward the outer peripheral side is limited (or pushed back toward the center side), so the central part of the semiconductor element is The first bonding material is pressed and displaced upward. As described above, the outer peripheral portion of the semiconductor element is pushed and displaced, while the central portion of the semiconductor element is pushed and displaced. As a result, in the semiconductor element, a relatively large tensile stress can be generated in a region between the outer peripheral portion that is displaced downward and the central portion that is displaced upward.

  From the above knowledge, it has been found that the region where damage is likely to occur in the semiconductor element is a region between the outer peripheral portion and the central portion where large tensile stress can occur. Therefore, in order to suppress damage to the semiconductor element, it is effective to increase the strength of the semiconductor element at least in a region between the outer peripheral portion and the central portion. For this reason, the present technology has focused on annealing. In general, in the manufacture of a semiconductor device, an annealing process is performed on a semiconductor element after forming an electrode in order to form a good ohmic contact between a semiconductor substrate and the electrode. However, the annealing process for heating the semiconductor element has a secondary effect of reducing the strength of the semiconductor element. In this regard, if laser annealing is used to locally heat a semiconductor element using a laser, the presence / absence or degree of annealing treatment is selectively determined by distinguishing the area where the intensity of the semiconductor element is required from other areas. Can be changed. That is, in a region where a large tensile stress can occur, the strength of the semiconductor element can be maintained by omitting the annealing treatment or relaxing the degree thereof. On the other hand, in a region where a large tensile stress cannot be generated, a satisfactory ohmic contact can be formed between the semiconductor substrate and the electrode by performing sufficient annealing.

  Based on the above-described technique, this specification provides a method for manufacturing a semiconductor device. The manufacturing method includes a step of preparing a semiconductor element having an upper surface electrode and a lower surface electrode, a step of bonding a first conductor plate to the lower surface electrode via a first bonding material, and a second bonding material to the upper surface electrode. Joining the second conductor plate. The area of the first joining region where the first conductor plate is joined to the lower electrode via the first joining material is the second joining region where the second conductor plate is joined to the second conductor plate via the second joining material. Bigger than. The step of preparing the semiconductor element includes an annealing step of irradiating the lower surface electrode of the semiconductor element with laser. In this annealing step, the first region of the lower electrode is irradiated with a laser having the first intensity, while the second region surrounding the first region of the lower electrode has a second intensity lower than the first intensity. Irradiation with a laser having Alternatively, the second region is not irradiated with a laser. Here, the boundary between the first region and the second region is located closer to the center than the outer peripheral edge of the second bonding region in plan view.

  In the manufacturing method described above, in the step of preparing the semiconductor element, an annealing process for irradiating the lower surface electrode of the semiconductor element with laser is performed. In this annealing step, the first region of the lower electrode is irradiated with a laser having the first intensity, while the second region surrounding the first region of the lower electrode has a second intensity lower than the first intensity. Irradiation with a laser having Alternatively, the second region is not irradiated with a laser. As a result, in the second region of the semiconductor element, the strength decrease due to the annealing process does not occur or the degree thereof is small, and the mechanical strength of the semiconductor element is maintained. Here, the second region is a region surrounding the first region, and the boundary between the first region and the second region is arranged closer to the center than the outer periphery of the second bonding region in plan view. Due to such a relationship, the second region includes a region where a large tensile stress can occur in the semiconductor element (that is, the region between the outer peripheral portion and the central portion described above). Since the strength of the semiconductor element is maintained in a region where a large tensile stress can occur, damage to the semiconductor element is suppressed. On the other hand, in the first region including the central portion of the semiconductor element, the generated tensile stress is relatively small, so that the annealing process can be sufficiently performed, and a good ohmic contact is provided between the semiconductor substrate and the electrode. Can be formed.

The top view of the semiconductor device 10 of an Example is shown. FIG. 2 is a cross-sectional view taken along line II-II in FIG. 1 and shows a cross-sectional structure of a semiconductor device 10. The deformation | transformation accompanying the temperature fluctuation of the semiconductor device 10 is shown typically. The analysis result of the tensile stress which arises in the semiconductor element 12 is shown. (A) is a cross-sectional view of the semiconductor device 10, (B) is a graph showing the tensile stress generated in the semiconductor element 12 at a low temperature, and (C) is a plan view of the semiconductor element 12 viewed from the lower surface electrode 16 side. is there. It is an example of setting the first region R1 and the second region R2 in the annealing process, (A) shows an example in which the first region R1 is set to the maximum, and (B) shows an example in which the first region R1 is set to the minimum. Show.

  With reference to the drawings, a semiconductor device 10 of an embodiment and a manufacturing method thereof will be described. As shown in FIG. 1, the semiconductor device 10 includes a semiconductor element 12, a lower surface side conductor plate 18, an upper surface side conductor plate 20, a conductor spacer 22, and a mold resin 24. The semiconductor element 12 is sealed in the mold resin 24. The mold resin 24 is made of an insulating material. Although not particularly limited, the material constituting the mold resin 24 may be a thermosetting resin material such as an epoxy resin.

  The semiconductor element 12 includes an upper surface electrode 14 and a lower surface electrode 16. The upper surface electrode 14 is located on the upper surface 12 a of the semiconductor element 12, and the lower surface electrode 16 is located on the lower surface 12 b of the semiconductor element 12. The specific type and structure of the semiconductor element 12 are not particularly limited. The semiconductor element 12 may be a power semiconductor element such as a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) or an IGBT (Insulated Gate Bipolar Transistor). The semiconductor element 12 can be configured using various semiconductor materials such as silicon (Si), silicon carbide (SiC), or gallium nitride (GaN). Although it does not specifically limit to the material which comprises the upper surface electrode 14 and the lower surface electrode 16, For example, aluminum type or another metal is employable.

  The lower surface side conductor plate 18 is a generally plate-shaped member, and has an upper surface 18a and a lower surface 18b located on the opposite side of the upper surface 18a. The upper surface 18 a of the lower surface side conductor plate 18 is joined to the lower surface electrode 16 of the semiconductor element 12 via the solder 26 inside the mold resin 24. Thereby, the lower surface side conductor plate 18 is electrically connected to the semiconductor element 12. Here, the lower surface side conductor plate 18 is an example of a first conductor plate in the technology disclosed in this specification, and the solder 26 is an example of a first bonding material in the technology disclosed in this specification. The lower surface side conductor plate 18 (that is, an example of the first conductor plate) can be configured by using a conductive material such as copper or another metal. Further, the lower conductor plate 18 and the semiconductor element 12 are not limited to the solder 26 and may be joined by other joining materials.

  The conductor spacer 22 is a generally plate-shaped or block-shaped member, and has an upper surface 22a and a lower surface 22b located on the opposite side of the upper surface 22a. The conductor spacer 22 is located in the mold resin 24. The lower surface 22 b of the conductor spacer 22 is joined to the upper surface electrode 14 of the semiconductor element 12 via the solder 28. Thereby, the upper surface electrode 14 of the semiconductor element 12 is electrically connected to the conductor spacer 22. The conductor spacer 22 is an example of a second conductor plate in the technology disclosed in this specification, and the solder 28 is an example of a second bonding material in the technology disclosed in this specification. The conductor spacer 22 (that is, an example of the second conductor plate) can be configured using a conductive material such as copper or another metal. Further, the conductor spacer 22 and the semiconductor element 12 are not limited to the solder 28 and may be joined by other joining materials.

  Similar to the lower surface side conductor plate 18, the upper surface side conductor plate 20 is also a generally plate-shaped member, and has an upper surface 20a and a lower surface 20b located on the opposite side of the upper surface 20a. The lower surface 20 b of the upper surface side conductor plate 20 is joined to the upper surface 22 a of the conductor spacer 22 via the solder 30 inside the mold resin 24. Thereby, the upper surface side conductor plate 20 is electrically connected to the conductor spacer 22, and is electrically connected to the semiconductor element 12 through the conductor spacer 22. The upper surface side conductor plate 20 can be configured using a conductive material such as copper or other metal.

  The lower surface 18 b of the lower surface side conductor plate 18 is exposed to the outside of the mold resin 24. The lower surface side conductor plate 18 is also thermally connected to the semiconductor element 12 and functions as a heat radiating plate that releases heat generated in the semiconductor element 12 to the outside. Similarly, the upper surface 20 a of the upper surface side conductor plate 20 is exposed to the outside of the mold resin 24. The upper surface side conductor plate 20 is also thermally connected to the semiconductor element 12 through the conductor spacer 22 and functions as a heat radiating plate that releases heat generated in the semiconductor element 12 to the outside. That is, the semiconductor device 10 of this embodiment has a double-sided cooling structure in which the heat sink is exposed on both sides of the mold resin 24.

  The semiconductor device 10 of the present embodiment is used in combination with a cooler (not shown) in order to suppress the temperature rise of the semiconductor device 10 because the semiconductor element 12 and the like generate heat when energized. Accordingly, when energization and interruption of the semiconductor device 10 are repeated, the temperature of the semiconductor device 10 also fluctuates up and down in synchronization therewith, and the semiconductor device 10 alternately repeats thermal expansion and thermal contraction. Here, the region where the lower surface side conductor plate 18 (that is, an example of the first conductor plate) is bonded to the lower surface electrode 16 of the semiconductor element 12 via the solder 26 (that is, an example of the first bonding material) One junction region C1 is assumed. Further, a region where the conductor spacer 22 (that is an example of the second conductor plate) is bonded to the upper surface electrode 14 of the semiconductor element 12 via the solder 28 (that is, an example of the second bonding material) is referred to as a second bonding region. Let C2. Comparing the areas of both, the area of the first junction region C1 is larger than the area of the second junction region C2, and the structure of the semiconductor device 10 is asymmetrical above and below the semiconductor element 12. With such a structure, since the thermal expansion occurring in the semiconductor device 10 is also asymmetrical above and below the semiconductor element 12, when the temperature of the semiconductor device 10 fluctuates as shown in FIG. May deform to warp. Such deformation locally increases the stress generated in the semiconductor element 12, and may cause damage to the semiconductor element 12 such as generation of cracks.

  Here, FIG. 3 (X) shows a state when the temperature of the semiconductor device 10 is increased, and FIG. 3 (Y) shows a state when the temperature of the semiconductor device 10 is decreased. As described above, when the temperature of the semiconductor device 10 fluctuates, the semiconductor device 10 is deformed so that the semiconductor element 12 is warped or deformed so that the warpage is returned. However, the direction in which the temperature changes (that is, rise or fall) and the direction of the warp that occurs in the semiconductor element 12 are not limited to the mode illustrated in FIG. 3, but the specific structure of the semiconductor device 10 and the industrial product Various changes may be made according to individual differences.

  The inventor has analyzed the deformation and stress generated in the semiconductor element, and obtained the following knowledge. When a current flows through the semiconductor device 10, the components of the semiconductor device 10 including the lower surface side conductor plate 18 and the conductor block 22 thermally expand, and the solders 26 and 28 positioned above and below the semiconductor element 12 move toward the outer periphery. To do. When such thermal expansion is repeated, the movement of the solder 28 positioned on the upper side of the semiconductor element 12 is restricted by the molding resin 24 positioned around the semiconductor element 12, so that the semiconductor element 12 having a relatively low rigidity. (See arrow S2 in FIG. 3Y). As a result, the outer peripheral portion A2 of the semiconductor element 12 is pressed by the solder 28 and displaced downward. Under the influence, the solder 26 positioned on the lower side of the semiconductor element 12 is limited in movement toward the outer peripheral side (or is pushed back toward the center side), so that the central portion A1 of the semiconductor element 12 is Then, it is pressed by the solder 26 and displaced upward (see arrow S1 in FIG. 3 (Y)). As described above, the outer peripheral portion of the semiconductor element 12 is pushed and displaced while the central portion of the semiconductor element is pushed and displaced. As a result, in the semiconductor element, a relatively large tensile stress can be generated in a region between the outer peripheral portion that is displaced downward and the central portion that is displaced upward.

  FIG. 4 shows the result of obtaining the tensile stress generated in the semiconductor element 12 by CAE (Computer Aided Engineering) analysis. FIG. 4 (B) shows the tensile stress (at low temperature) generated in the semiconductor element 12 for each number of power cycles (1000 times, 2000 times, 3000 times) that repeats energization and its stop, and FIG. (C) is a sectional view schematically showing a position where the tensile stress is generated, and a plan view of the lower surface electrode 16. As understood from FIG. 4, a relatively large tensile stress is generated in a region A <b> 3 between the outer peripheral portion A <b> 2 that is displaced downward of the semiconductor element 12 and the central portion A <b> 1 that is displaced upward. It can also be seen that stress is relatively difficult to occur in the central portion A1 of the semiconductor element.

  As described above, it can be seen that the region where damage is likely to occur in the semiconductor element 12 is a region where a large tensile stress can occur, that is, the region A3 between the outer peripheral portion A2 and the central portion A1. Therefore, in order to suppress damage to the semiconductor element 12, it is effective to increase the strength of the semiconductor element 12 at least in the region A3 between the outer peripheral portion A2 and the central portion A1. Therefore, the present technology focuses on the annealing process of the semiconductor element 12. Generally, in the manufacturing process of the semiconductor element 12, after the upper surface electrode 14 and the lower surface electrode 16 are formed in order to form a good ohmic contact between the upper surface electrode 14 and the lower surface electrode 16 and the semiconductor substrate (not shown). An annealing process is performed on the semiconductor element 12. The annealing process for heating the semiconductor element 12 has a secondary effect of reducing the strength of the semiconductor element 12. In this regard, if laser annealing is used to locally heat the semiconductor element 12 using a laser, the region where the strength of the semiconductor element 12 is required is distinguished from other regions, and the presence or absence or degree of annealing treatment is determined. It can be changed selectively. That is, in the region A3 where a large tensile stress can occur, the strength of the semiconductor element 12 can be maintained by omitting the annealing process or relaxing the degree thereof. On the other hand, in the region A1 where a large tensile stress cannot occur, a satisfactory ohmic contact can be formed between the upper surface electrode 14 and the lower surface electrode 16 and the semiconductor substrate by sufficiently performing the annealing treatment.

  Based on the above technique, a manufacturing method applied to the semiconductor device 10 of this embodiment will be described. This manufacturing method includes a step of preparing the semiconductor element 12 having the upper surface electrode 14 and the lower surface electrode 16, a step of bonding the lower surface side conductor plate 18 to the lower surface electrode 16 via the solder 26, and solder 28 to the upper surface electrode 14. And a step of joining the conductor spacers 22 to each other. As described above, the area of the first bonding region C1 where the lower surface side conductor plate 18 is bonded to the lower surface electrode 16 via the solder 26 is the second area where the conductor spacer 22 is bonded to the conductive spacer 22 via the solder 28. It is larger than the joining region C2. The step of preparing the semiconductor element 12 includes an annealing step of irradiating the semiconductor element 12 with a laser. In this annealing step, as shown in FIG. 5, the first region R1 of the semiconductor element 12 is irradiated with a laser having the first intensity, while the second region R2 surrounding the first region R1 of the semiconductor element 12 is irradiated on the second region R1. Irradiate a laser having a second intensity that is weaker than the first intensity. Alternatively, the second region R2 is not irradiated with a laser. Here, the boundary BL between the first region R1 and the second region R2 is located closer to the center than the outer peripheral edge of the second bonding region C2 in plan view.

  In the manufacturing method described above, in the step of preparing the semiconductor element 12, an annealing process is performed in which the lower surface electrode 16 of the semiconductor element 12 is irradiated with a laser. In this annealing step, first, the first region R1 of the lower electrode 16 is irradiated with a laser having a first intensity. On the other hand, the second region R2 surrounding the first region R1 of the lower surface electrode 16 is irradiated with a laser having a second intensity that is weaker than the first intensity. Alternatively, the second region R2 is not irradiated with a laser. As a result, in the second region R2 of the semiconductor element 12, the strength decrease due to the annealing process does not occur or the degree thereof is small, and the mechanical strength of the semiconductor element is maintained. Here, the second region R2 is a region surrounding the first region R1, and the boundary BL between the first region R1 and the second region R2 is closer to the center than the outer peripheral edge of the second bonding region C2 in plan view. Be placed. Due to such a relationship, in the second region R2, a region where a large tensile stress (especially the maximum tensile stress) can occur in the semiconductor element 12 (that is, the region A3 between the outer peripheral portion A2 and the central portion A1 described above). ) Is included. Since the strength of the semiconductor element is maintained in a region where a large tensile stress can occur, damage to the semiconductor element is suppressed. On the other hand, in the first region R1 including the central portion of the semiconductor element, the generated tensile stress is relatively small, so that the annealing process can be sufficiently performed, and the gap between the semiconductor substrate and each of the electrodes 14 and 16 is achieved. A good ohmic contact can be formed.

  Here, the position of the boundary BL between the first region R1 and the second region R2 can be variously determined according to the configuration of the semiconductor device 10, the analysis result of the tensile stress, and the like. In the example shown in FIG. 5A, the first region R1 that is irradiated with the laser having the first intensity (that is, the strong intensity) is enlarged to the maximum corresponding to the outer peripheral edge of the second bonding region C2. Has been. In this case, the first region R1 is substantially equal to the size of the outer shape of the conductor spacer 22. On the other hand, in the example shown in FIG. 5B, the first region R1 is set to be relatively narrow. Specifically, the size of the first region R1 is half the size of the outer shape of the conductor spacer 22. Is set to If the first region R1 to be sufficiently annealed is set to a size of at least one half of the outer shape of the conductor spacer 22, it is necessary between the semiconductor substrate and each of the electrodes 14 and 16. The ohmic contact property can be ensured.

  Several specific examples have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above. The technical elements described in the present specification or drawings exhibit technical usefulness alone or in various combinations.

10: Semiconductor element 12: Semiconductor element 12a: Upper surface 12b of semiconductor element: Lower surface 14 of semiconductor element: Upper surface electrode 16: Lower surface electrode 18: Lower surface side conductor plate (an example of a first conductor plate)
18a: Upper surface 18b of the lower surface side conductor plate: Lower surface 20 of the lower surface side conductor plate 20: Upper surface side conductor plate 20a: Upper surface 20b of the upper surface side conductor plate 22: Lower surface 22 of the upper surface side conductor plate: Conductor spacer
22a: Conductor spacer upper surface 22b: Conductor spacer lower surface 24: Mold resin 26: Solder (an example of a first bonding material)
28: Solder (an example of a second bonding material)
30: Solder

Claims (1)

A method for manufacturing a semiconductor device, comprising:
Preparing a semiconductor element having a top electrode and a bottom electrode;
Bonding a first conductor plate to the lower surface electrode via a first bonding material;
Bonding a second conductor plate to the upper surface electrode via a second bonding material;
With
The area of the first bonding region where the first conductor plate is bonded to the lower surface electrode via the first bonding material is such that the second conductor plate is bonded to the upper surface electrode via the second bonding material. Larger than the area of the second junction region,
The step of preparing the semiconductor element includes an annealing step of irradiating a laser to the lower surface electrode of the semiconductor element,
In the annealing step, the first region of the bottom electrode is irradiated with a laser having a first intensity, while the second region surrounding the first region of the bottom electrode is weaker than the first strength. Irradiating a laser having a second intensity or not irradiating a laser;
The boundary between the first region and the second region is located closer to the center than the outer periphery of the second bonding region in plan view.
A method for manufacturing a semiconductor device.

Images