JP2019008854A - Semiconductor memory device and method for writing to semiconductor memory device - Google Patents

Abstract

To provide a semiconductor storage device and a writing method to a semiconductor storage device in which an error at the time of reading out data from a memory cell is suppressed even if an environmental condition changes, compared to a case where the write voltage is not corrected.SOLUTION: A semiconductor storage device comprises: a memory cell array composed of a plurality of memory cells; and a cell voltage generation unit that includes a high voltage generation unit which boosts a power supply voltage to generate a high voltage which is a cell voltage to be applied to each of the plurality of memory cells, a correction current generation unit which generates a correction current for correcting change of the cell voltage with respect to ambient temperature, and a control signal generation unit which compares a detected voltage obtained by converting the high voltage into current with the target current maintaining the high voltage at the target voltage to generate a control signal controlling a boosting operation in the high voltage generation unit, and adds a reference current which is the target current corresponding to the room temperature and the correction current to obtain the target current.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a semiconductor memory device and a method for writing to the semiconductor memory device, and more particularly to a semiconductor memory device for controlling a read current so as to suppress an error caused by a read current from a memory cell and a method for writing to the semiconductor memory device. .

  Conventionally, Patent Document 1 is known as a document related to current control. A semiconductor integrated circuit disclosed in Patent Document 1 includes a first current control oscillation circuit that outputs an oscillation signal having a first frequency obtained by integrating a first gain to a first control current, a first control voltage, and a first reference voltage. A first voltage-current conversion circuit for adding a first output current obtained by integrating the second gain to the voltage difference to the first control current; a first reference current circuit for adding a constant current to the first control current; and a variable second output. A current output circuit for applying a current to the first control current.

  Patent Document 2 is also known. The PLL circuit disclosed in Patent Document 2 includes a phase comparator that generates a phase error voltage by comparing the phase of an input signal and the phase of a feedback signal, and a filter output voltage by removing a harmonic component of the phase error voltage. A loop filter for generating a current, a voltage-current conversion circuit for converting the filter output voltage into a phase error current, a bias current generating means for generating a bias current, and a control current by adding the phase error current and the bias current Includes an adder that generates a current control oscillator, a current control oscillator that generates an oscillation output signal in accordance with the control current, and a counter that generates a feedback signal in accordance with the oscillation output signal.

By the way, in a nonvolatile semiconductor memory device, for example, a flash memory, since a relatively large voltage is required for writing, a portion (cell voltage generation unit) for generating a high writing voltage is generally provided. An example of the cell voltage generation unit will be described with reference to FIG.
FIG. 11 is a block diagram showing a cell voltage generator 90 included in the semiconductor memory device according to the comparative example. As shown in FIG. 11, the cell voltage generation unit 90 includes a high voltage generation unit 92, a high voltage level detection unit 94, a high voltage level determination unit 96, a reference current generation unit 98, and a high voltage output unit 99. .

  The high voltage generation unit 92 includes a charge pump unit (not shown) for generating an output voltage VH that is a high voltage corresponding to a predetermined write voltage. The high voltage level detector 94 detects the level of the generated output voltage VH and outputs it as a detection current Idtc. The high voltage level determination unit 96 compares the detection current Idtc with the reference current Iref generated by the reference current generation unit 98, and generates a CPUMP control signal CPUMPEN for controlling the high voltage generation unit 92. The CPUMP control signal CPUMPEN stops the operation of the charge pump unit of the high voltage generator 92 when the detection current Idtc becomes equal to or higher than the reference current Iref, and generates a high voltage when the detection current Idtc becomes less than the reference current Iref. This signal restarts the operation of the charge pump unit of the unit 92.

  The graph of FIG. 12A shows the relationship between the detection current Idtc of the cell voltage generation unit 90 and the output voltage VH with a curve C2. That is, FIG. 12A shows the relationship between the output voltage VH on the horizontal axis and the detected current Idtc on the vertical axis and the position of the reference current Iref. As shown in FIG. 12A, by the operation of the cell voltage generation unit 90, the VH at the intersection P3 between the reference current Iref and the detection current Idtc is the cell voltage (write voltage, hereinafter referred to as “write voltage”). VHO is sometimes referred to as “target voltage”. As is clear from FIG. 12A, the target voltage shifts to the high voltage side when the reference current Iref is increased from the characteristics of the detection current Idtc with respect to the output voltage VH.

JP 2003-209440 A Japanese Patent Laid-Open No. 10-84278

  The output voltage VH0 (target voltage) becomes the write voltage VW, and this output voltage VH0 is applied to the source line of the memory cell array for writing. The write voltage VW varies due to temperature variation characteristics of the memory cell and the cell voltage generation unit. FIG. 12B shows the dependency of the current (read current, expressed as “cell current” in FIG. 12B) flowing in the memory cell at the time of reading after writing data 0 on the write voltage VW. As shown in FIG. 12B, the dependence of the cell current on the write voltage when the ambient temperature is room temperature in the semiconductor memory device according to the comparative example has a characteristic indicated by a solid curve C3 as an example. When data “0” is written to the memory cell, for example, when the write voltage VW1 is about 7.5 V, the cell current can be reduced to about 1 n (nano) A (intersection P4 in FIG. 12B). ).

However, when the ambient temperature rises from room temperature to a high temperature, the dependency of the cell current on the write voltage shifts in a direction in which the write voltage and the cell current increase as shown by a curve C4 indicated by a broken line.
Then, as indicated by <1> in FIG. 12B, the cell current increases to about 4 nA (intersection P5 in FIG. 12B). On the other hand, the output voltage VH of the cell voltage generation unit 90 may also vary depending on the temperature. For example, as shown in <2> of FIG. 12B, the output voltage VH drops to about 7.4 V (intersection of FIG. 12B). P6). In other words, even if the write voltage VW is set to the optimum value of 7.5 V at room temperature, the actual write voltage VW is VW2≈7.4 V, and the cell current temperature variation characteristic is also added, so that the cell current reaches about 10 nA. To increase. As a result, there is a concern that an error (an error in outputting data “0” as “1”) may occur due to the current of 10 nA flowing during reading.

  As is common in the past, if the rewriting requirement specification is a rewriting within a narrow temperature range, for example, in a factory, it will not be a problem, but in recent years, rewriting by, for example, end users over a wide range of temperature conditions has become the mainstream. As a result, the above phenomenon may become a problem. That is, even if the rewrite setting is optimized under the room temperature condition, the cell current for the same write voltage VW increases or the output voltage VH of the cell voltage generation unit 90 changes under the high temperature condition. As a result, an unexpected cell current flows at the time of reading, which may cause deterioration of read characteristics (read data error).

  In this regard, current correction is also performed in Patent Document 1 or Patent Document 2, but Patent Document 1 and Patent Document 2 are not concerned with the read current in the semiconductor memory device.

  In view of the above problems, the present invention provides a semiconductor memory device in which errors in reading data from a memory cell are suppressed even when environmental conditions change compared to a case where correction of a write voltage is not performed. It is another object of the present invention to provide a method for writing to a semiconductor memory device.

  A semiconductor memory device according to the present invention includes a memory cell array composed of a plurality of memory cells, and a high voltage generation for generating a high voltage that is a voltage applied to each of the plurality of memory cells by boosting a power supply voltage. A correction current generation unit that generates a correction current for correcting a variation of the cell voltage with respect to an ambient temperature, a detection current obtained by converting the high voltage into a current, and a target current that maintains the high voltage at a target voltage And a control signal for controlling the step-up operation in the high voltage generator is generated, and the reference current that is the target current corresponding to room temperature and the correction current are added to obtain the target current. A cell voltage generation unit including a signal generation unit.

  On the other hand, the writing method to the semiconductor memory device according to the present invention is a field effect transistor type memory cell having a floating gate, and has the same configuration as the memory cell and is used for correcting the writing voltage when writing to the memory cell. In a semiconductor memory device including a dummy cell unit and a high voltage generation unit that boosts a power supply voltage to generate a high voltage that is the write voltage, a read current when predetermined data is written to the memory cell is A method for writing to a semiconductor memory device that performs writing while correcting fluctuations in the write voltage due to a change in ambient temperature so as to be equal to a read current at room temperature, the memory cell and the dummy cell unit when receiving a rewrite command And the predetermined data is written to the dummy cell portion, Reading out the predetermined data written in the data section to obtain a read current, generating a correction current based on the read current, converting the high voltage into a current, and the read current at room temperature Based on the comparison result obtained by comparing the reference current based on the reference value and the correction current, the boosting operation in the high voltage generation unit is controlled to obtain a corrected write voltage, and the memory is obtained by the corrected write voltage. The cell is written.

  According to the present invention, compared with the case where the write voltage is not corrected, the semiconductor memory device in which errors in reading data from the memory cell are suppressed even when the environmental condition changes, and the writing to the semiconductor memory device It becomes possible to provide a method.

It is a block diagram which shows an example of a structure of the semiconductor memory device containing the cell voltage generation part which concerns on embodiment. It is a block diagram which shows an example of a structure of the cell voltage generation part which concerns on embodiment. (A) of the cell voltage generation part which concerns on embodiment is a circuit diagram which shows an example of a high voltage level detection part and a high voltage level determination part, (b) is a circuit diagram which shows an example of a high voltage output part. It is a block diagram which shows an example of the dummy cell current generation part of the cell voltage generation part which concerns on embodiment. (A) is a flowchart showing a write procedure to the semiconductor memory device according to the embodiment, (b) is a diagram showing the relationship between the control signal and the voltage applied to each terminal. It is a circuit diagram which shows a part of VWL control circuit which concerns on embodiment. (A), (b) is a circuit diagram which shows a part of VWL control circuit which concerns on embodiment. (A), (b) is a circuit diagram which shows an example of the VSL control circuit which concerns on embodiment. It is a circuit diagram which shows an example of the current mirror circuit which concerns on embodiment. 5 is a graph for explaining correction of a write voltage in the semiconductor memory device according to the embodiment. It is a block diagram which shows the cell voltage generation part which concerns on a comparative example. (A) is a graph which shows the relationship between the detection current and output voltage which concern on a comparative example, (b) is a graph explaining the change resulting from the environmental condition of the cell current which concerns on a comparative example.

  DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments for carrying out the present invention will be described in detail with reference to the drawings. In the semiconductor memory device and the method for writing to the semiconductor memory device according to the present embodiment, in the semiconductor memory device including the high-voltage cell voltage generation unit that generates the write voltage, the variation due to the environmental condition of the write voltage is corrected. ing.

  FIG. 1 is a block diagram showing a schematic configuration of a semiconductor memory device (memory) 10 including a cell voltage generation unit 40 according to the present embodiment.

  In FIG. 1, a semiconductor memory device 10 is a nonvolatile memory such as a flash memory, and includes a memory cell array 1, a controller 2, a row driver 3, and a column driver 4. As an example, the memory cell according to the present embodiment includes a MOS FET (Metal Oxide Field Effect Transistor) having a floating gate, and a read current when data “0” is written is almost 0. (For example, 1 nA or less), and the read current when data “1” is written is about 15 μA. When data “0” is written, a high voltage (about 7.5 V in this embodiment) is applied to the source line of the memory cell array 1 to accumulate electrons in the floating gate, and when data “1” is written. do nothing.

  In the memory cell array 1, a plurality of bit lines and a plurality of word lines intersecting with each bit line are juxtaposed, and data is stored (written) at the intersections of these bit lines and word lines. ) Memory cells (not shown) are formed.

  In response to the read command or the write command, the controller 2 supplies address information indicating a read or write address to the row driver 3 and also supplies a write voltage or a read access signal to be applied to the memory cell to the column driver. 4 is supplied. Further, the controller 2 sends an erase signal ER, a dummy cell write signal DPG, and a memory cell write signal PGM to a dummy cell control unit 60 described later.

  The row driver 3 selects a pair of word lines formed in the memory cell array 1 according to a write or read access signal and address information supplied from the controller 2 and supplies a predetermined selection voltage. As a result, the memory cells connected to the pair of word lines to which the selection voltage is supplied become the target of data reading or writing.

  The column driver 4 applies a read voltage for reading data to the bit line of the memory cell array 1 in accordance with the read access signal supplied from the controller 2. The column driver 4 includes a cell voltage generation unit 40 that generates a high voltage for writing data to the memory cell. The column driver 4 generates a write voltage corresponding to the data based on the high voltage generated by the cell voltage generation unit 40 in accordance with the write access signal supplied from the controller 2, and uses this as the bit line of the memory cell array 1. And applied to each memory cell.

  Next, the configuration of the cell voltage generator 40 will be described with reference to FIG. As shown in FIG. 2, the cell voltage generation unit 40 includes a high voltage generation unit (CPUMP) 42, a high voltage level detection unit (DTEC) 44, a high voltage level determination unit (COMP) 46, and a reference current generation unit (REF). 48, a high voltage output unit 50, and a dummy cell current generation unit 52. In FIG. 2, an adder (not shown) is provided at a position where the reference current Iref and the dummy cell write current IrefP are merged. The high voltage level detection unit 44, the high voltage level determination unit 46, the reference current generation unit 48, and the addition unit constitute a “control signal generation unit” according to the present invention.

  The high voltage generator 42 is a circuit that generates a high output voltage VH that is a write voltage applied to each memory cell of the memory cell array 1. In this embodiment, a charge pump type voltage generation circuit is employed as an example, and the standard value of the write voltage VW is about 7.5V. The generated output voltage VH is taken out via a high voltage output unit 50 described later and applied to the word line of the memory cell array 1. The high voltage generator 42 receives a CPUMP control signal CPUMPEN, which will be described later. When the CPUMP control signal CPUMPEN is at a high level (hereinafter, “H”), the boost operation of the charge pump is stopped, and the low level (hereinafter, “L”). ), The boosting operation is resumed.

  The high voltage level detector 44 receives the output voltage VH of the high voltage generator 42 and outputs a current corresponding to the output voltage VH as a detection current Idtc.

  The high voltage level determination unit 46 receives the detection current Idtc, compares it with the reference current Iref, and generates a CPUMP control signal CPUMPEN that controls the operation of the high voltage generation unit 42 according to the comparison result.

  The reference current generation unit 48 generates a reference current Iref that serves as a reference for comparison with the detection current Idtc. As described in the description of FIG. 12A, the write voltage is basically determined by the reference current Iref.

  FIG. 3A is a circuit diagram for explaining more detailed configurations of the high voltage level detection unit 44 and the high voltage level determination unit 46. As shown in FIG. 3A, the high voltage level detection unit 44 includes n N-type MOS FETs (hereinafter, “NMOS transistors”) NM1, NM2,. A level detection circuit 74 made of NMn is included. The output voltage VH from the high voltage generator 42 is connected to the source of the NMOS transistor NM1 of the level detection circuit 74, and the detection current Idtc is output from the drain of the NMOS transistor NMn.

  Since each of the NMOS transistors constituting the level detection circuit 74 is connected to the gate and the source, a potential difference corresponding to the threshold voltage Vtn is generated between the gate and the drain of each NMOS transistor. Thus, when the output voltage VH becomes equal to or higher than (Vtn · n) V (volt), the detection current Idtc starts to flow. Conversely, the detection current Idtc does not flow while the output voltage VH is less than (Vtn · n) V. In other words, (Vtn · n) is a breakdown voltage with respect to the output voltage VH.

  On the other hand, the high voltage level determination unit 46 includes a current detection circuit 70 and a comparator 72.

  The current detection circuit 70 includes NMOS transistors TN1, TN2, TN3, and TN4, and P-type MOS FETs (hereinafter referred to as “PMOS transistors”) TP1 and TP2 serving as constant current sources. The detection current Idtc flows to the GND (ground) via the NMOS transistor TN1, and the reference current Iref input from the reference current generation unit 48 flows to the GND via the NMOS transistor TN4. Each of the detection current Idtc and the reference current Iref is converted into a voltage by the current detection circuit 70 and compared by the comparator 72.

  In the comparator 72, the CPUMP control signal CPUMPEN that is an output is set to H when the detection current Idtc is equal to or higher than the reference current Iref, and the CPUMP control signal CPUMPEN is set to L when the detection current Idtc is less than the reference current Iref. The Of course, the logic of the CPUMP control signal CPUMPEN is an example, and may be reversed.

  As shown in FIG. 2, the CPUMP control signal CPUMPEN is input to the high voltage generator 42. As described above, when the CPUMP control signal CPUMPEN is H, the boost operation of the charge pump is stopped, and the CPUMP control signal CPUMPEN is low. In this case, the boosting operation of the charge pump is resumed. In the cell voltage generation unit 40 according to the present embodiment, the operation of the charge pump is intermittently performed in this manner, thereby reducing the current consumption in the high voltage generation unit 42 that generally has a large current consumption. VH is maintained at the target voltage (set to a constant voltage).

  Referring again to FIG. 2, the high voltage output unit 50 is a buffer for outputting the output voltage VH to the memory cell array 1. FIG. 3B shows a circuit diagram of the high voltage output unit 50. As shown in FIG. 3B, the high voltage output unit 50 is an inverter composed of a PMOS transistor TP3 and an NMOS transistor TN5.

  As shown in FIG. 2, the output voltage VH output from the high voltage generation unit 42 is input to the dummy cell current generation unit 52 via the high voltage output unit 50. Note that the voltage input to the dummy cell current generation unit 52 does not have to be equal to the output voltage VH, and may be a voltage proportional to the output voltage VH, for example.

  The dummy cell current generation unit 52 is a part that acquires a dummy cell write current IrefP that is a correction value of the cell current at a high temperature in order to set the write voltage to the memory cell at the high temperature to an optimum value. As shown in FIG. 2, the dummy cell write current IrefP is combined (added) with the reference current Iref and input to the high voltage level determination unit 46. Therefore, when the dummy cell write current IrefP is output, the reference current shown in FIG. 3A increases from Iref to (Iref + IrefP), so that the output voltage VH output from the high voltage generator 42 increases.

  Next, the dummy cell current generation unit 52 will be described in more detail with reference to FIG. As shown in FIG. 4, the dummy cell current generation unit 52 includes a dummy cell control unit 60, a dummy cell unit 62, and a current mirror unit 64.

The dummy cell unit 62 is a dummy memory cell that is provided in addition to the original memory cell and is operated when acquiring the dummy cell write current IrefP that is a correction value of the cell current. The dummy cell unit 62 according to the present embodiment is configured by connecting a plurality of dummy cells DC in parallel. A word line terminal VWL (hereinafter referred to as “VWL terminal”) for applying a word line voltage (hereinafter referred to as <VWL>) from the dummy cell control unit 60 is connected to the common gate, and a dummy cell is connected to the common source. A source line terminal VSL (hereinafter referred to as “VSL” terminal) for applying a source line voltage (hereinafter referred to as <VSL>) from the control unit 60 is connected. On the other hand, a dummy bit line terminal DBL (hereinafter referred to as “DBL terminal”) for applying a dummy bit line voltage (hereinafter referred to as <DBL>) from the current mirror unit 64 is connected to the common drain. Note that the number of dummy cells DC connected in parallel may be selected in consideration of the accuracy at the time of acquiring the read current.
Further, a redundant cell (a memory cell provided for replacement with a defective cell) provided in the semiconductor memory device 10 may be used as the dummy cell DC.

  As shown in FIG. 4, the dummy cell control unit 60 includes a VWL control circuit 66 and a VSL control circuit 68. The dummy cell control unit 60 receives the erase signal ER, the dummy cell write signal DPG, the memory cell write signal PGM, and the output voltage VH from the high voltage output unit 50 from the controller 2. The dummy cell control unit 60 generates an erase signal ER (hereinafter referred to as “ER signal”), a dummy cell write signal DPG (hereinafter referred to as “DPG signal”), a memory cell write signal PGM (hereinafter referred to as “PGM signal”), and an output voltage VH. The word line voltage <VWL>, source line voltage <VSL>, and dummy bit line voltage <DBL> are generated.

  The current mirror unit 64 mirrors the cell current of the dummy cell unit 62 acquired through the DBL terminal at a predetermined ratio, and generates a dummy cell write current IrefP. Further, the current mirror unit 64 generates a dummy bit line voltage <DBL> to be applied to the DBL terminal. The current mirror unit 64 also receives an ER signal, a DPG signal, and a PGM signal that control the operation of the current mirror unit 64.

  Next, with reference to FIG. 5A, a writing process to the memory cell array 1 in the semiconductor memory device 10 according to the present embodiment will be described. FIG. 5A shows a flowchart of a write process executed by the dummy cell control unit 60 in response to the erase signal ER, the dummy cell write signal DPG, and the memory cell write signal PGM from the controller 2.

  In the semiconductor memory device according to the comparative example including cell voltage generation unit 90 shown in FIG. 11, when a rewrite command is issued according to a normal flow, the memory cell region in the region designated as the rewrite target of memory cell array 1 is erased. Writing to the memory cell area is performed. On the other hand, in the writing process according to the present embodiment, writing to and reading from the dummy cell unit 62 are performed between erasing and writing of the memory cell region. In the flowchart of FIG. 5A, the reference current Iref is set so that the cell current is optimum at room temperature. In the flowchart of FIG. 5A, it is assumed that a rewrite command has already been issued by the controller 2.

As shown in FIG. 5A, when the erase signal ER is received in step S100, the memory cell region designated for rewriting and the dummy cell unit 62 are erased in the next step S102. In step S102, the word line voltage <VWL>, the source line voltage <VSL>, and the dummy bit line voltage <DBL> are set as follows as an example.
<VWL> = about 11V (output voltage VH)
<VSL> = GND
<DBL> = GND
For <VWL>, an output voltage VH of about 11 V generated by the high voltage generator 42 is used.
Further, as described above, the setting of <DBL> is performed in the current mirror unit 64.

When the dummy cell write signal DPG is received in the next step S104, writing to the dummy cell unit 62 is executed in step S106. In the present embodiment, data to be written to the dummy cell unit 62 is data “0”. At the time of writing to the dummy cell unit 62 according to the present embodiment, the output of the dummy cell write current IrefP is cut off at the current mirror unit 64. Therefore, the write voltage VW that provides the optimum cell current at room temperature is applied to the dummy cell section 62. In step S106, <VWL>, <VSL>, and <DBL> are set as follows as an example.
<VWL> = about 1.4V (ZVDD)
<VSL> = about 7.5V (output voltage VH)
<DBL> = about 0.3V
At this time, a current of about 4 μA flows as the cell current of the dummy cell unit 62 including a plurality of dummy cells DC. ZVDD is a voltage generated in the semiconductor memory device 10.

  When the memory cell write signal is received in the next step S108, a target voltage VHt, which is a write voltage VW to the memory cell region, is generated according to the following steps S110 to S114. In the present embodiment, steps S110 to S114 are shown as a flow, but these steps are executed as a circuit operation of the cell voltage generation unit 40.

  In step S110, the dummy cell unit 62 is read to generate a dummy cell write current IrefP. At this time, the read current in the dummy cell unit 62 flows from the current mirror unit 64 to the dummy cell unit 62 and the VSL terminal via the DBL terminal, and the dummy cell write current IrefP mirrors the read current at a predetermined ratio. Generate.

  In the next step S112, the dummy cell write current IrefP generated in step S110 is combined (added) to the reference current Iref, and the reference current is set to the target current Ireft = (Iref + IrefP). The high voltage level determination unit 46 that has received the target current Ireft generates a CPUMP control signal CPUMPEN based on the target current Ireft.

  In the next step S114, the high voltage generator 42 that has received the CPUMP control signal CPUMPEN performs charge-up until the output voltage VH reaches the target voltage VHt based on the CPUMP control signal CPUMPEN. The target voltage VHt generated in step S114 is applied to the memory cell region to be written as the write voltage VW via the high voltage output unit 50.

In the next step S116, writing to the target memory cell region is executed. The write voltage VW at the time of writing in step S116 is the target voltage VHt generated in step S114. In step S116, <VWL>, <VSL>, and <DBL> are set as follows as an example.
<VWL> = about 2.5V (VD25)
<VSL> = GND
<DBL> = about 0.5V
VD 25 is a voltage generated in the semiconductor memory device 10.
Thereafter, the writing process is terminated.

  FIG. 5B shows the relationship between the control signal described above and the voltage applied to each terminal. In FIG. 5B, for example, when the erase signal ER is “1” (H) and active, the voltages applied to the terminals are <VWL> = 11.0 V, <VSL> = GND (0 V), <DBL It means that> = GND.

  Next, specific circuits of the dummy cell control unit 60 and the current mirror unit 64 will be described with reference to FIGS. 6 and 7 are circuit diagrams of the VWL control circuit 66, FIG. 8 is a circuit diagram of the VSL control circuit 68, and FIG. 9 is a circuit diagram of the current mirror unit 64, respectively.

  As shown in FIG. 6, the VWL control circuit 66 includes an OR circuit 100, an inverter 101, an OR circuit 102, an inverter 103, level shift circuits 200 and 201, and a selection circuit 202.

  The OR circuit 100, the inverter 101, the OR circuit 102, and the inverter 103 generate logic values that control the level shift circuits 200 and 201 and the selection circuit 202 based on the ER signal, the DPG signal, and the PGM signal.

  The level shift circuit 200 includes transistors 104, 105, 106, 107, 108, and 109, and the power supply terminal of the level shift circuit 200 is connected to the output voltage VH of the high voltage generator 42 described above. On the other hand, the level shift circuit 201 includes transistors 110, 111, 112, 113, 114, and 115, and the power supply terminal of the level shift circuit 201 is connected to the power supply VVV. The power source VVV is supplied from a VVV generation circuit 208 shown in FIG.

  In the selection circuit 202, a circuit unit that supplies the output voltage VH configured by the transistors 117 and 119 and a circuit unit that supplies the power supply VVV configured by the transistors 118 and 120 have one end in common, and the transistors 121 and 122 have a common end. It is the structure connected to the output stage (gate) comprised from these. A word line voltage <VWL> is output from the output stage.

  As shown in FIG. 7A, the VVV generation circuit 208 includes a level shifter 203, an inverter 130, a transfer gate 204 composed of transistors 131 and 132, and a transfer gate 205 composed of transistors 133 and 134. ing. A power supply ZVDD is connected to the transfer gate 204, and a power supply VD25 is connected to the transfer gate 205. The power supply ZVDD and the power supply VD25 are voltages generated inside the semiconductor memory device 10. As shown in FIG. 5B, the power supply ZVDD gives <VWL> in the dummy cell write mode, and the power supply VD25 is in the memory cell write mode. Gives <VWL>.

  The level shifter 203 is a level shift circuit having an input terminal IN, an output terminal OUT, and a power input VI. FIG. 7B shows an internal circuit of the level shifter 203. As shown in FIG. 7B, the level shifter 203 includes an inverter 140 and transistors 141, 142, 143, 144. As shown in FIG. 7B, the level shifter 203 outputs the voltage input to the power input VI according to the signal input to the input terminal IN.

  As shown in FIG. 7A, a DPG signal or a PGM signal is input to the input terminal IN, and a power supply ZVDD or VD25 is input to the power input VI. When the DPG signal is input, ZVDD is input to the power supply input VI, and the power supply ZVDD is output from the terminal VVV. On the other hand, when the PGM signal is input, VD25 is input to the power supply input VI, and the power supply VD25 is output from the terminal VVV.

  The VWL control circuit 66 having the above configuration generates <VWL> shown in FIG. 5B based on each of the ER signal, the DPG signal, and the PGM signal. For example, when the ER signal = 1, the transistors 109 and 115 are turned on, and the transistors 117 and 119 are turned on. At this time, since the gates of the transistors 121 and 122 are L, the transistor 121 is turned on and the output voltage VH is output from the VWL terminal. That is, the output voltage VH (in the erase mode, 11.0 V, see FIG. 5B) is output from the VWL terminal via the transistors 117, 119, and 121.

  On the other hand, when the DPG signal = 1, the power supply ZVDD (1.4 V) is generated from the VVV generation circuit 208 shown in FIG. 7A, and this power supply ZVDD is applied to the level shift circuit 201 and the selection circuit 202 as the power supply VVV. Is done. When the DPG signal = 1, the transistors 108 and 114 are turned on and the transistors 118 and 120 are turned on. At this time, since the gates of the transistors 121 and 122 are L, the transistor 121 is turned on, and the power supply VVV, that is, the power supply ZVDD is output from the VWL terminal. That is, the power supply ZVDD (1.4 V, see FIG. 5B) is output from the VWL terminal via the transistors 118, 120, and 121.

  When the PGM signal = 1, the power supply VD25 (2.5 V) is generated from the VVV generation circuit 208 shown in FIG. 7A, and this power supply VD25 is applied to the level shift circuit 201 and the selection circuit 202 as the power supply VVV. Is done. When the PGM signal = 1, the transistors 108 and 114 are turned on, and the transistors 118 and 120 are turned on. At this time, since the gates of the transistors 121 and 122 are L, the transistor 121 is turned on, and the power supply VVV, that is, the power supply VD25 is output from the VWL terminal. That is, the power supply VD25 (2.5 V, see FIG. 5B) is output from the VWL terminal via the transistors 118, 120, and 121.

As shown in FIG. 8A, the VSL control circuit 68 includes a level shifter 203, a DPG signal is input to the input terminal IN, and an output voltage VH is input to the power input VI.
As a result, as shown in FIG. 8B, the output voltage VH is output as <VSL> from the output terminal OUT (due to the dummy cell write mode, VH = 7.5 V, see FIG. 5B).

  Next, a circuit example of the current mirror unit 64 will be described with reference to FIG. As shown in FIG. 9, the current mirror unit 64 includes transistors 150, 151, 152, 153, 154, and inverters 160, 162. A DPG signal is input to the gate of the transistor 150 via the inverter 160, a PGM signal is input to the gate of the transistor 152 via the inverter 162, and an ER signal is input to the gate of the transistor 153.

  A connection point between the transistors 150 and 152 and the transistor 153 is a DBL terminal. The transistors 151 and 152 and the transistor 154 form a current mirror circuit, and the dummy cell write current IrefP is output from the source of the transistor 154. The mirror ratio in the current mirror unit 64 is set by the ratio of the size of the transistor 151 and the size of the transistor 154. A fixed voltage of 0.3 V is connected to the drain of the transistor 150, and a power supply Vdd is connected to the drains of the transistors 151 and 154.

  In the current mirror unit 64 shown in FIG. 9, first, in the erase mode, the ER signal is set to 1 (H) and the transistor 153 is turned on, so that <DBL> becomes GND (see FIG. 5B). . At this time, since DPG = 0 (L) and PGM = 0 (L), the transistors 150 and 152 are off. Therefore, the current mirror circuit does not operate.

  In the dummy cell write mode, since the DPG signal = 1, the PGM signal = 0, and the ER signal = 0, the transistor 150 is turned on, the transistors 152 and 153 are turned off, and the 0.. 3V is output (see FIG. 5B). Therefore, the current mirror circuit does not operate.

  In the memory cell write mode, since the PGM signal = 1, the DPG signal = 0, and the ER signal = 0, the transistor 152 is turned on, the transistors 150 and 153 are turned off, and the DBL terminal is connected via the transistors 151 and 152. A cell current flows from to the dummy cell DC. At this time, <DBL> is set to 0.5V. In the memory cell write mode, the current mirror circuit operates, the dummy cell write current IrefP flows from the transistor 154 toward the Iref terminal of the current detection circuit 70, and is combined with the reference current Iref (see FIG. 3A).

  As described above, when writing to the memory cell region in step S116 shown in FIG. 5A, the dummy cell unit 62 is in a read state, and therefore when writing to the dummy cell unit 62 in step S106. Is shallow (when the write voltage VW is low), a cell current (read current) corresponding to the decrease in the write voltage VW flows, and a dummy cell write current IrefP is output from the current mirror unit 64. The dummy cell write current IrefP is combined with the reference current Iref to generate a target current Ireft, and the output voltage VH controlled by the target current Ireft is output as the target voltage VHt to perform writing in the memory cell region.

  Next, with reference to FIG. 10, the operation of the cell voltage generation unit 40 according to the present embodiment will be described. FIG. 10 shows the relationship between the dependence of the detection current Idtc on the output voltage VH (shown in FIG. 10 by a curve C1) in the cell voltage generator 40, the reference current Iref, and the target current Ireft.

  In FIG. 10, an output voltage VH0 at the intersection P1 of the detection current Idtc characteristic and the reference current Iref indicates a write voltage at room temperature T0. When the ambient temperature of the semiconductor memory device 10 rises to a temperature Tt equal to or higher than room temperature, the dummy cell write current IrefP corresponding to the rise temperature ΔT = (Tt−T0) is changed to the reference current Iref by the dummy cell current generation unit 52. These are added to obtain the target current Ireft. As the temperature Tt increases, the dummy cell write current IrefP, that is, the target current Ireft increases, and as a result, the target voltage VHt also shifts to the high voltage side (intersection P2 in FIG. 10).

  That is, according to the semiconductor memory device and the method for writing to the semiconductor memory device according to the present embodiment, the rewrite and read of the dummy cell unit 62 are always performed during the rewrite operation, and the result is reflected. Writing to the corresponding memory cell array 1 is executed. As a result, when writing to the dummy cell unit 62 is shallow (when the write voltage VW is low), the dummy cell write current IrefP is increased and added to the reference current Iref so that writing is performed with the output voltage shifted to the high voltage side. be able to. As a result, since writing is always performed with the optimum write voltage VW with respect to the cell current, it is possible to suppress deterioration in read characteristics from the memory cell array 1.

  In the present embodiment, an example has been described in which the reference current is corrected by always writing to and reading from the dummy cell unit 62 when writing to the memory cell. However, the present invention is not limited to this, and the dummy cell unit is used in a predetermined case. Writing to and reading from 62 may be stopped. In this case, for example, when the dummy cell write current IrefP is not generated in the rewriting to the predetermined number of memory cells, the writing to the dummy cell unit 62 is performed in the next rewriting to the predetermined number of memory cells. Reading may be stopped.

DESCRIPTION OF SYMBOLS 1 Memory cell array 2 Controller 3 Row driver 4 Column driver 10 Semiconductor memory device 40 Cell voltage generation part 42 High voltage generation part 44 High voltage level detection part 46 High voltage level determination part 48 Reference current generation part 50 High voltage output part 52 Dummy cell current Generation unit 60 Dummy cell control unit 62 Dummy cell unit 64 Current mirror unit 66 VWL control circuit 68 VSL control circuit 70 Current detection circuit 72 Comparator 74 Level detection circuit 90 Cell voltage generation unit 92 High voltage generation unit 94 High voltage level detection unit 96 High voltage Level determination unit 98 Reference current generation unit 99 High voltage output unit 100 OR circuit 101 Inverter 102 OR circuit 103 Inverter 130, 140 Inverter 160, 162 Inverter 200, 201 Level shift circuit 202 Selection circuit 203 Level shift 204, 205 Transfer gate 208 VVV generation circuit CPUMPEN CPUMP control signal DC Dummy cell VH, VH0 Output voltage VHt Target voltage VW Write voltage Idtc Detection current Iref Reference current Ireft Target current IrefP Dummy cell write current VWL Word line terminal VSL Source line terminal DBL Dummy bit Line terminal DPG Dummy cell write signal ER Erase signal PGM Memory cell write signal NM1-NMn NMOS transistors TP1-TP3 PMOS transistors TN1-TN5 NMOS transistors

Claims (7)

A memory cell array composed of a plurality of memory cells;
A high voltage generator for boosting a power supply voltage and generating a high voltage to be applied to each of the plurality of memory cells;
A correction current generator for generating a correction current for correcting a variation of the cell voltage with respect to an ambient temperature;
And a detection current obtained by converting the high voltage into a current and a target current for maintaining the high voltage at a target voltage to generate a control signal for controlling a boosting operation in the high voltage generator, and a room temperature A control signal generator that adds the reference current, which is the target current corresponding to the correction current, to the target current,
A cell voltage generator comprising:
A semiconductor memory device. The high voltage generator includes a charge pump unit that boosts the power supply voltage,
The control signal generation unit includes a high voltage level detection unit including a transistor that outputs a current flowing through the breakdown as the detection current when the high voltage exceeds a breakdown voltage, a reference current for generating the reference current The semiconductor memory device according to claim 1, further comprising: a generation unit; and a high voltage level determination unit that generates a signal for stopping the charge pump unit as the control signal when the detected current is equal to or greater than the target current. The cell voltage is a write voltage applied to the memory cell when writing predetermined data to the memory cell;
The write voltage at which a read current that flows through the memory cell when the target voltage is read after the predetermined data is written to the memory cell is equal to the read current at room temperature when the ambient temperature changes The semiconductor memory device according to claim 1 or 2. The correction current generation unit includes a dummy cell unit including a plurality of dummy cells having the same configuration as the memory cell, a current output unit that outputs the read current in the dummy cell unit by multiplying a predetermined coefficient, and the A dummy cell control unit for controlling the operation of the dummy cell unit is provided,
The dummy cell control unit writes the predetermined data to the dummy cell unit after erasing the memory cell region and the dummy cell unit when writing data to at least a part of the memory cell region of the memory cell array. Then, the current output unit is controlled so that the correction current is output based on a read current when the predetermined data written thereafter is read from the dummy cell unit, and is output from the high voltage generation unit. 4. The semiconductor memory device according to claim 3, wherein writing to the memory cell region is performed by the corrected target voltage. The memory cell comprises a field effect transistor having a floating gate;
5. The semiconductor memory device according to claim 3, wherein the predetermined data is data in which a read current when read after being written in the memory cell is substantially zero. 6. The relationship between the write voltage and the read current of the memory cell is such that the write voltage that gives the same read current increases with an increase in ambient temperature,
The semiconductor memory device according to claim 5, wherein the correction current generation unit generates the correction current according to an increment of the ambient temperature from room temperature. A field effect transistor type memory cell having a floating gate, a dummy cell portion having the same configuration as the memory cell and used for correcting a write voltage when writing to the memory cell, and a power supply voltage are boosted to obtain the write voltage. In a semiconductor memory device having a high voltage generating unit for generating a high voltage, the read current when predetermined data is written in the memory cell is equal to the read current at room temperature, so that the read current at room temperature becomes equal to the read current at room temperature. A method for writing to a semiconductor memory device that performs writing while correcting variations in the write voltage,
Erasing the memory cell and the dummy cell when receiving a rewrite command,
Write the predetermined data to the dummy cell portion,
Read the predetermined data written in the dummy cell unit to obtain a read current and generate a correction current based on the read current,
The boosting operation in the high voltage generator is controlled and corrected based on a comparison result of a comparison result of a detection current obtained by converting the high voltage into a current and a reference current based on the read current at room temperature and the correction current. Get the written voltage,
A method of writing to a semiconductor memory device, wherein writing to the memory cell is performed with the corrected write voltage.