JP2019096732A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having a trench extending in a lattice and having high avalanche resistance.
A semiconductor device is provided with an element region and an outer peripheral region, and trenches extending in a lattice shape are provided on the upper surface of a semiconductor substrate in the element region. A gate insulating film and a gate electrode are provided in the trench. The element region has an emitter region, a body region, and a drift region. The trench has a first portion extending in a first direction on the upper surface of the semiconductor substrate, a second portion extending in a direction different from the first direction, and a connection portion connecting the first portion and the second portion. . The width of the connection is wider than the widths of the first and second portions. The depth of the connection is deeper than the depth of the first and second portions.
[Selected figure] Figure 2

Description

  The technology disclosed herein relates to a semiconductor device.

  Patent Document 1 discloses a semiconductor device provided with trenches extending in a lattice shape. A gate insulating film and a gate electrode are disposed in the trench. An n-type emitter region and a p-type body region are provided in each of a plurality of regions (hereinafter referred to as divided regions) surrounded by the trench. An n-type drift region is provided in a range over the lower portions of the plurality of divided regions. The drift region is in contact with the gate insulating film at the lower side of the body region and at the lower end of the trench. A switching element is configured by the emitter region, the body region, the drift region and the gate electrode.

Unexamined-Japanese-Patent No. 2015-225872

  In a general trench gate type switching element, an electric field is concentrated in the drift region near the lower end of the trench in the off state. However, in the semiconductor device of Patent Document 1, since the density of the trench is high, it is difficult for the electric field to be concentrated in the drift region near the lower end of the trench. Therefore, a higher electric field is more likely to be generated in the outer peripheral area around the element region than in the element region in which the switching element is provided. Therefore, when the voltage applied to the semiconductor device is increased, avalanche breakdown is likely to occur earlier in the outer peripheral region than in the device region. Since the current path in the outer peripheral region is small, when avalanche breakdown occurs in the outer peripheral region, the density of the avalanche current becomes high and the temperature in the outer peripheral region becomes excessively high. Thus, since the avalanche breakdown occurs in the outer peripheral region, the semiconductor device of Patent Document 1 has a problem that the avalanche resistance is low. Therefore, the present specification provides a semiconductor device having a trench extending in a lattice and having high avalanche resistance.

  A semiconductor device disclosed in the present specification includes a semiconductor substrate, an upper electrode, a lower electrode, a trench, a gate insulating film, and a gate electrode. The semiconductor substrate includes an element region and an outer peripheral region around the element region. The upper electrode is in contact with the upper surface of the semiconductor substrate in the element region. The lower electrode is in contact with the lower surface of the semiconductor substrate. The trenches are provided on the upper surface in the element region, and extend in a lattice shape on the upper surface. The gate insulating film is disposed in the trench. The gate electrode is disposed in the trench and is insulated from the semiconductor substrate by the gate insulating film. The element region includes an emitter region, a body region, and a drift region. The emitter region is an n-type region which is disposed in each of a plurality of partition regions surrounded by the trenches extending in a lattice shape, in contact with the upper electrode, and in contact with the gate insulating film. The body region is a p-type region disposed inside each of the plurality of partition regions, in contact with the upper electrode, and in contact with the gate insulating film below the emitter region. The drift region is distributed in a range spanning lower portions of the plurality of divided regions and the outer peripheral region, and is an n-type region in contact with the gate insulating film at the lower side of the body region and the lower end of the trench. The width of the connection portion is wider than the widths of the first portion and the second portion. The depth of the connection portion is deeper than the depth of the first portion and the second portion.

  The drift region may be in contact with the body region, and another semiconductor region may exist between the drift region and the body region.

  In this semiconductor device, the width of the connection portion connecting the first portion and the second portion of the trench is wider than the width of the first portion and the second portion. According to such a configuration, when forming the trench by etching, the depth of the connection portion is deeper than the depth of the first portion and the second portion by the microloading effect. Although Patent Document 1 discloses that the trench is deepened in the connection portion, the trench can be further deepened in the connection portion than in Patent Document 1 by widening the width of the connection portion. As described above, when the trench is made deeper at the connection portion than in the conventional case, the electric field tends to be concentrated at the drift region near the lower end of the connection portion. Therefore, when the voltage applied to the semiconductor device rises, avalanche breakdown occurs earlier in the element region than in the outer peripheral region. The element region is in contact with the upper electrode and has a wide current path. Therefore, avalanche current can be distributed and flow in a wide current path, and local concentration of avalanche current can be suppressed. Therefore, it is possible to suppress that the element region is excessively heated by the avalanche current. Thus, the avalanche resistance of the semiconductor device is improved by causing the avalanche breakdown in the element region.

FIG. 2 is a top view of a semiconductor device. FIG. 2 is a cross-sectional perspective view of an element region. Sectional drawing of an element area | region. Sectional drawing of an element area | region and an outer periphery area | region. The top view which shows the shape of the trench in the upper surface of a semiconductor substrate. Sectional drawing of the trench in the VI-VI line of FIG. Sectional drawing of the trench in the VII-VII line of FIG. The top view which shows the shape of the trench of the modification in the upper surface of a semiconductor substrate. The top view which shows the shape of the trench of the modification in the upper surface of a semiconductor substrate. The top view which shows the shape of the trench of the modification in the upper surface of a semiconductor substrate. The top view which shows the shape of the trench of the modification in the upper surface of a semiconductor substrate.

  As shown in FIG. 1, the semiconductor device 10 of the embodiment has a semiconductor substrate 12 made of silicon. The semiconductor substrate 12 has an element region 60 and an outer peripheral region 62. The element region 60 is provided with a switching element. The element region 60 is disposed at the central portion of the semiconductor substrate 12. The peripheral region 62 surrounds the periphery of the element region 60. The outer peripheral region 62 is a region between the element region 60 and the outer peripheral end of the semiconductor substrate 12. In the following description, the x direction means one direction parallel to the upper surface of the semiconductor substrate 12, the y direction means a direction parallel to the upper surface of the semiconductor substrate 12 and orthogonal to the x direction, and the z direction is the semiconductor substrate The thickness direction of 12 is meant.

  FIG. 2 is a partial perspective view showing the upper surface and the cross section of the semiconductor device 10 in the element region 60. As shown in FIG. FIG. 3 shows a cross section of the semiconductor device 10 in the element region 60. As shown in FIG. FIG. 4 shows a cross section of the semiconductor device 10 in a range spanning the element region 60 and the outer peripheral region 62. As shown in FIG. As shown in FIGS. 3 and 4, the upper surface 12 a of the semiconductor substrate 12 in the element region 60 is covered by the upper electrode 22. In FIG. 2, the electrodes and the insulating film on the upper surface 12 a of the semiconductor substrate 12 are not shown. As shown in FIG. 4, the upper electrode 22 does not cover the upper surface 12 a of the semiconductor substrate 12 in the outer peripheral region 62. The upper surface 12 a of the semiconductor substrate 12 in the outer peripheral region 62 is covered with the insulating protective film 46. In other words, when the semiconductor substrate 12 is viewed in plan from the upper side, the range covered by the upper electrode 22 is the element region 60, and the range not covered by the upper electrode 22 is the outer peripheral region 62. As shown in FIGS. 2 to 4, the entire area of the lower surface 12 b of the semiconductor substrate 12 is covered by the lower electrode 26. That is, the lower electrode 26 is in contact with the lower surface 12 b in a range across the element region 60 and the outer peripheral region 62.

  A trench 14 is formed on the upper surface 12 a of the semiconductor substrate 12. FIG. 5 shows the shape of the trench 14 when the upper surface 12 a is viewed in plan from the upper side. As shown in FIG. 5, the trenches 14 extend in a lattice at the upper surface 12a. The semiconductor region on the upper surface 12 a side is divided into a plurality of substantially rectangular regions 50 by the trench 14. Hereinafter, the substantially rectangular area 50 divided by the trench 14 will be referred to as a divided area 50. The trench 14 has a first portion 14a linearly extending in the y direction, a second portion 14b linearly extending in the x direction, and a connection portion 14c connecting the first portion 14a and the second portion 14b. There is. In the connection portion 14 c, the width of the trench 14 is wider than the first portion 14 a and the second portion 14 b. As shown in FIGS. 6 and 7, in the connection portion 14c, the depth of the trench 14 is deeper than in the first portion 14a and the second portion 14b.

  As shown in FIGS. 2 and 3, the inner surface of the trench 14 is covered by the gate insulating film 16. A gate electrode 18 is disposed in the trench 14. The gate electrode 18 is insulated from the semiconductor substrate 12 by the gate insulating film 16. As shown in FIG. 3, the upper surface of the gate electrode 18 is covered with an interlayer insulating film 20. The upper electrode 22 covers the interlayer insulating film 20 and the upper surface 12 a of the semiconductor substrate 12. Gate electrode 18 is insulated from upper electrode 22 by interlayer insulating film 20. The upper electrode 22 is in contact with the upper surface 12 a of the semiconductor substrate 12 in the range where the interlayer insulating film 20 does not exist.

  An emitter region 30, an upper body region 32, a barrier region 34, a lower body region 36, a drift region 38, a buffer region 39, and a collector region 40 are formed inside the semiconductor substrate 12 in the element region 60.

  Emitter region 30 is an n-type semiconductor region. Two emitter regions 30 are disposed in each divided region 50. Emitter region 30 is in contact with gate insulating film 16 at the upper end portion of trench 14. Emitter region 30 is exposed on upper surface 12 a of semiconductor substrate 12. Emitter region 30 is in ohmic contact with upper electrode 22.

  The upper body region 32 is a p-type semiconductor region. The upper body region 32 is disposed in each of the divided regions 50. The upper body region 32 has a contact region 32a and a low concentration region 32b.

  The contact region 32a is a p-type semiconductor region having a high p-type impurity concentration. The contact area 32 a is an area exposed to the upper surface 12 a and disposed at the center of each divided area 50. The contact region 32 a is in ohmic contact with the upper electrode 22. The contact region 32 a is disposed between the two emitter regions 30.

  The low concentration region 32 b is a p-type semiconductor region having a p-type impurity concentration lower than that of the contact region 32 a. The low concentration region 32 b is disposed below the emitter region 30 and the contact region 32 a. The low concentration region 32 b is in contact with the emitter region 30 and the contact region 32 a from below. The low concentration region 32 b is exposed to the upper surface 12 a in the range where the emitter region 30 and the contact region 32 a do not exist. The low concentration region 32 b is in contact with the gate insulating film 16 below the emitter region 30.

  The barrier region 34 is an n-type semiconductor region. The barrier region 34 is disposed in each of the divided regions 50. The barrier region 34 is formed under the low concentration body region 32 b and is in contact with the low concentration body region 32 b from below. The barrier region 34 is separated from the emitter region 30 by a low concentration body region 32b. The barrier region 34 is in contact with the gate insulating film 16 below the low concentration body region 32 b.

  The lower body region 36 is a p-type semiconductor region. The lower body region 36 is disposed in each of the divided regions 50. The lower body region 36 is formed on the lower side of the barrier region 34 and is in contact with the barrier region 34 from the lower side. Lower body region 36 is separated from upper body region 32 by barrier region 34. The lower body region 36 is in contact with the gate insulating film 16 below the barrier region 34.

  The drift region 38 is an n-type semiconductor region. The n-type impurity concentration of drift region 38 is lower than the n-type impurity concentration of barrier region 34. The drift region 38 is disposed below the lower end of the trench 14. The drift region 38 is distributed in the range across the lower part of the plurality of divided regions 50. A part of the drift region 38 extends into each of the divided regions 50 and is in contact with the lower body region 36 from the lower side. Drift region 38 is separated from barrier region 34 by lower body region 36. Drift region 38 is in contact with gate insulating film 16 below lower body region 36. In other words, the drift region 38 is in contact with the gate insulating film 16 below the upper body region 32, the barrier region 34 and the lower body region 36. The drift region 38 is in contact with the gate insulating film 16 at the lower end of the trench 14. As shown in FIG. 4, drift region 38 extends from element region 60 to outer peripheral region 62.

  The buffer region 39 is an n-type semiconductor region. The n-type impurity concentration of buffer region 39 is higher than the n-type impurity concentration of drift region 38. The buffer region 39 is formed below the drift region 38 and is in contact with the drift region 38 from below. Buffer region 39 extends from element region 60 to outer peripheral region 62.

  The collector region 40 is a p-type semiconductor region. The p-type impurity concentration of collector region 40 is higher than the p-type impurity concentration of upper body region 32 and lower body region 36. The collector region 40 is formed below the buffer region 39 and is in contact with the buffer region 39 from the lower side. Collector region 40 extends from element region 60 to outer peripheral region 62. The collector region 40 is exposed to the lower surface 12 b of the semiconductor substrate 12. Collector region 40 is in ohmic contact with lower electrode 26. In place of the collector region 40, an n-type cathode region in ohmic contact with the lower electrode 26 may be provided in a part of the range exposed to the lower surface 12b of the semiconductor substrate 12.

  As shown in FIG. 4, a plurality of guard rings 44 are disposed in the outer peripheral region 62 in a range exposed to the upper surface 12 a. Each guard ring 44 is a p-type region. Each guard ring 44 has a ring shape that goes around the periphery of the element region 60. The drift region 38 in the outer peripheral region 62 is exposed to the upper surface 12 a in a range where the guard ring 44 is not provided. In place of the guard ring 44, another pressure-resistant structure (for example, a resurf layer or the like) may be provided.

  In the element region 60, an IGBT (insulated gate bipolar transistor) is formed by the emitter region 30, the upper body region 32, the barrier region 34, the lower body region 36, the drift region 38, the buffer region 39, the collector region 40, the gate electrode 18 and the like. Is configured.

  When the potential of the gate electrode 18 is controlled to a potential higher than the gate threshold, a channel is formed in the upper body region 32 and the lower body region 36 in the vicinity of the gate insulating film 16. The channel connects emitter region 30, barrier region 34 and drift region 38 to one another. When a potential higher than that of the upper electrode 22 is applied to the lower electrode 26 in a state in which a channel is formed, the upper electrode 22, the channel of the emitter region 30, the upper body region 32, the channel of the barrier region 34, and the channel of the lower body region 36 Electrons flow to the lower electrode 26 through the drift region 38, the buffer region 39 and the collector region 40. That is, the IGBT is turned on. At the same time, holes flow from the lower electrode 26 into the drift region 38 through the collector region 40 and the buffer region 39. As a result, the conductivity modulation phenomenon reduces the resistance of the drift region 38 and electrons flow through the drift region 38 with low loss. When the trenches 14 are formed in a lattice, holes do not easily flow to the upper electrode 22 side, and holes are easily accumulated in the drift region 38. Therefore, the resistance of drift region 38 can be reduced more effectively, and the loss generated in the IGBT is suppressed. When the potential of the gate electrode 18 is lowered to a potential lower than the gate threshold, the channel disappears and the current stops. That is, the IGBT is turned off.

  When the IGBT is turned off, a depletion layer spreads from lower body region 36 to drift region 38. As a result, substantially the entire drift region 38 is depleted. As a result, an electric field is generated in the drift region 38. The lower end of the trench 14 protrudes below the lower body region 36, so that the electric field tends to be concentrated near the lower end of the trench 14. In particular, in the present embodiment, since the trench 14 is locally deep in the connection portion 14c, the electric field tends to be concentrated in the vicinity of the lower end of the connection portion 14c. Therefore, avalanche breakdown is likely to occur in the drift region 38 near the lower end of the connection portion 14c. Therefore, when the potential of the lower electrode 26 is raised while the IGBT is off, avalanche breakdown occurs in the drift region 38 in the vicinity of the lower end of the connection portion 14c. That is, avalanche breakdown occurs earlier in the element region 60 than in the outer peripheral region 62. When an avalanche breakdown occurs, a large amount of holes are generated in the drift region 38. Holes generated in the drift region 38 in the element region 60 flow to the upper electrode 22. That is, an avalanche current flows to the upper electrode 22. The element region 60 is in contact with the upper electrode 22 in a wide range, so that avalanche current can flow in a dispersed manner in the element region 60. Therefore, excessive heat generation is suppressed in element region 60.

  If an avalanche breakdown occurs in the drift region 38 (for example, the drift region 38 near the guard ring 44) in the outer peripheral region 62, a large number of holes generated by the avalanche breakdown are the outer peripheral end 22a of the upper electrode 22 (see FIG. 4). It flows toward). Therefore, the avalanche current is concentrated in the semiconductor region near the outer peripheral end 22a. Therefore, excessive heat generation easily occurs in the semiconductor region near the outer peripheral end 22a. However, in the semiconductor device 10 of the present embodiment, avalanche breakdown occurs earlier in the element region 60 than in the outer peripheral region 62, so that avalanche breakdown can be suppressed in the outer peripheral region 62. Thus, excessive heat generation in the vicinity of the outer peripheral end 22a is suppressed.

  As described above, in this semiconductor device, the avalanche breakdown is generated earlier in the element region 60 than in the outer peripheral region 62, thereby suppressing the occurrence of the avalanche breakdown in the outer peripheral region 62. Further, even if avalanche breakdown occurs in the element region 60, the avalanche current is dispersed and flows, so excessive heat generation is suppressed. Therefore, the avalanche resistance of the semiconductor device 10 as a whole can be improved as compared to the conventional one.

  Next, a method of forming the trench 14 will be described. When forming the trench 14, first, a mask is formed on the upper surface 12 a of the semiconductor substrate 12. Next, an opening is formed in the mask. The openings are formed only in the area where the trench 14 is to be formed. Here, the width of the opening in the range in which the connection portion 14c is to be formed is made wider than the width of the opening in the range in which the first portion 14a and the second portion 14b are to be formed. Next, the upper surface 12a in the opening is etched by reactive ion etching. This forms lattice-like extending trenches 14. Since the connecting portion 14c is wide, the microloading effect causes the etching to proceed faster than the first portion 14a and the second portion 14b. Therefore, as shown in FIGS. 6 and 7, the depth of the connection portion 14c is deeper than the depths of the first portion 14a and the second portion 14b. According to this method, as shown in FIGS. 6 and 7, it is possible to easily form the trench 14 locally deepened at the connection portion 14c. Therefore, the semiconductor device 10 having high avalanche withstand capability can be easily manufactured.

  In the embodiment described above, as shown in FIG. 5, the connection portion 14c is substantially rectangular. However, as shown in FIGS. 8 and 9, the connection portion 14c may be triangular or semicircular. Further, as shown in FIG. 10, the connection portion 14c may be provided on one side of the second portion 14b. Further, as shown in FIG. 11, a connection portion 14c may be provided to connect the plurality of second portions 14b.

  In addition, the semiconductor device 10 of the embodiment described above has the barrier region 34. However, the barrier region 34 may not exist, and the upper body region 32 and the lower body region 36 may be integrated.

  As mentioned above, although embodiment was described in detail, these are only examples and do not limit the range of a claim. The art set forth in the claims includes various variations and modifications of the specific examples illustrated above. The technical elements described in the present specification or the drawings exhibit technical usefulness singly or in various combinations, and are not limited to the combinations described in the claims at the time of application. In addition, the techniques illustrated in the present specification or the drawings simultaneously achieve a plurality of purposes, and achieving one of the purposes itself has technical utility.

10: semiconductor device 12: semiconductor substrate 14: trench 14a: first portion 14b: second portion 14c: connection portion 16: gate insulating film 18: gate electrode 20: interlayer insulating film 22: upper electrode 26: lower electrode 30: emitter Region 32: upper body region 34: barrier region 36: lower body region 38: drift region 39: buffer region 40: collector region 44: guard ring 46: insulating protective film 50: partition region 60: element region 62: outer peripheral region

Claims (1)

A semiconductor device,
A semiconductor substrate comprising an element region and an outer peripheral region around the element region;
An upper electrode in contact with the upper surface of the semiconductor substrate in the element region;
A lower electrode in contact with the lower surface of the semiconductor substrate;
Trenches provided on the upper surface in the element region and extending in a lattice shape on the upper surface;
A gate insulating film disposed in the trench;
A gate electrode disposed in the trench and insulated from the semiconductor substrate by the gate insulating film;
Equipped with
The element region is
An n-type emitter region disposed inside each of the plurality of partition regions surrounded by the trenches extending in a grid shape, in contact with the upper electrode, and in contact with the gate insulating film;
A p-type body region disposed inside each of the plurality of divided regions, in contact with the upper electrode, and in contact with the gate insulating film below the emitter region;
An n-type drift region distributed in a range spanning lower portions of the plurality of divided regions and the outer peripheral region, and in contact with the gate insulating film at the lower side of the body region and the lower end of the trench;
And have
A connection portion connecting the first portion extending in a first direction on the upper surface, the second portion extending in a direction different from the first direction on the upper surface, and a connection portion connecting the first portion and the second portion And have
The width of the connection portion is wider than the widths of the first portion and the second portion,
The depth of the connection portion is deeper than the depths of the first portion and the second portion,
Semiconductor device.

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