JP2019092045A - Digital processing device, manufacturing method of digital processing device, and program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the performance of a digital processing device. A digital processing device (1), which is created using a programmable logic device, converts a data (D1) having a first bit number into a data (D2) having a first bit number, and a linear processing of the data (D2). And a linear processing unit 4 for performing. The processing unit 3 has a plurality of conversion circuits 31 created based on the look-up table description system and a plurality of conversion circuits 32 created based on the Boolean algebra description system. In the processing unit 3, N conversion circuits 31 of the plurality of conversion circuits 31 or N conversion circuits 32 of the plurality of conversion circuits 32 are allocated for each processing unit of the unit processing circuit. [Selection diagram] Figure 1

Description

  The present invention relates to a digital processing device, a method of manufacturing a digital processing device, and a program.

  It is known that a product using a large scale integrated circuit (LSI) such as an application specific integrated circuit (ASIC) and a field programmable gate array (FPGA) is used for a digital processing device which requires table reference processing. As such digital processing devices, for example, there are a signal processing device that performs filter processing by referring to filter coefficients from a table, and a security (encryption processing) device that performs non-linear conversion processing by table reference processing. In programmable logic devices such as FPGAs, hard macros and soft macros are used. In the soft macro, the circuit design of the table reference process is performed using a hardware description language (HDL) (see, for example, Patent Document 1).

  The description method using hardware description language includes a description method using look-up table (LUT; Look-Up-Table), a description method using Boolean algebra and an extension method in finite field theory There is. In the description method using Boolean algebra, it is necessary to describe uniquely in Boolean algebra, and due to its complexity, there is not much opportunity for the description method using Boolean algebra to be used. In the description method using the extension field in finite field theory, a large improvement in performance can be expected, but the practicality is poor because of the difficulty of the theory. Under such circumstances, a description method using a look-up table is frequently used from the viewpoint of simplicity.

JP 2003-323117 A

  However, there is room for improvement in the performance of a digital processing apparatus in which the table reference processing circuit is designed only by the description method using a look-up table.

  The present invention provides a digital processing device capable of improving performance, a method of manufacturing a digital processing device, and a program.

  A digital processing device according to one aspect of the present invention is a digital processing device created using a programmable logic device, which converts first data having a first number of bits into second data having a first number of bits. Processing unit, and a linear processing unit that performs linear processing of the second data. The processing unit includes a plurality of first conversion circuits created based on the look-up table description method and a plurality of second conversion circuits created based on the Boolean algebra description method, and the plurality of first conversion circuits And each of the plurality of second conversion circuits convert the first partial data having the second bit number of the first data into second partial data having the second bit number of the second data. . The linear processing unit has a unit processing circuit that performs linear processing using unit data having a third bit number that is N times the second bit number (N is an integer of 2 or more), and the processing unit performs processing For each unit, N first conversion circuits among the plurality of first conversion circuits or N second conversion circuits among the plurality of second conversion circuits are allocated.

  In this digital processing device, N first conversion circuits or N second conversion circuits are assigned to each processing unit. Therefore, in the processing unit, there are mixed conversion circuits created based on different description methods, and N conversion circuits created based on the same description method for each processing unit of the unit processing circuit included in the linear processing unit. Assigned. The various circuits created in the programmable logic device are based on being distributed at random and distributed, but circuits based on the same description system tend to be arranged together. Therefore, by allocating N conversion circuits created based on the same description method for each processing unit, the possibility that N conversion circuits are collectively arranged is increased. As a result, the mounting area of the circuit created in the programmable logic device can be reduced, or the processing speed of the circuit can be increased, so that the performance of the digital processing device can be improved.

  The unit processing circuit may change the arrangement order of the N second partial data included in the unit data. Since the N conversion circuits that supply the N second partial data processed by the unit processing circuit tend to be arranged collectively, the total of the wiring lengths of the wirings from the N conversion circuits to the unit processing circuit Is likely to become smaller. This reduces the footprint of the circuit created in the programmable logic device and increases the likelihood of faster processing speeds.

  The unit processing circuit may shift unit data by a predetermined number of bits. Since the N conversion circuits that supply unit data processed by the unit processing circuit tend to be arranged collectively, there is a possibility that the total of the wiring lengths of the wirings from the N conversion circuits to the unit processing circuit may be reduced. Increase. This reduces the footprint of the circuit created in the programmable logic device and increases the likelihood of faster processing speeds.

  A digital processing device according to one aspect of the present invention is a digital processing device created using a programmable logic device, which linearly processes predetermined data and outputs first data having a first number of bits. And a processing unit configured to convert the first data into second data having a first number of bits. The processing unit includes a plurality of first conversion circuits created based on the look-up table description method and a plurality of second conversion circuits created based on the Boolean algebra description method, and the plurality of first conversion circuits And each of the plurality of second conversion circuits convert the first partial data having the second bit number of the first data into second partial data having the second bit number of the second data. . The linear processing unit has a unit processing circuit that performs linear processing using unit data having a third bit number that is N times the second bit number (N is an integer of 2 or more), and the processing unit performs processing For each unit, N first conversion circuits among the plurality of first conversion circuits or N second conversion circuits among the plurality of second conversion circuits are allocated.

  In this digital processing device, N first conversion circuits or N second conversion circuits are assigned to each processing unit. Therefore, it becomes possible to improve the performance of the digital processing device as in the above-mentioned digital processing device.

  The unit processing circuit may calculate an exclusive OR of unit data and data having the third bit number. Since the N conversion circuits to which data based on the processing result of the unit processing circuit are supplied tend to be arranged collectively, the total of the wiring lengths of the wirings from the unit processing circuit to the N conversion circuits is reduced. The possibilities increase. This reduces the footprint of the circuit created in the programmable logic device and increases the likelihood of faster processing speeds.

  Each of the plurality of first conversion circuits and each of the plurality of second conversion circuits may perform non-linear conversion processing. In this case, it is possible to make it difficult to deduce the input data of the digital processing device from the output data of the digital processing device.

  A method of manufacturing a digital processing device according to another aspect of the present invention includes a plurality of first conversion circuits and a plurality of second conversion circuits, and has first data having a first number of bits and a first number of bits. A method of manufacturing a digital processing device, comprising: a processing unit for converting data into second data; and a linear processing unit for performing linear processing of second data, the circuit of the processing unit and the linear processing unit according to a programmable logic device And a creation step of creating a processing unit and a linear processing unit in the programmable logic device based on the description step of describing the function and the circuit function. Each of the plurality of first conversion circuits and each of the plurality of second conversion circuits includes first partial data having a second number of bits of the first data and second partial data having a second number of bits of the second data. The linear processing unit has a unit processing circuit that performs linear processing with unit data having a third bit number that is N times the second bit number (N is an integer equal to or greater than 2) converted into two-part data. . In the processing unit, N first conversion circuits among the plurality of first conversion circuits or N second conversion circuits among the plurality of second conversion circuits are assigned to each processing unit, and in the description process, The circuit functions of the plurality of first conversion circuits are described by the look-up table description method, and the circuit functions of the plurality of second conversion circuits are described by the Boolean algebra description method.

  In this method of manufacturing a digital processing device, the circuit functions of the plurality of first conversion circuits are described by the look-up table description method, and the circuit functions of the plurality of second conversion circuits are described by the Boolean algebra description method. Furthermore, in the processing unit, N first conversion circuits or N second conversion circuits are assigned to each processing unit. Therefore, it becomes possible to improve the performance of the digital processing device as in the above-mentioned digital processing device.

  A manufacturing method of a digital processing device according to another aspect of the present invention performs linear processing of predetermined data, and outputs a first data having a first number of bits, a plurality of first conversion circuits, and a plurality of first conversion circuits. And a processing unit for converting the first data into the second data having the first number of bits, the processing unit corresponding to the programmable logic device. And a creating step of creating the processing unit and the linear processing unit in the programmable logic device based on the circuit function. Each of the plurality of first conversion circuits and each of the plurality of second conversion circuits includes first partial data having a second number of bits of the first data and second partial data having a second number of bits of the second data. The linear processing unit has a unit processing circuit that performs linear processing with unit data having a third bit number that is N times the second bit number (N is an integer equal to or greater than 2) converted into two-part data. . In the processing unit, N first conversion circuits among the plurality of first conversion circuits or N second conversion circuits among the plurality of second conversion circuits are assigned to each processing unit, and in the description process, The circuit functions of the plurality of first conversion circuits are described by the look-up table description method, and the circuit functions of the plurality of second conversion circuits are described by the Boolean algebra description method.

  In this method of manufacturing a digital processing device, the circuit functions of the plurality of first conversion circuits are described by the look-up table description method, and the circuit functions of the plurality of second conversion circuits are described by the Boolean algebra description method. Furthermore, in the processing unit, N first conversion circuits or N second conversion circuits are assigned to each processing unit. Therefore, it becomes possible to improve the performance of the digital processing device as in the above-mentioned digital processing device.

  A program according to still another aspect of the present invention includes a plurality of first conversion circuits and a plurality of second conversion circuits, and transmits first data having a first number of bits to second data having a first number of bits. A program for causing a programmable logic device to function as a digital processing device including a processing unit that performs conversion and a linear processing unit that performs linear processing of second data, and creating a plurality of first conversion circuits in the programmable logic device And a second part for creating a plurality of second conversion circuits in the programmable logic device. The first part is described using a look-up table description method, the second part is described using a Boolean algebra description method, and each of the plurality of first conversion circuits and each of the plurality of second conversion circuits is First partial data having a second number of bits of the first data is converted into second partial data having a second number of bits of the second data. The linear processing unit has a unit processing circuit that performs linear processing using unit data having a third bit number that is N times the second bit number (N is an integer of 2 or more), and the processing unit performs processing For each unit, N first conversion circuits among the plurality of first conversion circuits or N second conversion circuits among the plurality of second conversion circuits are allocated.

  In this program, the first part is described using the look-up table description method, and the second part is described using the Boolean algebra description method. Furthermore, in the processing unit, N first conversion circuits or N second conversion circuits are assigned to each processing unit. Therefore, it becomes possible to improve the performance of the digital processing device as in the above-mentioned digital processing device.

  A program according to still another aspect of the present invention performs linear processing of predetermined data and outputs a first data having a first number of bits, a plurality of first conversion circuits, and a plurality of second conversions. A program for causing a programmable logic device to function as a digital processing device, comprising: a processing unit having a circuit and converting first data into second data having a first number of bits, wherein the plurality of programmable logic devices And a second part for producing a plurality of second conversion circuits in the programmable logic device. The first part is described using a look-up table description method, the second part is described using a Boolean algebra description method, and each of the plurality of first conversion circuits and each of the plurality of second conversion circuits is First partial data having a second number of bits of the first data is converted into second partial data having a second number of bits of the second data. The linear processing unit has a unit processing circuit that performs linear processing using unit data having a third bit number that is N times the second bit number (N is an integer of 2 or more), and the processing unit performs processing For each unit, N first conversion circuits among the plurality of first conversion circuits or N second conversion circuits among the plurality of second conversion circuits are allocated.

  In this program, the first part is described using the look-up table description method, and the second part is described using the Boolean algebra description method. Furthermore, in the processing unit, N first conversion circuits or N second conversion circuits are assigned to each processing unit. Therefore, it becomes possible to improve the performance of the digital processing device as in the above-mentioned digital processing device.

  According to the present invention, it is possible to improve the performance of a digital processing device.

FIG. 1 is a diagram showing the configuration of a digital processing device according to the first embodiment. FIG. 2 is a diagram showing a detailed configuration of the linear processing unit of FIG. FIG. 3 shows a modification of the digital processing device according to the first embodiment. FIG. 4 is a diagram showing the configuration of a digital processing device according to the second embodiment. FIG. 5 is a diagram for explaining the array conversion process of the array conversion circuit of FIG. FIG. 6 is a view showing a modification of the digital processing device according to the second embodiment.

  The details of the embodiments of the present invention will be described below with reference to the attached drawings. In the description of the drawings, the same reference numerals are used for the same or equivalent elements, and the overlapping description is omitted.

  FIG. 1 is a diagram showing the configuration of a digital processing device according to the first embodiment. FIG. 2 is a diagram showing a detailed configuration of the linear processing unit of FIG. The digital processing device 1 shown in FIG. 1 is a device for performing cryptographic processing conforming to the BORON standard. The digital processing device 1 is created using a programmable logic device. As a programmable logic device, for example, an FPGA and a PLD (Programmable Logic Device) are used.

  The digital processing device 1 includes an encrypted data generation unit 2, a processing unit 3, and a linear processing unit 4. The digital processing device 1 digitally processes input data having a first bit number (64 bits in FIG. 1) by the encryption data generation unit 2, the processing unit 3, and the linear processing unit 4 to obtain the first bit number. Output the output data that it has. In FIG. 1, one encryption data generation unit 2, one processing unit 3, and one linear processing unit 4 are shown, but the digital processing device 1 includes an encryption data generation unit 2, a processing unit 3, and a linear unit. A plurality of circuit units 10 are provided with the processing unit 4 as one circuit unit 10. The plurality of circuit units 10 are connected in series, and in the two circuit units 10 and 10 adjacent to each other, data Dout output from the circuit unit 10 at the previous stage is input as data Din to the circuit unit 10 at the subsequent stage. Ru. Note that bit numbers are assigned in ascending order from LSB (Least Significant Bit; least significant bit) to MSB (Most Significant Bit; most significant bit) to each bit included in the data Din. In the present embodiment, the bit number of the LSB is 0, and the bit number of the MSB is 63. The same applies to data Dout and data D1, D2, D3, and D4 described later.

  The cryptographic data generation unit 2 is a circuit that logically operates the data Din based on the cryptographic key data. Specifically, the cryptographic data generation unit 2 calculates XOR (exclusive OR) of the data Din and the encryption key data. Data Din is data having a first number of bits. The encryption key data is stored in advance in a memory (not shown), and is input to the encryption data generation unit 2 from the memory. The encryption key data may be sequentially generated by an encryption key generation circuit (not shown), and may be input to the encryption data generation unit 2 from the encryption key generation circuit. The encryption key data has a first bit number. The cryptographic data generation unit 2 outputs the calculation result to the processing unit 3 as data D1 (first data). Data D1 is data having a first number of bits.

  The processing unit 3 is a circuit that converts the data D1 into data D2 (second data). Data D2 is data having a first bit number. Specifically, the processing unit 3 generates data D2 by performing non-linear conversion processing of the data D1. The processing unit 3 outputs the data D2 to the linear processing unit 4. The processing unit 3 includes a plurality of conversion circuits 31 (a plurality of first conversion circuits) and a plurality of conversion circuits 32 (a plurality of second conversion circuits). The plurality of conversion circuits 31 and the plurality of conversion circuits 32 are arranged in parallel, and data d1 (first partial data) is input to each conversion circuit 31 and each conversion circuit 32. Data d1 is a part of data D1 and has a second bit number (4 bits in FIG. 1). The data d1 is data obtained by dividing all the data from the LSB to the MSB of the data D1 in the order of bit numbers in units of the second number of bits. In FIG. 1, the data D1 is configured by the sixteen data d1. Each of the plurality of conversion circuits 31 and each of the plurality of conversion circuits 32 performs conversion processing on the data d1 input thereto, and the processing unit 3 converts the data D1 into data D2.

  The conversion circuit 31 is a circuit created based on a description method (look-up table description method) using a look-up table. The conversion circuit 32 is a circuit created based on a description method using Boolean algebra (Boolean Algebra Description System). The conversion circuit 31 and the conversion circuit 32 have functions equivalent to each other.

  The conversion circuits 31 and 32 are circuits for converting the data d1. Specifically, conversion circuits 31 and 32 convert data d1 into data d2 (second partial data). Data d2 is a part of data D2 and has a second bit number. Data d2 is data obtained by dividing all the data from the LSB to the MSB of the data D2 in the order of bit numbers in units of the second number of bits. In FIG. 1, the data D2 is configured by the sixteen data d2. The conversion circuits 31 and 32 are logical operation circuits that implement a table reference circuit based on a truth table or the like that defines the relationship between the data d1 and the data d2. The conversion circuits 31 and 32 are also referred to as S-BOX (substitution box).

  In the processing unit 3, N of the plurality of conversion circuits 31 is selected for each data of the third bit number (16 bits in FIG. 1) that is N times (N is an integer of 2 or more) the second bit number of the data D1. N conversion circuits 32 among the conversion circuits 31 or the plurality of conversion circuits 32 are assigned. In the present embodiment, N = 4. Specifically, in the processing unit 3, the conversion circuit 32 is allocated to each of the four data d1 from the LSB to the fifteenth bit of the data D1. The conversion circuit 31 is assigned to four data d1 of 16th to 31st bits of the data D1. The conversion circuit 32 is assigned to four data d1 from the 32nd to 47th bits of the data D1. The conversion circuit 31 is assigned to four data d1 from the 48th bit to the MSB of the data D1.

  The linear processing unit 4 is a circuit that linearly processes the data D2. The linear processing unit 4 generates data Dout by linearly processing the data D2. The data Dout is data having a first bit number. The linear processing unit 4 outputs the data Dout as output data from the circuit unit 10. The linear processing unit 4 includes a shuffle circuit 41, a shift circuit 42, and an XOR execution circuit 43.

  The shuffle circuit 41 is a circuit that performs shuffle processing on the data D2. The shuffle process is a process of changing the arrangement order of the plurality of data d2 arranged in parallel included in the data D2. The shuffle circuit 41 shuffles the data D2 to generate data D3. The shuffle circuit 41 outputs the data D3 to the shift circuit 42. Data D3 is data having a first bit number. As shown in FIG. 2, the shuffle circuit 41 has a plurality of (here, four) shuffle circuits 41 a to 41 d (unit processing circuits). Each of the shuffle circuits 41a to 41d is a circuit that performs shuffle processing (linear processing) with unit data having the third bit number as a processing unit. Each of the shuffle circuits 41a to 41d changes the arrangement order of N (here, N = 4) data d2 included in unit data. The shuffle circuits 41a to 41d are arranged in parallel, and each of the shuffle circuits 41a to 41d is assigned to one of the four conversion circuits 31 and the four conversion circuits 32.

  Specifically, the shuffle circuit 41a is assigned to the four conversion circuits 32, and performs shuffle processing with the four data d2 from the LSB to the fifteenth bit of the data D2 as unit data. The shuffle circuit 41a outputs the shuffle processing result as data d3a to a shift circuit 42a described later. The shuffle circuit 41a places the data d2 from the LSB to the third bit of the data D2 at the eighth to eleventh bit positions in the data d3a, and the fourth to seventh bits of the data D2 Data d2 are arranged at the 12th to 15th bit positions in the data d3a. Shuffle circuit 41a places data d2 from the eighth to eleventh bits of data D2 at the third bit position from the LSB in data d3a to the twelfth to fifteenth bits of data D2 Data d2 are arranged at the fourth to seventh bit positions in data d3a.

  The shuffle circuit 41b is assigned to the four conversion circuits 31, and performs shuffle processing using four data d2 from the 16th to 31st bits of the data D2 as unit data. The shuffle circuit 41b outputs the shuffle processing result as data d3b to a shift circuit 42b described later. The shuffle circuit 41c is assigned to the four conversion circuits 32, and performs shuffle processing using four data d2 from the 32nd to 47th bits of the data D2 as unit data. The shuffle circuit 41c outputs the shuffle processing result as data d3c to a shift circuit 42c described later. The shuffle circuit 41d is assigned to the four conversion circuits 31, and performs shuffle processing using four data d2 from the 48th bit to the MSB of the data D2 as unit data. The shuffle circuit 41d outputs the shuffle processing result as data d3d to a shift circuit 42d described later.

  Data d3a to d3d are part of data D3 and have a third bit number. Data d3a to d3d are data obtained by dividing all the data from the LSB to the MSB of the data D3 in the unit of the third bit number in the order of bit numbers. In FIG. 2, data D3 is configured by the data d3a to d3d. The shuffle circuits 41b to 41d change the arrangement order of the plurality of data d2 in the same manner as the shuffle circuit 41a except that the plurality of (in this case, four) pieces of data d2 to be shuffled are different. Do. In the shuffle circuits 41a to 41d shown in FIG. 2, 4-bit data are shown as one line.

  The shift circuit 42 is a circuit that performs shift processing on the data D3. The shift process is a process of shifting each of the data d3a to d3d included in the data D3 by a predetermined number of bits. The shift circuit 42 shifts the data D3 to generate data D4. The shift circuit 42 outputs the data D4 to the XOR execution circuit 43. Data D4 is data having a first bit number. The shift circuit 42 has a plurality of (here, four) shift circuits 42 a to 42 d (unit processing circuits). The shift circuits 42a to 42d are arranged in parallel and assigned to data d3a to d3d, respectively. Each of the shift circuits 42a to 42d performs left shift processing (linear processing) with unit data having the third bit number as a processing unit.

  Specifically, the shift circuit 42a shifts the data d3a by 1 bit (shifts left) using the data d3a as unit data. The left shift is a process of cyclically shifting all the bits contained in the data to be shifted to a predetermined number of bits higher. The shift circuit 42a outputs the shift processing result as data d4a to XOR operation circuits 43a and 43c described later. In the shift process of shift circuit 42a, for example, the bit located in the LSB of data d3a is shifted to the first bit position in data d4a, and the first bit in data d3a is the second in data d4a , And the fifteenth bit of the data d3a is shifted to the bit position of the LSB in the data d4a.

  The shift circuit 42b shifts the data d3b to the left by 4 bits, using the data d3b as unit data. The shift circuit 42 b outputs the shift processing result as data d 4 b to an XOR operation circuit 43 b described later. The shift circuit 42 c shifts the data d 3 c to the left by 7 bits, using the data d 3 c as unit data. The shift circuit 42c outputs the shift processing result as data d4c to an XOR operation circuit 43c described later. The shift circuit 42d shifts the data d3d to the left by 9 bits, using the data d3d as unit data. The shift circuit 42d outputs the shift processing result as data d4d to XOR operation circuits 43b and 43d described later. Data d4a to d4d are part of data D4 and have a third bit number. The data d4a to d4d are data obtained by dividing all the data from the LSB to the MSB of the data D4 in the order of bit numbers in units of the third bit number. In FIG. 2, data D4 is configured by the data d4a to d4d. Note that FIG. 2 shows data d3a to d3d and data d4a to d4d, in which 16 bits of data are grouped into one line.

  The XOR execution circuit 43 is a circuit that performs an XOR operation process on the data D4. The XOR execution circuit 43 generates data Dout by performing an XOR operation process on the data D4. The XOR execution circuit 43 outputs the data Dout as output data from the circuit unit 10. The XOR execution circuit 43 has a plurality of (here, four) XOR operation circuits 43a to 43d. The XOR operation circuits 43a to 43d are arranged in parallel and assigned to the data d4a to d4d, respectively. Each of the XOR operation circuits 43a to 43d performs an XOR operation process (linear process) on the data d4a to d4d.

  Specifically, the XOR operation circuit 43c performs an XOR operation of the data d4a and the data d4c. The XOR operation circuit 43c outputs the operation result as data of the 32nd to 47th bits of the data Dout, and outputs the operation result to the XOR operation circuit 43d. The XOR operation circuit 43b performs an XOR operation on the data d4b and the data d4d. The XOR operation circuit 43b outputs the operation result as data from the 16th to 31st bits of the data Dout, and outputs the operation result to the XOR operation circuit 43a. The XOR operation circuit 43a performs an XOR operation on the data d4a and the operation result of the XOR operation circuit 43b. The XOR operation circuit 43a outputs the operation result as data from the LSB to the fifteenth bit of the data Dout. The XOR operation circuit 43d performs an XOR operation on the data d4d and the operation result of the XOR operation circuit 43c. The XOR operation circuit 43d outputs the operation result as data from the 48th bit to the MSB of the data Dout.

  FIG. 3 is a view showing a modification of the digital processing device according to the first embodiment. The digital processing device 1A shown in FIG. 3 differs from the digital processing device 1 shown in FIG. 1 in the assignment of the plurality of conversion circuits 31 and the plurality of conversion circuits 32 in the processing unit 3. Specifically, in the digital processing device 1A, the conversion circuit 31 is allocated to each of the four data d1 from the LSB to the fifteenth bit of the data D1. The conversion circuit 32 is assigned to four data d1 of 16th to 31st bits of the data D1. The conversion circuit 31 is assigned to four data d1 from the 32nd to 47th bits of the data D1. Conversion circuit 32 is assigned to each of four data d1 from the 48th bit to the MSB of data D1.

  Next, a method of manufacturing the digital processing device 1 will be described. Here, the case of using an FPGA as a programmable logic device will be described. The circuit unit 10 included in the digital processing device 1 is created using an FPGA. In the manufacture of the digital processing device 1, first, a program such as a circuit designer or the like in which a circuit function of the circuit unit 10 is described in a hardware description language is created. Then, the circuit function of the circuit unit 10 is written to the FPGA based on the program by a dedicated tool or the like, whereby the circuit unit 10 is created on the FPGA. Note that the FPGA in which the circuit function is not written is manufactured in advance. The manufacturing method of the digital processing device 1 includes a description step and a creation step.

  The description process is a process of describing the function of the circuit unit 10 provided in the digital processing device 1 according to the FPGA. Specifically, the circuit functions of the cryptographic data generation unit 2, the processing unit 3 and the linear processing unit 4 are described in a hardware description language corresponding to the FPGA. The program describing the circuit function includes a first part for creating a plurality of conversion circuits 31 in the FPGA and a second part for creating a plurality of conversion circuits 32 in the FPGA. The circuit functions of the conversion circuit 31 and the conversion circuit 32 are described so that the output value is uniquely determined for the input value based on the truth table or the like.

  The circuit functions of the plurality of conversion circuits 31 are described by a look-up table description method. That is, the first part of the program is described using the look-up table description method. Specifically, the 4-bit data d1 value (input value) and the data d2 value (output value) are expressed in hexadecimal numbers, and all hexadecimal input values 0 to F (in binary numbers 0000 to 1111) The circuit functions of the conversion circuits 31 are described so as to uniquely associate hexadecimal output values 0 to F with each other. The circuit function of each conversion circuit 31 associates, for example, B (1011 in binary number) as an output value with an input value of 2 (0010 in binary number), for an input value of 3 (binary number 0011) It is described that 1 (binary number 0001) is associated as an output value. Note that the input value and the output value may be uniquely associated by representing the input value and the output value in decimal.

The circuit functions of the plurality of conversion circuits 32 are described by the Boolean algebra description system. That is, the second part of the program is described using the Boolean algebraic description system. Specifically, the circuit function of each conversion circuit 32 is described so that each bit of data d2 is represented by a Boolean algebra (logical operation expression) including a plurality of bits of data d1. Assuming that the data d1 is (x3, x2, x1, x0) in binary notation, and the data d2 is (y3, y2, y1, y0) in binary notation, y0 of the data d2 is, for example, the following formula (1) Described by Boolean algebra like. here,! Denotes the negation (NOT) of xn (n is 0 to 3), & denotes the logical product (AND) operation, and | denotes the logical sum (OR) operation. Similarly, the other bits y1, y2 and y3 of the output value are also described by Boolean algebra uniquely determined from each bit (x0, x1, x2, x3) of the data d1.
y0 = (! x3 &! x2 & x1) | (! x2 & x1 & x0) | (! x3 & x2 &! x1) | (x2 &! x1 & x0) | (x3 &! x2 &! x1 &! x0) | (x3 & x2 & x1 &! x0) ... (1)

  The circuit functions of the conversion circuit 31 and the conversion circuit 32 are described so as to output the same value of the data d2 if the values of the data d1 are the same. A program including descriptions of circuit functions of the plurality of conversion circuits 31 and the plurality of conversion circuits 32 is also referred to as a source file. The program in which the circuit function is described is provided by being stored in a storage medium such as a flexible disk, a compact disc-read only memory (CD-ROM), a digital versatile disc (DVD) or a ROM, or a semiconductor memory. Also, the program described above may be provided via a network as a computer data signal superimposed on a carrier wave.

  Subsequently, the circuit unit 10 is created in the FPGA based on the circuit function described in the above program (creation step). In the creating step, for example, the above-mentioned program is converted into a net list obtained by translating the hardware description language into an intermediate language by a dedicated tool. Then, write data (object file) for writing to the FPGA is created from the netlist. Then, the write data is written to the FPGA by the write tool (configuration), whereby the circuit unit 10 including the processing unit 3 and the linear processing unit 4 in the FPGA is created. The digital processing device 1A is also manufactured in the same manner as the digital processing device 1.

Next, verification results of the effects of the digital processing devices 1 and 1A according to the first embodiment will be described. Tables 1 and 2 show the verification results when using Xilinx sp6 (product name) as the FPGA. The first verification example is the verification result in the digital processing device 1 shown in FIG. The second verification example is the verification result in the digital processing device 1A shown in FIG. The first comparative example is a comparison result when all conversion circuits included in the processing unit 3 are created based on the lookup table description method, and the second comparative example is all Boolean conversion description included in the conversion circuits included in the processing unit 3 It is a comparison result at the time of creating based on a system. Each of the digital processing devices in the first verification example, the second verification example, the first comparative example, and the second comparative example includes 24 circuit units. Table 1 shows the verification results in the case where each bit of input data and output data of the digital processing device is not assigned to a specific input / output terminal on the FPGA (IO-Floated). Further, Table 2 shows verification results in the case where each bit of input data and output data of the digital processing device is assigned to a specific input / output terminal on the FPGA (IO-Stuck). As an optimization option for circuit synthesis, select an option that places emphasis on the operating speed in the case of IO-Floated, and an option that places importance on the operating speed but gives a balance with the mounting area in the case of IO-Stuck. , Verified.

  With regard to the evaluation items in Table 1, “LUTs” is a look-up table that configures the logic block of the FPGA in order to realize the circuit configurations of the first verification example, the second verification example, the first comparative example, and the second comparative example. Indicates the number of units used and the unit is one. “Mounting area” indicates the mounting area of the circuit created in the FPGA, in this case, the number of used slices of the predetermined number of lookup tables and flip-flops of the FPGA, and the unit is the number of slices. "Operating speed" is the maximum frequency at which a digital processing device can operate, and its unit is megahertz (MHz). “Power consumption” indicates power consumed by a circuit created on an FPGA at an operating speed of 10 MHz, and its unit is milliwatt (mW).

  As shown in Tables 1 and 2, in the first verification example, the second verification example, the first comparative example, and the second comparative example, the number of look-up tables used on the FPGA was the same. In the case of IO-Floated, in the verification result of the first verification example, the mounting area is smaller than in the first comparative example and the second comparative example, and in the verification result of the second verification example, the operation speed is the first comparative example and It is faster than the second comparative example. On the other hand, in the case of the IO-Stuck, in the verification result of the first verification example, the mounting area becomes smaller compared to the first comparative example and the second comparative example, and the operation speed is further compared to the first comparative example and the second comparative example. It became faster. Further, in the verification result of the second verification example, the mounting area is smaller than that of the first comparative example and the second comparative example, and the operation speed is faster than that of the first comparative example and the second comparative example.

  In the case of IO-Floated, in the verification results of the first verification example and the second verification example, the power consumption is smaller than that of the comparative example of the first comparative example and the second comparative example where the power consumption is large. On the other hand, in the case of the IO-Stuck, in the verification result of the first verification example, the power consumption is smaller than that of the comparative example in which the power consumption is large among the first comparative example and the second comparative example. In the verification results of the second verification example, the power consumption is smaller than in the first comparative example and the second comparative example. From the above, it can be seen that in the first verification example and the second verification example, the performance is improved without causing a significant increase in power consumption as compared with the first comparative example and the second comparative example.

  In such digital processing devices 1 and 1A, each of the shuffle circuits 41a to 41d (unit processing circuits) and each of the shift circuits 42a to 42d (unit processing circuits) are four times the second bit number (4 bits). Linear processing is performed with unit data having a certain third bit number (16 bits) as a processing unit. Further, in the processing unit 3, four conversion circuits 31 or four conversion circuits 32 are allocated to each processing unit. The processing unit 3 mixes the conversion circuits 31 and 32 created based on different description methods, and assigns four conversion circuits 31 and 32 created based on the same description method for each processing unit. Although various circuits created in an FPGA (programmable logic device) are based on being distributed at random and distributed, circuits based on the same description system tend to be placed together. Therefore, by allocating four conversion circuits 31 and 32 created based on the same description method for each processing unit, the possibility that the four conversion circuits 31 and 32 are collectively arranged is increased. As a result, the mounting area of the circuit created in the FPGA can be reduced, or the processing speed of the circuit can be increased, so that the performance of the digital processing device can be improved.

  The shuffle circuits 41a to 41d (unit processing circuits) change the arrangement order of the four data d2 (second partial data) included in the unit data. When the four conversion circuits 32 supplying the four data d2 processed by the shuffle circuit 41a are arranged in a distributed manner, the total wiring length of the lines from the four conversion circuits 32 to the shuffle circuit 41a is It can be large. On the other hand, since the four conversion circuits 32 for supplying the four data d2 processed by the shuffle circuit 41a tend to be arranged collectively, there is a high possibility that the total of the wiring lengths becomes small. This reduces the mounting area of the circuit created in the FPGA and increases the possibility of increasing the processing speed. The same applies to the shuffle circuits 41b to 41d.

  The shift circuits 42a to 42d (unit processing circuits) shift the data d3a to d3d (unit data) by a predetermined number of bits. When the four conversion circuits 32 supplying data d3a processed by the shift circuit 42a via the shuffle circuit 41a are distributed, the four conversion circuits 32 via the shuffle circuit 41a shift circuit 42a. The total of the wire lengths of the wires up to the point may be large. On the other hand, since the four conversion circuits 32 tend to be arranged collectively, the possibility that the total of the wiring lengths becomes small increases. This reduces the mounting area of the circuit created in the FPGA and increases the possibility of increasing the processing speed. The same applies to the shift circuits 42b to 42d.

  Each of the plurality of conversion circuits 31 (first conversion circuit) and each of the plurality of conversion circuits 32 (second conversion circuit) perform non-linear conversion processing. Therefore, it is possible to make it difficult to deduce the input data of the digital processing devices 1 and 1A from the output data of the digital processing devices 1 and 1A.

  FIG. 4 is a diagram showing the configuration of a digital processing device according to the second embodiment. FIG. 5 is a diagram for explaining array conversion processing of the array processing circuit of FIG. The digital processing device 5 shown in FIG. 4 is a device for performing cryptographic processing conforming to the PRINTcipher standard. The digital processing device 5 is different from the digital processing device 1 according to the first embodiment in that the first bit number of input data and output data is 48 bits, and in place of the processing unit 3 and the linear processing unit 4 , And in that the processing unit 7 and the linear processing unit 6 are provided.

  In the digital processing device 5, the encryption data generation unit 2 performs an XOR operation on the data Din and the encryption key data, and outputs the operation result to the linear processing unit 6 as data D1. Data Din and D1 have a first bit number. In the present embodiment, the bit number of the MSB in the data Din is the 47th. The same applies to data D1 and data D5, D6, D7, and Dout described later. The linear processing unit 6 linearly processes the data D1 and outputs the linear processing result to the processing unit 7 as data D7 (first data). Data D7 is data having a first number of bits. The linear processing unit 6 includes an array conversion circuit 61, an XOR execution circuit 62, and a replacement circuit 63.

  The array conversion circuit 61 is a circuit that performs array conversion processing (linear processing) on the data D1. The array conversion process is a process of changing the array of a plurality of bits included in the data D1. The array conversion circuit 61 generates data D5 by performing an array conversion process of the data D1. The array conversion circuit 61 outputs the data D5 to the XOR execution circuit 62. Data D5 is data having a first bit number.

  As shown in FIG. 5, the array conversion circuit 61 arranges each bit from the 0th to the 15th bit number m in the data D1 at the (3 × m) th bit position in the data D5. The array conversion circuit 61 arranges each bit having the bit number m of the data D1 from the 16th to the 31st at the {3 × (m−16) +1} th bit position in the data D5. The array conversion circuit 61 arranges each bit of the bit number m of the data D1 from the 32nd to the 47th at the {3 × (m-32) +2} th bit position in the data D5.

  The XOR execution circuit 62 is a circuit that performs an XOR operation process on the data D5. The XOR execution circuit 62 generates data D6 by performing an XOR operation process on the data D5. The XOR execution circuit 62 outputs the data D6 to the substitution circuit 63. Data D6 is data having a first number of bits. The XOR execution circuit 62 includes an XOR operation circuit 62a. The XOR operation circuit 62a is assigned to data d51 from the LSB to the fifth bit of the data D5. The XOR operation circuit 62a performs an XOR operation process (linear process) on the data d51. The XOR operation circuit 62a outputs the operation result as data d61 to the replacement circuit 63. The XOR execution circuit 62 outputs the data d52 from the sixth bit of the data D5 to the MSB as the data d62 to the replacement circuit 63 without changing the value.

  Data d51 is a part of data D5, and has a third bit number (here, 6 bits). Data d52 is a part of data D5. The data D5 is composed of the data d51 and the data d52. Data d61 is a part of data D6 and has a third bit number. Data d62 is part of data D6. The data d6 is composed of the data d61 and the data d62. Data d52 and data d62 have the same number of bits (here, 42 bits).

  The XOR operation circuit 62a (unit processing circuit) performs an XOR operation of the data d51 and the round constant data. The XOR operation circuit 62a performs XOR operation processing (linear processing) with data d51 having a third bit number which is N times (N is an integer of 2 or more) the second bit number as unit data. In the present embodiment, N = 2. The round constant data is stored in advance in a memory (not shown), and is input from the memory to the XOR operation circuit 62a. The round constant data may be sequentially generated by a round constant generation circuit (not shown) and may be input from the round constant generation circuit to the XOR operation circuit 62a. Round constant data has a third bit number. The round constant data may have different values in each of the plurality of circuit units 10 included in the digital processing device 5.

  The replacement circuit 63 is a circuit that performs a replacement process on the data D6. The replacement process is a process of mutually replacing the bit position of each bit included in data having the second bit number (here, 3 bits) of the data D6. The substitution circuit 63 generates data D7 by performing substitution processing on data D6. Replacement circuit 63 outputs data D7 to processing unit 7. Data D7 is data having a first bit number. The substitution circuit 63 has a plurality of (in this case, sixteen) individual substitution circuits 64. The plurality of individual replacement circuits 64 are arranged in parallel, and each of the plurality of individual replacement circuits 64 is sequentially assigned from the LSB for each data having the second bit number in the data D6. The individual replacement circuit 64 performs a replacement process (linear process) on the data having the second bit number of the data D6.

  Specifically, the individual replacement circuit 64 interchanges the bit positions of the bits of the data input to the individual replacement circuit 64 in accordance with the 2-bit round key. The round key is stored in advance in a memory (not shown), and is input to each individual replacement circuit 64 from the memory. The round keys may be sequentially generated by a round key generation circuit (not shown), and may be input from the round key generation circuit to each individual replacement circuit 64. The round key may have different values in each of the plurality of circuit units 10 included in the digital processing device 5. The individual substitution circuit 64 changes the bit positions of each bit differently depending on the value of the round key. For example, when the value of the 2-bit round key is (0, 1), the individual replacement circuit 64 converts 3-bit data (p2, p1, p0) input to the individual replacement circuit 64 into bit positions of each bit. Are replaced with the replaced data (p1, p2, p0). When the value of the round key is (1, 0), the individual replacement circuit 64 replaces the data (p2, p1, p0) with the data (p2, p0, p1).

  Each individual substitution circuit 64 generates data d7 (first partial data) by performing substitution processing. Each individual replacement circuit 64 outputs the data d7 to the conversion circuit 31 or the conversion circuit 32. Data d7 is part of data D7 and has a second bit number. The plurality of data d7 is data obtained by dividing all the data from the LSB to the MSB of the data D7 in the order of bit numbers in units of the second number of bits. In FIG. 4, the data D <b> 7 is configured by the sixteen data d <b> 7.

  The processing unit 7 is a circuit that converts the data D7 into data Dout (second data). Data Dout is data having a first number of bits. Specifically, the processing unit 7 generates data Dout by performing non-linear conversion processing of the data D7. The processing unit 7 outputs the data Dout as output data from the circuit unit 10. In the processing unit 7, a plurality of conversion circuits 31 (a plurality of first conversion circuits) and a plurality of conversion circuits 32 (a plurality of second conversion circuits) are arranged in parallel. Data d7 is input to each conversion circuit 31 and each conversion circuit 32. Each of the plurality of conversion circuits 31 and each of the plurality of conversion circuits 32 performs conversion processing on the data d7 input thereto, and the processing unit 7 converts the data D7 into data Dout.

  Each conversion circuit 31 and each conversion circuit 32 convert data d7 to generate data dout (second partial data). The data dout has a second bit number. The data dout is part of data Dout. The plurality of data dout are data obtained by dividing all the data from the LSB to the MSB of the data Dout in the order of bit numbers in units of the second number of bits. In FIG. 4, the data Dout is composed of 16 pieces of data dout.

  In the processing unit 7, N of the plurality of conversion circuits 31 (here, N = 2) for each data of the third bit number N times (here, N = 2) the second bit number in the data D 7 Of the plurality of conversion circuits 32 (here, N = 2) among the plurality of conversion circuits 32 are allocated. Specifically, in the processing unit 7, the conversion circuit 31 is allocated to two data d7 from the LSB to the fifth bit of the data D7. The conversion circuit 31 is assigned to each of the two data d7 from the sixth to the eleventh bits of the data D7. The conversion circuit 31 is assigned to two data d7 of the 12th to 17th bits of the data D7. The conversion circuit 31 is assigned to two data d7 from the eighteenth to twenty-third bits of the data D7.

  In the processing unit 7, the conversion circuit 32 is assigned to each of the two data d7 from the 24th to 29th bits of the data D7. The conversion circuit 32 is assigned to two pieces of data d7 from the 30th bit to the 35th bit of the data D7. The conversion circuit 32 is assigned to two data d7 from the 36th to the 41st bit of the data D7. Conversion circuit 32 is assigned to two data d7 from the 42nd bit of data D7 to the MSB.

  FIG. 6 is a view showing a modification of the digital processing device according to the second embodiment. The digital processing device 5A shown in FIG. 6 is different from the digital processing device 5 shown in FIG. 4 in the assignment of the plurality of conversion circuits 31 and the plurality of conversion circuits 32 in the processing unit 7. Specifically, in the digital processing device 5A, the conversion circuit 31 is assigned to each of the two data d7 from the LSB to the fifth bit of the data D7. The conversion circuit 32 is assigned to two data d7 of the sixth to eleventh bits of the data D7. The conversion circuit 31 is assigned to two data d7 of the 12th to 17th bits of the data D7. The conversion circuit 32 is assigned to two data d7 of the 18th to 23rd bits of the data D7.

  In the digital processing device 5A, the conversion circuit 31 is allocated to the two data d7 from the 24th to the 29th bit of the data D7. The conversion circuit 32 is assigned to two pieces of data d7 from the 30th to 35th bits of the data D7. The conversion circuit 31 is assigned to two pieces of data d7 from the 36th to 41st bits of the data D7. Conversion circuit 32 is assigned to two data d7 from the 42nd bit of data D7 to the MSB.

  The digital processing devices 5 and 5A according to the second embodiment are manufactured using an FPGA in the same manner as the digital processing devices 1 and 1A according to the first embodiment. In the manufacture of the digital processing devices 5 and 5A, the circuit functions of the circuit unit 10 including the linear processing unit 6 and the processing unit 7 in the hardware description language, as in the manufacture of the digital processing devices 1 and 1A according to the first embodiment. The described program is created.

Next, verification results of the effects of the digital processing devices 5 and 5A according to the second embodiment will be described. Tables 3 and 4 show verification results when using Xilinx sp6 (product name) as an FPGA. The third verification example is the verification result in the digital processing device 5 shown in FIG. The fourth verification example is a verification result in the digital processing device 5A shown in FIG. The third comparative example is a comparison result when all conversion circuits included in the processing unit 7 are created based on the lookup table description method, and the fourth comparative example is all Boolean conversion description included in the conversion circuits included in the processing unit 7 It is a comparison result at the time of creating based on a system. Each of the digital processing devices in the third verification example, the fourth verification example, the third comparative example, and the fourth comparative example includes 48 circuit units. Table 3 shows the verification results in the case of IO-Floated, and Table 4 shows the verification results in the case of IO-Stuck. As an optimization option of the circuit synthesis, verification was performed by selecting an option in which the operating speed is emphasized in both of IO-Floated and IO-Stuck but the balance with the mounting area is also taken into consideration.

  As shown in Tables 3 and 4, in the third verification example, the fourth verification example, the third comparative example, and the fourth comparative example, the number of look-up tables used on the FPGA was the same. In the case of IO-Floated, in the verification result of the third verification example, the mounting area is smaller than in the third comparative example and the fourth comparative example, and the operation speed is faster than in the third comparative example and the fourth comparative example. became. According to the verification result of the fourth verification example, the mounting area is smaller than that of the third comparative example and the fourth comparative example, and the operation speed is faster than that of the third comparative example and the fourth comparative example. On the other hand, in the case of the IO-Stuck, in the verification result of the third verification example, the mounting area becomes smaller compared to the third comparative example and the fourth comparative example, and the operation speed is further compared to the third comparative example and the fourth comparative example. It became faster. Further, in the verification result of the fourth verification example, the operation speed is faster than that of the third comparative example and the fourth comparative example.

  In the case of IO-Floated, in the verification result of the third verification example, the power consumption is smaller than that of the comparative example in which the power consumption is large among the third comparative example and the fourth comparative example. In the verification result of the fourth verification example, the power consumption is smaller than in the third comparative example and the fourth comparative example. On the other hand, in the case of the IO-Stuck, in the verification results of the third verification example and the fourth verification example, the power consumption is smaller than in the third comparative example and the fourth comparative example. From the above, it can be seen that in the third verification example and the fourth verification example, the performance is improved without causing a significant increase in power consumption as compared with the third comparative example and the fourth comparative example.

  In such digital processing devices 5 and 5A, the XOR operation circuit 62a (unit processing circuit) processes unit data having a third bit number (6 bits) which is twice the second bit number (3 bits). Perform linear processing as Further, in the processing unit 7, two conversion circuits 31 (first conversion circuits) or two conversion circuits 32 (second conversion circuits) are allocated to each processing unit in the XOR operation circuit 62a (unit processing circuit). The processing unit 7 mixes the conversion circuits 31 and 32 created based on different description methods, and assigns two conversion circuits 31 and 32 created based on the same description method for each processing unit. Although various circuits created in an FPGA (programmable logic device) are based on being distributed at random and distributed, circuits based on the same description system tend to be placed together. For this reason, by allocating two conversion circuits 31 and 32 created based on the same description method for each processing unit, the possibility that two conversion circuits 31 and 32 are collectively arranged is increased. As a result, the mounting area of the circuit created in the FPGA can be reduced, or the processing speed of the circuit can be increased, so that the performance of the digital processing device can be improved.

  The XOR operation circuit 62a (unit processing circuit) performs an XOR operation on unit data and data having a third bit number (round key). Data based on the processing result of the XOR operation circuit 62a is input to two conversion circuits 31 allocated for each processing unit. When these two conversion circuits 31 are arranged in a distributed manner, the total of the wiring lengths of the wirings from the XOR operation circuit 62a to the two conversion circuits 31 via the replacement circuit 63 may be large. is there. On the other hand, since the two conversion circuits 31 tend to be arranged collectively, the possibility that the total of the wiring lengths becomes small increases. This reduces the mounting area of the circuit created in the FPGA and increases the possibility of increasing the processing speed.

  Note that the digital processing device, the method of manufacturing the digital processing device, and the program according to the present invention are not limited to the above embodiment.

  In the first and second embodiments, in the processing units 3 and 7, the same number of conversion circuits 31 and conversion circuits 32 in total are allocated, but the present invention is not limited to this. If the processing units 3 and 7 include a plurality of conversion circuits 31 and a plurality of conversion circuits 32, the number of conversion circuits 31 and the number of conversion circuits 32 may not be the same.

  Although the processing units 3 and 7 perform non-linear conversion processing, the present invention is not limited to this. The processing unit 3 may perform linear conversion processing of the data D1, and the processing unit 7 may perform linear conversion processing of the data D7.

  The unit processing circuits such as the shuffle circuits 41a to 41d only need to perform linear processing with unit data having a third bit number which is N times (N is an integer of 2 or more) the second bit number. In the processing units 3 and 7, N conversion circuits 31 or N conversion circuits 32 may be allocated to each processing unit.

  The digital processing devices 1, 1A, 5, 5A are devices for performing cryptographic processing, but are not limited thereto. The digital processors 1, 1A, 5, 5A may be signal processors that read the filter coefficients by means of a table lookup circuit. In addition, the digital processing devices 1, 1A, 5 and 5A may be devices provided with a circuit that performs table reference processing for converting the value of input data into output data having a value different from the value of the input data.

  1, 5 digital processing device 3, 7, processing unit 4, 6 linear processing unit 31 conversion circuit 32 conversion circuit.

Claims (10)

A digital processing device created using a programmable logic device, comprising:
A processing unit for converting first data having a first number of bits into second data having the first number of bits;
A linear processing unit that performs linear processing of the second data;
Equipped with
The processing unit includes a plurality of first conversion circuits created based on a lookup table description method, and a plurality of second conversion circuits created based on a Boolean algebra description method,
Each of the plurality of first conversion circuits and each of the plurality of second conversion circuits includes first partial data having a second number of bits of the first data and the second partial data of the second data. Convert to second partial data with bit number,
The linear processing unit has a unit processing circuit that performs linear processing with unit data having a third bit number that is N times the second bit number (N is an integer of 2 or more).
In the processing unit, N first conversion circuits among the plurality of first conversion circuits or N second conversion circuits among the plurality of second conversion circuits are allocated to each of the processing units,
Digital processing unit. The unit processing circuit changes the arrangement order of the N pieces of second partial data included in the unit data.
A digital processing device according to claim 1. The unit processing circuit shifts the unit data by a predetermined number of bits.
A digital processing device according to claim 1. A digital processing device created using a programmable logic device, comprising:
A linear processing unit which performs linear processing of predetermined data and outputs first data having a first number of bits;
A processing unit for converting the first data into second data having the first number of bits;
Equipped with
The processing unit includes a plurality of first conversion circuits created based on a lookup table description method, and a plurality of second conversion circuits created based on a Boolean algebra description method,
Each of the plurality of first conversion circuits and each of the plurality of second conversion circuits includes first partial data having a second number of bits of the first data and the second partial data of the second data. Convert to second partial data with bit number,
The linear processing unit has a unit processing circuit that performs linear processing with unit data having a third bit number that is N times the second bit number (N is an integer of 2 or more).
In the processing unit, N first conversion circuits among the plurality of first conversion circuits or N second conversion circuits among the plurality of second conversion circuits are allocated to each of the processing units,
Digital processing unit. The unit processing circuit calculates an exclusive OR of the unit data and the data having the third bit number.
The digital processing device according to claim 4. Each of the plurality of first conversion circuits and each of the plurality of second conversion circuits performs non-linear conversion processing.
The digital processing device according to any one of claims 1 to 5. A processing unit which has a plurality of first conversion circuits and a plurality of second conversion circuits and converts first data having a first number of bits into second data having the first number of bits; And a linear processing unit for performing linear processing.
A description step of describing circuit functions of the processing unit and the linear processing unit according to a programmable logic device;
A creating step of creating the processing unit and the linear processing unit in the programmable logic device based on the circuit function;
Equipped with
Each of the plurality of first conversion circuits and each of the plurality of second conversion circuits includes first partial data having a second number of bits of the first data and the second partial data of the second data. Convert to second partial data with bit number,
The linear processing unit has a unit processing circuit that performs linear processing with unit data having a third bit number that is N times the second bit number (N is an integer of 2 or more).
In the processing unit, N first conversion circuits among the plurality of first conversion circuits or N second conversion circuits among the plurality of second conversion circuits are allocated to each of the processing units,
In the description step, circuit functions of the plurality of first conversion circuits are described by a look-up table description method, and circuit functions of the plurality of second conversion circuits are described by a Boolean algebra description method.
Method of manufacturing digital processing device. A linear processing unit that performs linear processing of predetermined data and outputs first data having a first number of bits, a plurality of first conversion circuits, and a plurality of second conversion circuits; A processing unit for converting data into second data having a first number of bits;
A description step of describing circuit functions of the processing unit and the linear processing unit according to a programmable logic device;
A creating step of creating the processing unit and the linear processing unit in the programmable logic device based on the circuit function;
Equipped with
Each of the plurality of first conversion circuits and each of the plurality of second conversion circuits includes first partial data having a second number of bits of the first data and the second partial data of the second data. Convert to second partial data with bit number,
The linear processing unit has a unit processing circuit that performs linear processing with unit data having a third bit number that is N times the second bit number (N is an integer of 2 or more).
In the processing unit, N first conversion circuits among the plurality of first conversion circuits or N second conversion circuits among the plurality of second conversion circuits are allocated to each of the processing units,
In the description step, circuit functions of the plurality of first conversion circuits are described by a look-up table description method, and circuit functions of the plurality of second conversion circuits are described by a Boolean algebra description method.
Method of manufacturing digital processing device. A processing unit which has a plurality of first conversion circuits and a plurality of second conversion circuits and converts first data having a first number of bits into second data having the first number of bits; A program for causing a programmable logic device to function as a digital processing device including a linear processing unit that performs linear processing,
A first portion for creating the plurality of first conversion circuits in the programmable logic device;
A second portion for creating the plurality of second conversion circuits in the programmable logic device;
Equipped with
The first part is described using a look-up table description method,
The second part is described using a Boolean algebra description system,
Each of the plurality of first conversion circuits and each of the plurality of second conversion circuits includes first partial data having a second number of bits of the first data and the second partial data of the second data. Convert to second partial data with bit number,
The linear processing unit has a unit processing circuit that performs linear processing with unit data having a third bit number that is N times the second bit number (N is an integer of 2 or more).
In the processing unit, N first conversion circuits among the plurality of first conversion circuits or N second conversion circuits among the plurality of second conversion circuits are allocated to each of the processing units,
program. A linear processing unit that performs linear processing of predetermined data and outputs first data having a first number of bits, a plurality of first conversion circuits, and a plurality of second conversion circuits; A program for causing a programmable logic device to function as a digital processing device, comprising: a processing unit that converts data into second data having a first number of bits,
A first portion for creating the plurality of first conversion circuits in the programmable logic device;
A second portion for creating the plurality of second conversion circuits in the programmable logic device;
Equipped with
The first part is described using a look-up table description method,
The second part is described using a Boolean algebra description system,
Each of the plurality of first conversion circuits and each of the plurality of second conversion circuits includes first partial data having a second number of bits of the first data and the second partial data of the second data. Convert to second partial data with bit number,
The linear processing unit has a unit processing circuit that performs linear processing with unit data having a third bit number that is N times the second bit number (N is an integer of 2 or more).
In the processing unit, N first conversion circuits among the plurality of first conversion circuits or N second conversion circuits among the plurality of second conversion circuits are allocated to each of the processing units,
program.

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