JP2019091757A - Compound semiconductor device and manufacturing method for the same, power supply device, and high-frequency amplifier - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress an increase in off-leakage current, a decrease in mutual conductance and an increase in on-resistance. SOLUTION: A compound semiconductor device is mounted on a semiconductor laminated structure 3 including a carrier traveling layer 4, a source electrode 5 and a drain electrode 6 provided on the semiconductor laminated structure, and a semiconductor laminated structure between a source electrode and a drain electrode. A MIS (Metal-Insulator-Semiconductor) structure 10 in which an insulating film 8 and a metal layer 9 are laminated on a semiconductor laminated structure between the shotkey gate electrode and the drain electrode. It is provided with a back barrier region 11 which is provided below the MIS structure and whose bottom energy of the conduction band is higher than the regions adjacent to both sides in the direction along the carrier traveling layer. [Selection diagram] Fig. 1

Description

  The present invention relates to a compound semiconductor device, a method of manufacturing the same, a power supply device, and a high frequency amplifier.

Conventionally, there is a compound semiconductor device in which a source electrode, a drain electrode, and a gate electrode are formed on a semiconductor laminated structure.
In particular, compound semiconductor devices made of nitride semiconductors typified by GaN, AlN, InN, and mixed crystals thereof have attracted much attention as high-power electronic devices and short wavelength light emitting devices because of their excellent material properties.

  Many reports have been made on field effect transistors, particularly high electron mobility transistors (HEMTs) as high-power electronic devices, and applications such as high-power, high-efficiency amplifiers and high-power switching devices are considered. It is done.

JP 2012-23100 A JP 2013-211481 A JP 2002-359256 A

However, for example, in a general GaN-HEMT as shown in FIG. 12, as the gate length is shortened and the drain voltage is increased, the current travels below the semiconductor multilayer structure in the path shown by the arrow in the figure, There is a problem that the off leak current increases.
Therefore, in order to suppress the increase of the off leak current, a GaN-HEMT having a back barrier layer has been proposed as shown in FIG.

However, the increase in channel resistance directly under the gate electrode lowers the mutual conductance, and the access resistance due to the decrease in two-dimensional electron gas (2DEG: Dimensional electron gas) between the source electrode and the gate electrode and between the gate electrode and the drain electrode. There is a problem that the on-resistance is increased by the increase.
An object of the present invention is to suppress an increase in off-leakage current, a decrease in transconductance, and an increase in on-resistance.

  In one aspect, the compound semiconductor device is provided on a semiconductor stack structure including a carrier traveling layer, a source electrode and a drain electrode provided on the semiconductor stack structure, and a semiconductor stack structure between the source electrode and the drain electrode. (Metal-Insulator-Semiconductor) structure in which an insulating film and a metal layer are stacked on a semiconductor multilayer structure between a Schottky gate electrode, a Schottky gate electrode and a drain electrode, and metal layers constituting the MIS structure And a back barrier region where energy at the bottom of the conduction band is higher than regions adjacent to both sides in the direction along the carrier transit layer.

  In one aspect, the power supply device includes a transistor, and the transistor includes a semiconductor stack structure including a carrier traveling layer, a source electrode and a drain electrode provided on the semiconductor stack structure, and a semiconductor between the source electrode and the drain electrode. A MIS (Metal-Insulator-Semiconductor) structure in which an insulating film and a metal layer are laminated on a Schottky gate electrode provided on a laminated structure, and a semiconductor laminated structure between the Schottky gate electrode and the drain electrode And a back barrier region provided below the metal layer constituting the structure, wherein the energy at the bottom of the conduction band is higher than the regions adjacent on both sides in the direction along the carrier traveling layer.

  In one aspect, the high frequency amplifier includes an amplifier for amplifying an input signal, the amplifier includes a transistor, and the transistor includes a semiconductor laminated structure including a carrier transit layer, and a source electrode and a drain provided on the semiconductor laminated structure. An insulating film and a metal layer are laminated on the semiconductor laminated structure between the electrode, the Schottky gate electrode provided on the semiconductor laminated structure between the source electrode and the drain electrode, and the Schottky gate electrode and the drain electrode. A MIS (Metal-Insulator-Semiconductor) structure and a back provided under the metal layer constituting the MIS structure, in which the energy at the bottom of the conduction band is higher than the regions adjacent to both sides in the direction along the carrier traveling layer And a barrier region.

  In one aspect, a method of manufacturing a compound semiconductor device includes the steps of: forming a semiconductor stack structure including a carrier transit layer; forming a source electrode and a drain electrode on the semiconductor stack structure; and between the source electrode and the drain electrode Forming a Schottky gate electrode on the semiconductor laminated structure, forming an insulating film on the semiconductor laminated structure, laminating a metal layer on the insulating film and forming a MIS between the Schottky gate electrode and the drain electrode And forming the semiconductor laminated structure, in which the energy at the bottom of the conduction band is higher than the region adjacent to both sides in the direction along the carrier traveling layer. In the step of forming the back barrier region and forming the MIS structure, a metal layer constituting the MIS structure is formed above the back barrier region.

  As one aspect, it has an effect that an increase in off-leakage current, a decrease in transconductance, and an increase in on-resistance can be suppressed.

It is a typical sectional view showing the composition of the compound semiconductor device concerning a 1st embodiment. (A)-(D) are typical sectional drawing for demonstrating the manufacturing method of the compound semiconductor device concerning 1st Embodiment. It is a typical sectional view showing the composition of the compound semiconductor device concerning a 2nd embodiment. (A)-(D) are typical sectional drawing for demonstrating the manufacturing method of the compound semiconductor device concerning 2nd Embodiment. It is a typical sectional view showing the composition of the compound semiconductor device concerning a 3rd embodiment. It is a typical sectional view showing the composition of the modification of the compound semiconductor device concerning a 3rd embodiment. It is a typical sectional view showing the composition of the compound semiconductor device concerning a 4th embodiment. (A)-(D) are typical sectional drawings for demonstrating the manufacturing method of the compound semiconductor device concerning 4th Embodiment. It is a schematic plan view which shows the structure of the semiconductor device (semiconductor package) concerning 5th Embodiment. It is a schematic diagram which shows the structure of the PFC circuit contained in the power supply device concerning 5th Embodiment. It is a schematic diagram which shows the structure of the high frequency amplifier of 6th Embodiment. It is a typical sectional view for explaining the subject of the present invention. It is a typical sectional view for explaining the subject of the present invention.

Hereinafter, a compound semiconductor device according to an embodiment of the present invention, a method of manufacturing the same, a power supply, and a high frequency amplifier will be described with reference to the drawings.
First Embodiment
First, a compound semiconductor device according to the first embodiment and a method of manufacturing the same will be described with reference to FIGS. 1 and 2.

The compound semiconductor device according to the present embodiment is, for example, a field effect transistor using a compound semiconductor such as a nitride semiconductor.
Here, a field effect transistor using a nitride semiconductor, specifically, a GaN-based HEMT (GaN-HEMT) will be described as an example.
The GaN-HEMT of the present embodiment is, as shown in FIG. 1, a semiconductor multilayer structure 3 including an i-GaN electron traveling layer 2 on a semi-insulating SiC substrate 1, specifically, an i-GaN electron traveling layer 2. A semiconductor multilayer structure 3 including an i-AlGaN electron supply layer 4 is provided. In FIG. 1, 2DEG is indicated by a dotted line.

The semi-insulating SiC substrate 1 is referred to as SI (Semi-Insulating) -SiC substrate or a semiconductor substrate. The semiconductor multilayer structure 3 is also referred to as a GaN-based semiconductor multilayer structure, a nitride semiconductor multilayer structure, or a compound semiconductor multilayer structure. The i-GaN electron traveling layer 2 is also referred to as a carrier traveling layer. The i-AlGaN electron supply layer 4 is also referred to as a carrier supply layer.
Further, the present GaN-HEMT includes the source electrode 5 and the drain electrode 6 provided on the semiconductor multilayer structure 3. That is, the source electrode 5 and the drain electrode 6 are provided apart from each other on the semiconductor multilayer structure 3.

Further, the present GaN-HEMT includes a Schottky gate electrode 7 provided on the semiconductor multilayer structure 3 between the source electrode 5 and the drain electrode 6.
In addition, the present GaN-HEMT includes a MIS (Metal-Insulator-Semiconductor) structure 10 in which an insulating film 8 and a metal layer 9 are stacked on the semiconductor multilayer structure 3 between the Schottky gate electrode 7 and the drain electrode 6. .

In the present embodiment, a SiN film is provided as the insulating film 8 so as to cover the surface of the semiconductor multilayer structure 3, and the Schottky gate electrode 7 is formed on the SiN film 8 between the Schottky gate electrode 7 and the drain electrode 6. A metal layer 9 is provided which is made of the same metal material as the metal material that constitutes.
That is, on the semiconductor multilayer structure 3 between the Schottky gate electrode 7 and the drain electrode 6, a metal made of the same metal material as the metal material forming the Schottky gate electrode 7 via the SiN film as the insulating film 8. A layer 9 is provided.

This metal layer 9 can also be viewed as a gate electrode of a MIS structure provided between the Schottky gate electrode 7 and the drain electrode 6. In this case, the Schottky gate electrode 7 is referred to as a first gate electrode (Gate 1), and the gate electrode 9 of the MIS structure is also referred to as a second gate electrode (Gate 2).
The Schottky gate electrode 7 and the metal layer 9 are electrically connected to each other and have the same potential. That is, the Schottky gate electrode 7 having a different configuration and the gate electrode 9 of the MIS structure are connected in series. Thus, the present GaN-HEMT is a GaN-HEMT having dual gates at the same potential.

The metal layer 9 may be made of a metal material different from that of the Schottky gate electrode 7. In addition, although the SiN film is used as the insulating film 8, the present invention is not limited to this. For example, other insulating films (amorphous insulating films) such as SiO ₂ film, Al ₂ O ₃ film, and AlN film are used. Also good.
In addition, the present GaN-HEMT is provided below the metal layer 9 constituting the MIS structure 10, and the energy at the bottom of the conduction band is higher than the regions adjacent to both sides in the direction along the i-GaN electron traveling layer 2 I-AlGaN back barrier region 11 is provided.

In the present embodiment, the i-AlGaN back barrier region 11 is embedded in the i-GaN electron transit layer 2.
Further, in the present embodiment, the i-AlGaN back barrier region 11 is not provided below the Schottky gate electrode 7, and is provided only below the metal layer 9 constituting the MIS structure 10. That is, the i-AlGaN back barrier region 11 is not provided below the Schottky gate electrode 7 but is provided below the gate electrode 9 of the MIS structure.

Therefore, the i-AlGaN back barrier region 11 is a region where the energy at the bottom of the conduction band is adjacent to both sides in the direction along the i-GaN electron traveling layer 2 (here, i-GaN electron traveling layer 2; carrier traveling layer It is higher than the material).
A thin i-AlGaN layer may be provided so as to be continuous with the lower portion of the i-AlGaN back barrier region 11. Also in this case, in the i-AlGaN back barrier region 11, the energy at the bottom of the conduction band is higher than the regions adjacent to both sides in the direction along the i-GaN electron traveling layer 2 (here, the i-GaN electron traveling layer 2) Become.

Since it comprises in this way, it becomes possible to implement | achieve the GaN-HEMT which satisfy | fills low on-resistance, a favorable pinch off performance, and high transconductance (gm).
That is, as described above, the Schottky gate electrode 7 and the MIS structure 10 (the gate electrode 9 of the MIS structure) are provided, and these are set to the same potential to reduce parasitic resistance and channel resistance. In other words, it is provided only immediately below the metal layer (the gate electrode of the MIS structure) 9 that constitutes the MIS structure 10.

In this case, the threshold voltage of the Schottky gate electrode 7 is on the positive side of the threshold voltage of the gate electrode 9 of the MIS structure, and the threshold voltage (V _th ) of the gate electrode 9 of the MIS structure is sufficiently higher than that of the Schottky gate electrode 7 Because of the deepness, at the gate voltage at which the Schottky gate electrode 7 switches from off to on, the region directly under the gate electrode 9 of the MIS structure is sufficiently on.
Further, when the Schottky gate electrode 7 is turned off, the back barrier region 11 provided immediately under the gate electrode 9 of the MIS structure is firmly pinched off, so the off current (leakage current at the time of off) is sufficiently reduced. It becomes possible.

  Thus, low on-resistance and good pinch-off performance are realized by providing the back barrier region 11 just under the metal layer (gate electrode of MIS structure) 9 constituting the MIS structure 10, and the leakage current at the time of off By not providing the back barrier region 11 immediately below the Schottky gate electrode 7, it is possible to realize high mutual conductance.

In this case, the gate action of the entire transistor is performed by the Schottky gate electrode 7, and the reduction of the leakage current at the time of off is realized in the portion of the gate electrode 9 of the MIS structure.
Next, a method of manufacturing the GaN-HEMT according to the present embodiment will be described with reference to FIG.

Here, the case where the i-GaN buffer layer 12 is provided between the semi-insulating SiC substrate 1 and the i-GaN electron traveling layer 2 will be described by way of example (see FIG. 2D).
First, as shown in FIG. 2A, an i-GaN buffer layer 12 and a back barrier are formed on a semi-insulating SiC substrate 1 by using, for example, metal organic vapor phase epitaxy (MOVPE). An i-AlGaN layer 11X to be a region 11 is sequentially deposited.

Next, as shown in FIG. 2B, the resist is left in the back barrier region formation planned region (the region under the MIS structure planned formation region) using, for example, photolithography, and dry using, for example, a chlorine-based gas The i-AlGaN layer 11X is removed by etching.
Thus, the i-AlGaN back barrier region 11 is formed.
At this time, the underlying i-GaN layer 12 may be slightly etched away, or the i-AlGaN layer 11X may be slightly left.

Next, as shown in FIG. 2C, the i-GaN electron traveling layer 2 and the i-AlGaN electron supply layer 4 (for example, about 20 nm in thickness) are sequentially deposited again using the MOVPE method.
An i-GaN cap layer (for example, about 5 nm in thickness) may be deposited on the i-AlGaN electron supply layer 4.
As a result, the i-AlGaN back barrier region 11 is embedded in the i-GaN electron travel layer 2 to form the i-GaN electron travel layer 2 having the i-AlGaN back barrier region 11 therein, and the i-GaN electron travel layer 2 is formed thereon. The AlGaN electron supply layer 4 is laminated to form the semiconductor laminated structure 3.

Further, an i-AlGaN back barrier region 11 is formed in which the energy at the bottom of the conduction band is higher than the regions adjacent to both sides in the direction along the i-GaN electron traveling layer (carrier traveling layer) 2.
The process up to here is referred to as the process of forming the semiconductor laminated structure 3 including the carrier traveling layer 2.

Next, although not shown, an opening is provided in the element isolation region using, for example, photolithography, and element isolation is performed by, for example, dry etching using chlorine gas or ion implantation.
When the i-GaN cap layer is deposited, a resist mask having an opening in a region for forming a source electrode / drain electrode is provided using, for example, photolithography, and dry etching using a chlorine-based gas is performed, for example. , I-AlGaN electron supply layer 4 is exposed. At this time, the i-AlGaN electron supply layer 4 may be scraped a little.

  Next, as shown in FIG. 2D, for example, Ti (i.e., Ti (Al) on each i-AlGaN electron supply layer 4 in the region where the source electrode / drain electrode is to be formed, using photolithography and evaporation / liftoff techniques, for example. A source electrode 5 and a drain electrode 6 of about 20 nm / Al (about 200 nm) are formed. In this case, Ti is positioned closer to the semiconductor multilayer structure 3 (here, the i-AlGaN electron supply layer 4).

Then, heat treatment is performed, for example, at about 400 ° C. to about 1000 ° C., for example, about 550 ° C. in a nitrogen atmosphere to establish ohmic characteristics of the source electrode 5 and the drain electrode 6.
Note that this process is called a process of forming the source electrode 5 and the drain electrode 6 on the semiconductor multilayer structure 3.
Next, as shown in FIG. 2D, SiN is deposited on the entire surface to a thickness of about 2 nm to about 1000 nm, for example, about 100 nm using, for example, a plasma CVD (Chemical Vapor Deposition) method to form a SiN film (insulating film). Form 8

Thereby, a SiN film as the insulating film 8 is formed so as to cover the surface of the semiconductor multilayer structure 3 (here, the surface of the i-AlGaN electron supply layer 4).
Note that the formation method may be atomic layer deposition (ALD), sputtering, or the like. Further, this process is referred to as a process of forming the insulating film 8 on the semiconductor multilayer structure 3.
Next, as shown in FIG. 2D, for example, using photolithography, a resist mask (not shown) having an opening in a region where a Schottky gate electrode is to be formed is formed. For example, a fluorine-based gas is used. The SiN film 8 in the region where the Schottky gate electrode is to be formed is removed by dry etching.

  Next, as shown in FIG. 2D, for example, on the semiconductor laminated structure 3 in the region where the Schottky gate electrode is to be formed (here, on the i-AlGaN electron supply layer 4) using photolithography and deposition / liftoff techniques. And the Schottky gate electrode 7 made of, for example, Ni (about 30 nm) / Au (about 400 nm) on the insulating film 8 (here, on the SiN film) in the formation planned region of the metal layer 9 constituting the MIS structure 10 And the metal layer 9 constituting the MIS structure 10 is formed. Thereby, the MIS structure 10 is formed above the i-AlGaN back barrier region 11.

In this case, Ni is positioned closer to the semiconductor multilayer structure 3 (here, the i-AlGaN electron supply layer 4) and the insulating film 8 (SiN film). Further, the step of forming the Schottky gate electrode 7 and the step of forming the MIS structure 10 are performed in the same step.
This step is referred to as a step of forming the Schottky gate electrode 7 on the semiconductor multilayer structure 3 between the source electrode 5 and the drain electrode 6. Also, this step is referred to as a step of forming the MIS structure 10 between the Schottky gate electrode 7 and the drain electrode 6 by laminating the metal layer 9 on the insulating film 8.

Thus, the GaN-HEMT according to the present embodiment can be manufactured.
Therefore, the compound semiconductor device according to the present embodiment and the method for manufacturing the same have the effect of suppressing an increase in off-leakage current, a decrease in mutual conductance, and an increase in on-resistance.
In particular, as described above, in the GaN-HEMT, low on-resistance and good pinch-off performance can be achieved by arranging the back barrier region 11 only at the minimum necessary location (immediately below the metal layer 9 constituting the MIS structure 10). It is possible to realize a GaN-HEMT device satisfying high transconductance. This transistor can be used, for example, in a high frequency amplifier or a switching semiconductor device.

In addition, semiconductor laminated structure 3 of the above-mentioned embodiment is an example, and may be another semiconductor laminated structure. For example, any semiconductor laminated structure that can constitute a field effect transistor may be used. The semiconductor multilayer structure 3 is also referred to as a semiconductor epitaxial structure.
Further, for example, although the SiC substrate is used in the above-described embodiment, the present invention is not limited to this. For example, another substrate such as a semiconductor substrate such as a sapphire substrate, a Si substrate, or a GaAs substrate may be used. . Moreover, in the above-mentioned embodiment, although the semi-insulating substrate is used, it is not limited to this, for example, a conductive substrate of n-type conductivity or p-type conductivity may be used.

Also, for example, the layer structure of the source electrode 5, the drain electrode 6, the Schottky gate electrode 7 and the metal layer 9 in the above-described embodiment is an example, and another layer structure may be used. For example, the layer structure of the source electrode 5, the drain electrode 6, the Schottky gate electrode 7 and the metal layer (the gate electrode of the MIS structure) 9 in the above-described embodiment may be a single layer or multiple layers. good. Further, the method of forming the source electrode 5, the drain electrode 6, the Schottky gate electrode 7 and the metal layer (the gate electrode of the MIS structure) 9 in the above embodiment is merely an example, and it is formed by any other method. Also good.
Second Embodiment
Next, a compound semiconductor device according to the second embodiment and a method of manufacturing the same will be described with reference to FIGS. 3 and 4.

In the compound semiconductor device according to the present embodiment, as shown in FIG. 3, the Schottky gate electrode 7 and the metal layer 9 forming the MIS structure 10 are integrated with those of the above-described first embodiment (see FIG. 1). The point is different.
That is, in the present GaN-HEMT, as shown in FIG. 3, the portion 7X on the drain electrode 6 side of the Schottky gate electrode 7 is provided on the insulating film 8 (here, the SiN film), and the drain electrode It extends towards the 6 side.

A portion 7 </ b> X extending toward the drain electrode 6 of the Schottky gate electrode 7 functions as the metal layer 9 constituting the MIS structure 10. That is, on the semiconductor multilayer structure 3, the insulating film 8 and the metal layer 9 which is the portion 7 X extending toward the drain electrode 6 of the Schottky gate electrode 7 are stacked, and the MIS structure 10 is configured. .
Although FIG. 3 exemplifies the case where the buffer layer 12 is provided, the buffer layer 12 may not be provided.

The other configuration is the same as that of the first embodiment described above.
Next, a method of manufacturing the GaN-HEMT according to the present embodiment will be described with reference to FIG.
First, as shown in FIG. 4A, as in the case of the first embodiment described above, the i-GaN buffer layer 12 and the back barrier region are formed on the semi-insulating SiC substrate 1 using, for example, MOVPE. An i-AlGaN layer 11X to be 11 is sequentially deposited.

Next, as shown in FIG. 4B, similarly to the case of the first embodiment described above, the back barrier region formation planned region (the region under the MIS structure formation planned region) is formed using, for example, photolithography. With the resist left, the i-AlGaN layer 11X is removed by dry etching using, for example, a chlorine-based gas.
Thus, the i-AlGaN back barrier region 11 is formed.

Next, as shown in FIG. 4C, the i-GaN electron traveling layer 2 and the i-AlGaN electron supply layer 4 (for example, the i-AlGaN electron supply layer 4) are again formed by using the MOVPE method as in the first embodiment described above. Approximately 20 nm thick).
As a result, the i-AlGaN back barrier region 11 is embedded in the i-GaN electron travel layer 2 to form the i-GaN electron travel layer 2 having the i-AlGaN back barrier region 11 therein, and the i-GaN electron travel layer 2 is formed thereon. The AlGaN electron supply layer 4 is laminated to form the semiconductor laminated structure 3.

Further, an i-AlGaN back barrier region 11 is formed in which the energy at the bottom of the conduction band is higher than the regions adjacent to both sides in the direction along the i-GaN electron traveling layer (carrier traveling layer) 2.
The process up to here is referred to as the process of forming the semiconductor laminated structure 3 including the carrier traveling layer 2.

Next, although not shown, as in the case of the first embodiment described above, an opening is provided in the element isolation region using, for example, photolithography, for example, dry etching or ion implantation using a chlorine-based gas Device separation is performed by the method.
Next, as shown in FIG. 4D, as in the case of the first embodiment described above, each of the source electrode / drain electrode formation scheduled region is formed using, for example, the technique of photolithography and vapor deposition / lift off. A source electrode 5 and a drain electrode 6 made of, for example, Ti (about 20 nm) / Al (about 200 nm) are formed on the AlGaN electron supply layer 4.

Then, heat treatment is performed, for example, at about 400 ° C. to about 1000 ° C., for example, about 550 ° C. in a nitrogen atmosphere to establish ohmic characteristics of the source electrode 5 and the drain electrode 6.
Note that this process is called a process of forming the source electrode 5 and the drain electrode 6 on the semiconductor multilayer structure 3.
Next, as shown in FIG. 4D, as in the case of the first embodiment described above, SiN is deposited on the entire surface between about 2 nm and about 1000 nm, for example, using plasma CVD (Chemical Vapor Deposition). For example, about 100 nm is deposited to form a SiN film (insulating film) 8.

Thereby, a SiN film as the insulating film 8 is formed so as to cover the surface of the semiconductor multilayer structure 3 (here, the surface of the i-AlGaN electron supply layer 4).
Note that this process is called a process of forming the insulating film 8 on the semiconductor multilayer structure 3.
Next, as shown in FIG. 4D, as in the case of the first embodiment described above, a resist mask (not shown) having an opening in a Schottky gate electrode formation planned region using, for example, photolithography. And the SiN film 8 in a region where a Schottky gate electrode is to be formed, for example, by dry etching using a fluorine-based gas.

  Next, as shown in FIG. 4D, the semiconductor laminated structure 3 in the region where the Schottky gate electrode is to be formed (here, on the i-AlGaN electron supply layer 4) using photolithography and deposition / lift-off technology, for example. And the portion 7X on the drain electrode 6 side provided on the insulating film 8 (here, the SiN film) is made of, for example, Ni (about 30 nm) / Au (about 400 nm) so as to extend toward the drain electrode 6). The Schottky gate electrode 7 is formed. In this case, Ni is positioned closer to the semiconductor multilayer structure 3 (here, the i-AlGaN electron supply layer 4) and the insulating film 8 (SiN film).

  In this case, a portion 7 </ b> X extending toward the drain electrode 6 of the Schottky gate electrode 7 is the metal layer 9 constituting the MIS structure 10. That is, in the same process, the MIS structure 10 is formed by laminating the insulating film 8 and the metal layer 9 which is the portion 7X of the Schottky gate electrode 7 extending toward the drain electrode 6 side on the semiconductor multilayer structure 3. , And the Schottky gate electrode 7 are integrally formed. Thereby, the metal layer 9 constituting the MIS structure 10 is formed above the i-AlGaN back barrier region 11.

This step is referred to as a step of forming the Schottky gate electrode 7 on the semiconductor multilayer structure 3 between the source electrode 5 and the drain electrode 6. Also, this step is referred to as a step of forming the MIS structure 10 between the Schottky gate electrode 7 and the drain electrode 6 by laminating the metal layer 9 on the insulating film 8.
Thus, the GaN-HEMT according to the present embodiment can be manufactured.

Therefore, the compound semiconductor device according to the present embodiment and the method for manufacturing the same have the effect of suppressing an increase in off-leakage current, a decrease in mutual conductance, and an increase in on-resistance.
In particular, as described above, in the GaN-HEMT, low on-resistance and good pinch-off performance can be achieved by arranging the back barrier region 11 only at the minimum necessary location (immediately below the metal layer 9 constituting the MIS structure 10). It is possible to realize a GaN-HEMT device satisfying high transconductance. This transistor can be used, for example, in a high frequency amplifier or a switching semiconductor device.

In addition, semiconductor laminated structure 3 of the above-mentioned embodiment is an example, and may be another semiconductor laminated structure. For example, any semiconductor laminated structure that can constitute a field effect transistor may be used. The semiconductor multilayer structure 3 is also referred to as a semiconductor epitaxial structure.
Further, for example, although the SiC substrate is used in the above-described embodiment, the present invention is not limited to this. For example, another substrate such as a semiconductor substrate such as a sapphire substrate, a Si substrate, or a GaAs substrate may be used. . Moreover, in the above-mentioned embodiment, although the semi-insulating substrate is used, it is not limited to this, for example, a conductive substrate of n-type conductivity or p-type conductivity may be used.

Further, for example, the layer structure of the source electrode 5, the drain electrode 6, and the Schottky gate electrode 7 in the above-described embodiment is an example, and another layer structure may be used. For example, the layer structure of the source electrode 5, the drain electrode 6, and the Schottky gate electrode 7 in the above-described embodiment may be a single layer or a multilayer. Further, the method of forming the source electrode 5, the drain electrode 6, and the Schottky gate electrode 7 in the above-described embodiment is merely an example, and it may be formed by any other method.
Third Embodiment
Next, a compound semiconductor device according to the third embodiment and a method of manufacturing the same will be described with reference to FIGS. 5 and 6.

The compound semiconductor device according to the present embodiment is different from that of the above-described first embodiment (see FIG. 1), as shown in FIG. 5, in the material constituting the back barrier region.
That is, in the present GaN-HEMT, as shown in FIG. 5, the back barrier region 11 is made of i-InGaN (InGaN). That is, the present GaN-HEMT includes the i-InGaN back barrier region (InGaN back barrier region) 11.

Although FIG. 5 illustrates the case where the buffer layer 12 is provided, the buffer layer 12 may not be provided.
The other configuration and manufacturing method are the same as those of the above-described first embodiment.
Therefore, the compound semiconductor device according to the present embodiment and the method for manufacturing the same have the effect of suppressing an increase in off-leakage current, a decrease in mutual conductance, and an increase in on-resistance.

  In particular, as described above, in the GaN-HEMT, low on-resistance and good pinch-off performance can be achieved by arranging the back barrier region 11 only at the minimum necessary location (immediately below the metal layer 9 constituting the MIS structure 10). It is possible to realize a GaN-HEMT device satisfying high transconductance. This transistor can be used, for example, in a high frequency amplifier or a switching semiconductor device.

In the first embodiment and the present embodiment described above, the electron travel layer (carrier travel layer) 2 is made of GaN (i-GaN), and the back barrier region 11 is AlGaN (i-AlGaN) or InGaN (i-InGaN) ) But it is not limited to this.
For example, the electron transit layer (carrier transit layer) 2 is made of GaN, and the back barrier region 11 is made of AlGaN (i-AlGaN), InGaN (i-InGaN), AlN (i-AlN), p-GaN, p-AlGaN Or what is necessary is just to consist of these laminated structures. For example, as shown in FIG. 6, the back barrier region 11 may be made of p-GaN. That is, the p-GaN back barrier region 11 may be provided.

Also, for example, the electron transit layer (carrier transit layer) 2 is made of InGaN (i-InGaN), and the back barrier region 11 is made of AlGaN (i-AlGaN), GaN (i-GaN), AlN (i-AlN), It is good also as what consists of p-GaN, p-AlGaN, or these laminated structures.
Moreover, although this embodiment is described as a modification of the above-mentioned 1st embodiment, it is not restricted to this, In the composition of the above-mentioned 2nd embodiment, it is like this embodiment and its modification. Alternatively, the material of the back barrier region 11 may be changed.

In addition, semiconductor laminated structure 3 of the above-mentioned embodiment and its modification is an example, and may be another semiconductor laminated structure. For example, any semiconductor laminated structure that can constitute a field effect transistor may be used. The semiconductor multilayer structure 3 is also referred to as a semiconductor epitaxial structure.
Further, for example, although the SiC substrate is used in the above-described embodiment and the modification thereof, the present invention is not limited to this. For example, other substrates such as sapphire substrates, Si substrates, semiconductor substrates such as GaAs substrates, etc. You may use. Moreover, in the above-mentioned embodiment and its modification, although a semi-insulating substrate is used, it is not limited to this, for example, using a conductive substrate of n-type conductivity or p-type conductivity Also good.

Also, for example, the layer structure of the source electrode 5, the drain electrode 6, the Schottky gate electrode 7 and the metal layer 9 in the above-described embodiment is an example, and another layer structure may be used. For example, the layer structure of the source electrode 5, the drain electrode 6, the Schottky gate electrode 7 and the metal layer (the gate electrode of the MIS structure) 9 in the above-described embodiment may be a single layer or multiple layers. good. Further, the method of forming the source electrode 5, the drain electrode 6, the Schottky gate electrode 7 and the metal layer (the gate electrode of the MIS structure) 9 in the above embodiment is merely an example, and it is formed by any other method. Also good.
Fourth Embodiment
Next, a compound semiconductor device and a method of manufacturing the same according to a fourth embodiment will be described with reference to FIGS. 7 and 8.

The compound semiconductor device according to the present embodiment differs from that of the first embodiment described above (see FIG. 1) in the configuration of the semiconductor multilayer structure and in the material constituting the electron transit layer (carrier transit layer).
That is, the present compound semiconductor device is an InGaN-HEMT, and as shown in FIG. 7, an i-GaN buffer layer 12, an i-InGaN electron traveling layer (carrier traveling layer) 2, an i-AlGaN electron supply layer (carrier supply The semiconductor laminated structure 3 including the layer 4 is provided, and the i-AlGaN back barrier region 11 is embedded in the i-GaN buffer layer 12.

As described above, in the present InGaN-HEMT, the carrier traveling layer 2 is made of InGaN (i-InGaN), the GaN layer (i-GaN layer) 12 is provided under the carrier traveling layer 2, and the back barrier region 11 is Embedded in the GaN layer 12 and made of AlGaN (i-AlGaN).
In this case, an i-GaN buffer layer (GaN layer) 12 is formed under the i-InGaN electron traveling layer (carrier traveling layer) 2 in the step of forming a semiconductor multilayer structure in the method of manufacturing a compound semiconductor device. The back barrier region 11 may be formed to be embedded in the i-GaN buffer layer 12, and the back barrier region 11 may be made of AlGaN.

That is, first, as shown in FIG. 8A, the semi-insulating SiC substrate 1 is formed under the i-GaN buffer layer 12 on the semi-insulating SiC substrate 1 by using, for example, MOVPE as shown in FIG. A side portion 12A and an i-AlGaN layer 11X to be a back barrier region 11 are sequentially deposited.
Next, as shown in FIG. 8B, similarly to the case of the first embodiment described above, the back barrier region formation planned region (the region under the MIS structure planned formation region) is formed using, for example, photolithography. With the resist left, the i-AlGaN layer 11X is removed by dry etching using, for example, a chlorine-based gas.

Thus, the i-AlGaN back barrier region 11 is formed.
Next, as shown in FIG. 8C, again using the MOVPE method, the upper portion 12B of the i-GaN buffer layer 12, the i-InGaN electron traveling layer 2, the i-AlGaN electron supply layer 4 (for example, the thickness) Approximately 20 nm) in sequence.
As a result, the i-AlGaN back barrier region 11 is embedded in the i-GaN buffer layer 12, and the i-GaN buffer layer 12 having the i-AlGaN back barrier region 11 is formed therein, and the i-InGaN is formed thereon. The electron transit layer 2 and the i-AlGaN electron supply layer 4 are stacked to form the semiconductor multilayer structure 3.

Further, an i-AlGaN back barrier region 11 is formed in which the energy at the bottom of the conduction band is higher than the regions adjacent to both sides in the direction along the i-GaN electron traveling layer (carrier traveling layer) 2.
The process up to here is referred to as the process of forming the semiconductor laminated structure 3 including the carrier traveling layer 2.

Next, although not shown, as in the case of the first embodiment described above, an opening is provided in the element isolation region using, for example, photolithography, for example, dry etching or ion implantation using a chlorine-based gas Device separation is performed by the method.
Next, as shown in FIG. 8D, as in the case of the above-described first embodiment, each of the source electrode / drain electrode formation scheduled region is formed using, for example, the technique of photolithography and vapor deposition / lift off. A source electrode 5 and a drain electrode 6 made of, for example, Ti (about 20 nm) / Al (about 200 nm) are formed on the AlGaN electron supply layer 4.

Then, heat treatment is performed, for example, at about 400 ° C. to about 1000 ° C., for example, about 550 ° C. in a nitrogen atmosphere to establish ohmic characteristics of the source electrode 5 and the drain electrode 6.
Note that this process is called a process of forming the source electrode 5 and the drain electrode 6 on the semiconductor multilayer structure 3.
Next, as shown in FIG. 8D, as in the case of the first embodiment described above, SiN is deposited on the entire surface between about 2 nm and about 1000 nm, for example, using a plasma CVD (Chemical Vapor Deposition) method. For example, about 100 nm is deposited to form a SiN film (insulating film) 8.

Thereby, a SiN film as the insulating film 8 is formed so as to cover the surface of the semiconductor multilayer structure 3 (here, the surface of the i-AlGaN electron supply layer 4).
Note that this process is called a process of forming the insulating film 8 on the semiconductor multilayer structure 3.
Next, as shown in FIG. 8D, as in the case of the first embodiment described above, a resist mask (not shown) having an opening in a region where a Schottky gate electrode is to be formed, for example, using photolithography. And the SiN film 8 in a region where a Schottky gate electrode is to be formed, for example, by dry etching using a fluorine-based gas.

  Next, as shown in FIG. 8D, as in the case of the above-described first embodiment, the semiconductor laminated structure 3 in the schottky gate electrode formation planned region is formed using, for example, the technique of photolithography and vapor deposition / lift off. For example, Ni (about 30 nm) / on (here, on the SiN film) on the upper surface (here, on the i-AlGaN electron supply layer 4) and on the region for forming the metal layer 9 forming the MIS structure 10 A Schottky gate electrode 7 made of Au (about 400 nm) and a metal layer 9 constituting the MIS structure 10 are formed. Thereby, the MIS structure 10 is formed above the i-AlGaN back barrier region 11.

In this case, Ni is positioned closer to the semiconductor multilayer structure 3 (here, the i-AlGaN electron supply layer 4) and the insulating film 8 (SiN film). Further, the step of forming the Schottky gate electrode 7 and the step of forming the MIS structure 10 are performed in the same step.
This step is referred to as a step of forming the Schottky gate electrode 7 on the semiconductor multilayer structure 3 between the source electrode 5 and the drain electrode 6. Also, this step is referred to as a step of forming the MIS structure 10 between the Schottky gate electrode 7 and the drain electrode 6 by laminating the metal layer 9 on the insulating film 8.

Thus, the GaN-HEMT according to the present embodiment can be manufactured.
The other configuration and manufacturing method are the same as those of the above-described first embodiment.
Therefore, the compound semiconductor device according to the present embodiment and the method for manufacturing the same have the effect of suppressing an increase in off-leakage current, a decrease in mutual conductance, and an increase in on-resistance.

  In particular, as described above, in the InGaN-HEMT, low on-resistance and good pinch-off performance can be achieved by arranging the back barrier region 11 only at the minimum necessary location (immediately below the metal layer 9 constituting the MIS structure 10). It is possible to realize an InGaN-HEMT device that satisfies high transconductance. This transistor can be used, for example, in a high frequency amplifier or a switching semiconductor device.

Although the back barrier region 11 is made of AlGaN in the present embodiment, the present invention is not limited to this. For example, the back barrier region 11 may be made of AlGaN (i-AlGaN), AlN (i-AlN), p-GaN, p-AlGaN, or a stacked structure thereof.
That is, the carrier traveling layer 2 is made of InGaN (i-InGaN), the GaN layer (i-GaN layer) 12 is provided under the carrier traveling layer 2, and the back barrier region 11 is embedded in the GaN layer 12. It may be made of AlGaN (i-AlGaN), AlN (i-AlN), p-GaN, p-AlGaN, or a laminated structure thereof.

In addition, semiconductor laminated structure 3 of the above-mentioned embodiment and its modification is an example, and may be another semiconductor laminated structure. For example, any semiconductor laminated structure that can constitute a field effect transistor may be used. The semiconductor multilayer structure 3 is also referred to as a semiconductor epitaxial structure.
Further, for example, although the SiC substrate is used in the above-described embodiment and the modification thereof, the present invention is not limited to this. For example, other substrates such as sapphire substrates, Si substrates, semiconductor substrates such as GaAs substrates, etc. You may use. Moreover, in the above-mentioned embodiment and its modification, although a semi-insulating substrate is used, it is not limited to this, for example, using a conductive substrate of n-type conductivity or p-type conductivity Also good.

Further, for example, the layer structure of the source electrode 5, the drain electrode 6, and the gate electrode 7 in the above-described embodiment and the modification thereof is an example, and another layer structure may be used. For example, the layer structure of the source electrode 5, the drain electrode 6, and the gate electrode 7 in the above-described embodiment and the modified example thereof may be a single layer or a multilayer. Further, the method of forming the source electrode 5, the drain electrode 6, and the gate electrode 7 in the above-described embodiment and the modified example thereof is also merely an example, and may be formed by any other method.
Fifth Embodiment
Next, a compound semiconductor device, a method of manufacturing the same, and a power supply device according to a fifth embodiment will be described with reference to FIGS. 9 and 10. FIG.

The compound semiconductor device according to the present embodiment is a semiconductor package including the compound semiconductor device (HEMT; GaN-HEMT or InGaN-HEMT) of any of the above-described embodiments and modifications as a semiconductor chip. Note that the semiconductor chip is also referred to as a HEMT chip or a transistor chip.
Hereinafter, the discrete package will be described as an example.

As shown in FIG. 9, the present compound semiconductor device has a stage 30 on which the semiconductor chip 34 of any of the above-described embodiments and modifications is mounted, a gate lead 37, a source lead 39, and a drain lead 38. A bonding wire 36 (here, an Al wire) and a sealing resin 40 are provided. In addition, sealing resin is also called mold resin.
The gate pad 31, the source pad 32, and the drain pad 33 of the semiconductor chip 34 mounted on the stage 30 are connected to the gate lead 37, the source lead 39, and the drain lead 38 by Al wires 36, respectively. These are resin-sealed.

Here, the stage 30 with the substrate back surface of the semiconductor chip 34 fixed by the die attach agent 35 (here, solder) is electrically connected to the drain lead 38. The present invention is not limited to this, and the stage 30 may be electrically connected to the source lead 39.
Next, a method of manufacturing the compound semiconductor device (discrete package) according to the present embodiment will be described.

First, the semiconductor chip 34 (HEMT) of any of the above-described embodiments and modifications is fixed on the lead frame stage 30 using, for example, a die attach agent 35 (here, solder).
Next, the gate pad 31 of the semiconductor chip 34 is connected to the gate lead 37, the drain pad 33 is connected to the drain lead 38, and the source pad 32 is connected to the source lead 39 by bonding using, for example, an Al wire 36.

Thereafter, after resin sealing is performed by, for example, transfer molding, the lead frame is separated.
Thus, a compound semiconductor device (discrete package) can be manufactured.
Here, although the discrete package using each pad 31 to 33 of the semiconductor chip 34 as a bonding pad for wire bonding is described as an example, the present invention is not limited thereto, and other semiconductors It may be a package. For example, the semiconductor package may be a semiconductor package in which each pad of the semiconductor chip is used as a bonding pad for wireless bonding such as flip chip bonding. In addition, it may be a wafer level package. In addition, semiconductor packages other than discrete packages may be used.

Next, a power supply device including a semiconductor package including the above-described HEMT will be described with reference to FIG.
Hereinafter, a case where the HEMT included in the above-mentioned semiconductor package is used as a PFC (power factor correction) circuit included in a power supply device used for a server will be described as an example.

As shown in FIG. 10, the present PFC circuit includes a diode bridge 56, a choke coil 52, a first capacitor 54, the HEMT 51 included in the above-described semiconductor package, a diode 53, and a second capacitor 55.
Here, the present PFC circuit is configured by mounting the diode bridge 56, the choke coil 52, the first capacitor 54, the transistor 51 included in the semiconductor package described above, the diode 53, and the second capacitor 55 on a circuit board. It is done.

  In this embodiment, the drain lead 38, the source lead 39 and the gate lead 37 of the above-mentioned semiconductor package are respectively inserted into the drain lead insertion portion, the source lead insertion portion and the gate lead insertion portion of the circuit board It is fixed. Thus, the transistor 51 included in the above-described semiconductor package is connected to the PFC circuit formed on the circuit substrate.

  Further, in the present PFC circuit, one terminal of the choke coil 52 and the anode terminal of the diode 53 are connected to the drain electrode D of the HEMT 51. The other terminal of the choke coil 52 is connected to one terminal of the first capacitor 54, and the cathode terminal of the diode 53 is connected to one terminal of the second capacitor 55. The other terminal of the first capacitor 54, the source electrode S of the HEMT 51, and the other terminal of the second capacitor 55 are grounded. Also, a pair of terminals of the diode bridge 56 is connected to both terminals of the first capacitor 54, and the other pair of terminals of the diode bridge 56 is connected to an input terminal to which an alternating current (AC) voltage is input. ing. Further, both terminals of the second capacitor 55 are connected to an output terminal from which a direct current (DC) voltage is output. Further, a gate driver (not shown) is connected to the gate electrode G of the HEMT 51. Then, in the present PFC circuit, by driving the HEMT 51 by the gate driver, the AC voltage input from the input terminal is converted to a DC voltage and output from the output terminal.

Therefore, the power supply device according to the present embodiment has an advantage that the reliability can be improved. That is, since the compound semiconductor device (semiconductor chip 34) according to any of the above-described embodiments and modifications is provided, there is an advantage that a highly reliable power supply device can be constructed.
Here, although the case where the above-mentioned compound semiconductor device (semiconductor package including HEMT) is used for a PFC circuit included in a power supply device used for a server is described as an example, it is not limited thereto. Absent. For example, the above-described compound semiconductor device (semiconductor package including HEMT) may be used for electronic devices (electronic devices) such as computers other than servers. Further, the above-described compound semiconductor device (semiconductor package) may be used for another circuit (for example, a DC-DC converter or the like) included in the power supply device.
Sixth Embodiment
Next, a high frequency amplifier according to a sixth embodiment will be described with reference to FIG.

The high frequency amplifier according to the present embodiment is a high frequency amplifier (high power amplifier) including any of the compound semiconductor devices of the above-described embodiments and the modifications.
As shown in FIG. 11, the high frequency amplifier includes a digital predistortion circuit 41, mixers 42a and 42b, and a power amplifier 43. The power amplifier is also simply referred to as an amplifier.

The digital predistortion circuit 41 compensates for non-linear distortion of the input signal.
The mixers 42a and 42b mix an AC signal with an input signal whose nonlinear distortion has been compensated.
The power amplifier 43 amplifies an input signal mixed with an alternating current signal, and includes a compound semiconductor device according to any of the above-described embodiments and modifications, that is, a semiconductor chip including a HEMT. Note that the semiconductor chip is also referred to as a HEMT chip or a transistor chip.

In FIG. 11, for example, by switching the switch, the signal on the output side can be mixed with the AC signal by the mixer 42b and sent to the digital predistortion circuit 41.
Therefore, according to the high frequency amplifier according to the present embodiment, the compound semiconductor device according to each of the above-described embodiments and modifications is applied to the power amplifier 43, so that a highly reliable high frequency amplifier can be realized. It has the advantage of
[Others]
The present invention is not limited to the configurations described in the above-described embodiments and modifications, and can be variously modified without departing from the spirit of the present invention.

Hereinafter, additional notes will be disclosed regarding the above-described embodiments and modifications.
(Supplementary Note 1)
A semiconductor laminated structure including a carrier traveling layer;
A source electrode and a drain electrode provided on the semiconductor multilayer structure;
A Schottky gate electrode provided on the semiconductor multilayer structure between the source electrode and the drain electrode;
A MIS (Metal-Insulator-Semiconductor) structure in which an insulating film and a metal layer are laminated on the semiconductor laminated structure between the Schottky gate electrode and the drain electrode;
A back barrier region provided below the metal layer constituting the MIS structure, wherein energy at the bottom of the conduction band is higher than regions adjacent to both sides in the direction along the carrier traveling layer; Compound semiconductor device.

(Supplementary Note 2)
The compound semiconductor device according to claim 1, wherein the back barrier region is embedded in the carrier traveling layer.
(Supplementary Note 3)
The carrier traveling layer is made of GaN,
The compound semiconductor device according to claim 1 or 2, wherein the back barrier region is made of AlGaN, InGaN, AlN, p-GaN, p-AlGaN or a stacked structure thereof.

(Supplementary Note 4)
The carrier traveling layer is made of InGaN,
The compound semiconductor device according to claim 1 or 2, wherein the back barrier region is made of AlGaN, GaN, AlN, p-GaN, p-AlGaN, or a stacked structure thereof.

(Supplementary Note 5)
The carrier traveling layer is made of InGaN,
A GaN layer is provided under the carrier traveling layer,
The compound semiconductor device according to claim 1, wherein the back barrier region is embedded in the GaN layer and made of AlGaN, AlN, p-GaN, p-AlGaN, or a stacked structure thereof.

(Supplementary Note 6)
The compound semiconductor device according to any one of appendices 1 to 5, wherein the Schottky gate electrode and the metal layer are electrically connected.
(Appendix 7)
The compound semiconductor device according to any one of appendices 1 to 5, wherein the Schottky gate electrode and the metal layer are integrated.

(Supplementary Note 8)
Equipped with a transistor,
The transistor is
A semiconductor laminated structure including a carrier traveling layer;
A source electrode and a drain electrode provided on the semiconductor multilayer structure;
A Schottky gate electrode provided on the semiconductor multilayer structure between the source electrode and the drain electrode;
A MIS (Metal-Insulator-Semiconductor) structure in which an insulating film and a metal layer are laminated on the semiconductor laminated structure between the Schottky gate electrode and the drain electrode;
A back barrier region provided below the metal layer constituting the MIS structure, wherein energy at the bottom of the conduction band is higher than regions adjacent to both sides in the direction along the carrier traveling layer; Power supply device.

(Appendix 9)
It has an amplifier that amplifies the input signal,
The amplifier includes a transistor,
The transistor is
A semiconductor laminated structure including a carrier traveling layer;
A source electrode and a drain electrode provided on the semiconductor multilayer structure;
A Schottky gate electrode provided on the semiconductor multilayer structure between the source electrode and the drain electrode;
A MIS (Metal-Insulator-Semiconductor) structure in which an insulating film and a metal layer are laminated on the semiconductor laminated structure between the Schottky gate electrode and the drain electrode;
A back barrier region provided below the metal layer constituting the MIS structure, wherein energy at the bottom of the conduction band is higher than regions adjacent to both sides in the direction along the carrier traveling layer; High frequency amplifier to be.

(Supplementary Note 10)
Forming a semiconductor laminate structure including a carrier traveling layer;
Forming a source electrode and a drain electrode on the semiconductor multilayer structure;
Forming a Schottky gate electrode on the semiconductor stack structure between the source electrode and the drain electrode;
Forming an insulating film on the semiconductor laminated structure;
And depositing a metal layer on the insulating film to form a MIS (Metal-Insulator-Semiconductor) structure between the Schottky gate electrode and the drain electrode.
Forming a back barrier region in which the energy at the bottom of the conduction band is higher than the region adjacent to both sides in the direction along the carrier traveling layer in the step of forming the semiconductor multilayer structure;
In the step of forming the MIS structure, the metal layer forming the MIS structure is formed above the back barrier region.

(Supplementary Note 11)
10. The method for manufacturing a compound semiconductor device according to claim 10, wherein the step of forming the Schottky gate electrode and the step of forming the MIS structure are performed in the same step.
(Supplementary Note 12)
The method of manufacturing a compound semiconductor device according to claim 11, wherein the Schottky gate electrode and the metal layer are integrally formed.

(Supplementary Note 13)
15. The compound semiconductor device according to any one of claims 10 to 12, wherein the back barrier region is formed so as to be embedded in the carrier traveling layer in the step of forming the semiconductor laminated structure. Method.
(Supplementary Note 14)
The carrier traveling layer is made of GaN,
The method of manufacturing a compound semiconductor device according to any one of appendices 10 to 13, characterized in that the back barrier region is made of AlGaN, InGaN, AlN, p-GaN, p-AlGaN or a laminated structure thereof. .

(Supplementary Note 15)
The carrier traveling layer is made of InGaN,
The method for manufacturing a compound semiconductor device according to any one of appendices 10 to 13, characterized in that the back barrier region is made of AlGaN, GaN, AlN, p-GaN, p-AlGaN, or a stacked structure thereof. .

(Supplementary Note 16)
The carrier traveling layer is made of InGaN,
In the step of forming the semiconductor laminated structure, a GaN layer is formed under the carrier traveling layer, and the back barrier region is formed to be embedded in the GaN layer.
15. The method for manufacturing a compound semiconductor device according to any one of appendices 10 to 12, wherein the back barrier region is made of AlGaN, AlN, p-GaN, p-AlGaN, or a laminated structure thereof.

1 Substrate (semi-insulating SiC substrate)
2 Electron traveling layer (carrier traveling layer; i-GaN electron traveling layer; i-InGaN electron traveling layer)
3 Semiconductor Layered Structure 4 Electron Supply Layer (Carrier Supply Layer; i-AlGaN Electron Supply Layer)
5 source electrode 6 drain electrode 7 Schottky gate electrode 7X portion of drain electrode side of Schottky gate electrode 8 insulating film (SiN film)
9 metal layer 10 MIS structure 11 back barrier region (i-AlGaN back barrier region; i-InGaN back barrier region; p-GaN back barrier region)
11X i-AlGaN layer 12 buffer layer (i-GaN buffer layer)
12A i-GaN buffer layer lower portion 12B i-GaN buffer layer upper portion 30 stage 31 gate pad 32 source pad 33 drain pad 34 semiconductor chip 35 die attach agent 36 bonding wire 37 gate lead 38 drain lead 39 source lead 40 Sealing resin 41 Digital predistortion circuit 42a, 42b Mixer 43 Power amplifier 51 HEMT
52 choke coil 53 diode 54 first capacitor 55 second capacitor 56 diode bridge

Claims (10)

A semiconductor laminated structure including a carrier traveling layer;
A source electrode and a drain electrode provided on the semiconductor multilayer structure;
A Schottky gate electrode provided on the semiconductor multilayer structure between the source electrode and the drain electrode;
A MIS (Metal-Insulator-Semiconductor) structure in which an insulating film and a metal layer are laminated on the semiconductor laminated structure between the Schottky gate electrode and the drain electrode;
A back barrier region provided below the metal layer constituting the MIS structure, wherein energy at the bottom of the conduction band is higher than regions adjacent to both sides in the direction along the carrier traveling layer; Compound semiconductor device.   The compound semiconductor device according to claim 1, wherein the back barrier region is embedded in the carrier traveling layer. The carrier traveling layer is made of GaN,
The compound semiconductor device according to claim 1, wherein the back barrier region is made of AlGaN, InGaN, AlN, p-GaN, p-AlGaN, or a stacked structure thereof. The carrier traveling layer is made of InGaN,
The compound semiconductor device according to claim 1, wherein the back barrier region is made of AlGaN, GaN, AlN, p-GaN, p-AlGaN, or a stacked structure thereof. The carrier traveling layer is made of InGaN,
A GaN layer is provided under the carrier traveling layer,
The compound semiconductor device according to claim 1, wherein the back barrier region is embedded in the GaN layer and made of AlGaN, AlN, p-GaN, p-AlGaN, or a stacked structure thereof.   The compound semiconductor device according to any one of claims 1 to 5, wherein the Schottky gate electrode and the metal layer are electrically connected.   The compound semiconductor device according to any one of claims 1 to 5, wherein the Schottky gate electrode and the metal layer are integrated. Equipped with a transistor,
The transistor is
A semiconductor laminated structure including a carrier traveling layer;
A source electrode and a drain electrode provided on the semiconductor multilayer structure;
A Schottky gate electrode provided on the semiconductor multilayer structure between the source electrode and the drain electrode;
A MIS (Metal-Insulator-Semiconductor) structure in which an insulating film and a metal layer are laminated on the semiconductor laminated structure between the Schottky gate electrode and the drain electrode;
A back barrier region provided below the metal layer constituting the MIS structure, wherein energy at the bottom of the conduction band is higher than regions adjacent to both sides in the direction along the carrier traveling layer; Power supply device. It has an amplifier that amplifies the input signal,
The amplifier includes a transistor,
The transistor is
A semiconductor laminated structure including a carrier traveling layer;
A source electrode and a drain electrode provided on the semiconductor multilayer structure;
A Schottky gate electrode provided on the semiconductor multilayer structure between the source electrode and the drain electrode;
A MIS (Metal-Insulator-Semiconductor) structure in which an insulating film and a metal layer are laminated on the semiconductor laminated structure between the Schottky gate electrode and the drain electrode;
A back barrier region provided below the metal layer constituting the MIS structure, wherein energy at the bottom of the conduction band is higher than regions adjacent to both sides in the direction along the carrier traveling layer; High frequency amplifier to be. Forming a semiconductor laminate structure including a carrier traveling layer;
Forming a source electrode and a drain electrode on the semiconductor multilayer structure;
Forming a Schottky gate electrode on the semiconductor stack structure between the source electrode and the drain electrode;
Forming an insulating film on the semiconductor laminated structure;
And depositing a metal layer on the insulating film to form a MIS (Metal-Insulator-Semiconductor) structure between the Schottky gate electrode and the drain electrode.
Forming a back barrier region in which the energy at the bottom of the conduction band is higher than the region adjacent to both sides in the direction along the carrier traveling layer in the step of forming the semiconductor multilayer structure;
In the step of forming the MIS structure, the metal layer forming the MIS structure is formed above the back barrier region.

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