JP2019071579A - Differential amplifier, pixel circuit and solid-state imaging device - Google Patents

Abstract

To provide a differential amplifier capable of narrowing a pitch of pixel circuits, and of suppressing reduction in output range.SOLUTION: A differential amplifier 51 has a non-inverted input terminal 61, an inverted input terminal 62 and an output terminal 63. The differential amplifier 51 comprises: an input differential pair 66 including NMOS transistors 71 and 72; a current mirror pair 67 including PMOS transistors 73 and 74; and a constant current source 68 including an NMOS transistor 75. Each threshold voltage of the NMOS transistors 71 and 72 is larger than that of the NMOS transistor 75.SELECTED DRAWING: Figure 5

Description

  The present invention relates to a differential amplifier, a pixel circuit including the differential amplifier, and a solid-state imaging device including the pixel circuit.

  In general, a solid-state imaging device includes a plurality of photodiodes formed in a one-dimensional or two-dimensional array on a substrate, and a pixel circuit that receives and processes output signals from each of the plurality of photodiodes. Prepare. Also, the pixel circuit includes an amplifier and an integration capacitor. The pixel circuit receives the signal output from the photodiode, stores the charge in the integration capacitance unit, and outputs a voltage value corresponding to the charge storage amount from the output terminal of the amplifier.

  A differential amplifier (see Patent Document 1) is used as an amplifier in a pixel circuit. In this case, the reference voltage is input to the first input terminal of the differential amplifier, and the signal from the photodiode is input to the second input terminal. In the differential amplifier, since these two input terminals are in an imaginary short relationship, the potential difference between the two input terminals is substantially zero. Accordingly, since the photodiode can be driven with a reverse bias voltage of substantially zero, dark current can be suppressed. In this respect, it is preferable to use a differential amplifier in the pixel circuit.

  In solid-state imaging devices, high integration of photodiodes is required to improve spatial resolution and reduce costs. That is, an increase in the number of photodiodes formed on a substrate and a reduction in the pitch of pixels (area reduction of each photodiode) are required. In order to achieve high integration, the solid-state imaging device may be configured such that a first substrate on which a plurality of photodiodes are formed and a second substrate on which a plurality of pixel circuits are formed are opposed to each other. In particular, in the case where the photodiode is formed on the first substrate made of compound semiconductor and the pixel circuit is formed on the second substrate made of silicon, the first substrate and the second substrate are separated from each other. Ru. In this case, high integration of the pixel circuit on the second substrate is also required along with high integration of the photodiode on the first substrate. That is, narrowing of the pixel circuits on the second substrate (narrowing of the layout of the pixel circuits) is also required.

Japanese Patent Laid-Open No. 6-216666

  The inventors of the present invention obtained the following findings in the process of researching narrowing of a pixel circuit including a differential amplifier. That is, the size of the output range of the differential amplifier is limited by the circuit configuration of the differential amplifier. In order to increase the output range, it is conceivable to devise on the circuit, such as providing an output buffer at the rear stage of the differential amplifier as described in Patent Document 1. However, in this case, the circuit scale of the pixel circuit including the differential amplifier is increased, which is against the purpose of narrowing the pixel circuit.

  In addition, in order to narrow the pitch of the pixel circuit, it is necessary to manufacture the pixel circuit using a fine CMOS process. However, since the differential amplifier fabricated by the fine CMOS process is driven by a low power supply voltage, the output range of the differential amplifier is correspondingly reduced.

  The present invention has been made based on such findings of the present inventor, and it is an object of the present invention to provide a differential amplifier capable of narrowing the pixel circuit and suppressing the reduction of the output range. To aim.

  The differential amplifier of the present invention is a differential amplifier having a first input terminal, a second input terminal and an output terminal. The differential amplifier of the present invention includes: (1) a first MOS transistor of the first conductivity type and a second MOS transistor, wherein sources of the first MOS transistor and the second MOS transistor are connected to a common node, and a gate of the first MOS transistor is An input differential pair connected to one input terminal, the gate of the second MOS transistor being connected to the second input terminal, and (2) a third MOS transistor and a fourth MOS transistor of the second conductivity type; The first reference voltage is input to the source of each of the four MOS transistors, the drain of the third MOS transistor is connected to the drain of the first MOS transistor, the drain of the fourth MOS transistor is connected to the drain and the output terminal of the second MOS transistor, and the third MOS transistor And a current mirror pair in which the gate of each of the fourth MOS transistors is connected to the drain of the third MOS transistor, and (3) a fifth MOS transistor of the first conductivity type, and the second reference voltage is input to the source of the fifth MOS transistor And a constant current source connected to a common node of the drain of the fifth MOS transistor and to which the third reference voltage is input to the gate of the fifth MOS transistor. The threshold voltage of each of the first MOS transistor and the second MOS transistor is larger than the threshold voltage of the fifth MOS transistor.

  One of the first conductivity type and the second conductivity type is N-type, and the other is P-type. One of the first reference potential and the second reference potential is the power supply potential Vdd, and the other is the ground potential. The third reference potential is a potential applied to the gate of the fifth MOS transistor in order to use the fifth MOS transistor as a constant current source.

  In the present invention, the impurity concentration of the channel region under the gate of each of the first MOS transistor and the second MOS transistor is preferably higher than the impurity concentration of the channel region under the gate of the fifth MOS transistor. Further, it is also preferable that the conductivity type or the impurity concentration is different between the gate of each of the first MOS transistor and the second MOS transistor and the gate of the fifth MOS transistor.

  The pixel circuit of the present invention is provided between the differential amplifier of the present invention described above and the second input terminal and the output terminal of the differential amplifier, and stores charge according to a signal input to the second input terminal. And a signal having a value according to the charge storage amount of the integration capacitance unit is output from the output terminal of the differential amplifier.

  A solid-state imaging device according to the present invention includes the above-described pixel circuit according to the present invention and a photodiode, and the pixel circuit inputs a signal output from the photodiode in response to light reception to a second input terminal of the differential amplifier. An output signal having a value corresponding to the amount of light received is output from the output terminal of the differential amplifier. Preferably, the plurality of photodiodes are formed on the first substrate, the plurality of pixel circuits are formed on the second substrate, and the first substrate and the second substrate are disposed to face each other.

  According to the present invention, it is possible to narrow the pitch of the pixel circuit and to suppress the reduction of the output range of the differential amplifier.

FIG. 1 is a perspective view showing the configuration of the solid-state imaging device 1. FIG. 2 is a cross-sectional view showing the configuration of the solid-state imaging device 1. FIG. 3 is a circuit diagram showing the basic configuration of the photodiode 11 and the CTIA 50. As shown in FIG. FIG. 4 is a circuit diagram showing a detailed configuration of the pixel circuit 21. As shown in FIG. FIG. 5 is a circuit diagram of the differential amplifier 51. As shown in FIG. FIG. 6 is a diagram showing the configuration of a circuit used in the simulation. FIG. 7 is a graph showing simulation results.

  Hereinafter, with reference to the accompanying drawings, modes for carrying out the present invention will be described in detail. In the description of the drawings, the same elements will be denoted by the same reference symbols, without redundant description. The present invention is not limited to these exemplifications, is shown by the claims, and is intended to include all modifications within the scope and meaning equivalent to the claims.

  FIG. 1 is a perspective view showing the configuration of the solid-state imaging device 1. FIG. 2 is a cross-sectional view showing the configuration of the solid-state imaging device 1. The solid-state imaging device 1 has a configuration in which the second substrate 20 is disposed on the package 30 and the first substrate 10 is disposed on the second substrate 20. A plurality of photodiodes 11 are formed in a two-dimensional array on the first substrate 10. The photodiode 11 may be made of a compound semiconductor, and may be made of, for example, InGaAs. A plurality of pixel circuits 21 are two-dimensionally arrayed and formed on the second substrate 20. The pixel circuit 21 may be made of silicon.

  The photodiode 11 and the CTIA 50 (described later) of the pixel circuit 21 correspond to each other in a one-to-one manner. That is, the CTIA 50 is provided for each pixel. The first substrate 10 and the second substrate 20 are disposed to face each other, and the corresponding photodiodes 11 and the pixel circuits 21 are electrically connected to each other by the bumps 41. Each photodiode 11 is supplied with a reference voltage via the bump 41 and outputs a charge generated according to the amount of incident light to the pixel circuit 21. The electrode 22 formed on the second substrate 20 and the electrode 32 formed on the package 30 are electrically connected to each other by a bonding wire 42. Each pixel circuit 21 is supplied with a reference voltage and a control signal via the bonding wire 42, and receives the charge from the photodiode 11 and outputs the result of processing for each pixel.

  FIG. 3 is a circuit diagram showing the basic configuration of the photodiode 11 and the CTIA 50. As shown in FIG. The CTIA 50 includes a differential amplifier 51, an integration capacitor 52, and a switch 53 for reset. The differential amplifier 51 has a non-inverted input terminal (first input terminal), an inverted input terminal (second input terminal), and an output terminal. The integration capacitor portion 52 and the switch 53 are connected in parallel to each other, and provided between the inverting input terminal and the output terminal of the differential amplifier 51. The anode of the photodiode 11 is electrically connected to the inverting input terminal of the differential amplifier 51. The inp voltage is input to the cathode of the photodiode 11 and the non-inversion input terminal of the differential amplifier 51. Since the inverting input terminal and the non-inverting input terminal of the differential amplifier 51 are in an imaginary short relationship, the potential difference between these two input terminals is substantially zero. Therefore, since the photodiode 11 is driven with a reverse bias voltage of substantially zero, dark current can be suppressed.

  The differential amplifier 51, the integration capacitance unit 52, and the switch 53 constitute a capacitive feedback trans-impedance amplifier (CTIA: Capacitive Trans-Impedance Amplifier). When the switch 53 is in the on state, the integration capacitance unit 52 is discharged, and the voltage value output from the output terminal of the differential amplifier 51 becomes an initial value. When the switch 53 is in the OFF state, charges are accumulated in the integration capacitance unit 52 in accordance with the signal output from the photodiode 11, and the voltage value corresponding to the amount of accumulated charges is the differential amplifier 51. Output from the output terminal of The switch 53 can be formed of a MOS transistor.

  FIG. 4 is a circuit diagram showing a detailed configuration of the pixel circuit 21. As shown in FIG. The pixel circuit 21 shown in this figure includes a PMOS transistor 54 as a switch for sampling, a capacitor for sample and hold 55, and a source follower circuit, in addition to the CTIA 50 including the differential amplifier 51, the integration capacitor 52 and the switch 53. And an NMOS transistor 57 as a switch for output selection. Although the circuit configuration of the differential amplifier 51 is shown in this figure, it will be described later with reference to FIG.

  The source of the PMOS transistor 54 is connected to the output terminal of the differential amplifier 51. The drain of the PMOS transistor 54 is connected to one end of the capacitor 55. The other end of the capacitive portion 55 is at a reference potential (ground potential). In the PMOS transistor 54, on / off operation between the source and the drain is controlled by the sample signal input to the gate. When the PMOS transistor 54 changes from the on state to the off state, the voltage value output from the output terminal of the differential amplifier 51 immediately before that is held by the capacitance unit 55.

  The NMOS transistor 56 and the NMOS transistor 57 are connected in series between the reference potential input terminal and the video line. The drain of the NMOS transistor 56 is at the reference potential (power supply potential Vdd). The source of the NMOS transistor 56 is connected to the drain of the NMOS transistor 57. The source of the NMOS transistor 57 is connected to the video line. The NMOS transistor 56 inputs the voltage value held by the capacitance unit 55 to the gate, and has a resistance value corresponding to the voltage value between the drain and the source. The on / off operation between the source and the drain of the NMOS transistor 57 is controlled by the shift signal inputted to the gate. When the NMOS transistor 57 is turned on, a signal corresponding to the voltage value held by the capacitance unit 55 is output to the video line.

  The pixel circuit 21 is provided for each pixel. A plurality of pixel circuits 21 are connected to the signal processing circuit by a common video line. The NMOS transistors 57 of the plurality of pixel circuits 21 connected to the common video line are sequentially turned on. The signal processing circuit selectively inputs a signal output from any of the pixel circuits 21 in which the NMOS transistor 57 is on among the plurality of pixel circuits 21 connected to the common video line, and the input signal Process

  FIG. 5 is a circuit diagram of the differential amplifier 51. As shown in FIG. The differential amplifier 51 has a non-inverted input terminal (first input terminal) 61, an inverted input terminal (second input terminal) 62, and an output terminal 63. Differential amplifier 51 includes an input differential pair 66 including an NMOS transistor (first MOS transistor) 71 and an NMOS transistor (second MOS transistor) 72, a PMOS transistor (third MOS transistor) 73 and a PMOS transistor (fourth MOS transistor) 74. A current mirror pair 67 and a constant current source 68 including an NMOS transistor (fifth MOS transistor) 75 are provided.

  The NMOS transistor 71 and the NMOS transistor 72 have the same configuration. The sources of the NMOS transistors 71 and 72 are connected to the common node 64. The gate of the NMOS transistor 71 is connected to the noninverting input terminal 61. The gate of the NMOS transistor 72 is connected to the inverting input terminal 62.

  PMOS transistor 73 and PMOS transistor 74 have the same configuration. The first reference voltage (power supply potential Vdd) is input to the sources of the PMOS transistors 73 and 74, respectively. The drain of the PMOS transistor 73 is connected to the drain of the NMOS transistor 71. The drain of the PMOS transistor 74 is connected to the drain of the NMOS transistor 72 and the output terminal 63. The gate of each of the PMOS transistors 73 and 74 is connected to the drain of the PMOS transistor 73.

  The second reference voltage (ground potential) is input to the source of the NMOS transistor 75. The drain of the NMOS transistor 75 is connected to the common node 64. The third reference voltage (bias voltage vb1) is input to the gate of the NMOS transistor 75.

  In the differential amplifier 51 having such a circuit configuration, the threshold voltage of each of the NMOS transistors 71 and 72 is larger than the threshold voltage of the NMOS transistor 75. In this way, even if the power supply voltage is lowered due to the adoption of the fine CMOS process, it is possible to suppress the decrease in the output range of the differential amplifier 51. Further, since the circuit scale (the number of transistors) of the differential amplifier 51 does not change, it is preferable for narrowing the pitch of the pixel circuit 21 including the differential amplifier 51.

  Next, the reason why the reduction of the output range of the differential amplifier 51 can be suppressed by making the threshold voltage of each of the NMOS transistors 71 and 72 larger than the threshold voltage of the other NMOS transistors will be described below.

The various parameters of the NMOS transistor are as follows. The voltage value of the common node 64 is p1. The input voltage value of the non-inverted input terminal 61 is taken as inp. The threshold voltage is V _th . The gate width is W. Let L be the gate length. The drain current is I _d . Carrier mobility is μ. _Let the capacitance value per unit area of the insulating layer under the gate be _Cox . Let 仕事_{G be} the work function of the gate. Let 関 数_{S be} the work function of the semiconductor. Let the dielectric constant of the semiconductor be ε _s . Let q be the elementary charge. The impurity concentration of the channel region under the gate and N _A. In addition, the Fermi potential and φ _P. Among these parameters, there is the relationship of the following equations (1) and (2).

The voltage value output from the output terminal 63 of the differential amplifier 51 is restricted in the range from the input voltage value inp of the non-inverting input terminal 61 to the voltage value p1 of the common node 64. Therefore, if threshold voltage _{Vth of} each of NMOS transistors 71 and 72 is increased, voltage value p1 of common node 64 can be reduced, and the output range of differential amplifier 51 can be increased.

To increase the threshold voltage V _th may be increasing the impurity concentration N _A of the channel region. That is, the impurity concentration _{N A} of the channel region under the gate of the NMOS transistor to be increased threshold voltage _{V th,} may be higher than the other NMOS transistors.

Alternatively, the conductivity type or the impurity concentration may be made different between the gate of an NMOS transistor whose threshold voltage V _th is desired to be increased and the gate of another NMOS transistor. That is, the difference (Φ _G −Φ _S ) between the work function _{G G} of the gate and the work function ( _{S of the} semiconductor in the above equation (2) depends on the conductivity type of the gate and the impurity concentration. The threshold voltage V _th can be increased by increasing the difference (Φ _G −Φ _S ). Generally, polysilicon is used as a material of the gate.

In the case of an NMOS transistor, the threshold voltage V _th can be increased by making the gate made of polysilicon P-type rather than N-type. When the gate of the NMOS transistor is N-type, the threshold voltage V _th can be increased by reducing the impurity concentration. When the gate of the NMOS transistor is P-type, the threshold voltage V _th can be increased by increasing the impurity concentration. On the other hand, in the case of a PMOS transistor, the threshold voltage V _th can be increased by making the gate made of polysilicon N-type rather than P-type. When the gate of the PMOS transistor is N-type, the threshold voltage V _th can be increased by increasing the impurity concentration. When the gate of the PMOS transistor is P-type, the threshold voltage V _th can be increased by decreasing the impurity concentration.

Alternatively, the capacitance value _Cox per unit area of the insulating layer under the gate of the NMOS transistor whose threshold voltage _Vth is desired to be increased may be reduced. Specifically, to increase the threshold voltage V _th , a material with a small relative dielectric constant may be used as the insulating layer under the gate, or the insulating layer may be thick.

  Next, simulation results will be described. FIG. 6 is a diagram showing the configuration of a circuit used in the simulation. The simulation circuit shown in this figure uses the constant current source 11A instead of the photodiode 11 in the circuit shown in FIG. That is, this constant current source 11A simulates a photodiode that generates a fixed amount of charge in time.

  FIG. 7 is a graph showing simulation results. Two cases A and B were assumed in the simulation. In case A, the threshold voltage of each of the NMOS transistors 71, 72, 75, 56, 57 is set to 0.65V. In case B, the threshold voltage of each of the NMOS transistors 71 and 72 is 1.00 V, and the threshold voltage of each of the NMOS transistors 75, 56, and 57 is 0.65 V. The input voltage value inp of the non-inverting input terminal is 2.7V. The output current value of the constant current source 11A was 3 nA. The on period of the switch 53 is 30 μs. The capacitance value of the integral capacitance unit 52 is 30 pF.

  In the case A where the threshold voltage of the NMOS transistors 71 and 72 is the same as the threshold voltage of the other NMOS transistors, the voltage value output from the output terminal of the differential amplifier 51 is from 2.7V to 1.75V. In the case B where the threshold voltage of the NMOS transistors 71 and 72 is larger than the threshold voltage of the other NMOS transistors, the voltage value output from the output terminal of the differential amplifier 51 is from 2.7V to 1.4V. It was confirmed that the output range was larger in case B than in case A. The difference in output range between case A and case B was 0.35 V, the same as the difference in threshold voltage.

  In the above embodiments, the first conductivity type is N-type and the second conductivity type is P-type. Conversely, the first conductivity type may be P-type and the second conductivity type may be N-type. In the above embodiments, the case where the differential amplifier is used as one component of the pixel circuit in the solid-state imaging device has been described. However, the differential amplifier can be used in other circuits.

  DESCRIPTION OF SYMBOLS 1 solid imaging device 10 first substrate 11 photodiode 20 second substrate 21 pixel circuit 22 electrode 30 package 32 electrode 41 bump 42 bonding wire 50 ... CTIA, 51 ... differential amplifier, 52 ... integral capacitance unit, 53 ... switch, 54 ... PMOS transistor, 55 ... capacitance unit, 56 ... NMOS transistor, 57 ... NMOS transistor, 61 ... non-inverting input terminal (first input terminal , 62 ... inverted input terminal (second input terminal), 63 ... output terminal, 64 ... common node, 66 ... input differential pair, 67 ... current mirror pair, 68 ... constant current source, 71 ... NMOS transistor (first MOS) Transistors), 72 ... NMOS transistors (second MOS transistors) 73 ... PMOS transistors (third MOS transistors) 74 PMOS transistor (second 4MOS transistor), 75 ... NMOS transistor (second 5MOS transistor).

Claims (6)

A differential amplifier having a first input terminal, a second input terminal and an output terminal, wherein
A source of the first MOS transistor and a second MOS transistor is connected to a common node, and a gate of the first MOS transistor is connected to the first input terminal. An input differential pair in which the gate of the second MOS transistor is connected to the second input terminal;
A first reference voltage is input to the source of each of the third MOS transistor and the fourth MOS transistor, and the drain of the third MOS transistor is connected to the drain of the first MOS transistor. A current mirror pair connected such that the drain of the fourth MOS transistor is connected to the drain of the second MOS transistor and the output terminal, and the gates of the third MOS transistor and the fourth MOS transistor are connected to the drain of the third MOS transistor When,
A fifth reference voltage is input to the source of the fifth MOS transistor, the drain of the fifth MOS transistor is connected to the common node, and the third reference is applied to the gate of the fifth MOS transistor. A constant current source to which a voltage is input,
Equipped with
The threshold voltage of each of the first MOS transistor and the second MOS transistor is larger than the threshold voltage of the fifth MOS transistor.
Differential amplifier. The impurity concentration of the channel region under the gate of each of the first MOS transistor and the second MOS transistor is higher than the impurity concentration of the channel region under the gate of the fifth MOS transistor.
The differential amplifier according to claim 1. The conductivity type or the impurity concentration is different between the gate of each of the first MOS transistor and the second MOS transistor and the gate of the fifth MOS transistor.
The differential amplifier according to claim 1. The differential amplifier according to any one of claims 1 to 3.
An integration capacitance unit provided between the second input terminal and the output terminal of the differential amplifier and storing charge according to a signal input to the second input terminal;
Equipped with
Outputting a signal having a value according to the charge storage amount of the integration capacitance unit from the output terminal of the differential amplifier;
Pixel circuit. A pixel circuit according to claim 4 and a photodiode.
The pixel circuit inputs a signal output from the photodiode according to light reception to the second input terminal of the differential amplifier, and an output signal of a value according to the amount of light received is the output of the differential amplifier Output from the terminal,
Solid-state imaging device. A plurality of the photodiodes are formed on a first substrate;
A plurality of the pixel circuits are formed on a second substrate;
The first substrate and the second substrate are disposed to face each other.
The solid-state imaging device according to claim 5.

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