JP2019071269A - Light emission control circuit, light source device, and projection type video display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress the energy stored in an inductor from being emitted without being used for light emission in the case of performing analog dimming and digital dimming, and the period for passing a current through a light emitting element in digital dimming is short. Also prevents the current of the light emitting element from dropping. A light emission control circuit includes a drive circuit that generates a first control signal to control a first switching element, and a switch that generates a second control signal to control a second switching element. It includes a control circuit. The switch control circuit maintains the second control signal in the deactivated state during the period in which the first control signal is deactivated when the on-duty ratio of the first control signal is equal to or greater than a predetermined value. However, when the on-duty ratio of the first control signal is less than a predetermined value, the second control signal is maintained in the activated state for a part of the period during which the first control signal is deactivated. .. [Selection diagram] FIG. 8

Description

  The present invention relates to a light emission control circuit which controls light emission in a light source device using a light emitting element such as a laser diode or a light emitting diode. Furthermore, the present invention relates to a light source device using such a light emission control circuit, a projection type video display device using such a light source device, and the like.

  Analog light control and digital light control are known as a method of adjusting the brightness in a light source device using light emitting elements such as a laser diode (LD) and a light emitting diode (LED). For example, analog dimming is realized by controlling a switching regulator that drives a light emitting element to adjust the magnitude of the current flowing to the light emitting element. On the other hand, digital light adjustment is realized by on / off controlling switching transistors connected in series to light emitting elements to adjust the length of a period in which current flows in the light emitting elements.

  As a related technique, in Patent Document 1, in order to improve the light control characteristic such that the relation between the light control instruction and the degree of light control is largely different between the light control region where the light source is relatively bright and the dark light control region. There is disclosed a light source drive device capable of making the relationship between the magnitude of the dimming instruction signal and the output current linear in a wider dimming area.

  As shown in FIG. 2 of Patent Document 1, in the light source drive device, the converter circuit unit 3 including the inductor L1 and the switch element Q1 connected in series to the LED module 12 is controlled to convert the converter circuit unit. Analog dimming is used to adjust the magnitude of the output current Io supplied to the LED module 12 from 3.

  Further, Patent Document 2 discloses a power supply device aiming to improve the power efficiency of the LED lamp device. As shown in FIG. 3 of Patent Document 2, in this power supply device, the switching element 316 connected in series to the LED lamp 106 is on / off controlled at a predetermined frequency, and current flows in the LED lamp 106. Digital dimming is used to adjust the length of the period.

JP, 2015-135738, A (paragraph 0010-0012, FIG. 2) JP, 2009-200053, A (paragraph 0014-0017, FIG. 3)

  A circuit for analog light control disclosed in Patent Document 1 and a circuit for digital light control disclosed in Patent Document 2 when both of analog light control and digital light control are performed in one light source device When combined with each other, each circuit operates independently. Therefore, even after the first switching element for digital dimming (the switching element 316 in Patent Document 2) shifts from the on state to the off state, the second switching element for analog dimming (switch element in Patent Document 1) Q1) may perform on / off operation.

  During the period in which the first switching element is in the off state, no current flows in the light emitting element, but when the second switching element is in the on state, the inductor (inductor L1 of Patent Document 1) to the second switching A current flows to the negative terminal of the DC power supply through the element. Therefore, the energy stored in the inductor is released without being used for light emission in the light emitting element. As a result, in the projection type video display apparatus using such a light source device, there is a problem that useless power loss occurs.

  On the other hand, it is conceivable to maintain the second switching element in the off state while the first switching element is in the off state, but if doing so, the on period of the second switching element is from the originally required on period. There is also a risk of shortening. This is a problem when the on period of the first switching element is shorter than the originally required on period of the second switching element (for example, when the on duty ratio of the first switching element is less than 5%). Become.

  In such a case, sufficient energy is not stored in the inductor, and the energy stored in the inductor gradually decreases during the off period of the second switching element, so the current flowing through the light emitting element indicates in analog dimming Therefore, the brightness of the light emitting element is insufficient.

  In particular, in the case of using a laser diode as a light emitting element, the current flowing through the laser diode does not reach the critical current of laser oscillation, so that the laser diode may not emit light. Moreover, there is a possibility that the brightness of the image projected by the projection type video display apparatus using such a light source device may run short.

  Therefore, in view of the above point, the first object of the present invention is that energy stored in the inductor is released without being used for light emission when performing both analog light control and digital light control. An object is to provide a light emission control circuit which can be suppressed to reduce power loss. The second object of the present invention is that, when performing such light emission control, the first switching element is in the on state even when the period during which current flows through the light emitting element in digital dimming is short. During a period, it is to prevent the current flowing to the light emitting element from being lower than the current indicated in the analog dimming. Furthermore, the third object of the present invention is to provide a light source device using such a light emission control circuit, and a projection type video display device etc using the light source device.

  In order to solve at least a part of the above problems, a light emission control circuit according to a first aspect of the present invention controls a current flowing to a light emitting element connected between a first node and one end of an inductor. A light emission control circuit for controlling a first switching element and a second switching element for controlling a current flowing from the other end of the inductor to the second node, wherein the first switching element is turned on or off To activate or deactivate the first control signal, and to activate or deactivate the second control signal during a period in which the first control signal is activated. And a switching control circuit for turning on or off the switching element 2 in the case where the on-duty ratio of the first control signal is equal to or greater than a predetermined value. And maintaining the second control signal in the inactive state during a period in which the first control signal is inactivated, and the on-duty ratio of the first control signal is less than a predetermined value. The second control signal is maintained in the activated state for a part of the period during which the control signal of the second control signal is inactivated.

  According to the first aspect of the present invention, when the on-duty ratio of the first control signal for digital dimming is equal to or more than a predetermined value, the analog is generated during the period in which the first control signal is inactivated. The second switching element is maintained in the off state by maintaining the second control signal for dimming in the inactivated state. As a result, when performing both analog light control and digital light control, it is possible to reduce power loss by suppressing the release of energy stored in the inductor without being used for light emission. .

  In addition, when the on-duty ratio of the first control signal for digital dimming is less than the predetermined value, the second for analog dimming is performed in part of a period in which the first control signal is inactivated. The second switching element is maintained in the on state by maintaining the control signal in the active state. Thus, even when the period during which current flows to the light emitting element in digital dimming is short, energy can be compensated for the inductor, and the current flowing to the light emitting element can be prevented from being lower than the current instructed in analog dimming .

  Here, when the on-duty ratio of the first control signal is less than the predetermined value, the switching control circuit performs a predetermined period after the first control signal transitions from the activated state to the inactivated state. The second control signal may be maintained in the activated state. Thus, the energy compensated in the inductor can be continuously increased by extending the period in which the second switching element is in the ON state by a predetermined period after the first control signal is deactivated. .

  Further, in the switching control circuit, the second control signal is inactivated even during the period in which the on-duty ratio of the first control signal is less than the predetermined value and the first control signal is activated. If not, the second control signal may be maintained in the activated state for a predetermined period. Thus, the pulse width of the second control signal can be extended only when the second control signal is activated as a single pulse while the first control signal is activated.

  Furthermore, when the on-duty ratio of the first control signal is the first value, the switching control circuit sets the predetermined period to the first period, and the on-duty ratio of the first control signal is the first. In the case of the second value smaller than the value, the predetermined period may be set to a second period longer than the first period. As a result, the energy compensated for in the inductor can be further increased when the period during which current flows through the light emitting element in digital dimming is shorter.

  Alternatively, the switching control circuit may adjust the predetermined period in accordance with the current flowing to the light emitting element. Thereby, when the current flowing to the light emitting element is smaller, the energy compensated for in the inductor can be further increased.

  Further, in the switching control circuit, when the on-duty ratio of the first control signal is less than the predetermined value, the current flowing to the light emitting element is higher than the predetermined value when the first control signal is activated. If smaller, the period for maintaining the second control signal in the activated state after the transition of the first control signal from the activated state to the inactivated state is extended by the first period, and the first control signal The second control signal is activated after the first control signal transitions from the activation state to the inactivation state when the current flowing to the light emitting element is larger than the predetermined value when the second activation signal is activated. The period of maintaining the state may be shortened by the second period.

  In that case, it is desirable that the second period be longer than the first period. For example, it is set when the on-duty ratio is the first value when the on-duty ratio of the first control signal changes from the first value to the second value larger than the first value. If the second control signal is generated according to the extension period, the current flowing to the light emitting element becomes excessive. Therefore, when the extension period is set next, the excess current can be eliminated early by shortening the extension period by the second period, which is longer than the first period.

  In the above, the light emission control circuit may receive information on the on-duty ratio of the first control signal from the outside. Thereby, the switching control circuit can adjust the inactivation timing of the second control signal based on the information on the on-duty ratio of the first control signal.

  According to a second aspect of the present invention, there is provided a light emission control circuit comprising: a first switching element for controlling a current flowing to a light emitting element connected between a first node and one end of an inductor; A light emission control circuit for controlling a second switching element for controlling a current flowing to the second node, the first control signal being activated or not for turning on or off the first switching element; And activating or deactivating the second control signal to turn on or off the second switching element during a period in which the first control signal is activated. When the current flowing to the light emitting element when the control signal of 1 is activated is smaller than a predetermined value, the activation of the second control signal during the period when the first control signal is inactivated. Ban The period is shortened, and when the current flowing to the light emitting element when the first control signal is activated is larger than a predetermined value, the first control signal is deactivated during the first period. And a switching control circuit for extending a period for inhibiting activation of the control signal of (2).

  According to the second aspect of the present invention, when the current flowing to the light emitting element is smaller than a predetermined value when the first control signal for digital light adjustment is activated, the first control signal is The period of disabling activation of the second control signal for analog dimming is shortened within the period of inactivation. Thus, even when the period during which current flows to the light emitting element in digital dimming is short, energy can be compensated for the inductor, and the current flowing to the light emitting element can be prevented from being lower than the current instructed in analog dimming .

  In addition, when the current flowing to the light emitting element is larger than a predetermined value when the first control signal for digital dimming is activated, the period during which the first control signal is inactivated. The period for inhibiting the activation of the second control signal for analog dimming is extended. As a result, when performing both analog light control and digital light control, it is possible to reduce power loss by suppressing the release of energy stored in the inductor without being used for light emission. .

  In the light emission control circuit according to the first or second aspect of the present invention, when the inactivation timing of the second control signal is adjusted based on the current flowing to the light emitting element, the light emission control circuit It may further include a sample and hold circuit that samples and holds a voltage proportional to the current flowing to the light emitting element when the control signal is activated. When the on-duty ratio of the first control signal decreases, the period during which current flows in the light emitting element is shortened. However, the sample and hold circuit has a higher operating speed than the operational amplifier and accurately measures the current flowing in the light emitting element. Can.

  A light source device according to a third aspect of the present invention is connected between any one of the light emission control circuits described above, a light emitting element, an inductor, first and second switching elements, and one end of an inductor and a first node. And a diode connected between the other end of the inductor and the first node, and when the first and second switching elements are in the on state, current flows in the light emitting element and the inductor When energy is stored in the inductor and the first switching element is on and the second switching element is off, the energy stored in the inductor causes a current to flow in the light emitting element and the diode, and the first switching is performed. When the element is off and the second switching element is on, current flows in the capacitor and the inductor. Energy is stored in inductor.

  According to the third aspect of the present invention, the light emission control circuit suppresses the release of the energy stored in the inductor without being used for light emission, and the period during which current flows to the light emitting element in digital dimming is By preventing a decrease in the current flowing to the light emitting element even in the case of a short time, it is possible to provide a light source device with less power loss and capable of accurately controlling the brightness.

  The projection type video display concerning the 4th viewpoint of the present invention is provided with the light source device concerning the 3rd viewpoint of the present invention. According to the fourth aspect of the present invention, the brightness of the projected image is accurately reduced while reducing the power consumption of the projection type video display device using a light source device which can accurately control the brightness with a small power loss. Can be controlled.

FIG. 1 is a circuit diagram of a light source device including a light emission control circuit according to a first embodiment of the present invention. FIG. 2 is a circuit diagram showing a configuration example of a drive circuit and a switching control circuit shown in FIG. 6 is a timing chart for explaining an operation example of the light emission control circuit shown in FIG. FIG. 6 is a circuit diagram of a light source device including a light emission control circuit according to a second embodiment of the present invention. FIG. 5 is a timing chart comparing the operation of the light emission control circuit shown in FIG. 1 and FIG. 4. FIG. 5 is a circuit diagram showing a configuration example of a clock signal generation circuit shown in FIG. 4; FIG. 7 is a waveform chart showing waveforms of respective parts of the clock signal generation circuit shown in FIG. 6; FIG. 10 is a circuit diagram of a light source device including a light emission control circuit according to a third embodiment of the present invention. FIG. 9 is a circuit diagram of the switching control circuit shown in FIG. 8 and its feedback loop. 7 is a timing chart for explaining an operation example in the first dimming mode. 7 is a timing chart for explaining an operation example in a second dimming mode. The timing chart for demonstrating the operation example in 3rd light control mode. The timing chart for demonstrating the operation example in 4th light control mode. FIG. 10 is a circuit diagram of a light source device including a light emission control circuit according to a fourth embodiment of the present invention. FIG. 15 is a circuit diagram showing a configuration example of a switching control circuit shown in FIG. FIG. 15 is a waveform chart for explaining an operation example of the light emission control circuit shown in FIG. 14; The circuit diagram of the light source device provided with the light emission control circuit which concerns on the 6th Embodiment of this invention. FIG. 18 is a circuit diagram showing an example of configuration of a switching control circuit shown in FIG. 17; FIG. 18 is a waveform chart for explaining an operation example of the light emission control circuit shown in FIG. 17; FIG. 16 is a circuit diagram showing a configuration example of a switching control circuit in a seventh embodiment. The circuit diagram of the light source device provided with the light emission control circuit which concerns on the 8th Embodiment of this invention. BRIEF DESCRIPTION OF THE DRAWINGS The block diagram which shows the structural example of the projection type video display apparatus concerning one Embodiment of this invention. The figure explaining operation | movement of the light source device which concerns on 8th Embodiment. The figure explaining operation | movement of the light source device which concerns on 8th Embodiment.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that the same reference numerals are given to the same components, and redundant description will be omitted.
First Embodiment
FIG. 1 is a circuit diagram showing a configuration example of a light source device provided with a light emission control circuit according to a first embodiment of the present invention. As shown in FIG. 1, the light source device includes a light emission control circuit 100, a light emitting element 110, an inductor L1, a P channel MOS transistor QP1 which is a first switching element, and an N channel which is a second switching element. It includes a MOS transistor QN1, a diode D1, resistors R1 to R3, and capacitors C1 to C4.

  The power supply potential VDD on the high potential side is supplied to the first node N1 of the light source device, and the power supply potential VSS on the low potential side is supplied to the second node N2. FIG. 1 shows the case where the power supply potential VSS is the ground potential (0 V). The transistor QP1, the light emitting element 110, the resistor R1, the inductor L1, the transistor QN1, and the resistor R2 are connected in series between the first node N1 and the second node N2. The light emitting element 110 includes, for example, at least one laser diode (LD) or light emitting diode (LED), and emits light at a brightness according to the magnitude of the supplied current.

  The transistor QP1 may be connected between the light emitting element 110 and the resistor R1 or between the resistor R1 and the inductor L1, but in the example shown in FIG. 1, the transistor QP1 is connected to the first node N1. It is connected between the light emitting element 110. The transistor QP1 has a source connected to the first node N1, a drain connected to the light emitting element 110, and a gate to which the first control signal DDRV is applied.

  The transistor QP1 is provided for digital dimming, and controls the current flowing to the light emitting element 110 connected between the first node N1 and one end of the inductor L1. The transistor QP1 turns on when the first control signal DDRV is activated to low level, and turns off when the first control signal DDRV is deactivated to high level. When the first control signal DDRV is alternately activated and deactivated, the transistor QP1 performs a switching operation.

  The resistor R1 is connected between the light emitting element 110 and one end of the inductor L1, has a small resistance value of, for example, about 50 mΩ, and is used to detect the current flowing to the transistor QP1 and the light emitting element 110. . The transistor QN1 has a drain connected to the other end of the inductor L1, a source connected to the second node N2 via the resistor R2, and a gate to which the second control signal GATE is applied. .

  The transistor QN1 is provided for analog dimming and controls the current flowing from the other end of the inductor L1 to the second node N2. The transistor QN1 is turned on when the second control signal GATE is activated to a high level, and turned off when the second control signal GATE is deactivated to a low level. When the second control signal GATE is alternately activated and deactivated, the transistor QN1 performs switching operation.

  The resistor R2 is connected between the source of the transistor QN1 and the second node N2, has a small resistance value of, for example, about 100 mΩ, and is used to detect the current flowing in the transistor QN1. In addition to the MOS transistor, a bipolar transistor, an IGBT (insulated gate bipolar transistor), a thyristor or the like can be used as the switching element.

  The diode D1 is connected between the other end of the inductor L1 and the first node N1, and has an anode connected to the other end of the inductor L1 and a cathode connected to the first node N1. ing. As the diode D1, for example, a Schottky barrier diode or the like having a forward voltage lower than that of a PN junction diode and a high switching speed is used.

  The capacitor C1 is connected between the first node N1 and the second node N2 to smooth the power supply voltage (VDD-VSS). The capacitor C4 is connected between one end of the inductor L1 and the first node N1, and steps down the power supply voltage (VDD-VSS) to smooth the obtained step-down voltage.

<Light emission control circuit>
The light emission control circuit 100 receives the digital light adjustment signal DCS and the analog light adjustment signal ACS from an external microcomputer or the like, and controls the transistors QP1 and QN1 of the light source device. Although FIG. 1 shows an example in which the light emission control circuit 100 is incorporated in one semiconductor device (IC), the light emission control circuit 100 may be configured of a plurality of discrete components or ICs. Also, the diode D1, the resistor R1, or the resistor R2 may be incorporated in the IC.

  As shown in FIG. 1, the light emission control circuit 100 includes an internal regulator 10, level shifters 21 and 22, a drive circuit 30, a clock signal generation circuit 40, a switching control circuit 50, a drive circuit 60, and switching control. It includes slope compensation circuit 71 to comparator 75 provided in the feedback loop of circuit 50.

  The internal regulator 10 includes, for example, a reference voltage generation circuit configured of a band gap reference circuit or the like, and generates an internal power supply potential VDA supplied to the internal circuit of the IC based on the power supply potential VDD. The capacitor C2 is connected between the output terminal of the internal regulator 10 and the second node N2 to smooth the internal power supply voltage (VDA-VSS). The level shifters (L / S) 21 and 22 shift the high level potential of the digital dimming signal DCS to a potential compatible with the internal circuit of the IC.

  The drive circuit 30 generates a first control signal DDRV that controls the transistor QP1 based on the digital dimming signal DCS supplied from the level shifter 21. For example, the drive circuit 30 generates the first control signal DDRV by inverting the digital dimming signal DCS to generate an inversion signal and making the high level potential of the inversion signal substantially equal to the power supply potential VDD. .

  In that case, when the digital dimming signal DCS is activated to a high level, the transistor QP1 is turned on, and a current flows in the light emitting element 110. Therefore, by changing the duty ratio of the digital light adjustment signal DCS, digital light adjustment can be performed by changing a period in which current flows in the light emitting element 110.

  The clock signal generation circuit 40 includes, for example, a CR oscillation circuit or the like, and generates a clock signal CLK having a predetermined frequency by performing an oscillation operation. The oscillation frequency of the CR oscillation circuit is determined by the time constant which is the product of the capacitance value of the capacitor and the resistance value of the resistor. The resistor R3 is externally attached to the IC in order to adjust the oscillation frequency of the CR oscillation circuit.

  The switching control circuit 50 generates a second control signal GATE for controlling the transistor QN1 based on the clock signal CLK, the reset signal RST, and the digital dimming signal DCS supplied from the level shifter 21. The second control signal GATE is applied to the gate of the transistor QN1 via the drive circuit 60 configured of a driver amplifier or the like. The power supply potential supplied to drive circuit 60 may be internal power supply potential VDA or another power supply potential higher than internal power supply potential VDA.

  When the transistors QP1 and QN1 are in the on state, a current flows from the first node N1 to the second node N2 via the light emitting element 110, the inductor L1, etc., and the electrical energy is converted to magnetic energy in the inductor L1. Accumulated. When the transistor QP1 is in the on state and the transistor QN1 is in the off state, the magnetic energy stored in the inductor L1 is released as electrical energy and a current flows in the light emitting element 110, the diode D1, and the like. When the transistor QP1 is in the off state and the transistor QN1 is in the on state, current flows in the capacitor C4 and the inductor L1 and the like, and energy is stored in the inductor L1.

  The slope compensation circuit 71 adds a bias voltage to the voltage across the current detection resistor R2 to generate a detection signal DET, and supplies the detection signal DET to the non-inverting input terminal of the comparator 75. The current sense amplifier 72 amplifies the voltage between both ends of the current detection resistor R1 to generate an output signal, and supplies the output signal to the inverting input terminal of the operational amplifier 73.

  An analog dimming signal ACS is supplied to the non-inverting input terminal of the operational amplifier 73. The operational amplifier 73 amplifies the difference between the voltage of the analog dimming signal ACS and the voltage of the output signal of the current sense amplifier 72 to generate an error signal ERR, and supplies the error signal ERR to the switch circuit (SW) 74.

  The switch circuit 74 includes, for example, an analog switch, and is turned on when the digital dimming signal DCS supplied from the level shifter 22 is activated, and the digital dimming signal DCS is inactivated. When it is off. Thus, the voltage of the error signal ERR generated when the transistor QP1 is in the on state is held by the capacitor C3 and supplied to the inverting input terminal of the comparator 75.

  The comparator 75 compares the voltage of the detection signal DET supplied from the slope compensation circuit 71 with the voltage of the error signal ERR to generate a reset signal RST corresponding to the comparison result, and switches the reset signal RST to the switching control circuit 50. Supply to

  The switching control circuit 50 activates the second control signal GATE to high level in synchronization with the rising of the clock signal CLK when the digital dimming signal DCS is activated to high level and the transistor QP1 is in the on state. Do. Accordingly, the transistor QN1 is turned on, and a current flows from the first node N1 to the resistor R2 for current detection via the light emitting element 110, the inductor L1, and the like.

  The current flowing through the inductor L1 gradually increases with time. As the current flowing to the resistor R2 through the inductor L1 or the like increases, the voltage of the detection signal DET also increases. When the voltage of the detection signal DET exceeds the voltage of the error signal ERR held in the capacitor C3, the reset signal RST is activated to the high level. As a result, the second control signal GATE is inactivated to a low level, and the transistor QN1 is turned off.

  In such PWM (pulse width modulation) operation, when the voltage of the analog dimming signal ACS rises, the on-duty ratio of the second control signal GATE increases, and the period during which the transistor QN1 is in the on state is long. The current flowing to the light emitting element 110 is increased. Therefore, by changing the voltage of the analog light adjustment signal ACS, the current flowing to the light emitting element 110 can be changed to perform analog light adjustment.

  On the other hand, when the transistor QP1 is in the off state, no current flows in the light emitting element 110. However, when the transistor QN1 is turned on, a current flows from the inductor L1 to the second node N2 through the transistor QN1, so the energy stored in the inductor L1 is released without being used for light emission in the light emitting element 110 It will As a result, in the projection type video display apparatus using such a light source device, there is a problem that useless power loss occurs.

  Therefore, in the present embodiment, when the switching control circuit 50 alternately activates and deactivates the second control signal GATE, the first control is performed so that the drive circuit 30 turns off the transistor QP1. While the signal DDRV is inactivated, the second control signal GATE is inactivated to turn off the transistor QN1.

  FIG. 2 is a circuit diagram showing a configuration example of the drive circuit and the switching control circuit shown in FIG. As shown in FIG. 2, the drive circuit 30 includes a level shifter 31 and a driver amplifier 32 to which the power supply potential VDD and the power supply potential VSS (ground potential) are supplied. The level shifter 31 inverts, for example, the digital dimming signal DCS supplied from the level shifter 21 shown in FIG. 1 to generate a first control signal DDRV. The high level potential of the first control signal DDRV is approximately equal to the power supply potential VDD. The first control signal DDRV is applied to the gate of the transistor QP1 (FIG. 1) via the driver amplifier 32. Note that the power supply potential VDD and the power supply potential VHB may be supplied to the level shifter 31 and the driver amplifier 32.

  The switching control circuit 50 includes, for example, an RS flip flop 51 and an AND circuit 52. The RS flip-flop 51 is set in synchronization with the rising of the clock signal CLK when the reset signal RST is at low level, and activates the output signal to high level, and when the clock signal CLK is at low level, The signal is reset in synchronization with the rise of the reset signal RST to inactivate the output signal to a low level.

  The AND circuit 52 generates a second control signal GATE by obtaining the logical product of the digital dimming signal DCS and the output signal of the RS flip flop 51. Therefore, when the digital dimming signal DCS is inactivated to low level, the first control signal DDRV is inactivated to high level, and the second control signal GATE is inactivated to low level. .

<Operation example>
FIG. 3 is a timing chart for explaining an operation example of the light emission control circuit shown in FIG. In FIG. 3, the amplitude of the signal is normalized to be constant. In this example, the drive circuit 30 inverts the digital dimming signal DCS to generate a first control signal DDRV. When the first control signal DDRV is activated to a low level, the transistor QP1 is turned on, and when the first control signal DDRV is deactivated to a high level, the transistor QP1 is turned off. Become.

  For example, the drive circuit 30 always activates the first control signal DDRV in the first dimming mode in which the light emitting element 110 emits light relatively brightly. On the other hand, in the second dimming mode in which the drive circuit 30 causes the light emitting element 110 to emit light relatively darkly (darker than the first dimming mode), the first control signal is generated according to the duty ratio of the digital dimming signal DCS. By alternately activating and deactivating DDRV, the length of a period in which current flows in the light emitting element 110 is adjusted.

  The switching control circuit 50 emits light by alternately activating and deactivating the second control signal GATE in accordance with the voltage of the analog dimming signal ACS in the first dimming mode and the second dimming mode. The magnitude of the current flowing to the element 110 is adjusted. Thus, in the first dimming mode in which the light emitting element 110 emits light relatively brightly, only analog dimming is performed, and in the second dimming mode in which the light emitting element 110 emits relatively dark, analog dimming is performed. In addition, digital dimming can be performed.

  When the second control signal GATE is activated to a high level, the transistor QN1 is turned on, and when the second control signal GATE is deactivated to a low level, the transistor QN1 is turned off. Become. As shown in FIG. 3, the switching control circuit 50 deactivates the second control signal GATE to low level during the period T0 in which the drive circuit 30 deactivates the first control signal DDRV to high level. Do.

  According to the light emission control circuit 100 according to the present embodiment, when performing both of the analog light adjustment and the digital light adjustment, the period during which the digital light adjustment transistor QP1 is turned off and the current does not flow to the light emitting element 110 , The analog dimming transistor QN1 is maintained in the off state. Thus, it is possible to reduce the power loss by suppressing the energy stored in the inductor L1 from being released without being used for light emission.

Second Embodiment
FIG. 4 is a circuit diagram showing a configuration example of a light source device provided with a light emission control circuit according to a second embodiment of the present invention. In the second embodiment, a clock signal generation circuit 40a is used in place of the clock signal generation circuit 40 in the first embodiment shown in FIG. In other respects, the second embodiment may be similar to the first embodiment. 5 is a timing chart comparing operations of the light emission control circuit shown in FIG. 1 and FIG. In FIG. 5, the amplitude of the signal is normalized to be constant.

  In the light emission control circuit 100 according to the first embodiment shown in FIG. 1, the clock signal generation circuit 40 operates independently of the digital dimming signal DCS. Therefore, when the digital dimming transistor QP1 performs a switching operation and the light emitting element 110 emits light intermittently, the first control signal DDRV is activated depending on the timing at which the digital dimming signal DCS is activated. The timing at which the second control signal GATE (1) is activated first is delayed. Alternatively, as shown in FIG. 5, the activation period T1 in which the second control signal GATE (1) is first maintained in the activated state after the activation of the first control signal DDRV is shortened.

  If the timing at which the transistor QN1 first turns on after the transistor QP1 turns on is delayed, the light emission timing of the light emitting element 110 may be delayed or light emission may occur in a state where sufficient energy is not stored in the inductor L1. A sufficient current does not flow in the element 110. In addition, when the activation period T1 is short, the transistor QN1 is switched to the OFF state while sufficient energy is not accumulated in the inductor L1, so that a sufficient current does not flow in the light emitting element 110. As a result, the light emission timing or the brightness of the light emitting element 110 may be varied, which may cause the operator of the light source device to feel discomfort. In addition, there is a possibility that the brightness of an image projected by a projection type video display using such a light source device may change.

  Therefore, in the second embodiment, the switching control circuit 50 starts the activation of the second control signal GATE in synchronization with the activation of the first control signal DDRV. Thus, when the light emitting element 110 emits light intermittently due to digital dimming, the transistor QN1 is also turned on when the transistor QP1 is turned on, so that the fluctuation of the light emission timing of the light emitting element 110 or the fluctuation of the brightness is reduced. can do. In addition, it is possible to reduce the fluctuation of the brightness of the image projected by the projection type video display device provided with such a light source device.

  Furthermore, switching control circuit 50 sets activation period T1 (FIG. 5) in which second control signal GATE is first maintained in the activated state after activation of first control signal DDRV as a predetermined period or more. Also good. Here, the predetermined period is within 95% or less of the activation period T2 in which the second control signal GATE is maintained in the activated state for the second time after the activation of the first control signal DDRV. Is desirable.

  Thereby, when the light emitting element 110 intermittently emits light due to digital dimming, the transistor QN1 is turned on, sufficient energy is accumulated in the inductor L1, and then the transistor QN1 is shifted to the off state. The variation of the brightness of 110 can be reduced. On the other hand, in the case of masking the pulse of the second control signal GATE generated first after the activation of the first control signal DDRV, although the generation of a short pulse can be prevented, the second There is a problem that activation of the control signal GATE is delayed.

  The light emission control circuit 100 shown in FIG. 4 includes a clock signal generation circuit 40a that starts generation of the clock signal CLK in synchronization with activation of the first control signal DDRV supplied from the level shifter 22. The circuit 50 activates the second control signal GATE in synchronization with the clock signal CLK. Thus, the activation timing of the second control signal GATE can be synchronized with the activation timing of the first control signal DDRV.

  6 is a circuit diagram showing a configuration example of the clock signal generation circuit shown in FIG. 4, and FIG. 7 is a waveform diagram showing waveforms of respective parts of the clock signal generation circuit shown in FIG. The clock signal generation circuit 40a operates by being supplied with the internal power supply potential VDA of the IC and the power supply potential VSS. In the following, it is assumed that the power supply potential VSS is the ground potential (0 V).

  As shown in FIG. 6, clock signal generation circuit 40a includes constant current sources 41 and 42, comparator 43, buffer circuit 44, inverter 45, P channel MOS transistor QP2, N channel MOS transistors QN2 to QN4. , Resistors R4 to R6, and a capacitor C5.

  The constant current source 41 is connected between the wiring of the internal power supply potential VDA of the IC and the non-inverting input terminal of the comparator 43. The constant current source 42 is connected between the non-inverting input terminal of the comparator 43 and the line of the power supply potential VSS via the transistor QN3. For example, the constant current sources 41 and 42 are respectively formed of a P channel MOS transistor and an N channel MOS transistor which supply a constant current by applying a predetermined bias voltage between the gate and the source.

  The comparator 43 compares the input potential V1 supplied to the non-inverted input terminal with the input potential V2 supplied to the inverted input terminal, and outputs a clock signal CLK corresponding to the comparison result from the output terminal. The buffer circuit 44 buffers and outputs the clock signal CLK supplied from the comparator 43. The inverter 45 inverts the digital dimming signal DCS and outputs it.

  The transistor QP2 has a source connected to the non-inversion input terminal of the comparator 43, a drain connected to the inversion input terminal of the comparator 43, and a gate to which the digital dimming signal DCS is applied. The transistor QN2 has a drain connected to the output terminal of the comparator 43, a source connected to the line of the power supply potential VSS, and a gate to which the output signal of the inverter 45 is applied.

  The capacitor C5 is connected between the non-inverting input terminal of the comparator 43 and the line of the power supply potential VSS. The resistor R4 is connected between the wiring of the internal power supply potential VDA of the IC and the inverting input terminal of the comparator 43. The resistors R5 and R6 are connected in series between the inverting input terminal of the comparator 43 and the wiring of the power supply potential VSS.

  The transistor QN3 has a drain connected to the non-inversion input terminal of the comparator 43, a source connected to the line of the power supply potential VSS via the constant current source 42, and a gate to which the output signal of the comparator 43 is applied. have. The transistor QN4 has a drain connected to the connection point of the resistors R5 and R6, a source connected to the line of the power supply potential VSS, and a gate to which the output signal of the comparator 43 is applied.

  When the digital dimming signal DCS is inactivated to the low level (VSS), the transistors QP2 and QN2 are in the on state. As a result, the clock signal CLK output from the comparator 43 becomes low level, and the transistors QN3 and QN4 are in the off state.

Therefore, the input potentials V1 and V2 supplied to the comparator 43 are substantially equal to the divided voltage VH obtained by dividing the power supply voltage VDA by the resistors R4 to R6.
VH = {(R5 + R6) / (R4 + R5 + R6)} VDA (1)
In practice, the input potentials V1 and V2 are slightly higher than the divided voltage VH represented by the equation (1) due to the current supplied from the constant current source 41. In addition, the capacitor C5 is charged by the input potential V1.

  When the digital dimming signal DCS is activated to the high level (VDA), the transistors QP2 and QN2 are turned off. Thereby, the non-inverted input terminal and the inverted input terminal of the comparator 43 are electrically separated. The input potential V2 at the inverting input terminal of the comparator 43 drops to the divided voltage VH expressed by the equation (1) and becomes lower than the input potential V1 at the non-inverting input terminal of the comparator 43. The clock signal CLK output from 43 transitions to the high level, and the transistors QN3 and QN4 are turned on.

Therefore, since the charge stored in the capacitor C5 is discharged through the transistor QN3 and the constant current source 42, the input potential V1 of the non-inverting input terminal of the comparator 43 gradually decreases toward the power supply potential VSS. . Further, the input potential V2 of the inverting input terminal of the comparator 43 immediately decreases to the divided voltage VL represented by the following equation (2).
VL = {R5 / (R4 + R5)} VDA (2)

  When the input potential V1 at the non-inverted input terminal of the comparator 43 is lower than the divided voltage VL, the clock signal CLK output from the comparator 43 transitions to the low level, and the transistors QN3 and QN4 are turned off. Therefore, since the capacitor C5 is charged by the current supplied from the constant current source 41, the input potential V1 of the non-inverting input terminal of the comparator 43 gradually rises toward the internal power supply potential VDA of the IC. Further, the input potential V2 of the inverting input terminal of the comparator 43 immediately rises to the divided voltage VH represented by the equation (1).

  When the input potential V1 at the non-inversion input terminal of the comparator 43 rises above the divided voltage VH, the clock signal CLK output from the comparator 43 transitions to the high level. By repeating such an operation, the clock signal generation circuit 40a generates a clock signal CLK having a predetermined frequency.

Third Embodiment
FIG. 8 is a circuit diagram showing a configuration example of a light source device provided with a light emission control circuit according to a third embodiment of the present invention. In the third embodiment, a switching control circuit 50a is used in place of the switching control circuit 50 in the second embodiment shown in FIG. In addition, a circuit provided in the feedback loop of the switching control circuit 50a is added. In other respects, the third embodiment may be similar to the second embodiment.

  As in the second embodiment, when the transistor QN1 is maintained in the off state while the transistor QP1 is in the off state, the on period of the transistor QP1 is short (for example, the on duty ratio is less than 5%) In addition, the on period of the transistor QN1 may be shorter than the originally required on period.

  In such a case, sufficient energy is not stored in the inductor L1, and the energy stored in the inductor L1 gradually decreases in the off period of the transistor QN1, so that the current flowing through the light emitting element 110 is the analog dimming signal ACS. Therefore, the luminance of the light emitting element 110 is insufficient.

  Therefore, in the third embodiment, the switching control circuit 50a sets the second control signal GATE to turn on or off the transistor QN1 in a period during which the first control signal DDRV is activated. When the first control signal DDRV is inactivated, the second control signal GATE is inactivated while the activation or inactivation is performed and the on-duty ratio of the first control signal DDRV is equal to or greater than a predetermined value. When the first control signal DDRV is maintained in the activated state and the on-duty ratio of the first control signal DDRV is less than a predetermined value, the second control signal is generated during a portion of the period in which the first control signal DDRV is inactivated. Keep GATE active.

  According to the third embodiment, when the on-duty ratio of the first control signal DDRV for digital dimming is equal to or more than a predetermined value, the analog is generated during the period in which the first control signal DDRV is inactivated. By maintaining the second dimming control signal GATE in the inactive state, the transistor QN1 is maintained in the OFF state. Thereby, when performing both analog light control and digital light control, it is possible to reduce the power loss by suppressing the energy stored in the inductor L1 from being released without being used for light emission Become.

  Also, when the on-duty ratio of the first control signal DDRV for digital dimming is less than a predetermined value, the part for a period during which the first control signal DDRV is inactivated is for analog dimming. By maintaining the second control signal GATE in the activated state, the transistor QN1 is maintained in the on state. Thus, even when the period during which current flows through the light emitting element 110 in digital dimming is short, energy is compensated for the inductor L1, and the current flowing through the light emitting element 110 is lower than the current instructed in analog dimming. Can be prevented.

  As shown in FIG. 8, in the feedback loop of the switching control circuit 50a, in addition to the slope compensation circuit 71 to the comparator 75 in the second embodiment shown in FIG. 4, a sample hold circuit 76 and a current sense amplifier 77; A selection circuit 78 is provided.

  The drive circuit 30 activates or deactivates the first control signal DDRV in order to turn on or off the transistor QP1. For example, the drive circuit 30 inverts the digital dimming signal DCS supplied from the level shifter 21 to generate an inversion signal, and makes the high level electric potential of the inversion signal approximately equal to the power supply potential VDD. To generate the control signal DDRV.

  The slope compensation circuit 71 adds a bias voltage to the voltage across the current detection resistor R2 to generate a detection signal DET, and supplies the detection signal DET to the non-inverting input terminal of the comparator 75. The current sense amplifier 72 amplifies the voltage across the resistor R1 (current detection voltage), which is proportional to the current flowing to the light emitting element 110, and generates an output signal. The sample and hold circuit 76 operates by being supplied with the power supply potential VDD (for example, 50 V) and the power supply potential VHB (for example, 45 V), and flowing through the light emitting element 110 when the first control signal DDRV is activated. And hold the current detection voltage proportional to.

  When the on-duty ratio of the first control signal DDRV decreases, the period in which the current flows in the light emitting element 110 is shortened, but the sample and hold circuit 76 has an operating speed faster than that of the operational amplifier and the current flowing in the light emitting element 110 It can be measured well. The current sense amplifier 77 amplifies the current detection voltage held in the sample and hold circuit 76 to generate an output signal.

  The selection circuit 78 selects one of the output signal of the current sense amplifier 72 and the output signal of the current sense amplifier 77 in accordance with the selection signal supplied from the switching control circuit 50 a, and selects the selected signal from the operational amplifier 73. Supply to the inverting input terminal. An analog dimming signal ACS is supplied to the non-inverting input terminal of the operational amplifier 73. The operational amplifier 73 amplifies the difference between the voltage of the analog dimming signal ACS and the voltage of the signal selected by the selection circuit 78 to generate an error signal ERR, and supplies the error signal ERR to the switch circuit 74.

  The switch circuit 74 is turned off in a period in which the digital dimming signal DCS is inactivated to a low level and in a predetermined mask period according to a control signal supplied from the switching control circuit 50a, and is turned on in other periods. It becomes. As a result, the voltage of the error signal ERR generated when the switch circuit 74 is in the on state is held by the capacitor C3 and supplied to the inverting input terminal of the comparator 75.

  The comparator 75 compares the voltage of the detection signal DET supplied from the slope compensation circuit 71 with the voltage of the error signal ERR to generate a comparison result signal COMP according to the comparison result, and controls the switching of the comparison result signal COMP. It supplies to the circuit 50a.

  The switching control circuit 50a is a second control signal for turning on or off the transistor QN1 based on the clock signal CLK, the comparison result signal COMP, and the digital dimming signal DCS supplied from the level shifter 21. Activate or deactivate GATE.

  FIG. 9 is a circuit diagram showing a configuration example of the switching control circuit shown in FIG. 8 and a circuit of its feedback loop. In this example, switching control circuit 50 a includes RS flip flop 51, AND circuit 52, inverter 53, delay circuit 54, switch circuits 55 and 56, OR circuit 57, and condition setting circuit 58. There is.

  The RS flip-flop 51 is set in synchronization with the rising of the clock signal CLK when the output signal of the OR circuit 57 is at the low level, and activates the second control signal GATE to the high level. When it is low level, it is reset in synchronization with the rise of the output signal of the OR circuit 57 to inactivate the second control signal GATE to low level.

  The inverter 53 inverts the digital dimming signal DCS supplied from the level shifter 21 (FIG. 8) to generate an output signal. The delay circuit 54 is composed of, for example, delay elements such as a plurality of inverters with gate delay, or resistors and capacitors, and delays the output signal of the inverter 53 by the delay time TD.

  The AND circuit 52 generates an output signal by calculating the logical product of the output signal of the inverter 53 and the output signal of the delay circuit 54. The output signal of the AND circuit 52 goes low when the digital dimming signal DCS is activated, and goes high when the delay time TD elapses after the digital dimming signal DCS is deactivated.

  The switch circuits 55 and 56 are formed of, for example, analog switches, and select one of the output signal of the inverter 53 and the output signal of the AND circuit 52. The OR circuit 57 generates an output signal by calculating the logical sum of the signal selected by the switch circuits 55 and 56 and the comparison result signal COMP output from the comparator 75. An output signal of the OR circuit 57 is supplied to a reset terminal of the RS flip flop 51.

  In the OR circuit 57, when the signal selected by the switch circuits 55 and 56 becomes high level, or the voltage of the detection signal DET rises above the voltage of the error signal ERR and the comparison result signal COMP becomes high level, Generate a high level output signal. As a result, the RS flip flop 51 is reset to inactivate the second control signal GATE.

  The condition setting circuit 58 is formed of, for example, a logic circuit including a combinational circuit or a sequential circuit, and controls the switch circuits 55 and 56, the switch circuit 74, and the selection circuit 78. Selection circuit 78 includes switch circuits 78a and 78b formed of, for example, N channel MOS transistors or various transistors, and selects one of the output signal of current sense amplifier 72 and the output signal of current sense amplifier 77. Then, the selected signal is supplied to the inverting input terminal of the operational amplifier 73.

<First operation example>
In the first operation example, the light emission control circuit 100 (FIG. 8) outputs information on the on duty ratio of the digital dimming signal DCS, that is, information on the on duty ratio of the first control signal DDRV to an external microcomputer or the like. Receive from Thereby, the switching control circuit 50a can adjust the inactivation timing of the second control signal GATE based on the information on the on-duty ratio of the first control signal DDRV.

  For example, four types of dimming modes are set according to the on-duty ratio of the first control signal DDRV, and information specifying the current dimming mode is supplied to the condition setting circuit 58. The condition setting circuit 58 sets conditions for inactivating the second control signal GATE based on the information specifying the current dimming mode, and generates the selection signals SEL1 to SEL4.

  In the first dimming mode, the on-duty ratio of the first control signal DDRV is 100%, and only analog dimming is performed. In the second dimming mode, the on-duty ratio of the first control signal DDRV is 50% or more and less than 100%, and in the third dimming mode, the on-duty ratio of the first control signal DDRV is 5 % And less than 50%, and in the fourth dimming mode, the on-duty ratio of the first control signal DDRV is greater than 0% and less than 5%. In the second to fourth dimming modes, both analog dimming and digital dimming are performed. In the present embodiment or another embodiment, the on-duty ratio may have a lower limit (for example, 1%).

  In the first dimming mode and the second dimming mode, the condition setting circuit 58 activates the selection signal SEL1 and deactivates the selection signal SEL2. As a result, the switch circuit 78a is turned on and the switch circuit 78b is turned off, so that the output signal of the current sense amplifier 72 is supplied to the inverting input terminal of the operational amplifier 73.

  On the other hand, in the third dimming mode and the fourth dimming mode, the condition setting circuit 58 deactivates the selection signal SEL1 and activates the selection signal SEL2. As a result, the switch circuit 78a is turned off and the switch circuit 78b is turned on, so that the output signal of the current sense amplifier 77 is supplied to the inverting input terminal of the operational amplifier 73.

  Therefore, when the on-duty ratio of the first control signal DDRV is 50% or more, the output signal of the current sense amplifier 72 for amplifying the current detection voltage proportional to the current flowing through the light emitting element 110 is the second control. It is used to adjust the inactivation timing of the signal GATE. On the other hand, when the on-duty ratio of the first control signal DDRV is less than 50%, the output signal of the current sense amplifier 77 for amplifying the current detection voltage held in the sample and hold circuit 76 is the second control signal. It is used to adjust the inactivation timing of GATE.

  In the first to third dimming modes, the condition setting circuit 58 activates the selection signal SEL3 and deactivates the selection signal SEL4. As a result, the switch circuit 55 is turned on and the switch circuit 56 is turned off, so that the output signal of the inverter 53 is supplied to one input terminal of the OR circuit 57. The other input terminal of the OR circuit 57 is supplied with the comparison result signal COMP output from the comparator 75.

  The OR circuit 57 is high when the digital dimming signal DCS is inactivated to low level or the voltage of the detection signal DET is higher than the voltage of the error signal ERR and the comparison result signal COMP becomes high level. Generate a level output signal. As a result, the RS flip flop 51 is reset to inactivate the second control signal GATE. Therefore, if the on-duty ratio of the first control signal DDRV is 5% or more, the second control signal GATE is maintained in the inactive state during the period when the first control signal DDRV is inactivated. Be done.

  On the other hand, in the fourth dimming mode, the condition setting circuit 58 deactivates the selection signal SEL3 and activates the selection signal SEL4. As a result, the switch circuit 55 is turned off and the switch circuit 56 is turned on, so that the output signal of the AND circuit 52 is supplied to one input terminal of the OR circuit 57. The other input terminal of the OR circuit 57 is supplied with the comparison result signal COMP output from the comparator 75.

  In the OR circuit 57, the delay time TD elapses after the digital dimming signal DCS is inactivated to the low level, or the voltage of the detection signal DET rises higher than the voltage of the error signal ERR and the comparison result signal COMP Goes high, producing a high level output signal. As a result, the RS flip flop 51 is reset to inactivate the second control signal GATE. Therefore, when the on-duty ratio of the first control signal DDRV is less than 5%, the second control signal GATE is activated in part of the period in which the first control signal DDRV is inactivated. Maintained.

  Since the current flowing through the inductor L1 (FIG. 8) gradually increases after the transistor QN1 is turned on, if the on-duty ratio of the first control signal DDRV is small, the first control signal DDRV is deactivated. Before and after the timing, the comparison result signal COMP output from the comparator 75 maintains the low level.

  10 to 13 are timing charts for explaining an operation example in the first to fourth dimming modes. As shown in FIG. 10, in the first dimming mode, the digital dimming signal DCS is always activated to the high level, and the second control signal GATE is activated to the high level and inactive to the low level. Analog dimming is performed by the conversion. On the other hand, as shown in FIGS. 11 to 13, in the second to fourth dimming modes, the digital dimming signal DCS is also activated to a high level and deactivated to a low level, and analog dimming and digital are performed. Both dimming and dimming are performed.

  As shown in FIGS. 11 and 12, in the second dimming mode and the third dimming mode, the second control signal GATE is activated to the high level in synchronization with the rising of the digital dimming signal DCS. Be done. Further, the second control signal GATE is forcibly inactivated to the low level in synchronization with the fall of the digital dimming signal DCS.

  As shown in FIG. 13, in the fourth dimming mode, the second control signal GATE is activated to the high level in synchronization with the rising of the digital dimming signal DCS. On the other hand, when the second control signal GATE is inactivated, the second control signal GATE is not synchronized with the fall of the digital dimming signal DCS, and the delay time TD (from the fall of the digital dimming signal DCS) It is maintained in the activated state for a predetermined period of time and then inactivated to a low level.

  As shown in FIG. 11, in the second dimming mode, the condition setting circuit 58 is activated in a predetermined mask period (MASK TIME) immediately after the digital dimming signal DCS transitions to the activated state. A mask signal MASK may be generated. The mask signal MASK is used to turn off the switch circuit 74. Thereby, the influence of measurement error due to the slow operation speed of current sense amplifier 72 can be avoided.

  Further, as shown in FIGS. 12 and 13, in the third light control mode and the fourth light control mode, the condition setting circuit 58 performs a predetermined operation immediately before the digital light control signal DCS transitions to the inactive state. A sample hold signal SHS may be generated which is activated in the sample hold period (S / H TIME).

  The sample hold signal SHS is used to cause the sample hold circuit 76 to perform a sample hold operation. Thus, the sample and hold circuit 76 can perform the sample and hold operation after the current flowing to the light emitting element 110 is stabilized. Alternatively, the sample hold signal SHS may be supplied to the light emission control circuit 100 (FIG. 8) from an external microcomputer or the like.

  Thus, switching control circuit 50a activates first control signal DDRV when the on-duty ratio of first control signal DDRV is less than a predetermined value (5% in this example). The second control signal GATE is maintained in the activated state for a predetermined period after transitioning to the non-activated state. Thus, the energy compensated for the inductor L1 can be continuously increased by extending the period in which the transistor QN1 is in the ON state for a predetermined period after the first control signal DDRV is deactivated.

  At this time, switching control circuit 50a sets second control signal GATE in a period in which the on-duty ratio of first control signal DDRV is less than a predetermined value and first control signal DDRV is activated. The second control signal GATE may be maintained in the activated state for a predetermined period when the second control signal GATE is not inactivated. Thereby, the pulse width of the second control signal GATE can be extended only when the second control signal GATE is activated as a single pulse in a period in which the first control signal DDRV is activated. it can.

  Therefore, the condition setting circuit 58 activates the selection signal SEL3 and selects, for example, when the comparison result signal COMP is at a high level even once during the period when the digital dimming signal DCS is activated. Deactivate signal SEL4. The state is released next time the digital dimming signal DCS is activated.

<Second operation example>
In the second operation example, the condition setting circuit 58 may set the condition for deactivating the second control signal GATE even if the information on the on-duty ratio of the digital dimming signal DCS is not supplied from the outside. it can. For example, the condition setting circuit 58 generates the selection signals SEL1 to SEL4 based on the digital dimming signal DCS and the comparison result signal COMP output from the comparator 75.

  The condition setting circuit 58 sets the on-duty ratio of the first control signal DDRV to a predetermined value or more when the comparison result signal COMP is at a high level even once during the period in which the digital dimming signal DCS is activated. It is determined that the selection signals SEL1 and SEL3 are activated, and the selection signals SEL2 and SEL4 are inactivated.

  As a result, the switch circuit 78a is turned on and the switch circuit 78b is turned off, so that the output signal of the current sense amplifier 72 is supplied to the inverting input terminal of the operational amplifier 73. Further, since the switch circuit 55 is turned on and the switch circuit 56 is turned off, the output signal of the inverter 53 is supplied to one input terminal of the OR circuit 57. The other input terminal of the OR circuit 57 is supplied with the comparison result signal COMP output from the comparator 75.

  The OR circuit 57 is high when the digital dimming signal DCS is inactivated to low level or the voltage of the detection signal DET is higher than the voltage of the error signal ERR and the comparison result signal COMP becomes high level. Generate a level output signal. As a result, the RS flip flop 51 is reset to inactivate the second control signal GATE. Therefore, when the on-duty ratio of first control signal DDRV is equal to or higher than the predetermined value, second control signal GATE is in the inactive state during the period when first control signal DDRV is inactivated. Maintained.

  On the other hand, the condition setting circuit 58 sets the on-duty ratio of the first control signal DDRV to a predetermined value when the comparison result signal COMP is not activated even once during the period in which the digital dimming signal DCS is activated. The selection signals SEL1 and SEL3 are inactivated while the selection signals SEL2 and SEL4 are activated.

  As a result, the switch circuit 78a is turned off and the switch circuit 78b is turned on, so that the output signal of the current sense amplifier 77 is supplied to the inverting input terminal of the operational amplifier 73. Further, since the switch circuit 55 is turned off and the switch circuit 56 is turned on, the output signal of the AND circuit 52 is supplied to one input terminal of the OR circuit 57. The other input terminal of the OR circuit 57 is supplied with the comparison result signal COMP output from the comparator 75.

  In the OR circuit 57, the delay time TD elapses after the digital dimming signal DCS is inactivated to the low level, or the voltage of the detection signal DET rises higher than the voltage of the error signal ERR and the comparison result signal COMP Goes high, producing a high level output signal. As a result, the RS flip flop 51 is reset to inactivate the second control signal GATE. Therefore, when the on-duty ratio of the first control signal DDRV is less than the predetermined value, the second control signal GATE is activated in part of the period in which the first control signal DDRV is inactivated. It is maintained in the state.

  Since the current flowing through inductor L1 (FIG. 8) gradually increases after transistor QN1 is turned on, if the on-duty ratio of first control signal DDRV is small, first control signal DDRV is not Before and after the activated timing, the comparison result signal COMP output from the comparator 75 maintains the low level.

Fourth Embodiment
FIG. 14 is a circuit diagram showing a configuration example of a light source device provided with a light emission control circuit according to a fourth embodiment of the present invention. In the fourth embodiment, a switching control circuit 50b is used in place of the switching control circuit 50 in the second embodiment shown in FIG. In addition, a comparator 79, an inverter 80, an up / down counter 81, and a pulse width extending circuit 82 are added. In the other respects, the fourth embodiment may be similar to the second embodiment.

  The slope compensation circuit 71 adds a bias voltage to the voltage across the current detection resistor R2 to generate a detection signal DET, and supplies the detection signal DET to the non-inverting input terminal of the comparator 75. The current sense amplifier 72 amplifies the voltage across the resistor R1 (current detection voltage), which is proportional to the current flowing to the light emitting element 110, and generates an output signal. The comparator 75 compares the voltage of the detection signal DET supplied from the slope compensation circuit 71 with the voltage of the error signal ERR to generate a comparison result signal COMP according to the comparison result, and controls the switching of the comparison result signal COMP. It supplies to the circuit 50b.

  The comparator 79 compares the voltage of the output signal of the current sense amplifier 72 with the voltage of the analog dimming signal ACS to generate an output signal ICOMP according to the comparison result. The output signal ICOMP of the comparator 79 is high when the current flowing through the light emitting element 110 is smaller than a predetermined value, and is low when the current flowing through the light emitting element 110 is larger than the predetermined value. Note that a certain response time is required for the output voltage of current sense amplifier 72 and the output level of comparator 79 to change, so the previous state is maintained when digital dimming signal DCS falls. ing. The output signal ICOMP of the comparator 79 is supplied to the up / down counter 81.

  The inverter 80 inverts the digital dimming signal DCS supplied from the level shifter 22 and supplies it to the up / down counter 81. The up / down counter 81 performs an up-counting operation or a down-counting operation in accordance with the output signal ICOMP of the comparator 79 in synchronization with the fall of the digital dimming signal DCS.

  For example, when the power is turned on, the count value of the up / down counter 81 is reset to the initial value. The up / down counter 81 increments the count value when the output signal ICOMP of the comparator 79 is high level in synchronization with the fall of the digital dimming signal DCS, and the output signal ICOMP of the comparator 79 is low level Decrement the count value at a certain time.

  The pulse width extending circuit 82 is formed of, for example, a logic circuit including a combinational circuit or a sequential circuit, and selects the activation period (pulse width) of the second control signal GATE based on the count value of the up / down counter 81. To generate the selection signal SEL used to output the selection signal SEL to the switching control circuit 50b.

  The switching control circuit 50b turns the transistor QN1 on or off based on the clock signal CLK, the comparison result signal COMP, the selection signal SEL, and the digital dimming signal DCS supplied from the level shifter 21. 2. Activate or deactivate control signal GATE of 2.

  FIG. 15 is a circuit diagram showing a configuration example of the switching control circuit shown in FIG. In this example, the switching control circuit 50 b includes an RS flip flop 51, an AND circuit 52, an inverter 53, an OR circuit 57, and a variable delay circuit 59.

  The RS flip-flop 51 is set in synchronization with the rising of the clock signal CLK when the output signal of the OR circuit 57 is at the low level, and activates the second control signal GATE to the high level. When it is low level, it is reset in synchronization with the rise of the output signal of the OR circuit 57 to inactivate the second control signal GATE to low level.

  The inverter 53 inverts the digital dimming signal DCS to generate an output signal, and supplies the output signal to the variable delay circuit 59. The variable delay circuit 59 includes a plurality of delay circuits to which the output signal of the inverter 53 is supplied in parallel, and a selection circuit 59a for selecting one of the output signals of the inverter 53 and the output signals of the plurality of delay circuits. Contains. For example, each delay circuit is composed of a delay element such as a plurality of inverters with a gate delay or a resistor and a capacitor, and the selection circuit 59a is composed of a plurality of analog switches or the like.

  The plurality of delay circuits have different delay times TD1, TD2,..., TDn, and delay the digital dimming signal DCS inverted by the inverter 53. Further, the selection circuit 59a selects the delay time TD of the digital dimming signal DCS inverted by the inverter 53 in accordance with the selection signal SEL supplied from the pulse width extension circuit 82 (FIG. 14).

  The AND circuit 52 generates an output signal by calculating the logical product of the output signal of the inverter 53 and the output signal of the variable delay circuit 59. The output signal of the AND circuit 52 goes low when the digital dimming signal DCS is activated, and goes high when the delay time TD elapses after the digital dimming signal DCS is deactivated ( TD 0 0).

  The OR circuit 57 generates an output signal by obtaining the logical sum of the output signal of the AND circuit 52 and the comparison result signal COMP output from the comparator 75 (FIG. 14). An output signal of the OR circuit 57 is supplied to a reset terminal of the RS flip flop 51. The OR circuit 57 outputs a high level when the output signal of the AND circuit 52 goes high or the voltage of the detection signal DET rises above the voltage of the error signal ERR and the comparison result signal COMP goes high. Generate a signal. As a result, the RS flip flop 51 is reset to inactivate the second control signal GATE.

<Operation example>
An operation example of the light emission control circuit according to the fourth embodiment of the present invention will be described with reference to FIGS. 14 to 16. FIG. 16 is a waveform diagram for explaining an operation example of the light emission control circuit shown in FIG.

  When the digital dimming signal DCS is activated to the high level, the first control signal DDRV is activated to the low level, the transistor QP1 is turned on, and the current ILD flows to the light emitting element 110. The switching control circuit 50b activates or deactivates the second control signal GATE to turn on or off the transistor QN1 in a period during which the first control signal DDRV is activated.

  When the second control signal GATE is activated to a high level in synchronization with the activation of the digital dimming signal DCS, the transistor QN1 is turned on, and the current IL flows in the inductor L1. The current IL flowing through the inductor L1 gradually increases with time. In the period shown in FIG. 16, since the current IL flowing through the inductor L1 is small, the comparison result signal COMP output from the comparator 75 is at the low level.

  As shown in FIG. 16, when the current ILD flowing through the light emitting element 110 is smaller than a predetermined value when the first control signal DDRV is activated, the output signal ICOMP of the comparator 79 becomes high level. And the up / down counter 81 is set to the up count mode.

  Thereafter, when the digital dimming signal DCS is inactivated to the low level, the first control signal DDRV is inactivated to the high level, the transistor QP1 is turned off, and the current ILD of the light emitting element 110 is stopped. Further, since the up / down counter 81 increments the count value in synchronization with the falling edge of the digital light adjustment signal DCS, the count value of the up / down counter 81 increases more than the previous value.

  The pulse width extension circuit 82 outputs, to the switching control circuit 50b, a selection signal SEL for selecting an output signal of a delay circuit having a delay time TD corresponding to the difference between the count value and the initial value. In switching control circuit 50b, selection circuit 59a selects an output signal of a delay circuit having an increased delay time TD. As a result, after the delay time TD elapses since the digital dimming signal DCS is inactivated, the output signal of the AND circuit 52 becomes high level, the output signal of the OR circuit 57 becomes high level, and the RS flip-flop 51 deactivates the second control signal GATE.

  Here, a period in which the output signal of the AND circuit 52 is at a high level corresponds to a period in which the activation of the second control signal GATE for analog dimming is prohibited. Therefore, if the delay time TD increases, the period during which the activation of the second control signal GATE for analog dimming is inhibited within the period in which the first control signal DDRV for digital dimming is inactivated. Is shortened.

  When the second control signal GATE is inactivated to a low level, the transistor QN1 is turned off, and the current IL flowing through the inductor L1 decreases. Each time the digital dimming signal DCS is activated and deactivated, the pulse width of the second control signal GATE gradually increases by repeating such an operation.

  Next, when the current ILD flowing through the light emitting element 110 when the digital dimming signal DCS is activated to the high level becomes larger than a predetermined value, the output signal ICOMP of the comparator 79 becomes the low level. And the up / down counter 81 is set to the down count mode.

  When the digital dimming signal DCS is inactivated to the low level, the first control signal DDRV is inactivated to the high level, the transistor QP1 is turned off, and the current ILD of the light emitting element 110 is stopped. Further, since the up / down counter 81 decrements the count value in synchronization with the fall of the digital light adjustment signal DCS, the count value is smaller than the previous value.

  The pulse width extension circuit 82 outputs, to the switching control circuit 50b, a selection signal SEL for selecting an output signal of a delay circuit having a delay time TD corresponding to the difference between the count value and the initial value. In switching control circuit 50b, selection circuit 59a selects an output signal of a delay circuit having a reduced delay time TD. Thus, the second control signal GATE is inactivated to the low level after the delay time TD has elapsed since the digital dimming signal DCS is inactivated.

  When the count value of the up / down counter 81 becomes equal to or less than the lower limit value, the pulse width extension circuit 82 outputs a selection signal SEL for selecting the output signal of the inverter 53 to the switching control circuit 50b. In the switching control circuit 50b, the selection circuit 59a selects the output signal of the inverter 53. Thereby, when the digital dimming signal DCS is deactivated, the second control signal GATE is deactivated to a low level.

  Here, a period in which the output signal of the AND circuit 52 is at a high level corresponds to a period in which the activation of the second control signal GATE for analog dimming is prohibited. Therefore, if the delay time TD is reduced, the period during which the activation of the second control signal GATE for analog dimming is inhibited within the period in which the first control signal DDRV for digital dimming is inactivated. Is extended. This period is extended up to equal to the inactivation period of the first control signal DDRV.

  When the second control signal GATE is inactivated to a low level, the transistor QN1 is turned off, and the current IL flowing through the inductor L1 decreases. Every time the digital dimming signal DCS is activated and deactivated, the pulse width of the second control signal GATE converges to an appropriate value by repeating the increase or decrease of the pulse width of the second control signal GATE. Do.

  As described above, according to the fourth embodiment, when the current flowing to the light emitting element 110 is smaller than a predetermined value when the first control signal for digital dimming DDRV is activated, the first method can be used. The period for inhibiting the activation of the second control signal GATE for analog light adjustment is shortened within the period in which the control signal DDRV is deactivated. Thus, even when the period during which current flows through the light emitting element 110 in digital dimming is short, energy is compensated for the inductor L1, and the current flowing through the light emitting element 110 is lower than the current instructed in analog dimming. Can be prevented.

  In addition, when the current flowing to the light emitting element 110 is larger than a predetermined value when the first control signal DDRV for digital light adjustment is activated, the first control signal DDRV is inactivated. The period for inhibiting the activation of the second control signal GATE for analog dimming is extended within the period. Thereby, when performing both analog light control and digital light control, it is possible to reduce the power loss by suppressing the energy stored in the inductor L1 from being released without being used for light emission Become.

<Modification of Fourth Embodiment>
Like the light emission control circuit 100 shown in FIG. 8, the light emission control circuit 100 shown in FIG. 14 samples a current detection voltage proportional to the current flowing through the light emitting element 110 when the first control signal DDRV is activated. And a current sense amplifier 77 for amplifying the current detection voltage held in the sample hold circuit 76 to generate an output signal. In that case, the output signal of the current sense amplifier 77 is supplied to the inverting input terminal of the comparator 79.

Fifth Embodiment
In the fifth embodiment of the present invention, the switching control circuit 50a in the third embodiment shown in FIG. 9 includes a variable delay circuit 59 shown in FIG. Thereby, the period for extending the pulse width of the second control signal GATE can be made variable. In the other points, the fifth embodiment may be the same as the third embodiment.

  The switching control circuit 50a deactivates the second control signal GATE in a period in which the first control signal DDRV is inactivated when the on-duty ratio of the first control signal DDRV is equal to or higher than a predetermined value. And the first control signal DDRV is switched from the activation state to the inactivation state when the on-duty ratio of the first control signal DDRV is less than the predetermined value. The second control signal GATE is maintained in the activated state.

  In that case, when the on-duty ratio of the first control signal DDRV is the first value, the switching control circuit 50a sets the predetermined period to the first period, and the on-duty of the first control signal DDRV. If the ratio is a second value smaller than the first value, the predetermined period may be set to a second period longer than the first period. As a result, when the period in which current flows to the light emitting element 110 in digital dimming is shorter, energy to be compensated for in the inductor L1 can be further increased.

  For example, five types of dimming modes are set according to the on-duty ratio of the first control signal DDRV, and information specifying the current dimming mode is supplied to the condition setting circuit 58. Condition setting circuit 58 sets the predetermined period to zero and the on-duty ratio of first control signal DDRV is 4% in the dimming mode in which the on-duty ratio of first control signal DDRV is 5% or more. In a certain dimming mode, a predetermined period is set to TA1 (TA1> 0).

  Further, the condition setting circuit 58 sets the predetermined period to TA2 (TA2> TA1) in the dimming mode in which the on-duty ratio of the first control signal DDRV is 3%, and turns on the first control signal DDRV. In the dimming mode in which the duty ratio is 2%, the predetermined period is set to TA3 (TA3> TA2), and in the dimming mode in which the on-duty ratio of the first control signal DDRV is 1%, the predetermined period is Set to TA4 (TA4> TA3).

  Furthermore, the light emission control circuit 100 shown in FIG. 8 may include the comparator 79 to the pulse width extending circuit 82 shown in FIG. In that case, the switching control circuit 50a may adjust the predetermined period in accordance with the current flowing through the light emitting element 110 in accordance with the selection signal SEL supplied from the pulse width extending circuit 82. Thereby, when the current flowing to the light emitting element 110 is smaller, the energy compensated to the inductor L1 can be further increased.

  For example, when the current flowing through the light emitting element 110 is smaller than a predetermined value when the first control signal DDRV is activated, the up / down counter 81 activates and deactivates the digital dimming signal DCS. Every time the count value is incremented, the difference between the count value and the initial value is gradually increased. The pulse width extension circuit 82 sequentially generates a selection signal SEL for selecting an output signal of a delay circuit having a delay time TD according to the difference between the count value and the initial value, and selects the selection signal SEL. Supply to

  In the variable delay circuit 59 (FIG. 15) provided in the switching control circuit 50a, the selection circuit 59a sequentially selects the output signal of the delay circuit having a gradually larger delay time TD according to the selection signal SEL. Thereby, the extension period of the pulse width of the second control signal GATE gradually increases.

  Alternatively, when the on-duty ratio of the first control signal DDRV is less than a predetermined value, the switching control circuit 50a determines that the current flowing to the light emitting element 110 is predetermined when the first control signal DDRV is activated. When the first control signal DDRV transitions from the activated state to the inactivated state, the period for maintaining the second control signal GATE in the activated state is extended by the first period. When the current flowing to the light emitting element 110 is larger than a predetermined value when the first control signal DDRV is activated, the first control signal DDRV transitions from the activated state to the inactivated state. The period for maintaining the second control signal GATE in the activated state may be shortened by the second period.

  In that case, it is desirable that the second period be longer than the first period. For example, when the on-duty ratio of the first control signal DDRV changes from a first value (for example, 1%) to a second value (for example, 2%) larger than the first value, the on-duty ratio When the second control signal GATE is generated according to the extension period set when the value of the first control signal is a first value, the current flowing to the light emitting element 110 becomes excessive. Therefore, when the extension period is set next, the excess current can be eliminated early by shortening the extension period by the second period, which is longer than the first period. For example, the second period may be twice the first period.

Sixth Embodiment
FIG. 17 is a circuit diagram showing a configuration example of a light source device provided with a light emission control circuit according to a sixth embodiment of the present invention. In the sixth embodiment, a switching control circuit 50c is used instead of the switching control circuit 50 shown in FIG. 1 or FIG. In addition, a detection circuit 90 is added to compare the potential difference between both ends of the light emitting element 110 with the reference voltage VREF. Otherwise, the sixth embodiment may be similar to the first or second embodiment.

  As shown in FIG. 17, the detection circuit 90 includes resistors R7 to R10, an operational amplifier 91, and a comparator 92, and may further include a DAC 93 and a switch circuit 94. The resistors R7 and R8 constitute a first voltage dividing circuit that divides the power supply potential VDD. The resistors R9 and R10 constitute a second voltage dividing circuit that divides the detection potential VLD at the connection point of the capacitor C4 and the inductor L1. The voltage dividing ratio of the first voltage dividing circuit may be equal to the voltage dividing ratio of the second voltage dividing circuit.

  Thereby, the first and second voltage dividing circuits divide the potential difference between both ends of the capacitor C4 at a predetermined voltage dividing ratio, and for example, the operational amplifier 91 operated by receiving the power supply potential of 5 V and 0 V is The obtained potential difference is amplified at a predetermined amplification factor. Since the transistor QP1 is periodically turned on according to the first control signal DDRV, the potential difference between both ends of the capacitor C4 is substantially equal to the potential difference between both ends of the light emitting element 110.

  The comparator 92 compares the output voltage of the operational amplifier 91 with the reference voltage VREF to generate an output signal VCOMP according to the comparison result. Thus, detection circuit 90 deactivates output signal VCOMP to a low level when the potential difference between both ends of light emitting element 110 is smaller than a predetermined value, and the potential difference between both ends of light emitting element 110 is a predetermined value. When it is larger than this value, the output signal VCOMP is activated to the high level.

  The detection circuit 90 may be supplied with a reference voltage VREF, which is used to detect whether the potential difference between both ends of the light emitting element 110 is smaller or larger than a predetermined value, from an external microcomputer or the like. Alternatively, the detection circuit 90 may receive information (data) DREF related to the reference voltage VREF from an external microcomputer or the like. The DAC 93 converts externally supplied data DREF into a reference voltage VREF.

  In that case, even if the voltage-current characteristics of the light emitting element 110 fluctuate due to temperature, the fluctuation due to temperature is compensated for by setting the reference voltage VREF according to the temperature from a microcomputer or the like having temperature information of the light source device. can do. Furthermore, a switch circuit 94 may be provided so that one of the externally supplied reference voltage VREF and the reference voltage VREF supplied from the DAC 93 can be selected. The output signal VCOMP of the detection circuit 90 is supplied to the switching control circuit 50c.

  The switching control circuit 50 c turns on or off the transistor QN 1 based on the clock signal CLK, the reset signal RST, the output signal VCOMP of the detection circuit 90, and the digital dimming signal DCS supplied from the level shifter 21. In order to activate or deactivate the second control signal GATE.

  FIG. 18 is a circuit diagram showing a configuration example of the switching control circuit shown in FIG. In this example, the switching control circuit 50c includes an RS flip flop 51, an AND circuit 52, and an inverter 53.

  The RS flip-flop 51 activates the output signal to a high level in synchronization with the clock signal CLK, and synchronizes the output signal with the reset signal RST generated based on the current flowing through the transistor QN1 and the current flowing through the light emitting element 110. Deactivate. The AND circuit 52 corresponds to a mask circuit that masks the output signal of the RS flip flop 51 according to the output signal VCOMP of the detection circuit 90.

  When stopping the circuit of the RS flip flop 51 or the feedback loop in order to mask the output signal of the RS flip flop 51, although it takes time to return the second control signal GATE, the output signal of the RS flip flop 51 is masked In this case, the time required for the recovery of the second control signal GATE can be shortened.

  The inverter 53 inverts the output signal VCOMP of the detection circuit 90 and supplies the inverted signal to the AND circuit 52. The AND circuit 52 outputs the output signal of the RS flip flop 51 as the second control signal GATE when the output signal VCOMP of the detection circuit 90 is inactivated to low level and the output signal of the inverter 53 is high level. When the output signal VCOMP of the detection circuit 90 is activated to a high level and the output signal of the inverter 53 is at a low level, the second control signal GATE is maintained in the activated state.

<Operation example>
An operation example of the light emission control circuit according to the sixth embodiment of the present invention will be described with reference to FIGS. 17 to 19. FIG. 19 is a waveform diagram for describing an operation example of the light emission control circuit shown in FIG. FIG. 19 shows the case where the on-duty ratio of the digital dimming signal (the on-duty ratio of the first control signal DDRV) is less than a predetermined value.

  When the digital dimming signal DCS is activated to the high level, the first control signal DDRV is activated to the low level, the transistor QP1 is turned on, and the current ILD flows to the light emitting element 110. As a result, when the detection potential VLD rises above the threshold and the potential difference between both ends of the light emitting element 110 becomes smaller than a predetermined value, the output signal VCOMP of the detection circuit 90 is inactivated to a low level.

  When the output signal VCOMP of the detection circuit 90 is inactivated to a low level, the AND circuit 52 outputs the output signal of the RS flip flop 51 as a second control signal GATE. Thus, the switching control circuit 50c activates the second control signal GATE for at least a part of the period to turn on the transistor QN1 when the potential difference between both ends of the light emitting element 110 is smaller than a predetermined value. Turn

  When the second control signal GATE is activated to a high level, the transistor QN1 is turned on, and the current IL flows to the inductor L1. The current IL flowing through the inductor L1 gradually increases with time. During the period shown in FIG. 19, since the current IL flowing through the inductor L1 is small, the reset signal RST output from the comparator 75 is at the low level.

  Thereafter, when the digital dimming signal DCS is inactivated to the low level, the first control signal DDRV is inactivated to the high level, the transistor QP1 is turned off, and the current ILD of the light emitting element 110 is stopped. As a result, the current is not supplied from the light emitting element 110 to the inductor L1, so the detection potential VLD gradually falls. When the detection potential VLD falls below the threshold and the potential difference between both ends of the light emitting element 110 becomes larger than a predetermined value, the output signal VCOMP of the detection circuit 90 is activated to the high level.

  When the output signal VCOMP of the detection circuit 90 is activated to the high level, the AND circuit 52 deactivates the output signal to the low level. Thereby, switching control circuit 50 c maintains second control signal GATE in the inactive state to turn off transistor QN 1 when the potential difference between both ends of light emitting element 110 is larger than the predetermined value. .

  When the second control signal GATE is inactivated to a low level, the transistor QN1 is turned off, the current IL flowing through the inductor L1 decreases, and the fall of the detection potential VLD is stopped. Thus, the switching control circuit 50c regulates the activation and deactivation of the second control signal GATE so that the potential difference between both ends of the light emitting element 110 approaches a predetermined value.

  Although not shown in FIG. 19, when the on-duty ratio of the digital dimming signal DCS is equal to or more than a predetermined value, the reset signal RST is activated before the output signal VCOMP of the detection circuit 90 is activated. May be In that case, the switching control circuit 50c deactivates the second control signal GATE in synchronization with the activation of the reset signal RST. Furthermore, the switching control circuit 50c may repeat activation and inactivation of the second control signal GATE in synchronization with the clock signal CLK and the reset signal RST.

  According to the sixth embodiment, when the potential difference between both ends of the light emitting element 110 is larger than a predetermined value, the transistor is kept in the inactive state by maintaining the second control signal GATE for analog light adjustment. QN1 is maintained in the off state. Thereby, when performing both analog light control and digital light control, even if the first control signal DDRV for digital light control is deactivated and the transistor QP1 is turned off, it is stored in the inductor L1. It is possible to reduce power loss by suppressing the release of energy without being used for light emission.

  When the potential difference between both ends of the light emitting element 110 is smaller than a predetermined value, the transistor QN1 is turned on by activating the second control signal GATE for analog dimming for at least a part of the period. Become. Thus, even when the period during which current flows through the light emitting element 110 in digital dimming is short, energy is compensated for the inductor L1, and the current flowing through the light emitting element 110 is lower than the current instructed in analog dimming. Can be prevented.

Seventh Embodiment
FIG. 20 is a circuit diagram showing a configuration example of a switching control circuit according to a seventh embodiment of the present invention. In the seventh embodiment, a switching control circuit 50d shown in FIG. 20 is used instead of the switching control circuit 50c in the sixth embodiment shown in FIG. In the other points, the seventh embodiment may be similar to the sixth embodiment.

  The light emission control circuit 100 receives information on the on-duty ratio of the digital dimming signal DCS, that is, information on the on-duty ratio of the first control signal DDRV from an external microcomputer or the like. Thereby, the switching control circuit 50d can set the condition for activation or deactivation of the second control signal GATE based on the information on the on-duty ratio of the first control signal DDRV.

  In the example shown in FIG. 20, the switching control circuit 50d includes an RS flip flop 51, an AND circuit 52, an inverter 53, and an OR circuit 57. In addition, the mode is high when the on-duty ratio of the first control signal DDRV is equal to or greater than a predetermined value, and is low when the on-duty ratio of the first control signal DDRV is less than the predetermined value. The signal MOD is supplied to the switching control circuit 50d.

  For example, two types of dimming modes are set according to the on-duty ratio of the first control signal DDRV. In the first dimming mode, the on-duty ratio of the first control signal DDRV is 5% to 100%, and in the second dimming mode, the on-duty ratio of the first control signal DDRV is 0. Greater than% and less than 5%. In that case, the mode signal MOD goes high in the first dimming mode and goes low in the second dimming mode.

  The RS flip-flop 51 is set in synchronization with the rising of the clock signal CLK when the reset signal RST is at low level, and activates the output signal to high level, and when the clock signal CLK is at low level, The signal is reset in synchronization with the rise of the reset signal RST to inactivate the output signal to a low level.

  The inverter 53 inverts the mode signal MOD to generate an output signal. The OR circuit 57 generates an output signal by obtaining the logical sum of the digital dimming signal DCS and the output signal of the inverter 53. The AND circuit 52 generates an output signal by obtaining the logical product of the output signal of the RS flip flop 51 and the output signal of the OR circuit 57.

  When the on-duty ratio of the first control signal DDRV is equal to or higher than a predetermined value, the mode signal MOD becomes high level, the output signal of the inverter 53 becomes low level, and the OR circuit 57 generates a digital dimming signal. The DCS is supplied to one input terminal of the AND circuit 52. When the digital dimming signal DCS is activated to the high level, the AND circuit 52 outputs the output signal of the RS flip flop 51 as the second control signal GATE, and the digital dimming signal DCS is inactivated to the low level. When this is done, the output signal is deactivated to low level.

  Thereby, the switching control circuit 50d turns on or off the transistor QN1 in a period in which the first control signal DDRV is activated when the on-duty ratio of the first control signal DDRV is equal to or greater than a predetermined value. In addition to activating or deactivating the second control signal GATE to attain the state, the second control signal GATE is maintained in the inactivated state while the first control signal DDRV is inactivated. .

  On the other hand, when the on-duty ratio of the first control signal DDRV is less than the predetermined value, the mode signal MOD goes low, the output signal of the inverter 53 goes high, and the OR circuit 57 goes high. Signal is supplied to one input terminal of the AND circuit 52. The AND circuit 52 outputs the output signal of the RS flip flop 51 as a second control signal GATE.

  Thereby, the switching control circuit 50d activates or deactivates the second control signal GATE asynchronously with the first control signal DDRV when the on-duty ratio of the first control signal DDRV is less than the predetermined value. Turn The transistor QN1 is turned on when the second control signal GATE is activated, and turned off when the second control signal GATE is deactivated.

  According to the seventh embodiment, when the on-duty ratio of the first control signal DDRV for digital dimming is equal to or more than a predetermined value, the analog is generated during the period in which the first control signal DDRV is inactivated. By maintaining the second dimming control signal GATE in the inactive state, the transistor QN1 is maintained in the OFF state. Thereby, when performing both analog light control and digital light control, it is possible to reduce the power loss by suppressing the energy stored in the inductor L1 from being released without being used for light emission Become.

  In addition, when the on-duty ratio of the first control signal DDRV for digital dimming is less than a predetermined value, the second control signal GATE for analog dimming is activated asynchronously with the first control signal DDRV. Alternatively, the transistor QN1 is turned on or off asynchronously with the first control signal DDRV by inactivation. Thus, even when the period during which current flows through the light emitting element 110 in digital dimming is short, energy is compensated for the inductor L1, and the current flowing through the light emitting element 110 is lower than the current instructed in analog dimming. Can be prevented.

Eighth Embodiment
In the light source device described above, it is also possible to use an N-channel MOS transistor as a first switching element instead of the P-channel MOS transistor QP1. In the following, as an example, the case where an N-channel MOS transistor is used as the first switching element in the light source device shown in FIG. 1 will be described.

  FIG. 21 is a circuit diagram showing a configuration example of a light source device provided with a light emission control circuit according to an eighth embodiment of the present invention. As shown in FIG. 21, in this light source device, an N channel MOS transistor QN5 is used as a first switching element, and diodes D2 and D3, a Zener diode D4, a resistor R11, and capacitors C6 and C7 are added. It is done.

  The transistor QN5 has a drain connected to the light emitting element 110, a source connected to one end of the inductor L1, and a gate to which the first control signal DDRV is applied. Drive circuit 30a activates first control signal DDRV to a high level to turn on transistor QN5 according to digital dimming signal DCS, and turns on first control signal DDRV to turn transistor QN5 off. Deactivate to low level.

  23 and 24 are diagrams for explaining the operation of the light source device of FIG. As shown in FIG. 23, the first control signal DDRV and the second control signal GATE transition between a low level (for example, 0 V) and a high level (for example, 7.5 V). When the first control signal DDRV is activated to a high level, a current flows from the drive circuit 30a to the gate of the transistor QN5 via the capacitor C6, the voltage between the gate and the source of the transistor QN5 rises, and the transistor QN5 It will be on. The Zener diode D4 clamps the gate-source voltage of the transistor QN5 not to exceed a predetermined voltage (for example, 7.5 V).

  As shown in FIG. 21, a resistor R11 is provided between the gate and the source of the transistor QN5. The reason why the resistor R11 is provided will be described later. As shown in FIG. 23, when the first control signal DDRV transitions from low level to high level, the gate-source voltage of the transistor QN5 rises. In digital dimming, when the duty of the first control signal DDRV is large, the period in which the first control signal DDRV is at the high level becomes long. At this time, the gate-source voltage of the transistor QN5 gradually decreases due to the resistor R11. The third control signal GATE 'is used to maintain the gate-source voltage of the transistor QN5. That is, as shown in FIG. 23, while the first control signal DDRV is maintained in the activated state, the third control signal GATE 'transitions between the low level and the high level. As a result, the capacitor C7 and the diodes D2 and D3 perform a rectifying operation, and the gate-source voltage of the transistor QN5 is maintained above the threshold voltage. That is, the capacitor C7 is provided between the output terminal of the third control signal GATE 'and the anode terminal of the diode D3. When the third control signal GATE 'is at a low level, the anode terminal of the diode D3 is substantially at the source voltage of the transistor QN5 by the diode D2. When the third control signal GATE 'transitions from low level to high level, the voltage at the anode terminal of the diode D3 rises. As a result, the voltage at the gate of the transistor QN5 connected to the cathode terminal of the diode D3 is increased. Thus, while the first control signal DDRV is at a high level, the gate-source voltage of the transistor QN5 can be maintained by the third control signal GATE '.

  When the first control signal DDRV is inactivated to a low level, current flows from the source of the transistor QN5 to the drive circuit 30a through the diodes D2 and D3 and the capacitor C6, and the gate-source voltage of the transistor QN5 is As it descends, the transistor QN5 is turned off. The resistor R11 reduces the voltage between the gate and the source of the transistor QN5 to maintain the transistor QN5 in the OFF state, when the light emitting device stops light emission for a long time at the time of standby or the like.

  As shown in FIG. 23, when the first control signal DDRV transitions from high level to low level, if the third control signal GATE 'is high level, the third control signal GATE' is low level. Transition to The third control signal GATE 'is at a low level while the first control signal DDRV is at a low level. If the third control signal GATE 'is high when the first control signal DDRV is low, the capacitor C7 and the diode D3 may turn on the transistor QN5. Therefore, when the first control signal DDRV transitions from the high level to the low level, the third control signal GATE 'transitions to the low level.

  As shown in FIG. 24, in the digital light adjustment, when the duty of the first control signal DDRV is small, the period in which the first control signal DDRV is at the high level is shortened. At this time, assuming that the transistor QN1 is turned off at the timing when the transistor QN5 is turned off, the transistor QN1 is turned on only during the high level period of the first control signal DDRV. Since energy is stored in the inductor L1 when the transistor QN1 is on, energy is less likely to be stored in the inductor L1 if the on period of the transistor QN1 is short. That is, when the duty of the first control signal DDRV is small, the brightness of the light emission of the light emitting element 110 may be insufficient compared to the brightness expected in digital light control.

  Therefore, as shown in FIG. 24, the second control signal GATE transitions from high level to low level after a predetermined period elapses after the first control signal DDRV transitions from high level to low level. . As a result, the on period of the transistor QN1 is extended, so that the light emitting element 110 can emit light with appropriate brightness in digital dimming even when the duty of the first control signal DDRV is small. As described above, when the first control signal DDRV transitions from the high level to the low level, the third control signal GATE 'transitions to the low level. That is, the third control signal GATE 'is a signal different from the second control signal GATE.

  As shown in FIG. 21, the light emission control circuit 100 includes an output circuit 61 that outputs a third control signal GATE '. For example, the output circuit 61 is an AND circuit. The AND circuit obtains the logical product of the first control signal DDRV and the second control signal GATE, and outputs the result as a third control signal GATE '. The output circuit 61 may be included in the switching control circuit 50. Further, the output circuit 61 may output a third control signal GATE 'based on the first control signal DDRV and the output signal of the switching control circuit 50. The output signal of the switching control circuit 50 is a signal that the switching control circuit 50 outputs to the drive circuit 60. Further, the output circuit 61 generates a third control signal GATE ′ based on the digital dimming signal DCS and the second control signal GATE, or based on the digital dimming signal DCS and the output signal of the switching control circuit 50. May be output.

  When the second control signal GATE may be maintained in the inactivated state during the inactivation period of the first control signal DDRV, the second control signal GATE is used as the third control signal GATE ′. Can also be used.

  In the sixth embodiment shown in FIG. 17, since the second control signal GATE can be activated and deactivated even in the inactivation period of the first control signal DDRV, the second control signal GATE A different third control signal GATE 'is used. For example, the third control signal GATE ′ is generated by providing the switching control circuit 50 with an AND circuit for obtaining the logical product of the digital dimming signal DCS or the first control signal DDRV and the second control signal GATE. .

  According to the above embodiment, while the light emission control circuit 100 suppresses the release of the energy stored in the inductor L1 without being used for light emission, the period during which current flows to the light emitting element 110 in digital dimming is By preventing the decrease in the current flowing to the light emitting element 110 even in the short case, it is possible to provide a light source device which can accurately control the brightness with a small power loss. Further, the light emission control circuit 100 receives a first control signal DDRV and a second control signal GATE adjusted according to the on-duty ratio of the first control signal DDRV from an external microcomputer or the like. The light emission control may be performed.

<Projection type image display device>
Next, a projection type video display (video projector) according to an embodiment of the present invention will be described. FIG. 22 is a block diagram showing a configuration example of a projection type video display according to an embodiment of the present invention. The projection type video display apparatus 200 is supplied with power supply voltage from the outside and also supplied with image data from an image data supply apparatus such as a personal computer or a video player, and an image is displayed on a screen (projection surface) 300 based on the image data. Is a display device that projects

  As shown in FIG. 22, the projection display apparatus 200 includes a power supply circuit 210, an image data processing unit 220, a control unit 230, a light source device 240, a panel 250, and a projection optical system 260. . The light source device 240 includes a light emission control circuit 100 and a light emitting element 110.

  The power supply circuit 210 generates a logic power supply voltage based on a power supply voltage of AC 100 V supplied from the outside, for example, and supplies it to the image data processing unit 220, the control unit 230, etc. Then, the light emission control circuit 100 of the light source device 240 is supplied. The light emission control circuit 100 generates, for example, an internal power supply voltage of approximately DC30V to 40V based on a power supply voltage of approximately DC50V.

  The image data processing unit 220 and the control unit 230 are configured by, for example, one or more microcomputers. The image data processing unit 220 processes image data supplied from the outside to generate an image signal and a synchronization signal for display, and supplies the image signal and the synchronization signal to the panel 250 to drive the panel 250. Draw.

  The control unit 230 controls each unit of the projection display 200 according to an operation performed by the operator using a remote control or an operation panel (not shown). When the operator instructs light adjustment, the control unit 230 generates the digital light adjustment signal DCS and the analog light adjustment signal ACS for performing the light adjustment instructed by the operator, and the light emission of the light source device 240 The control circuit 100 is supplied.

  The light source device 240 emits light with brightness according to the digital light adjustment signal DCS and the analog light adjustment signal ACS supplied from the control unit 230, and irradiates the panel 250 with light. For example, when the light emitting element 110 includes a plurality of laser diodes that generate blue light, the light source device 240 receives a blue light generated by a part of the laser diodes and generates a yellow light; The light emitting device may further include a light separating unit that separates red light and green light from light. In that case, the light source device 240 can generate light of three colors of R (red), G (green), and B (blue).

  The panel 250 modulates the light emitted from the light source device 240 according to the image signal and the synchronization signal supplied from the image data processing unit 220. For example, the panel 250 may include three liquid crystal panels corresponding to three colors of RGB. Each liquid crystal panel forms an image by changing the transmittance of light in a plurality of pixels arranged in a matrix. Modulated light modulated by the panel 250 is guided to the projection optical system 260.

  The projection optical system 260 includes at least one lens. For example, the projection lens, which is a lens group for projecting and forming modulated light modulated by the panel 250 on the screen 300, changes the state of the stop of the projection lens, the state of zoom, or the shift position. Various mechanisms are provided in the projection optical system 260. The mechanisms are controlled by the controller 230. The projection optical system 260 projects the modulated light onto the screen 300 to display an image on the screen 300. According to the present embodiment, using the light source device 240 capable of accurately controlling the brightness with less power loss, the brightness of the projected image can be accurately controlled while reducing the power consumption of the projection type video display device. be able to.

  The present invention is not limited to the embodiments described above, and many modifications can be made within the technical concept of the present invention by those skilled in the art. For example, it is also possible to combine and implement a plurality of embodiments selected from the embodiments described above.

  DESCRIPTION OF SYMBOLS 10 ... Internal regulator, 21, 22, 31 ... Level shifter, 30, 30a, 60 ... Drive circuit, 32 ... Driver amplifier, 40, 40a ... Clock signal generation circuit, 41, 42 ... Constant current source, 43 ... Comparator, DESCRIPTION OF SYMBOLS 44 ... Buffer circuit, 45 ... Inverter, 50, 50a, 50b, 50c, 50d ... Switching control circuit, 51 ... RS flip flop, 52 ... AND circuit, 53 ... Inverter, 54 ... Delay circuit, 55, 56 ... Switch circuit, 57 OR circuit 58 condition setting circuit 59 variable delay circuit 59a selection circuit 61 output circuit 71 slope compensation circuit 72, 77 current sense amplifier 73 operational amplifier 74 switch circuit 75, 79 ... comparator, 76 ... sample hold circuit, 78 ... selection circuit, 78a, 8b: switch circuit, 80: inverter, 81: up-down counter, 82: pulse width extension circuit, 90: detection circuit, 91: operational amplifier, 92: comparator, 93: DAC, 94: switch circuit, 100: light emission control circuit 110: light emitting element, 200: projection type image display device, 210: power supply circuit, 220: image data processing unit, 230: control unit, 240: light source device, 250: panel, 260: projection optical system, 300: screen, QP1 to QP2 P-channel MOS transistors, QN1 to QN5 N-channel MOS transistors D1 to D3 diodes D4 zener diodes L1 inductors C1 to C7 capacitors R1 to R11 resistors

Claims (12)

A first switching element controlling a current flowing to a light emitting element connected between a first node and one end of the inductor; and a second switching element controlling a current flowing from the other end of the inductor to the second node A light emission control circuit that controls the device and
A driving circuit that activates or deactivates a first control signal to turn on or off the first switching element;
A switching control circuit that turns on or off the second switching element by activating or deactivating a second control signal during a period in which the first control signal is activated;
Equipped with
The switching control circuit is
When the on-duty ratio of the first control signal is equal to or more than a predetermined value, the second control signal is maintained in the inactive state during the period when the first control signal is inactivated ,
When the on-duty ratio of the first control signal is less than the predetermined value, the second control signal is activated in a part of a period in which the first control signal is inactivated. Light emission control circuit to maintain. The switching control circuit is
When the on-duty ratio of the first control signal is less than the predetermined value, the second control is performed in a predetermined period after the first control signal transitions from the activated state to the inactivated state. The light emission control circuit according to claim 1, wherein the signal is maintained in an activated state. The switching control circuit is
The on-duty ratio of the first control signal is less than the predetermined value, and the second control signal is never inactivated during a period in which the first control signal is activated. The light emission control circuit according to claim 2, wherein the second control signal is maintained in an activated state during the predetermined period. The switching control circuit is
When the on-duty ratio of the first control signal is a first value, the predetermined period is set to a first period, and the on-duty ratio of the first control signal is higher than the first value. The light emission control circuit according to claim 2 or 3, wherein the predetermined period is set to a second period longer than the first period in the case of a small second value. The switching control circuit is
The light emission control circuit according to claim 2, wherein the predetermined period is adjusted in accordance with a current flowing through the light emitting element. The switching control circuit is
When the on-duty ratio of the first control signal is less than the predetermined value, the current flowing through the light emitting element is smaller than the predetermined value when the first control signal is activated. A period during which the second control signal is maintained in the activated state after the transition of the first control signal from the activated state to the inactivated state is extended by the first period, and the first control is performed. When the current flowing through the light emitting element when the signal is activated is larger than the predetermined value, the second control signal transitions from the activated state to the inactivated state. The light emission control circuit according to claim 1, wherein a period for maintaining the control signal in the activated state is shortened by a second period.   The light emission control circuit according to claim 6, wherein the second period is longer than the first period.   The light emission control circuit according to any one of claims 1 to 7, wherein information on the on-duty ratio of the first control signal is externally received. A first switching element controlling a current flowing to a light emitting element connected between a first node and one end of the inductor; and a second switching element controlling a current flowing from the other end of the inductor to the second node A light emission control circuit that controls the device and
A driving circuit that activates or deactivates a first control signal to turn on or off the first switching element;
In a period in which the first control signal is activated, the second control signal is activated or deactivated to turn on or off the second switching element, and the first control signal is activated. Activation of the second control signal during a period in which the first control signal is inactivated when the current flowing to the light emitting element is smaller than a predetermined value when the second control signal is activated Period is inhibited, and the first control signal is inactivated when the current flowing through the light emitting element is larger than the predetermined value when the first control signal is activated. A switching control circuit which extends a period during which the activation of the second control signal is inhibited within the period
A light emission control circuit comprising:   The light emission according to any one of claims 5 to 9, further comprising a sample and hold circuit for sampling and holding a voltage proportional to the current flowing to the light emitting element when the first control signal is activated. Control circuit. The light emission control circuit according to any one of claims 1 to 10.
The light emitting element, the inductor, and the first and second switching elements;
A capacitor connected between one end of the inductor and the first node;
A diode connected between the other end of the inductor and the first node;
When the first and second switching elements are in the on state, current flows through the light emitting element and the inductor, energy is stored in the inductor, and the first switching element is in the on state. When the second switching element is in the off state, the energy stored in the inductor causes a current to flow to the light emitting element and the diode, and the first switching element is in the off state and the second switching element is on. A light source device in which, when in a state, current flows through the capacitor and the inductor to store energy in the inductor.   A projection type video display provided with the light source device according to claim 11.

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