JP2019068275A - Integrated circuit for oscillation - Google Patents

Abstract

To provide an integrated circuit for oscillation in which frequency band is widened by shortening the oscillation start time, and lowering current consumption during steady oscillation.SOLUTION: An integrated circuit for oscillation includes a CMOS inverter consisting of series connection of MOS transistors PM1, NM1, an oscillation part 1 having a feedback resistor 11, and load capacities 12, 13, and used by connecting a crystal resonator 2 thereto, a bootstrap circuit 30 for detecting the amplitude of an oscillation signal A outputted from the oscillation part 1, and a MOS transistor PM20 having a voltage source Vref and a current source 40 as power supply means of the oscillation part 1, and controlling the supply voltage of the oscillation part 1 by a start signal B of the bootstrap circuit 30. When the bootstrap circuit 30 is not detecting the fact that the amplitude of the oscillation signal A has reached a prescribed level or more after oscillation start, the PM20 is turned ON and a voltage satisfying the oscillation conditions is supplied to the oscillation part 1, and when the fact that the amplitude of the oscillation signal A has reached a prescribed level or more is detected, the PM20 is turned OFF and a minimum current required for sustaining oscillation is supplied to the oscillation part 1 from the current source 40.SELECTED DRAWING: Figure 1

Description

        The present invention relates to an integrated circuit for oscillation provided with an oscillation circuit.

        The oscillation circuit is required to have a short oscillation startup time from oscillation startup to a steady oscillation state and stable oscillation operation. In order to ensure oscillation with a crystal oscillator, it is necessary to set the negative resistance to 3 to 10 times the equivalent series resistance CI value of the crystal at the start of oscillation, but when oscillation is stable, the negative resistance is the equivalent series resistance of the crystal. The oscillation can be continued if it is at least one time the CI value. There are known techniques for reducing power consumption by increasing the negative resistance at the start of oscillation and reducing the negative resistance after the start of oscillation (Patent Documents 1, 2 and 3).

JP, 2014-155184, A Unexamined-Japanese-Patent No. 4-94201 Japanese Patent Application Laid-Open No. 56-023005

        The oscillation integrated circuit disclosed in Patent Document 1 includes a CMOS inverter formed by series connection of first and second MOS transistors, a feedback resistor connected in parallel to the CMOS inverter, and an input terminal and an output terminal of the CMOS inverter. And an oscillation unit used by connecting a piezoelectric vibrator, an oscillation detection circuit detecting a change in amplitude of an oscillation signal output from the oscillation unit, and detection of the oscillation detection circuit The adjustment circuit is provided with an adjustment means for adjusting a current supplied to the CMOS inverter by a signal, and the oscillation detection circuit does not detect that the amplitude of the oscillation signal has reached a predetermined magnitude or more after oscillation is started. When a current satisfying the oscillation condition is supplied to the 1 MOS transistor and it is detected that the amplitude of the oscillation signal has reached a predetermined magnitude or more And supplies a current smaller than the current.

        In the integrated circuit for oscillation of Patent Document 1, the adjustment means is configured by a bias circuit controlled by the output of the oscillation detection circuit to generate a gate voltage of the first MOS transistor, and the bias circuit is generated after oscillation is started. When the oscillation detection circuit does not detect that the amplitude of the oscillation signal has reached a predetermined magnitude or more, driving is started while biasing the gate of the first MOS transistor with a power supply via a resistor. After the oscillation detection circuit detects that the amplitude of the oscillation signal has reached a predetermined magnitude or more, the first MOS transistor is driven with a smaller current than when it is biased and driven by the power supply. It controls to drive.

        The configuration of the integrated circuit for oscillation of Patent Document 1 will be described in detail based on FIG. 8 of the accompanying drawings. The oscillation integrated circuit is a series connection of a P-type MOS transistor (hereinafter referred to as a PMOS transistor) PM1 as a first MOS transistor and an N-type MOS transistor (hereinafter referred to as an NMOS transistor) NM1 as a second MOS transistor. And an oscillation detection circuit 3 for detecting a change in the amplitude of an oscillation signal output from the oscillation section 1, and an oscillation detection circuit 3. A bias circuit 4 controlled by the output of the circuit 3 to generate a gate voltage of the PMOS transistor PM1, an output circuit 5, and a filter circuit 6 which is a narrow signal removal circuit are provided.

        The oscillating unit 1 includes a CMOS inverter, a feedback resistor 11 connected in parallel to the CMOS inverter, a load capacitance 12 connected to the input terminal of the CMOS inverter, and a load capacitance 13 connected to the output terminal of the CMOS inverter . The output terminal of the bias circuit 4 is connected to the gate of the PMOS transistor PM1 via the resistor 7, and the capacitor 8 is connected between the gates of the PMOS transistor PM1 and the NMOS transistor NM1. In the CMOS inverter, the source of the PMOS transistor PM1 is connected to the high potential (constant potential Vref), and the source of the NMOS transistor NM1 is connected to the low potential power supply (ground potential Vss).

        As shown in FIG. 9 of the accompanying drawings, the bias circuit 4 has two PMOS transistors PM2 and PM3, the source of the PMOS transistor PM2 is connected to the constant potential Vref, and the drain is connected to the source of the PMOS transistor PM3. Also, the detection signal B output from the oscillation detection circuit 3 is input to the gate. The drain and the gate of the PMOS transistor PM3 are commonly connected to the ground potential Vss via the resistor 41. The gate of the PMOS transistor PM3 is further connected to a low pass filter configured of a resistor 42 and a capacitor 43, and the output of the low pass filter becomes an input of the oscillating unit 1 through the resistor 7 (see FIG. 8). However, the low pass filter (the resistor 42 and the capacitor 43) is not essential.

        The output circuit 5 includes an amplifier circuit, a frequency divider circuit, an output drive circuit, and the like, and generates the signal C to be output to the outside based on the oscillation signal from the oscillation unit 1. The output signal output state and the oscillation signal not reaching the steady oscillation state have the signal output stop state in which the output is stopped. The filter circuit 6 has a time constant for charging and discharging, and the output voltage level is set depending on whether the detection signal B of the oscillation detection circuit 3 is at the H level or the L level. When the detection signal B is at H level, the signal output stop instruction level is obtained. When the detection signal B is at L level, the signal output instruction level is obtained. The output voltage level does not change if the change of the detection signal B of the oscillation detection circuit 3 is within a predetermined time determined by the time constant. Thus, the output circuit 5 is controlled to the signal output state or the signal output stop state by the output voltage level of the filter circuit 6 according to the change of the detection signal B of the oscillation detection circuit 3.

        Subsequently, the operation of the embodiment of Patent Document 1 will be described. As shown in FIG. 10 of the accompanying drawings, when the power is turned on, the amplitude of the output signal A of the oscillation unit 1 is small, and when the oscillation detection circuit 3 is in the oscillation undetected state, the detection signal B is H level. The PMOS transistor PM2 of the circuit 4 is in the off state. Therefore, the gate voltage of the PMOS transistor PM1 becomes the ground potential Vss, and the PMOS transistor PM1 is turned on, the current I Vref flows, and the current supplied to the oscillating unit 1 increases. As a result, when the amplitude of the output signal A increases and the steady oscillation state where the amplitude is greater than or equal to a predetermined value is detected, the detection signal B of the oscillation detection circuit 3 that detects this becomes L level.

        When the detection signal B of the oscillation detection circuit 3 becomes L level, the PMOS transistor PM2 of the bias circuit 4 is turned on, the gate voltage of the PMOS transistor PM1 rises and becomes Vss + α, and the current flowing through the PMOS transistor PM1 decreases from IVref Supply current to the oscillating unit 1 decreases. Thus, when the oscillating unit 1 reaches the steady oscillation state, the current consumption is reduced, and the oscillation state is maintained, and the output signal A is output from the output circuit 5 as the output signal C. The changes in the gate voltage and current of the PMOS transistor PM1 shown in FIG. 10 do not accurately indicate the actual amounts of change, but show a general tendency.

        When the amplitude of the output signal A becomes smaller and becomes smaller than a predetermined value as the current supplied to the oscillation unit 1 decreases, the detection signal B of the oscillation detection circuit 3 that detects this becomes H level. When the detection signal B becomes H level, the PMOS transistor PM2 of the bias circuit 4 is turned off, the gate voltage of the PMOS transistor PM1 becomes Vss, the current I Vref flows, and the current supplied to the oscillator 1 increases. To go. Then, when the amplitude of the output signal A becomes large and a steady oscillation state of a predetermined level or more is achieved, the detection signal B of the oscillation detection circuit 3 that detects this becomes L level again.

        In the low power consumption type crystal oscillation circuit of Patent Document 2, a crystal oscillation circuit in which a feedback circuit having a crystal oscillator is connected in parallel to a CMOS transistor amplifier circuit, and an oscillation signal output from the crystal oscillation circuit are input to obtain a predetermined level or more. A level detection circuit for outputting a pulse signal, a reference voltage generation circuit for inputting the pulse signal and outputting a reference voltage lower than a power supply voltage, and amplification of a value lower than the power supply voltage by inputting the reference voltage The reference voltage is increased when the pulse signal is not output from the level detection circuit, and the reference voltage is decreased when the pulse signal is output from the level detection circuit. Do. As a result, the voltage of the amplification circuit changes with the level of the oscillation signal output from the crystal oscillation circuit. After the start of oscillation, when the level detection circuit does not detect that the level of the oscillation signal has reached a predetermined level or more, a voltage satisfying the oscillation condition is supplied to the crystal oscillation circuit, and the level of the oscillation signal is When it is detected that the size has reached a predetermined size or more, a low voltage is supplied to reduce power consumption.

        The low power consumption crystal oscillation circuit device of Patent Document 3 uses a complementary MOS inverter as an amplifier, and applies a voltage to a voltage supply unit of a crystal oscillation circuit in which a feedback circuit having a crystal oscillator is connected in parallel with the complementary MOS inverter. The adjustment means is connected, the output of the crystal oscillation circuit is connected to the gate circuit through the divider circuit and the switching element, and the gate circuit is further connected to the applied voltage adjustment means. The applied voltage adjusting means measures the number of outputs of the oscillation signal and outputs a count signal when the number reaches a predetermined number. It has a MOS switch circuit operated by the output of the signal generation circuit. After starting the oscillation, the diode circuit is short-circuited by the MOS switch circuit until a predetermined time determined by the oscillation signal frequency and the number of oscillation signal measurement, thereby supplying a voltage satisfying the oscillation condition to the crystal oscillation circuit. By opening the diode circuit in the MOS switch circuit, a low voltage is supplied by a voltage drop due to the diode to reduce power consumption.

        The integrated circuit for oscillation of Patent Document 1 drives an oscillation circuit with a constant current (IVref) at oscillation startup. For this reason, as the frequency is lower, the negative resistance becomes larger, and the oscillation abnormality at the start of oscillation becomes more likely to occur. Therefore, it is difficult to cope with a wide frequency, mainly corresponding to 32 KHz for a clock, and 32 KHz × 128 = 4 MHz and 32 KHz × 512 = 16 MHz, which are multiples of the frequency that divides the oscillation frequency and outputs 32 KHz.

        Since the low power consumption type crystal oscillation circuit of Patent Document 2 drives the oscillation circuit with the oscillation start time constant voltage, the fluctuation of negative resistance is reduced compared with the circuit of Patent Document 1, and it is easy to cope with a wide frequency. Become. However, since a constant voltage during steady-state oscillation is manufactured with a switched capacitor circuit, the voltage increases as the frequency decreases, and as a result, the current consumption increases. Therefore, the circuit of Patent Document 2 also has difficulty in dealing with wide frequencies, and 32 KHz for clocks and multiples of 32 KHz × 128 = 4 MHz, 32 KHz × 512 = 16 MHz for dividing the oscillation frequency and outputting 32 KHz It corresponds to

        The low power consumption crystal oscillation circuit device circuit of Patent Document 3 is driven by a constant voltage source both at the time of oscillation start and at the time of steady oscillation. For this reason, a large fluctuation of negative resistance does not occur. However, since the voltage drop due to the forward voltage (VF) of the diode is used as the reference voltage of the constant voltage source during steady state oscillation, the settable voltage is determined by the forward voltage (VF) of the diode. As a result, the adjustable voltage is limited and an optimum value design can not be made.

        SUMMARY OF THE INVENTION It is a first object of the present invention to provide an integrated circuit for oscillation provided with an oscillation circuit capable of dealing with a wide frequency while shortening the oscillation start time and reducing the power consumption during steady oscillation. . The second object of the present invention is to stabilize the output to be output to the outside even in the oscillation unstable state at the time of oscillation start, and further, even when the oscillation amplitude is temporarily decreased due to external noise etc. at the steady oscillation. The third purpose is to stabilize the output to be

        In order to achieve the first object of the present invention, an oscillation integrated circuit according to claim 1 of the present invention comprises an inverter, a feedback resistor connected in parallel to the inverter, and a load capacitance connected to each of an input terminal and an output terminal of the inverter. An oscillation unit that connects the piezoelectric vibrator and outputs an oscillation signal, a start circuit that outputs an oscillation start signal after oscillation start of the oscillation unit, a voltage source and a current source as power supply means of the oscillation unit When the oscillation start signal of the start circuit is not output, the voltage source is turned on to supply a voltage satisfying the oscillation condition to the oscillation unit, and when the oscillation start signal of the start circuit is output, the voltage source Is turned off to supply the minimum current necessary for continuing the oscillation from the current source to the oscillation unit.

        In order to achieve the first object, the oscillation integrated circuit according to claim 2 of the present invention detects the amplitude of the oscillation signal output from the oscillation unit and starts oscillation when the amplitude reaches a predetermined magnitude or more. A signal is provided, and when the amplitude of the oscillation signal does not reach a predetermined magnitude or more, the oscillation start signal is stopped.

        Similarly, in order to achieve the first object, the oscillation integrated circuit according to the present invention measures the number of clocks of the oscillation signal output from the oscillation unit and outputs the oscillation activation signal when a predetermined number is reached. It features.

        Similarly, in order to achieve the first object, the oscillation integrated circuit according to the present invention outputs the oscillation start signal after a predetermined time after the start condition of the start circuit is satisfied such as power application or oscillation start input signal. It features.

        In order to achieve the second object, an integrated circuit for oscillation according to claim 3 of the present invention includes an output circuit that generates a signal to be output to the outside based on an oscillation signal from the oscillation unit, and the output circuit An output state and an output stop state of a signal to be output to the outside are controlled by an oscillation start signal of the start circuit.

        In order to achieve the third object, in the integrated circuit for oscillation of the present invention, the start circuit includes a circuit for detecting the amplitude of the oscillation signal output from the oscillation unit and a charge / discharge circuit, whereby the amplitude is greater than a predetermined level. When the amplitude of the oscillation signal does not reach a predetermined magnitude or more, it is discharged at a predetermined time constant to stop the oscillation activation signal.

        According to the integrated circuit for oscillation of claim 1 of the present invention, the oscillation startup time is shortened and the consumption current in steady oscillation is reduced by changing the drive method of the oscillation unit between oscillation start and steady oscillation. And can handle a wide range of frequencies. The corresponding frequency of the general integrated circuit for oscillation at constant voltage startup can be from 30 KHz to 4 MHz, or from 4 MHz to 60 MHz. After the start of oscillation, this can be changed to constant current drive as it is. However, when the constant current value is adjusted to the high frequency, the current value at the low frequency becomes the same as at the constant voltage driving time. Therefore, in order to achieve low power consumption, which is the purpose of this patent, it is better to narrow the frequency range to about half.

        At the time of oscillation startup, since the voltage is driven, abnormal oscillation due to excessive negative resistance at low frequency is eliminated. During steady-state oscillation, because the constant current drive is performed with the minimum current, even if the negative resistance at low frequencies is large, it is not sufficiently smaller than the negative resistance at the start of oscillation, which causes no problem.

        Since the value of the constant current is determined by the W value of the transistor used for the current source, fine adjustment is possible and an optimum design can be performed.

        The constant current supplied by the current source is the minimum current necessary for continuing the oscillation smaller than the current flowing in the voltage drive at the time of oscillation start, so that even if the constant current flows, the voltage is driven at the time of oscillation start. Thus, the current source always flows the current of the same value, and thus does not need a bias circuit for changing the current value. The change circuit required to change to the steady oscillation state is only the circuit that stops the output of the constant voltage source, and no complex circuit is required here. Furthermore, if the constant voltage source is turned off to increase the resistance, the power consumed by the constant voltage source can be reduced, resulting in lower power consumption.

        In the integrated circuit for oscillation according to claim 2 of the present invention, the start circuit detects a change in the amplitude of the oscillation signal output from the oscillation unit even when large disturbance noise enters during steady oscillation and oscillation stops. The oscillation start signal is stopped by the fact that the amplitude has not reached a predetermined magnitude or more. As a result, the negative resistance is increased and it is possible to restart in a short time.

        According to the oscillation integrated circuit of claim 2 of the present invention, the output circuit that generates the signal to be output to the outside based on the oscillation signal has a small oscillation signal amplitude at the time of oscillation start-up and an unstable oscillation when the frequency is unstable. Is in the signal output stop state. As a result, the circuit driven by the output circuit is also stopped and the malfunction can be prevented.

        In the integrated circuit for oscillation according to claim 1 of the present invention, the start-up circuit includes a circuit that detects the amplitude of the oscillation signal output from the oscillation unit and a charge / discharge circuit, whereby disturbance noise is introduced during steady-state oscillation. Even when the oscillation amplitude temporarily decreases, the oscillation start signal is output up to a predetermined time constant. Therefore, since the output circuit does not have a signal output stop state, a stable output can be obtained without causing an intermittent signal output stop state of the output circuit.

FIG. 1 is a block diagram showing an entire configuration in a first embodiment of the present invention. Explanatory drawing which shows the relationship between the output signal A from an oscillation part, the internal charging / discharging capacity | capacitance of a starting circuit, the starting signal B, and the output signal C of an output circuit. FIG. 5 is a block diagram showing an entire configuration in a second embodiment of the present invention. FIG. 8 is a block diagram showing the entire configuration in a third embodiment of the present invention. The block diagram which shows the whole structure in the 4th Embodiment of this invention. The block diagram which shows the whole structure in the 5th Embodiment of this invention. The block diagram which shows the whole structure in the 6th Embodiment of this invention. FIG. 2 is a block diagram showing an entire configuration in an embodiment of Patent Document 1. FIG. 5 is a configuration diagram of a bias circuit of Patent Document 1. Explanatory drawing which shows the relationship between the detection signal of the oscillation detection circuit of patent document 1, and the gate voltage and electric current of a 1st MOS transistor.

        The purpose of providing an integrated circuit for oscillation provided with an oscillation circuit capable of shortening the oscillation start-up time and reducing current consumption during steady-state oscillation and capable of coping with a wide frequency by supplying the oscillation unit by the start-up circuit. The power supply is realized by switching between the oscillation start voltage source and the steady oscillation current source.

        An embodiment of the first configuration of the integrated circuit for oscillation of the present invention will be described based on FIG. 1 of the accompanying drawings. The oscillation integrated circuit is a series connection of a P-type MOS transistor (hereinafter referred to as a PMOS transistor) PM1 as a first MOS transistor and an N-type MOS transistor (hereinafter referred to as an NMOS transistor) NM1 as a second MOS transistor. And a start circuit 30 for detecting the amplitude of the output signal A output from the oscillation unit 1; and the oscillation unit 1; A third PMOS transistor PM20 having a voltage source Vref and a current source 40 as power supply means and controlling a voltage supplied to the oscillation unit 1 by a start signal B of the start circuit 30 and an output circuit 5 are provided.

        The oscillating unit 1 includes a CMOS inverter, a feedback resistor 11 connected in parallel to the CMOS inverter, a load capacitance 12 connected to the input terminal of the CMOS inverter, and a load capacitance 13 connected to the output terminal of the CMOS inverter . In the CMOS inverter, the source of the PMOS transistor PM1 is connected to the high potential (the drain of the current source 40 and PM20), and the source of the NMOS transistor NM1 is connected to the low potential power supply (ground potential Vss). The CMOS inverter has an advantage that it is easy to obtain a gain as an amplifier of the oscillation unit 1 and has a small size, and is widely used for an oscillation circuit, but there is no problem with other types of inverters.

        The start-up circuit 30 includes an NMOS inverter including an NMOS transistor NM30 and a pull-up resistor 32, a pull-down resistor 31 connected to the input terminal of the NMOS inverter, a DC cut capacitor 33, and a charge / discharge capacitor connected to the output terminal of the NMOS inverter. 34 and an inverter 35. The high potential power supply of the start-up circuit is connected to the power supply potential Vdd of the integrated circuit for oscillation.

        As shown in the attached drawing 2, the start circuit 30 changes the level of the start signal B according to the amplitude of the output signal A from the oscillator 1. When the amplitude of the output signal A is lower than the threshold voltage (Vth) of NM30, the start signal B is L level, and when the amplitude of the output signal A is higher than the threshold voltage (Vth) of NM30, the start signal B is set to H level . That is, the state of the start signal B when the oscillation start signal is output becomes H level.

        The ON resistance of NM30 of the NMOS inverter is small, and the pull-up resistor 32 is designed to be large. As shown in the attached drawing 2, when the amplitude of the output signal A from the oscillation unit 1 becomes equal to or higher than the threshold voltage (Vth) of NM30, the charge / discharge capacity 34 is discharged in a short time and the start signal B is at H level. The charge / discharge capacity 34 is charged for a long time by the pull-up resistor 32 when the output signal A of the output signal A becomes equal to or lower than the threshold voltage (Vth) of the NM 30, and sets the start signal B to L level.

        The current source 40 is made of a current mirror circuit that copies the reference current source, and the current value (I) of the current source 40 is the current value (IR) of the reference current source and the transistor W size (WR) of the reference current source. And the transistor W size (W) of the current source 40. These become relational expressions of I = IR × W ÷ WR. The reference current source does not need to be newly created because it uses the reference current source used for the constant voltage source (Vref).

        The output circuit 5 includes an amplifier circuit, a frequency divider circuit, an output drive circuit, and the like, and generates an output signal C to be output to the outside based on the output signal A from the oscillation unit 1. When the signal B is at L level, the oscillation signal that does not reach the steady oscillation state stops outputting the signal, and when the activation signal B of the start circuit 30 is at H level, the signal output state that outputs the oscillation signal in steady oscillation state Have a function.

        Subsequently, the operation of this embodiment will be described. When the power supply is turned on, the amplitude of the output signal A from the oscillation unit 1 is small, and when the oscillation is not detected in the start circuit 30, the start signal B is L level and the PMOS transistor PM20 is in the on state. Therefore, the voltage source Vref is supplied to the oscillation unit 1 together with the current source 40. At this time, since the current of the current source 40 is the minimum current necessary to continue oscillation smaller than the current flowing at the time of driving the voltage source Vref, voltage driving is performed even if a constant current flows. A concrete example of 54 MHz crystal oscillation is described. The current at the voltage source Vref = 1 V at the time of oscillation startup is 500 μA, and the constant current value at the time of steady oscillation is 50 μA. The current source 40 always passes the current of the same value, and thus does not need a bias circuit that changes the current value. Furthermore, when the start signal B is at L level, the output signal C is in the signal output stop state. When the amplitude of the output signal A of the oscillator 1 becomes large and the amplitude becomes greater than a predetermined value, the start signal B of the start circuit 30 which detects this becomes H level.

        When the start signal B of the start circuit 30 becomes H level, the PM 20 is turned off and the supply of the voltage source Vref to the oscillation unit 1 is stopped. As a result, the oscillation unit 1 is in a steady oscillation state of constant current drive in which the minimum current necessary for continuing the oscillation by the current source 40 is supplied. Furthermore, the output signal A from the oscillation unit 1 is output from the output circuit 5 as the output signal C, and a stable signal output state is achieved.

        Even when disturbance noise is introduced, the start circuit 30 is charged when the amplitude of the output signal A from the oscillation unit 1 reaches a predetermined magnitude or more and outputs an oscillation start signal, and the output signal A from the oscillation unit 1 is When the amplitude does not reach a predetermined magnitude or more, it has a charge / discharge circuit which discharges at a predetermined time constant and stops the oscillation start signal. Therefore, even if disturbance noise enters and the amplitude of the output signal A decreases as shown by the dotted frame in FIG. 2 of the attached drawings, the start signal B does not immediately become L level. As a result, the output circuit 5 is a stable signal. The output state can be maintained.

        FIG. 3 of the accompanying drawings shows a second embodiment of the present invention, in which a current source 40 is connected to the source of the NMOS transistor MN1 of the CMOS inverter, and the CMOS inverter is a source of the PMOS transistor PM1. Is connected to the high potential power supply (power supply potential Vdd), and the source of the NMOS transistor NM1 is connected to the low potential (current source 40 and NM20 drain). About the other structure, the same code | symbol is attached | subjected to the component corresponding to 1st Embodiment, and detailed description is abbreviate | omitted.

        Subsequently, the operation of this embodiment will be described. The H level and L level operations of the start signal B of the start circuit 30 are reverse to those of the first embodiment, and in Example 2, when the amplitude of the output signal A becomes equal to or higher than the set level, the start signal B is L level, When the output signal A falls below the set level, the start signal B is set to H level. Along with this, the operating condition of the start signal B of the output circuit is also changed. When the power is turned on and the amplitude of the output signal A from the oscillation unit 1 is small and the output signal A in the start circuit 30 is below the set level, the start signal B is H level and the NMOS transistor NM20 is in the on state. Therefore, the voltage source Vref is supplied to the oscillation unit 1 together with the current source 40. At this time, since the current of the current source 40 is the minimum current value necessary to continue oscillation smaller than the current flowing at the time of driving the voltage source Vref, voltage driving is performed even if a constant current flows. Therefore, the oscillation unit 1 is voltage driven without using a circuit that changes the bias of the current source. Furthermore, when the start signal B is at H level, the output signal C is in the signal output stop state. When the amplitude of the output signal A of the oscillation unit 1 increases and this amplitude becomes greater than a predetermined value, the start signal B of the start circuit 30 that detects this becomes L level.

        When the start signal B of the start circuit 30 becomes L level, the NM 20 is turned off and the supply of the voltage source Vref to the oscillation unit 1 is stopped. As a result, the oscillation unit 1 is in a steady oscillation state of constant current drive in which the minimum current necessary for continuing the oscillation by the current source 40 is supplied. Furthermore, the output signal A from the oscillation unit 1 is output from the output circuit 5 as the output signal C, and a stable signal output state is achieved.

        FIG. 4 of the accompanying drawings shows a third embodiment of the present invention, in which the configuration of the CMOS inverter of the oscillation unit 1 of the first embodiment is changed. The CMOS inverter includes a series connection of a first PMOS transistor PM1 and a second NMOS transistor NM1. The CMOS inverter further includes a bias resistor 7 for generating a gate voltage of the PMOS transistor PM1, and AC gates PM1 and NM1. A feedback capacitor 8 is provided to couple the voltage. Since the configuration other than the inverter is not changed, the same reference numerals are given to the components corresponding to the first embodiment, and the detailed description will be omitted.

        FIG. 5 of the accompanying drawings shows a fourth embodiment of the present invention, in which the CMOS inverter of the oscillation unit 1 of the first embodiment is changed to an NMOS inverter. The NMOS inverter NM2 includes a series connection of a first NMOS transistor NM1 and a second NMOS transistor NM2, and the source and gate of the NMOS inverter NM2 are connected to a high potential. Since the configuration other than the inverter is not changed, the same reference numerals are given to the components corresponding to the first embodiment, and the detailed description will be omitted.

        FIG. 6 of the accompanying drawings shows a fifth embodiment of the present invention, in which the CMOS inverter of the oscillation unit 1 of the first embodiment is replaced with an NPN inverter. An NPN inverter comprising a series connection of a first NPN transistor NPN1 and a load resistor 9 is provided. Since the configuration other than the inverter is not changed, the same reference numerals are given to the components corresponding to the first embodiment, and the detailed description will be omitted.

        FIG. 7 of the accompanying drawings shows a sixth embodiment of the present invention, in which the CMOS inverter of the oscillation unit 1 of the second embodiment is changed to a PMOS inverter. A PMOS inverter is formed by series connection of a first PMOS transistor PM1 and a load resistor 9. The load resistor 9 may be changed to the PMOS transistor PM2 as in the fourth embodiment. Since the configuration other than the inverter is not changed, the same reference numerals are given to the components corresponding to those of the second embodiment, and the detailed description will be omitted.

        As another start-up circuit, a counting circuit and a flip-flop circuit which measure the number of clocks of the output signal A of the oscillating unit 1 similar to the control signal generation circuit of Patent Document 3 and output an oscillation start signal when a predetermined number is reached. There is a starting circuit configured with a starting circuit configured, and a constant current charge timer circuit that outputs an oscillation starting signal after a predetermined time after the oscillation start conditions such as power supply application and an oscillation start input signal are satisfied. The measurement time is divided into about three types depending on the corresponding crystal. For example, 3 msec, 8 msec, 13 msec, etc. are suitable for this measurement time.

The circuit configuration shown in the embodiment as an inverter is a part of it. There are various circuit configurations other than the embodiment.

DESCRIPTION OF SYMBOLS 1 oscillator part 2 crystal oscillator 5 output circuit 7 bias resistance 8 feedback capacity 9 load resistance 11 feedback resistance 12 and 13 load capacity 30 starting circuit 31 pull-down resistance 32 pull-up resistance 33 DC cut capacity 34 charge / discharge capacity 35 inverter 40 current source PM1, PM20 PMOS transistor NM1, NM2 NMOS transistor NM20, NM30 NMOS transistor NPN1 NPN transistor

Claims (3)

An oscillating unit having an inverter, a feedback resistor connected in parallel to the inverter, and a load capacitance connected to each of the input terminal and the output terminal of the inverter, and connected to the piezoelectric vibrator to output an oscillation signal;
A start circuit for outputting an oscillation start signal after oscillation start of the oscillation unit;
It has a voltage source and a current source as power supply means of the oscillation unit,
When the oscillation start signal of the start circuit is not output, the voltage source is turned on to supply a voltage satisfying the oscillation condition to the oscillation unit, and when the oscillation start signal of the start circuit is output, the voltage source is turned off. An oscillation integrated circuit that supplies the minimum current necessary for continuing oscillation to the oscillation unit from the current source;       The start-up circuit detects the amplitude of the oscillation signal output from the oscillation unit and outputs an oscillation start-up signal when the amplitude reaches a predetermined magnitude or more, and the amplitude of the oscillation signal reaches a predetermined magnitude or more 2. The integrated circuit for oscillation according to claim 1, wherein the oscillation start signal is stopped when not. The output circuit includes an output circuit that generates a signal to be output to the outside based on an oscillation signal from the oscillation unit, and the output circuit is an output state and an output stop state of a signal to be output to the outside according to the oscillation activation signal of the activation circuit. The integrated circuit for oscillation according to claim 1, wherein is controlled.