JP2019068118A - Semiconductor integrated circuit and digital-analog conversion circuit, and driving method of semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit which operates at high speed and has a low risk of malfunction. The present invention is a semiconductor integrated circuit including a current switch circuit. In the current switch circuit, a predetermined voltage is applied to the gate to turn it on, and the first transistor whose drain is connected to the current output terminal and the switch control signal are input to the gate to pass the current flowing from the source of the first transistor to the ground. It includes a second transistor that turns ON / OFF, and a third transistor that turns ON / OFF the connection between the gate and the source of the first transistor by inputting a switch control signal to the gate. The first transistor may be an input / output N-channel MOS field effect transistor. The second transistor can be a core N-channel MOS field effect transistor. The third transistor can be a core P-channel MOS field effect transistor. [Selection diagram] Fig. 1

Description

  The present invention relates to a semiconductor integrated circuit, a digital-analog converter circuit, and a method of driving a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit including a MOS field effect transistor, a digital-analog converter circuit, and a method of driving a semiconductor integrated circuit.

  In recent years, with the progress of high integration due to the miniaturization of semiconductor integrated circuits by deep submicron technology, an increase in leakage current due to the miniaturization of MOS field effect transistors constituting the semiconductor integrated circuit is becoming a problem. The leakage current can be reduced, for example, by increasing the gate insulating film thickness and the gate length of the MOS field effect transistor. However, the operating speed of the MOS field effect transistor decreases as the thickness of the gate insulating film and the length of the gate increase. Therefore, in a semiconductor integrated circuit for applications that require high processing speed, it is a problem how to reduce the leak current while realizing high processing speed.

  In a semiconductor integrated circuit, as an example of a technique aiming to reduce a leak current while realizing high-speed processing speed, a main circuit configured of a MOS field effect transistor and an enable signal in a standby state are turned off. A transistor circuit including a leak current interrupting MOS field effect transistor for interrupting a leak current path of the main circuit, wherein the leak current interrupting MOS field effect transistor has a channel length longer than that of the MOS field effect transistor constituting the main circuit. Are known (see, for example, Patent Document 1).

  Further, as another example of the technology, there are a logic circuit configured of MOS field effect transistors, and a MOS field effect transistor for blocking leakage current which shuts off a leakage current path of the logic circuit by turning off an enable signal during standby. As a MOS field effect transistor for leakage current blocking, there is known a semiconductor integrated circuit whose leakage current is smaller than that of a MOS field effect transistor which constitutes a logic circuit (see, for example, Patent Document 2).

  According to these techniques, the enable signal is turned on only when operating the logic circuit to make the MOS field effect transistor for leakage current cut-off, and the enable signal is turned off when the logic circuit is on standby to cut off the leakage current. By making the MOS field effect transistor non-conductive, it is possible to reduce unnecessary power consumption due to leakage current when the logic circuit is on standby.

JP, 2002-164775, A JP 2008-085348 A

  As described above, as the MOS field effect transistor is miniaturized to operate at high speed, the leak current inevitably increases. That is, it can be said that the leakage current of the MOS field effect transistor is in a trade-off relationship with respect to the speeding up of the operation speed. Therefore, if the gate insulating film of the MOS field effect transistor is thinned and the gate length is shortened in order to realize a logic circuit operating at high speed, the leakage current increases accordingly, and as a result, the ON / OFF current ratio of the logic circuit It decreases and it becomes easy to produce a malfunction. In the above-mentioned prior art, since the reduction of the leak current is regarded as the standby time of the logic circuit, the leak current reduces the ON / OFF current ratio to cause a malfunction while the logic circuit is operating as described above. The problem of becoming easy will arise.

  The present invention has been made in view of such a situation, and an object thereof is to provide a semiconductor integrated circuit which operates at high speed and is less likely to malfunction.

  More specifically, one object of the present invention is to increase the ON / OFF current ratio of the current switch circuit by reducing the leak current at the time of OFF of the current switch circuit in the semiconductor integrated circuit. It is to avoid the deterioration of the operating characteristics due to the leak current at the time of OFF.

  Another object of the present invention is to provide a digital-analog conversion circuit which operates at high speed and is less likely to malfunction.

  Another object of the present invention is to provide a method of driving a semiconductor integrated circuit which operates at high speed and is less likely to malfunction.

  The present invention for solving the above-mentioned problems includes the invention-specifying matters or technical features shown below.

  That is, the present invention according to one aspect is a semiconductor integrated circuit provided with a current switch circuit. In the current switch circuit, a predetermined voltage is applied to the gate to be turned on, and a first transistor whose drain is connected to the current output terminal, a switch control signal is input to the gate, and the current flows from the source of the first transistor to ground. It includes a second transistor that turns on / off current, and a third transistor that receives the switch control signal at its gate and turns on / off the connection between the gate and the source of the first transistor. The first transistor may be an input / output N channel MOS field effect transistor. The second transistor may be a core N-channel MOS field effect transistor. The third transistor may be the core P-channel MOS field effect transistor.

  The current switch circuit can be operated by the switch control signal while the predetermined voltage is applied to the gate of the first transistor and the first transistor is turned on. In the operating current switch circuit, while the switch control signal is at the high level, the second transistor is turned on, whereby an output current flows through the first transistor and the second transistor. In addition, while the switch control signal is at the low level, in the current switch circuit in operation, the output current is cut off by turning off the second transistor. Furthermore, while the switch control signal is at low level, the third transistor is turned on to connect and short-circuit the gate and source of the first transistor, thereby turning off the first transistor.

  And since the first transistor is an input / output MOS field effect transistor, the leakage current is smaller than that of the second transistor. Furthermore, since the leak current required of the second transistor flows from the gate of the first transistor through the third transistor, the leak current of the second transistor is an output current flowing from the drain of the first transistor to the ground. It has no effect at all.

  Because of this, while the switch control signal is at the low level, the magnitude of the leakage current of the current switch circuit depends on the leakage current of the first transistor and is less than or equal to the leakage current of the first transistor. Therefore, the ON / OFF current ratio of the current switch circuit can be increased by thickening the gate insulating film of the first transistor, so that there is a possibility that a malfunction may occur due to the reduction of the ON / OFF current ratio due to the leak current. It can be reduced.

  In addition, since the third transistor can make the gate insulating film thinner than the first transistor, high-speed switch operation is possible. Therefore, the time from when the switch control signal goes low to when the first transistor is turned off and the leak current of the current switch circuit becomes less than or equal to the leak current of the first transistor can be extremely shortened.

  Furthermore, as described above, since the first transistor is an input / output MOS field effect transistor, the leakage current is smaller than that of the second transistor. Therefore, while the switch control signal is at the low level, the magnitude of the leakage current of the current switch circuit depends on the magnitude of the leakage current of the first transistor. In addition, since the gate insulating film of the second transistor can be made thin enough to allow high-speed operation, high-speed switch operation is possible. The operating speed of the current switch circuit depends on the operating speed of the second transistor. Thus, the current switch circuit can operate at high speed according to the switch control signal.

  Thus, it is possible to provide a semiconductor integrated circuit which operates at high speed and is less likely to malfunction.

  The semiconductor integrated circuit may include a constant current control circuit that performs constant current control on an output current of the current switch circuit.

  Thus, while the switch control signal is at the high level, that is, while the second transistor is on, the output current of the current switch circuit can be controlled to a predetermined magnitude.

  The constant current control circuit may include a current mirror output side transistor forming a current mirror circuit that controls an output current of the current switch circuit based on a reference current.

  Thereby, while the switch control signal is at the high level, the output current of the current switch circuit can be constant current controlled based on the reference current.

  In the current switch circuit, the predetermined voltage is applied to the gate to be turned on, a fourth transistor whose drain is connected to the current output terminal, and a logic inversion signal of the switch control signal is input to the gate; A fifth transistor that turns on / off the current flowing from the source to the ground of the transistor; and a sixth transistor that receives a logic inversion signal of the switch control signal at its gate and turns on / off the connection between the gate and the source of the fourth transistor The source of the second transistor may be connected to the source of the fifth transistor. The fourth transistor may be an input / output N channel MOS field effect transistor. The fifth transistor may be the core N-channel MOS field effect transistor. The sixth transistor may be the P-channel MOS field effect transistor for core.

  As a result, it is possible to provide a semiconductor integrated circuit which is provided with a current switch circuit constituted by a differential amplifier circuit, operates at high speed, and is less likely to malfunction.

  The semiconductor integrated circuit corresponds to each bit of a digital signal of n (n is an integer of 1 or more) bits, and n based on the n current switch circuits connected in parallel and a digital control signal. And a switch control unit that outputs the switch control signal corresponding to each of the current switch circuits, wherein the constant current control circuit is configured to output current of each of the n current switch circuits. The output current of each of the n current switch circuits may be controlled so that the current corresponds to the corresponding bit of the n-bit digital signal.

  Accordingly, it is possible to realize a current output type digital-analog conversion chip which operates at high speed and is less likely to malfunction.

  Furthermore, the present invention according to another aspect relates to the semiconductor integrated circuit, a control circuit that generates the digital control signal based on the n-bit digital signal, and a total output current of the n current switch circuits. And an analog signal output circuit for outputting an analog signal.

  Thus, it is possible to realize a digital-analog conversion circuit that operates at high speed and is less likely to malfunction.

  The control circuit includes a delay circuit that delays the rising or falling timing of the digital control signal with respect to the rising or falling timing of the n-bit digital signal, and the rising or falling timing of the digital control signal is the second It can correspond to the timing at which the transistor switches from ON to OFF.

  The current switch circuit described above slightly increases the delay in the rising timing of the output current. The increase in the delay in the rise timing of the output current itself is extremely small to hardly cause any problem in operating the current switch circuit at high speed. However, the ON / OFF duty ratio of the output current of the current switch circuit causes an error due to the delay of the rising timing of the output current.

  According to the delay circuit, the fall timing of the output current of the current switch circuit can be delayed by delaying the rise or fall timing of the digital control signal with respect to the rise or fall timing of the digital signal. This makes it possible to offset an increase in the delay in the rising timing of the output current of the current switch circuit, thereby reducing the ON / OFF duty ratio error caused by the delay in the rising timing of the output current of the current switch circuit. be able to.

  Thereby, in the current output type digital-analog conversion circuit, it is possible to reduce the error of the ON / OFF duty ratio caused due to the delay of the rising timing of the output current of the current switch circuit.

  Furthermore, according to another aspect of the present invention, a predetermined voltage is applied to the gate of the first transistor whose drain is connected to the current output terminal to turn on the first transistor, and from the source of the first transistor to the ground. The switch control signal is input to the gate of the second transistor which turns ON / OFF the flowing current, and the switch control signal is input to the gate of the third transistor which turns ON / OFF the connection between the gate and the source of the first transistor. And a method of driving a semiconductor integrated circuit. The first transistor may be an input / output N channel MOS field effect transistor. The second transistor may be the core N-channel MOS field effect transistor. The third transistor may be the core P-channel MOS field effect transistor.

  According to the present invention, it is possible to provide a method of driving a semiconductor integrated circuit which operates at high speed and is less likely to malfunction.

  According to the present invention, it is possible to provide a semiconductor integrated circuit which operates at high speed and is less likely to malfunction.

  More specifically, according to the present invention, in the semiconductor integrated circuit, the ON / OFF current ratio of the current switch circuit is increased by reducing the leak current when the current switch circuit is OFF, and the current switch circuit is turned OFF. It is possible to avoid the deterioration of the operating characteristics due to the leak current at the time of

  Further, according to the present invention, it is possible to provide a digital-analog conversion circuit which operates at high speed and is less likely to malfunction.

  Further, according to the present invention, it is possible to provide a method of driving a semiconductor integrated circuit which operates at high speed and is less likely to malfunction.

  Other technical features, objects, effects, and advantages of the present invention will be made clear by the following embodiments described with reference to the attached drawings.

FIG. 1 is a circuit diagram illustrating a configuration of a digital-analog conversion circuit according to the present invention. It is a circuit diagram of the 1st example of a current switch circuit, and is a circuit diagram illustrating the state where a current switch circuit is ON. It is a circuit diagram of 1st Example of a current switch circuit, and is a circuit diagram illustrating the state where the current switch circuit is OFF. FIG. 7 is a circuit diagram of a second embodiment of the current switch circuit. FIG. 7 is a circuit diagram of a third embodiment of the current switch circuit. It is a circuit diagram of a 4th example of a current switch circuit. FIG. 2 is a circuit diagram illustrating an example of a circuit configuration of a control circuit. It is the graph which illustrated the output signal waveform of the current switch circuit. It is the graph which illustrated the voltage waveform of the digital control signal which a control circuit outputs. It is the graph which illustrated the output signal waveform of the current switch circuit.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the embodiments described below are merely examples, and there is no intention to exclude the application of various modifications and techniques not explicitly stated below. The present invention can be implemented with various modifications (for example, combining the respective embodiments) without departing from the scope of the present invention. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. The drawings are schematic and do not necessarily match the actual dimensions, ratios, etc. There may be parts where the dimensional relationships and proportions differ among the drawings.

  The configuration of the digital-analog conversion circuit according to the present invention will be described with reference to FIG.

  FIG. 1 is a circuit diagram illustrating the configuration of a digital-analog conversion circuit according to the present invention. As shown in the figure, a digital-analog conversion circuit 1 according to the present invention includes, for example, a semiconductor integrated circuit 10, a current mirror bias circuit 20, a control circuit 30, and an analog signal output circuit 40.

The semiconductor integrated circuit 10 corresponds to, for example, n current switch circuits 11 ₁ , 11 ₂ ,... 11 _n connected in parallel corresponding to respective bits of n (n is an integer of 1 or more) bits of a digital signal. , A switch control unit 12 that outputs switch control signals SC _{1 to} SC _n corresponding to each of the _n current switch circuits 11 ₁ , 11 ₂ ,... 11 _n based on the digital control signal, and a current output terminal 13 ,including. The semiconductor integrated circuit 10 is manufactured by, for example, a 40 nm process and is a semiconductor integrated circuit with a power supply voltage Vdd of 1.1 V, but is not particularly limited thereto, and is manufactured by, for example, a 90 nm or less process. It may be a semiconductor integrated circuit. The semiconductor integrated circuit 10 may be any semiconductor integrated circuit as long as it is typically a semiconductor integrated circuit including a current switch circuit.

Current switch circuit 11 ₁ includes, for example, the first transistor QA _1, the second transistor QB ₁ and the third transistor QC _1. Similarly, current switch circuit 11 _2, the first transistor QA _2, includes a second transistor QB ₂ and the third transistor QC _2, current switch circuit 11 _n includes a first transistor QA _n, second transistor QB _n and the Three transistors QC _n are included. Moreover, current switch circuit ₁₁ 1, ₁₁ 2, ... 11 _n, the current switching circuit ₁₁ 1, ₁₁ 2 may include a constant current control circuit for constant current control of the output current _I 1 ~I _n of ... 11 _n.

Current switch circuit 11 _1, as an example of the constant current control circuit may include a current mirror output transistors QD _1. Current mirror output transistors QD ₁ constitute a current mirror circuit for controlling on the basis of the output current I ₁ of the current switch circuits 11 ₁ to a current (reference current) of the constant current source 21. Moreover, current switch circuit 11 ₂ may include a current mirror output transistors QD _2. Current mirror output transistors QD ₂ constitute a current mirror circuit for controlling on the basis of the output current I ₂ of the current switch circuits 11 ₂ to the current (reference current) of the constant current source 21. Similarly, the current switch circuit 11 _n can include a current mirror output side transistor QD _n . Current mirror output transistors QD _n constitute a current mirror circuit for controlling on the basis of the output current I _n of the current switch circuits 11 _n to the current (reference current) of the constant current source 21. The configuration of the constant current control circuit is not particularly limited to the current mirror output side transistors QD ₁ , QD ₂ ,..., QD _n , and may be configured by a circuit using resistors having different resistance values, for example current switch circuits ₁₁ 1, ₁₁ 2, the output current _I 1 ~I _n of ... 11 _n as long as the circuit capable of constant current control may be a circuit of any structure.

In the current switching circuit 11 _1, a first drain of the transistor QA ₁ is connected to the current output terminal 13. The first source of the transistor QA ₁ is connected to the drain of the current mirror output transistors QD _1. The source of the current mirror output transistors QD ₁ is connected to the second drain of the transistor QB _1. The second source of the transistor QB ₁ is connected to ground. The source of the third transistor QC ₁ is connected to the first gate of the transistor QA _1, the third drain of the transistor QC ₁ is connected to the first source of the transistor QA _1. Second transistors QB ₁ and the third gate of the transistor QC ₁ is connected to the switch control unit 12.

In the current switching circuit 11 _1, the first transistor QA _1, for example, operate to ON when the power supply voltage Vdd is applied to the gate. The second transistor QB ₁ is, for example, when the switch control signal SC ₁ is input to the gate operates to turn ON / OFF the current flowing to ground via the QD ₁ from a first source of the transistor QA _1. The third transistor QC _1, for example, when the switch control signal SC ₁ is input to the gate, the first transistor QA ₁ gate - operates to OFF / ON the connection between the source.

In current switch circuit 11 _2, the drain of the first transistor QA ₂ is connected to the current output terminal 13. The source of the first transistor QA ₂ is connected to the drain of the current mirror output transistors QD _2. The source of the current mirror output transistors QD ₂ is connected to the second drain of the transistor QB _2. The source of the second transistor QB ₂ is connected to ground. The drain of the third transistor QC ₂ is connected to the gate of the first transistor QA _2, the source of the third transistor QC ₂ is connected to the first source of the transistor QA _2. The gates of the second transistor QB ₂ and the third transistor QC ₂ are connected to the switch control unit 12.

In current switch circuit 11 _2, the first transistor QA _2, for example, operate to ON when the power supply voltage Vdd is applied to the gate. The second transistor QB _2, for example, when the switch control signal SC ₂ is input to the gate operates to turn ON / OFF the current flowing to ground via the QD ₂ from the first source of the transistor QA _2. The third transistor QC _2, for example, when the switch control signal SC ₂ is input to the gate of the first transistor QA ₂ gate - operates to OFF / ON the connection between the source.

In current switch circuit 11 _n, the drain of the first transistor QA _n is connected to the current output terminal 13. The source of the first transistor QA _n is connected to the drain of the current mirror output transistors QD _n. The source of the current mirror output side transistor QD _n is connected to the drain of the second transistor QB _n . The source of the second transistor QB _n is connected to the ground. The drain of the third transistor QC _n is connected to the gate of the first transistor QA _n, the source of the third transistor QC _n is connected to the source of the first transistor QA _n. The gates of the second transistor QB _n and the third transistor QC _n are connected to the switch control unit 12.

In current switch circuit 11 _n, the first transistor QA _n, for example, operate to ON when the power supply voltage Vdd is applied to the gate. The second transistor QB _n, for example, when the switch control signal SC _n is input to the gate operates to turn ON / OFF the current flowing to ground via the QD _n from the source of the first transistor QA _n. The third transistor QC _n, for example, when the switch control signal SC _n is input to the gate, the gate of the first transistor QA _n - operate to OFF / ON the connection between the source.

The first transistors QA ₁ , QA ₂ ,... QA _n may be, for example, input / output N channel MOS field effect transistors. The second transistors QB ₁ , QB ₂ ,... QB _n may be, for example, core N-channel MOS field effect transistors. The third transistors QC ₁ , QC ₂ ,... QC _n may be, for example, core P-channel MOS field effect transistors. The current mirror output side transistors QD ₁ , QD ₂ ,... QD _n may be, for example, core N-channel MOS field effect transistors. The first transistor _QA 1, _QA 2, ... QA _n, the thickness of the second transistor _QB 1, _QB 2, ... QB _n and the third transistor _QC 1, _QC 2, ... gate insulating film of the QC _n is a semiconductor integrated circuit 10 in accordance with the specifications of, and more, specifically, for example, current switch circuit ₁₁ 1, ₁₁ 2, ... 11 in accordance with the operating speed and oN / OFF current ratio is required in _n, it is appropriately selected it can. The core MOS is a MOS with a relatively thin gate insulating film, a short minimum gate length, and a low withstand voltage in one process, but is capable of high-speed operation, and an input / output MOS is a single MOS. The gate insulating film is relatively thick in the process, the distance of the gate length is longer than that for the core, and the MOS is a MOS that has high withstand voltage but high speed operation is difficult.

The circuit configuration of each of the current switch circuits 11 ₁ , 11 ₂ ,... 11 _n is not limited to the above-described circuit configuration. To explain the current switching circuit 11 ₁ in, for example, it may be circuitry that interchanged positional relationship between the current mirror output transistors QD ₁ and the second transistor QB _1. More specifically, for example, the first source of the transistor QA ₁ is connected to the second drain of the transistor QB _1, the second source of the transistor QB ₁ is connected to the drain of the current mirror output transistors QD _1, the current mirror or as a circuit configuration in which the source of the output side transistor QD ₁ is connected to the ground.

The voltage applied to the gates of the first transistors QA ₁ , QA ₂ ,... QA _n is not limited to the power supply voltage Vdd, and for example, the second transistor QB ₁ , which is a core MOS field effect transistor, _If the voltage is lower than the withstand voltage of QB ₂ , ... QB _n and the third transistor QC ₁ , QC ₂ , ... QC _n and the first transistors QA ₁ , QA ₂ , ... QA _n turn on, It may be any voltage.

The current mirror bias circuit 20 includes a constant current source 21 and a current mirror input side transistor QE. The constant current source 21 is a current source which supplies a constant current which is a reference current of the current mirror circuit. The current mirror input side transistor QE configures a current mirror circuit that controls each of the output currents I1 to In of the current switch circuits 11 ₁ , 11 ₂ ,... 11 n based on the reference current. More specifically, the drain of the current mirror input side transistor QE is connected to the constant current source 21 and the source is connected to the ground. Further, the gate and the drain of the current mirror input side transistor QE are connected. Furthermore, the gate of the current mirror input side transistor QE is the current mirror output transistors _QD 1, _QD 2, is connected to the gates of ... QD _n.

The current mirror bias circuit 20 and the current mirror output transistors _QD 1, _QD 2, ... a current mirror circuit composed of QD _n, the current switch circuits _{11 1, 11 2, ... 11} n output currents _I 1 ~I _n of Are controlled to have a current corresponding to the corresponding bit of the n-bit digital signal. For example, the output current I ₁ of the current switch circuits 11 ₁ controlled by a current mirror output transistor QD ₁ corresponds to 0-th bit of the n-bit digital signal, therefore, the current of 2 ⁰ × (1 ×) It is controlled. Output current I ₂ of the current switch circuits 11 _2, which is controlled by the current mirror output transistors QD ₂ corresponds to 1 bit of the n-bit digital signal, therefore, is controlled to a current of 2 x ¹ (2 times) Ru. Output current I _n of the current switch circuits 11 _n are controlled by a current mirror output transistor QD _n corresponds to n-1 th bit of the n-bit digital signal, therefore, it is controlled by the 2 ^n-1 times the current Ru. As another embodiment, the current mirror bias circuit 20 and the current mirror output transistors _QD 1, _QD 2, the current mirror circuit composed of ... QD _n, the current switch circuits _{11 1, 11 2, ... 11} n of the output current I ₁ ~I _n may be controlled so that all the same current. In this case, the current switch circuits 11 ₁ , 11 ₂ ,... 11 _n may be provided by the number n = 2 ^N with respect to the digital signal of N bits.

  The control circuit 30 generates a digital control signal based on, for example, an n-bit digital signal, and outputs the digital control signal to the switch control unit 12. The control circuit 30 is, for example, a circuit that receives a digital signal of parallel data, converts it into a digital signal of serial data, and outputs the digital signal to the switch control unit 12. However, the control circuit 30 is not particularly limited thereto.

Analog signal output circuit 40, for example, current switch circuits _{11 1, 11 2, ... 11} n output currents _I 1 analog signal corresponding to the total current of ~I _n, i.e., the value corresponding to n-bit digital signal Output analog signal. The analog signal output circuit 40 may include, for example, a constant current source and a current mirror circuit (not shown) powered by the power supply voltage Vdd, but is not particularly limited thereto.

First Embodiment
Current switch circuits ₁₁ 1, ₁₁ 2, the operation of ... 11 _n, the current switch circuits 11 ₁ to example will be explained with reference to FIGS.

Figure 2 is an example of a circuit diagram of a current switching circuit 11 ₁ of the first embodiment, showing a state in which current switch circuit 11 ₁ is ON. Further, FIG. 3 is an example of a circuit diagram of a current switching circuit 11 ₁ of the first embodiment, showing a state in which current switch circuit 11 ₁ is turn OFF.

The driving method of the current switching circuit 11 _1, for example, a turning ON the first transistor QA ₁ by applying a power supply voltage Vdd to the first gate of the transistor QA _1, the switch control signal SC to the second gate of the transistor QB ₁ includes inputting a _1, and to the third gate of the transistor QC ₁ inputs the switch control signal SC _1, a.

Current switch circuit 11 _1, for example, while the power supply voltage Vdd to the gate of the first transistor QA ₁ is ON is applied, a state capable of operation by the switch control signal SC _1. Current switch circuit 11 ₁ in operation, while the switch control signal SC ₁ is H level, the second transistor QB ₁ is turned ON, whereby the first transistor QA ₁ from the current output terminal 13, the current mirror output side output current _{I 1} to the ground flows through the transistor QD ₁ and the second transistor QB ₁ (FIG. 2). The current value of the output current I _1, as described above, a predetermined value is constant-current controlled by the current mirror output transistors QD _1.

On the other hand, while the switch control signal SC ₁ is at L level, the output current _{I 1} is interrupted by the second transistor QB ₁ is turned OFF. Furthermore, while the switch control signal SC ₁ is at the L level, the third transistor QC ₁ is the gate of the first transistor QA ₁ to ON - between the source are short-circuited are connected, whereby the first transistor QA ₁ also Turn off (Figure 3).

In Figure 3, the leakage current _{I a} of the first transistor QA ₁ flows from the current output terminal 13 first transistor QA _1, to the ground through the current mirror output transistors QD ₁ and the second transistor QB _1. On the other hand, the leakage current _{I b} of the second transistor QB ₁ flows to the ground from the first transistor QA ₁ gate through a third transistor QC _1. Therefore, current switching circuit 11 ₁ of the leakage current, i.e., current flowing from the first transistor QA ₁ drain to ground, received only a negligible influence of the second transistor QB ₁ of the leakage current I _b.

Therefore, the switch control signal between SC ₁ is at the L level, the leakage current to the current switch circuit 11 ₁ of the output side, i.e., the first transistor QA ₁ from the current output terminal 13, the current mirror output transistors QD ₁ and the second leakage current flowing through the transistor QB ₁ to ground is equal to the first transistor QA ₁ of the leakage current _{I a.} The first transistor QA ₁ is a input-output MOS field effect transistor. Therefore, the gate - under the same conditions of the potential difference between the source 0V is leakage current I _a of the first transistor QA ₁ is smaller than before. Therefore, by reducing the first transistor QA ₁ of the leakage current _{I a,} it is possible to increase the ON / OFF current ratio of the current switch circuits 11 _1, the reduction of ON / OFF current ratio due to the leakage current It is possible to reduce the possibility of a malfunction.

The third transistor QC _1, since it is possible to thin the gate insulating film than the first transistor QA _1, is capable of high-speed switching operation. Therefore, the timing of the switch control signal SC ₁ becomes L level, the time until the leakage current of the current switch circuits 11 ₁ first transistor QA ₁ is turned OFF becomes the first transistor QA ₁ of the leakage current _{I a} very It can be shortened.

Further, as described above, the first transistor QA ₁ are the input-output MOS field effect transistor is small leakage current than the second transistors QB _1. Therefore, the size between the current switching circuit 11 ₁ of the leakage current switch control signal SC ₁ is at L level depends on the size of the first transistor QA ₁ of the leakage current. The second transistor QB _1, since it is possible to sufficiently thin the gate insulating film to the extent capable of high-speed operation, it is capable of high-speed switching operation. Then, the operation speed of the current switch circuit 11 ₁ is dependent on the second operating speed of the transistor QB _1. Accordingly, the current switching circuit 11 ₁ can operate at high speed in accordance with the switch control signal SC _1.

  Thus, it is possible to provide the semiconductor integrated circuit 10 which operates at high speed and is less likely to malfunction.

Second Embodiment
A second embodiment of a current switch circuit 11 ₁ will be described with reference to FIG.
Figure 4 is an example of a circuit diagram of a current switching circuit 11 ₁ of the second embodiment.

Current switch circuit 11 ₁ of the second embodiment, for example, the power supply voltage Vdd is applied to the gate turned ON, and the first transistor _{QA 1a} having a drain connected to the current output terminal 13 _a, the gate switch control signal SC ₁ is input, the second transistor QB _1a that turns ON / OFF the current flowing from the source to the ground of the first transistor QA _1a , and the switch control signal SC ₁ is input to the gate, and between the gate and source of the first transistor QA _1a And a third transistor QC _1a that turns on / off the connection of The source of the first transistor QA _1a is connected to the drain of the second transistor QB _1a . The source of the second transistor _{QB 1a} is connected to the drain of the current mirror output transistors QD _1. The source of the current mirror output transistors QD ₁ is connected to ground. The drain of the third transistor _{QC 1a} is connected to the gate of the first transistor _{QA 1a,} the source of the third transistor _{QC 1a} is connected to the source of the first transistor _{QA 1a.}

Moreover, current switch circuit 11 ₁ of the second embodiment, for example, the power supply voltage Vdd is applied to the gate turned ON, the fourth transistor QA _1b having a drain connected to the current output terminal 13 _b, switch control to the gate is input logic inversion signal _{SC 1R} signal SC _1, and a fifth transistor _{QB 1b} to oN / OFF a current flowing from the source to the ground of the fourth transistor _{QA 1b,} the logic inversion signal of the switch control signal SC ₁ to the gate _{SC 1R} And the sixth transistor QC 1 _b that turns on / off the connection between the gate and the source of the fourth transistor QA 1 _b . The source of the fourth transistor QA 1 _b is connected to the drain of the fifth transistor QB 1 _b . The source of the fifth transistor QB 1 _b is connected to the drain of the current mirror output side transistor QD ₁ . The drain of the sixth transistor _{QC 1b} is connected to the gate of the fourth transistor _{QA 1b,} the source of the sixth transistor _{QC 1b} is connected to a source of the fourth transistor QA ₁ b. The source of the fifth transistor QB 1 _b is connected to the source of the second transistor QB ₁ a.

The first transistor QA _1a may be, for example, an input / output N channel MOS field effect transistor. The second transistor QB _1a may be, for example, an N channel MOS field effect transistor for core. The third transistor _{QC 1a} may be, for example, a P-channel MOS field-effect transistor for the core. Similarly, the fourth transistor QA 1 _b may be, for example, an input / output N channel MOS field effect transistor. The fifth transistor QB 1 _b may be, for example, an N-channel MOS field effect transistor for core. The sixth transistor QC 1 _b may be, for example, a core P-channel MOS field effect transistor. Current mirror output transistors QD ₁ may be, for example, N-channel MOS field-effect transistor for the core.

Thus, the current switching circuit 11 ₁ of the second embodiment is a differential amplifier circuit. According to current switch circuits 11 ₁ of the second embodiment, it is possible to provide a semiconductor integrated circuit 10 comprising a current switch circuit 11 ₁ consists of a risk is small differential amplifier circuit operates at a high speed, and erroneous operation .

Third Embodiment
Figure 5 is an example of a circuit diagram of a current switching circuit 11 ₁ of the third embodiment.

Current switch circuit 11 ₁ of the third embodiment does not include the current mirror output transistors QD _1, the first source of the transistor QA ₁ is connected to the second drain of the transistor QB _1, the second transistor QB ₁ in that the source is connected to the ground, different from the current switching circuit 11 ₁ of the first embodiment. The circuit configuration of the other is omitted since the same circuit configuration as the current switch circuit 11 ₁ of the first embodiment, the same to the components detailed denoted by the same reference numerals explained.

Current switch circuit 11 ₁ of the third embodiment of such a circuit configuration, similar to the current switch circuit 11 ₁ of the first embodiment, and operates at high speed, and to provide a semiconductor integrated circuit 10 possibly with less malfunction be able to.

Fourth Embodiment
Figure 6 is an example of a circuit diagram of a current switching circuit 11 ₁ in the fourth embodiment.

Current switch circuit 11 ₁ of the fourth embodiment does not include the current mirror output transistors QD _1, in that the source of the source and the second transistor QB _1b of the second transistor QB _1a is connected to the ground, It differs from the current switching circuit 11 ₁ of the second embodiment. The circuit configuration of the other is omitted since the same circuit configuration as the current switch circuit 11 ₁ of the second embodiment, the same to the components detailed denoted by the same reference numerals explained.

Current switch circuit 11 ₁ of the fourth embodiment of such a circuit configuration, similar to the current switch circuit 11 ₁ of the second embodiment operates in high speed, and is composed of a differential amplifier circuit risk is small malfunction it is possible to provide a semiconductor integrated circuit 10 which current comprises a switch circuit 11 ₁ that.

<Control circuit>
The configuration of control circuit 30 will be described in detail with reference to FIGS. 7 to 10.

FIG. 7 is a circuit diagram illustrating an example of a circuit configuration of control circuit 30. Referring to FIG. As shown in the figure, the control circuit 30 inputs digital signals VL _{0 to} VL ₃ which are parallel data of 4 bits as an example of a digital signal of n bits, and performs digital control which is a digital signal of serial data It is a digital logic circuit that converts to the signal VO_SEL and outputs it. The control circuit 30 includes, for example, two NAND circuits 311 and 312, two NOR circuits 313 and 314, a NOT circuit 315, and a buffer circuit 316.

The NAND circuit 311 is, for example, a two-input NAND circuit. A NAND circuit 311, 4 digital signal VL ₁ digital signal VL ₀ and 1 bit of 0-th bit of the bit of the digital signal. The NAND circuit 312 is, for example, a two-input NAND circuit. A NAND circuit 312, 4 digital signal VL ₂ and 3 bit digital signal VL ₃ of 2 bit of the bits of the digital signal. The NOR circuit 313 is, for example, a 2-input NOR circuit. The output signal of the NAND circuit 311 and the output signal of the NAND circuit 312 are input to the NOR circuit 313. The NOR circuit 314 is, for example, a 2-input NOR circuit. The output signal of the NOR circuit 313 and the output signal of the buffer circuit 316 are input to the NOR circuit 314. For example, an output signal of the NOR circuit 314 is input to the NOT circuit 315. An output signal of the NOT circuit 315 is input to the switch control unit 12 (FIG. 1) of the semiconductor integrated circuit 10 as a digital control signal VO_SEL. The buffer circuit 316 receives, for example, an output signal of the NOR circuit 313.

The digital signals VL _{0 to} VL ₃ are, for example, digital signals of negative logic. When all the digital signals VL _{0 to} VL ₃ are at the H level, the control circuit 30 outputs the digital control signal VO_SEL at the H level. On the other hand, when one of the digital signals VL _{0 to} VL ₃ becomes L level, the control circuit 30 outputs a digital control signal VO_SEL of L level.

Buffer circuit 316 typically functions as a delay circuit, and corresponds to the falling timing of digital control signal VO_SEL (the timing of falling from H level to L level) of 4-bit digital signals VL _{0 to} VL ₃ . This is a circuit for shifting (delaying) the timing corresponding to the timing at which the 2-transistor QB ₁ switches from ON to OFF. In the NOR circuit 314, the output signal changes from L level to H level when both of the two input signals change from H level to L level. Therefore, for example, when any of 4-bit digital signals VL _{0 to} VL ₃ goes from H level to L level, the output signal of NOR circuit 313 goes from H level to L level, and further, the output of buffer circuit 316 When the signal changes from H level to L level, the output signal of the NOR circuit 314 changes from L level to H level. Therefore, with respect to the fall timings of the 4-bit digital signals VL _{0 to} VL ₃ , the fall timing of the digital control signal VO_SEL is intentionally delayed by the delay time generated in the buffer circuit 316.

On the other hand, in the NOR circuit 314, when either of the two input signals changes from the L level to the H level, the output signal changes from the H level to the L level at that time. Therefore, when any of the 4-bit digital signals VL _{0 to} VL ₃ goes from L level to H level, the output signal of NOR circuit 314 goes H at the point when the output signal of NOR circuit 313 goes from L level to H level. Go from level to L level. Therefore, no intentional delay occurs in the rising timing of the digital control signal VO_SEL with respect to the rising timings of the 4-bit digital signals VL _{0 to} VL ₃ .

Although the circuit for shifting (delaying) the fall timing of the digital control signal VO_SEL with respect to the fall timing of the 4-bit digital signals VL _{0 to} VL ₃ has been described as an example, the present invention is particularly limited thereto is not. For example, if the circuit configuration corresponds to the timing at which the second transistor QB ₁ switches from ON to OFF, the rising timing (the timing from L level to H level) of the 4-bit digital signals VL _{0 to} VL ₃ is 4 The rise timing of the digital control signal VO_SEL with respect to the rise timing of the bit digital signals VL _{0 to} VL ₃ may be shifted (delayed).

Figure 8 is a graph showing the output signal waveform of the current switch circuit 11 _1. In the graph of FIG. 8, the horizontal axis represents time t, the vertical axis represents the output current I of the current switch circuit 11 _1. The solid line waveform in FIG. 8, an illustration of the output current waveform of the current switch circuits 11 ₁ of the first embodiment shown in FIGS. 1 to 3, the broken line waveform in FIG. 8, FIGS. 1 to 3 in the current switching circuit 11 ₁ of the first embodiment illustrated in a diagrammatic representation of the output current waveform when a structure without the third transistor QC _1.

Current switch circuits 11 ₁ according to the present invention, when compared with the structure without the third transistor QC _1, as described above, the leakage current to the output side is decreased. Decline of the leakage current to the current switch circuit 11 ₁ of the output side ΔI corresponds to the difference between the first transistor QA ₁ the leakage current and the second transistor leakage QB _1. The current switch circuit 11 ₁ according to the present invention, when compared with the structure without the third transistor QC _1, as shown, the delay time from the rising timing of the digital control signal VO_SEL to the rise timing of the output current I Increase by t1. Increase itself delay the rise timing of the output current I, in terms of operating the current switch circuit 11 ₁ at high speed, it is the degree of extremely small that matters little. However, ON / OFF duty ratio of the output current I of the current switch circuits 11 ₁ would error caused by an increase in the delay of the rising timing of the output current I.

  FIG. 9 is a graph showing a voltage waveform of the digital control signal VO_SEL output from the control circuit 30. In FIG. 9, the horizontal axis is time t, and the vertical axis is voltage V of digital control signal VO_SEL. The waveform of the solid line in FIG. 9 illustrates the voltage waveform of the digital control signal VO_SEL output by the control circuit 30 illustrated in FIG. 7. The waveform of the dashed line in FIG. 9 corresponds to that in the control circuit 30 illustrated in FIG. The voltage waveform of the digital control signal VO_SEL is illustrated in the case where the NOR circuit 314 is replaced with a NOT circuit without providing the buffer circuit 316.

Figure 10 is a graph illustrating an output signal waveform of the current switch circuit 11 _1. In the graph of FIG. 10, the horizontal axis represents time t, the vertical axis represents the output current I of the current switch circuit 11 _1. The solid line waveform in FIG. 10 is carried out based on the digital control signal VO_SEL the control circuit 30 illustrated in FIG. 7 outputs, the switch control of the current switching circuit 11 ₁ of the first embodiment shown in FIGS. 1 to 3 Output current waveform in the case of The waveform of the broken line in FIG. 10 is based on the digital control signal VO_SEL when the NOR circuit 314 is changed to a NOT circuit without providing the buffer circuit 316 in the control circuit 30 shown in FIG. an output current waveform in the case of performing the switching control of the current switching circuit 11 ₁ of the first embodiment shown in to 3.

As described above, with respect to the falling timings of the 4-bit digital signals VL _{0 to} VL ₃ , there is an intentional delay in the falling timing of the digital control signal VO_SEL by the delay time t 2 generated in the buffer circuit 316. It occurs (Figure 9). Thus, by delaying the fall timing of the digital control signal VO_SEL respect to the falling timing of the digital signal _VL 0 _{~VL 3,} the amount corresponding the delay time _{t 2,} the fall of the output current I of the current switch circuits 11 ₁ You can delay the timing. Thereby, it is possible to cancel out the delay time t ₁ of the rising timing of the output current I of the current switch circuits 11 _1, ON / OFF caused due to the delay of the rising timing of the output current I of the current switch circuits 11 ₁ Errors in the duty ratio can be reduced (FIG. 10).

Other Embodiments
Each of the above-described embodiments is an example for describing the present invention, and the present invention is not limited to the embodiments. The present invention can be practiced in various forms without departing from the scope of the invention.

  For example, in the method disclosed herein, the steps, operations or functions may be performed in parallel or in different orders, as long as the results are not inconsistent. The steps, operations and functions described are merely provided as examples, and some of the steps, operations and functions may be omitted without departing from the scope of the invention, and may be combined with one another. One or more steps, operations or functions may be added.

  In addition, although various embodiments are disclosed herein, the specific features (technical matters) in one embodiment may be added to the other embodiments or modified while appropriately improving the technical features. Specific features in the form can be substituted, and such form is also included in the scope of the present invention.

  The present invention can be widely used in the field of semiconductor integrated circuits.

DESCRIPTION OF SYMBOLS 10 semiconductor integrated circuits 11 ₁ and 11 _{2 to} 11 _n current switch circuit 12 switch control units 13 and 13 _a , 13 _b current output terminal 20 current mirror bias circuit 21 constant current source 30 control circuit 40 analog signal output circuit 311, 312 NAND circuit 313 and 314 NOR circuit 315 NOT circuit 316 buffer circuits QA ₁ and _QA 2 _{~QA n} first transistors QB ₁ and _QB 2 _{~QB n} second transistors QC ₁ and _QC 2 _{~QC n} third transistors QD ₁ and QD ₂ ~ QD _n current mirror output side transistor QE current mirror input side transistor

Claims (8)

Equipped with a current switch circuit,
The current switch circuit is
A first transistor which is an input / output N-channel MOS field effect transistor whose gate is applied with a predetermined voltage to be turned on and whose drain is connected to the current output terminal;
A second transistor that is a core N-channel MOS field effect transistor that receives a switch control signal at its gate and turns on / off the current flowing from the source of the first transistor to the ground;
And a third transistor that is a core P-channel MOS field effect transistor that receives the switch control signal at its gate and turns on / off the connection between the gate and the source of the first transistor.
Semiconductor integrated circuit.   The semiconductor integrated circuit according to claim 1, further comprising: a constant current control circuit that performs constant current control on an output current of the current switch circuit.   The semiconductor integrated circuit according to claim 2, wherein the constant current control circuit includes a current mirror output side transistor forming a current mirror circuit that controls an output current of the current switch circuit based on a reference current. Integrated circuit. The semiconductor integrated circuit according to any one of claims 1 to 3, wherein the current switch circuit is
A fourth transistor which is an input / output N-channel MOS field effect transistor whose gate is applied with the predetermined voltage to be turned on and whose drain is connected to the current output terminal;
A fifth transistor that is a core N-channel MOS field effect transistor that receives a logic inversion signal of the switch control signal at its gate, and turns on / off the current flowing from the source of the fourth transistor to the ground;
And a sixth transistor that is a core P-channel MOS field effect transistor that receives a logic inversion signal of the switch control signal at its gate and turns on / off the connection between the gate and the source of the fourth transistor;
A semiconductor integrated circuit, wherein a source of the second transistor and a source of the fifth transistor are connected. The semiconductor integrated circuit according to any one of claims 2 to 4, wherein n pieces of n corresponding to each bit of a digital signal of n (n is an integer of 1 or more) bits are connected in parallel. Current switch circuit,
A switch control unit that outputs the switch control signal corresponding to each of the n current switch circuits based on a digital control signal;
The constant current control circuit is configured such that an output current of each of the n current switch circuits is a current corresponding to a corresponding bit of the n bit digital signal. Semiconductor integrated circuit that controls each output current. A semiconductor integrated circuit according to claim 5;
A control circuit that generates the digital control signal based on the n-bit digital signal;
A digital-to-analog conversion circuit comprising: an analog signal output circuit that outputs an analog signal according to a total output current of the n current switch circuits. 7. The digital-to-analog converter circuit according to claim 6, wherein
The control circuit includes a delay circuit that delays the rising or falling timing of the digital control signal with respect to the rising or falling timing of the n-bit digital signal, and the rising or falling timing of the digital control signal is the second Digital-analog conversion circuit corresponding to the timing at which the transistor switches from ON to OFF. Applying a predetermined voltage to the gate of the first transistor, which is an input / output N channel MOS field effect transistor whose drain is connected to the current output terminal, to turn on the first transistor;
Inputting a switch control signal to a gate of a second transistor that is an N-channel MOS field effect transistor for core that turns on / off a current flowing from the source of the first transistor to the ground;
And V. inputting the switch control signal to the gate of a third transistor, which is a core P-channel MOS field effect transistor, for turning on / off the gate-source connection of the first transistor.
Method of driving a semiconductor integrated circuit.

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