JP2019057664A - Method of manufacturing semiconductor device - Google Patents

Abstract

An object of the present invention is to improve the reliability of a semiconductor device. A method of manufacturing a semiconductor device includes a step of performing a plurality of wafer tests on a semiconductor wafer to form a plurality of probe marks PM on each of a plurality of pad electrodes PD; and connecting the ball portion Wb of the wire to the pad electrode PD so as to be covered with the ball portion Wb of the wire. Each of the plurality of probe marks PM has, in a cross-sectional view, a protrusion CV protruding from the main surface of the pad electrode PD and a recess CC recessed from the main surface. In addition, at the junction Wc between the ball portion Wb of the wire and the pad electrode PD, the two adjacent probe marks PM have a separation distance equal to or less than the diameter of the probe marks PM in a plan view. Each recess CC of the PM is spaced apart from each other. [Selection drawing] Fig. 12

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a technique effective when applied to a method for manufacturing a semiconductor device in which a wire is connected to the surface of a pad electrode having a plurality of probe marks.

  In JP-A-2005-116724 (Patent Document 1) and JP-A-2008-192971 (Patent Document 2), a plurality of pad electrodes (electrode pads, bonding pads) formed on a semiconductor chip are connected to probe needles (electrode pads, bonding pads). A technique for connecting a ball portion of a wire (bonding wire) to a pad electrode so as to cover a probe mark formed on the pad electrode after performing a wafer test by pressing the probe) is disclosed.

JP 2005-116724 A JP 2008-192971 A

  In the same manner as in Patent Document 1 and Patent Document 2 described above, the inventor of the present application performs a wafer test several times by pressing the probe needle on the surface of the pad electrode for high integration of the semiconductor device, We are investigating a technique for connecting a wire to the surface of a pad electrode on which a probe mark is formed using a wire bonding method. However, the number of wafer test processes has increased with the increase in functionality of semiconductor devices, and the number of probe marks formed on the surface of the pad electrode has also increased. Under such circumstances, the present inventor has come to recognize the problem that when a wire is connected to a pad electrode so as to overlap a large number of probe traces, the wire peels off from the pad electrode.

  In the semiconductor device, it is desired to improve the reliability of the semiconductor device.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  A method for manufacturing a semiconductor device according to an embodiment includes a step of performing a plurality of wafer tests on a semiconductor wafer to form a plurality of probe marks on each of a plurality of pad electrodes, and a plurality of probe marks, Connecting the ball portion of the wire to the pad electrode so as to cover the ball portion of the wire. Each of the plurality of probe marks has a convex portion protruding from the main surface of the pad electrode and a concave portion recessed from the main surface in a cross-sectional view. In addition, at the joint between the wire ball portion and the pad electrode, two adjacent probe marks have a separation distance equal to or smaller than the diameter of the probe mark in plan view, and each of the plurality of probe marks has a recessed portion. Are separated from each other.

  According to one embodiment, the reliability of a semiconductor device can be improved.

It is a process flow figure showing a manufacturing process of a semiconductor device of this embodiment. It is a top view which shows the structure of the semiconductor chip of this Embodiment. It is principal part sectional drawing of the semiconductor chip in the wafer test process of this Embodiment. It is a principal part expanded sectional view of FIG. It is a principal part top view of the semiconductor chip which is an examination example. It is sectional drawing which follows the X1-X1 line | wire of FIG. It is sectional drawing of the wafer test apparatus used at the wafer test process of this Embodiment. It is a top view of the semiconductor wafer in the wafer test process of this Embodiment. It is sectional drawing of the semiconductor wafer explaining the wafer test process of this Embodiment. It is a top view of the pad electrode explaining the wafer test process of this Embodiment. It is a top view of the pad electrode of this Embodiment. It is principal part sectional drawing which follows the X2-X2 line | wire of FIG. It is a perspective view explaining the dicing process of this Embodiment. It is sectional drawing explaining the die-bonding process of this Embodiment. It is sectional drawing explaining the wire bonding process of this Embodiment. It is sectional drawing explaining the resin sealing process of this Embodiment. It is sectional drawing of the semiconductor device of this Embodiment. It is a principal part top view and principal part sectional drawing which show the pad electrode of a 1st modification. It is the principal part top view and principal part sectional drawing which show the pad electrode of a 2nd modification. It is a top view which shows the pad electrode of a 3rd modification. It is a top view which shows the pad electrode of a 4th modification.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like.

  Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say.

  Similarly, in the following embodiments, when referring to the shape, positional relationship, etc., of components, etc., unless otherwise specified, and in principle, it is considered that this is not clearly the case, it is substantially the same. Including those that are approximate or similar to the shape. The same applies to the above numerical values and ranges.

  In all the drawings for explaining the embodiments, the same members are denoted by the same reference symbols in principle, and the repeated explanation thereof is omitted. In order to make the drawings easy to understand, even a plan view may be hatched.

(Embodiment)
FIG. 1 is a process flow diagram showing manufacturing steps of the semiconductor device of the present embodiment. FIG. 2 is a plan view showing the configuration of the semiconductor chip of the present embodiment. The semiconductor device of this embodiment includes the semiconductor chip shown in FIG.

  As shown in FIG. 1, the semiconductor device according to the present embodiment sequentially includes a wafer preparation step (S1), a plurality of wafer test steps (S2), a wafer dicing step (S3), a die bonding step (S4), and a wire. Although it has a bonding process (S5) and a resin sealing process (S6), each process is mentioned later.

  FIG. 2 is a plan view showing a semiconductor chip C on which, for example, a microcomputer is formed, and is a diagram showing a layout configuration of each element formed on the semiconductor chip C. In FIG. 2, the semiconductor chip C has a CPU (Central Processing Unit) 1, a RAM (Random Access Memory) 2, an analog circuit 3, and a flash memory 4. The semiconductor chip C has a plurality of pad electrodes (bonding pads, external connection terminals) PD which are input / output terminals with the outside in the peripheral region of the rectangular semiconductor chip C. The plurality of pad electrodes PD are arranged in a ring shape in a peripheral region surrounding a circuit formation region in which the CPU 1, RAM 2, analog circuit 3 and flash memory 4 are formed. In the present embodiment, one semiconductor chip has a plurality of pad electrodes PD as an example. However, this is a semiconductor chip in which only one pad electrode PD is formed. May be.

  The CPU (circuit) 1 is also called a central processing unit and corresponds to the heart of a computer or the like. The CPU 1 reads out and decodes instructions from the storage device, and performs various operations and controls based on the instructions, and requires high-speed processing. Therefore, a MISFET (Metal Insulator Semiconductor Field Effect Transistor) constituting the CPU 1 requires relatively high speed operation and low power consumption among elements formed on the semiconductor chip C. That is, the CPU 1 is mainly formed of a low breakdown voltage MISFET. The CPU 1 includes a plurality of logic circuits composed of a plurality of MISFETs.

  The RAM (circuit) 2 is a memory that can read stored information at random, that is, read stored information at any time, or write new stored information, and is also called a memory that can be written and read at any time. Here, an SRAM (Static RAM) using a static circuit is used, and the SRAM is an occasional write / read memory that does not require a memory holding operation. The MISFET constituting the RAM 2 is formed of a low breakdown voltage MISFET.

  The analog circuit 3 is a circuit that handles a voltage or current signal that changes continuously in time, that is, an analog signal, and includes, for example, an amplifier circuit, a conversion circuit, a modulation circuit, an oscillation circuit, and a power supply circuit. These analog circuits 3 include a high voltage MISFET.

  The flash memory (memory circuit) 4 is a nonvolatile memory that can electrically perform a write operation and an erase operation. The memory cell of the flash memory 4 has a gate electrode, a charge storage unit, and a source region and a drain region. Since a high voltage is used in the write operation or erase operation of the memory cell, the flash memory 4 has a booster circuit, and the booster circuit is formed of a high breakdown voltage MISFET.

  The semiconductor chip C shown in FIG. 2 is formed on a semiconductor substrate SB called a semiconductor wafer WF (see FIGS. 3 and 8). That is, a plurality of semiconductor chips C are arranged in a matrix on the semiconductor wafer WF. Then, the wafer test process (S2) shown in FIG. 1 is performed a plurality of times on each of the semiconductor chips C formed on the semiconductor wafer WF. The wafer test step (S2) is, for example, a step of inspecting electrical characteristics of a circuit formed on the semiconductor chip C, and is performed on the semiconductor wafer WF including the semiconductor chip C. The wafer test process (S2) includes various types such as “high temperature test”, “room temperature test”, “low temperature test”, “room temperature test after burn-in”, “memory test”, “logic test”, and “contact check”. Includes tests. For example, the “high temperature test” is performed in a state where the semiconductor wafer WF is held at a temperature of 90 ° C. or higher and 130 ° C. or lower, for example.

  FIG. 3 is a fragmentary cross-sectional view of the semiconductor chip in the wafer test process of the present embodiment. 4 is an enlarged cross-sectional view of a main part of FIG.

  As shown in FIG. 3, the wafer test step (S2) is performed by bringing the probe needle PB into contact with the pad electrode PD of the semiconductor chip C. Here, one pad electrode PD and one probe needle PB in contact with the pad electrode PD are shown. However, in the wafer test process, the probe needle PB is similarly applied to a plurality of other pad electrodes PD. Be touched. That is, the probe needle PB is simultaneously brought into contact with the plurality of pad electrodes PD. That is, the tip end portion PBt of the probe needle PB is in contact with the main surface PDa of the pad electrode PD. The pad electrode PD is made of, for example, a conductor film containing aluminum (Al) as a main component, but a trace amount of silicon (Si) or copper (Cu) may be contained in the aluminum. For example, the film thickness of the pad electrode PD is 1.0 to 2.0 μm. The pad electrode PD is disposed on the insulating film IF1 formed on the semiconductor substrate SB.

  As shown in FIG. 3, the pad electrode PD is covered with an insulating film IF2 formed over the pad electrode PD and the insulating film IF1. However, the insulating film IF2 has an opening OP, and the main surface PDa of the pad electrode PD is exposed from the insulating film IF2 through the opening OP. In other words, the sidewall (peripheral surface) PDs of the pad electrode PD and the peripheral region of the main surface PDa of the pad electrode PD are covered with the insulating film IF2. The planar shape of the opening OP is, for example, a square, but includes a substantially square whose corner is processed into an arc or a straight line. Further, the planar shape of the opening OP is not necessarily a square, and may be a rectangle or a substantially rectangle. In the following description, the pad electrode PD means a pad electrode PD in a region exposed from the opening OP. For example, the length of one side of the square opening OP is 50 to 65 μm. Incidentally, in this embodiment, it is 65 μm.

  The probe needle PB is pressed against the pad electrode PD with a desired load from a direction perpendicular to the main surface PDa of the pad electrode PD. Here, the term “perpendicular” includes within a range of ± 5 ° from the direction perpendicular to the main surface PDa of the pad electrode PD. That is, in the present embodiment, “vertical probe card” is a target, and “cantilever probe card” is not a target.

  4 is an enlarged cross-sectional view of a main part in the area AR1 of FIG. 3, and also shows a plan view of the probe mark PM. That is, the probe mark PM is formed on the main surface PDa of the pad electrode PD by the load received from the probe needle PB. Here, since the cross section of the probe needle PB is circular, the probe mark PM has a circular concave portion CC and a ring-shaped (annular) convex portion CV. Although not shown, a natural oxide film (aluminum oxide film) is formed on the main surface PDa of the pad electrode PD. In the wafer test step (S2), the natural oxide film is formed in the recess CC of the probe mark PM. Is destroyed. As shown in FIG. 4, the bottom of the concave portion CC has a height H1 lower than the height H0 of the main surface PDa of the pad electrode PD, and the top of the convex portion CV has a height H2 higher than the height H0. Have Here, the heights H0, H1, and H2 are based on, for example, the main surface SBa or the back surface SBb of the semiconductor substrate SB shown in FIG. Here, the depth of the concave portion CC, that is, the difference between the height H0 and the height H1 is 0.5 to 0.6 μm. Further, the recess CC has a circular shape with a radius r1 (for example, 3.0 μm ≦ r1 ≦ 3.5 μm). The convex portion CV has a ring shape and is positioned so as to surround the concave portion CC. The radius r2 (for example, 4.0 μm ≦ r2 ≦ 5 μm) outside the convex portion CV is larger than the radius r1 of the concave portion CC. Further, since the size PMx in the X direction and the size PMy in the Y direction of the probe mark PM are equal, PMy / PMx = 1. If the size PMy in the Y direction is larger than the size PMx in the X direction of the probe mark PM, PMy / PMx> 1.5 in the “cantilever probe card”. 5> PMy / PMx> 1.0. That is, in the “vertical probe card”, the size PMx in the X direction and the size PMy in the Y direction of the probe mark PM are substantially equal. The cross section of the probe needle PB is not limited to a circle, but may be a square or a rectangle. In that case, the probe mark PM is also square or rectangular, but the relationship between the X direction and the Y direction (1.5> PMy / PMx> 1.0) is the same.

<Examination examples and issues>
Next, a study example and its problem will be described with reference to FIGS. FIG. 5 is a plan view of an essential part of a semiconductor chip as an examination example. 6 is a cross-sectional view taken along line X1-X1 of FIG. FIGS. 5 and 6 are pads in which a high-temperature storage test is performed after performing a plurality of wafer test steps (S2), a wire bonding step (S5), and a resin sealing step (S6) in the process flow diagram of FIG. The state of the electrode PD is shown. The high temperature storage test was, for example, 200 ° C. and 470 hours.

  In the study example shown in FIG. 5, a plurality of probe marks PM are densely formed near the center PDc of the pad electrode PD. And the recessed part CC of adjacent probe mark PM has mutually overlapped. FIG. 5 shows the outer shape of the ball portion Wb of the wire W and the outer shape of the bonding portion (connecting portion) Wc between the ball portion Wb and the pad electrode PD. Incidentally, the diameter of the wire W is 23 μm, and the diameter of the ball portion Wb is 50 μm. The plurality of probe marks PM are all arranged inside the joint (connection part) Wc. In other words, all the probe marks PM are covered with the ball portion Wb (more precisely, the joint portion Wc). The inventor of the present application confirmed the phenomenon that the joint Wc of the wire W peels from the pad electrode PD when there is a region where the probe marks PB are densely present in the joint Wc.

First, the wire W is a copper wire whose main component is copper (Cu). As shown in FIG. 6, an alloy layer CuAl ₂ , an alloy layer Cu ₉ Al ₄ , and an alloy layer CuAl are formed at the joint Wc between the pad electrode PD and the ball Wb of the wire W. The alloy layer CuAl ₂ has a feature that the growth is relatively fast at a relatively low temperature, and the alloy layer Cu ₉ Al ₄ has a feature that the growth is relatively fast at a relatively high temperature. At the interface between the alloy layer CuAl ₂ and the alloy layer Cu ₉ Al ₄ The alloy layer CuAl has grown. When the pad electrode PD is held in a high temperature atmosphere for a long time by the resin sealing step (S6) and the high temperature storage test performed after the wire bonding step (S5), the present inventor responds to the probe mark PM. Growth of the silicon-rich alloy layer Cu ₉ Al ₄ proceeds in the region. Then, it is considered that the alloy layer Cu ₉ Al ₄ undergoes volume expansion, the accompanying peeling stress PS extends around the ball portion Wb, and the ball portion Wb peels from the pad electrode PD.

In the wire bonding step (S5), since a thermocompression bonding method using ultrasonic vibration is used, a natural oxide film (aluminum oxide film) formed on the main surface PDa of the pad electrode PD is applied to the ball portion Wb. The alloy layer CuAl ₂ is formed at a portion where the natural oxide film is broken by the ultrasonic vibration. However, if the natural oxide film formed on the main surface PDa of the pad electrode PD is broken by the probe needle PB in the wafer test step (S2), the alloy layer CuAl ₂ is more likely to grow in that portion. That is, as shown in FIG. 6, in a region where probe marks PM (particularly, the concave portion CC) are densely formed and overlapped (in other words, in the vicinity of the center PDc of the pad electrode PD), compared to the periphery thereof, The alloy layer CuAl ₂ is formed thick. In other words, when the concave portions CC of the adjacent probe marks PM overlap, a wide and thick alloy layer CuAl ₂ is formed. When the pad electrode PD becomes high temperature, the reaction between the alloy layer CuAl ₂ and the copper (Cu) of the wire W proceeds, and the ratio of copper (Cu) to aluminum (Al) is high, “copper rich alloy Cu ₉ Al ₄ "is formed. That is, the alloy layer Cu ₉ Al ₄ is also wide and thick in the region where the probe marks PM are densely arranged and overlapped.

Therefore, as shown in FIG. 5, when a plurality of probe marks PM are densely arranged and the concave portions CC of the adjacent probe marks PM overlap, the copper-rich alloy layer Cu ₉ Al ₄ is wide, And since it forms thickly, the ball | bowl part Wb of the wire W will peel from the pad electrode PD by the volume expansion. The present embodiment provides a technique for solving such a problem.

  That is, in the present embodiment, when a large number of probe marks PM are formed on the pad electrode PD, the recesses CC of the probe marks PM are not overlapped, that is, the recesses CC of the adjacent probe marks PM are separated from each other. As described above, the probe needle PB is brought into contact with the pad electrode PD, thereby preventing the ball portion Wb of the wire W from being separated from the pad electrode PD.

<Method for Manufacturing Semiconductor Device>
In addition to FIGS. 1 to 4 described above, a method for manufacturing the semiconductor device of the present embodiment will be described with reference to FIGS. FIG. 7 is a cross-sectional view of the wafer test apparatus used in the wafer test process of the present embodiment. FIG. 8 is a plan view of the semiconductor wafer in the wafer test process of the present embodiment. FIG. 9 is a cross-sectional view of a semiconductor wafer for explaining the wafer test process of the present embodiment. FIG. 10 is a plan view of the pad electrode for explaining the wafer test process of the present embodiment. FIG. 11 is a plan view of the pad electrode of the present embodiment. FIG. 12 is a cross-sectional view of a principal part taken along line X2-X2 in FIG. FIG. 13 is a perspective view for explaining the dicing process of the present embodiment. FIG. 14 is a cross-sectional view for explaining the die bonding step of the present embodiment. FIG. 15 is a cross-sectional view for explaining the wire bonding step of the present embodiment. FIG. 16 is a cross-sectional view for explaining the resin sealing step of the present embodiment. FIG. 17 is a cross-sectional view of the semiconductor device of this embodiment.

  First, the wafer preparation step (S1) shown in FIG. 1 is performed. A semiconductor wafer WF shown in FIG. 8 is prepared. A plurality of semiconductor chips C11 to C73 are arranged in a matrix on the semiconductor wafer WF. The configuration of each of the plurality of semiconductor chips C11 to C73 is as described in FIG.

  Next, the wafer test process (S2) shown in FIG. 1 is performed. First, an example of a wafer test apparatus will be described with reference to FIG. The prober 6 includes a prober base 7, an XYZ drive table 8, a wafer suction table 9, a probe card 11 to which probe needles PB are attached, and a test head 14. On the XYZ drive table 8 on the prober base 7, a wafer suction table 9 is installed. A semiconductor wafer WF is mounted on the wafer suction table 9. The wafer suction table 9 has a heating mechanism and a suction mechanism. In the wafer test step (S2), the semiconductor wafer WF is vacuum-sucked to the wafer suction table 9 and set to a desired temperature by the heating mechanism. Has been. A probe card support portion 12 is provided on a support column 10 provided on the prober base 7, and the probe card support portion 12 holds a probe card 11 having a large number of probe needles PB. A test head 14 is provided above the probe card 11, and the probe card 11 and the test head 14 are electrically and mechanically connected by a pogo pin 13. That is, the probe needle PB and the test head 14 are electrically connected. The test head 14 can transmit and receive electrical signals to and from the tester 5.

  Further, as the XYZ drive table 8 is raised in the Z direction, the probe needle PB is brought into contact with the semiconductor wafer WF. As described with reference to FIG. 3, the probe needle PB is brought into contact with the pad electrode PD from a direction perpendicular to the main surface PDa of the pad electrode PD.

  As shown in FIG. 8, a plurality of semiconductor chips C11 to C73 are arranged in a matrix on the semiconductor wafer WF. Since the plurality of semiconductor chips C11 to C73 are not divided individually, each of the semiconductor chips C11 to C73 may be referred to as a chip formation region in the state of the semiconductor wafer WF. In the wafer test step (S2), four adjacent semiconductor chips are tested at a time in order to shorten the test time. Note that the number of semiconductor chips to be tested simultaneously is not limited to four. Each of the inspection target areas CA1 to CA4 indicates a semiconductor chip to be tested at the same time. As shown in FIG. 8, for example, the inspection target areas CA1, CA2, CA3, and CA4 are sequentially applied to the semiconductor wafer WF. The semiconductor chip is tested while relatively moving the probe needle PB (or the probe card 11) shown in FIG. The inspection target area CA1 includes semiconductor chips C31, C32, C41 and C42, the inspection target area CA2 includes semiconductor chips C33, C34, C43 and C44, and the inspection target area CA3 includes a semiconductor chip C35. , C36, C45, and C46, and the inspection target area CA4 includes semiconductor chips C36, C37, C46, and C47.

  Here, the reason why the semiconductor chips C36 and C46 are redundantly included in the inspection target areas CA3 and CA4 will be described. As shown in FIG. 9, the semiconductor wafer WF includes a chip formation area CFA in which a plurality of semiconductor chips C31 to C37 are formed, and a peripheral area PA surrounding the chip formation area CFA. When a cross section of the semiconductor wafer WF is viewed macroscopically, a portion of the semiconductor wafer WF corresponding to the chip formation region CFA has a flat main surface (front surface) WFa. On the other hand, the main surface (front surface) of the portion corresponding to the peripheral area PA in the semiconductor wafer WF is inclined by the angle θ with respect to the main surface (front surface) WFa of the portion corresponding to the chip formation area CFA. That is, the portion of the semiconductor wafer WF corresponding to the peripheral area PA has the inclined portion WFb. That is, the thickness of the semiconductor wafer WF is thinner in the peripheral area PA than in the chip formation area CFA, and in the peripheral area PA is thinner at the end WFt than the chip formation area CFA side. In other words, in a cross-sectional view, the thickness of the portion corresponding to the peripheral region PA in the semiconductor wafer WF is thinner than the thickness of the portion corresponding to the plurality of chip formation regions CFA in the semiconductor wafer WF.

  Here, since the semiconductor chip C36 has been tested in the inspection target area CA3, the semiconductor chip C37 and the peripheral area PA of the semiconductor wafer WF are contacted in the inspection target area CA4 without bringing the probe needle PB into contact with the semiconductor chip C36. Consider the case of contact. When the probe needle PB is brought into contact with the inclined portion WFb of the peripheral area PA, the probe needle PB is bent, and the probe needle PB needs to be repaired before the next test, which increases manufacturing time and manufacturing cost. There was found. In the present embodiment, in order to omit the repair work, as described above, the probe needle PB is again brought into contact with the semiconductor chips C36 and C46 in the inspection target area CA4.

  As shown in FIG. 10, two probe marks PM (CA3) and PM (CA4) are formed on the pad electrode PD of the semiconductor chip C36 by performing the test on the inspection target areas CA3 and CA4. Here, it is important that the two probe marks PM (CA3) and PM (CA4) are separated from each other without overlapping. It is important that at least the concave portion CC of the probe mark PM (CA3) and the concave portion CC of the probe mark PM (CA4) are separated from each other without overlapping. In addition, in FIG. 10, the ball | bowl part Wb and the junction part Wc of the wire W are shown for reference. Two probe marks PM (CA3) and PM (CA4) are formed inside the joint Wc.

  Similar to the test method for the semiconductor chips C31 to C37 and C41 to C47 included in the inspection target areas CA1 to CA4, the tests for the other semiconductor chips C11 to C13, C21 to C25, C51 to C57, C61 to C65, and C71 to C73 Also implement. Although not shown, it can be easily estimated that a plurality of probe marks PM are formed on the pad electrode PD in a plurality of semiconductor chips, similarly to the semiconductor chips C36 and C46 described above.

  That is, by performing one wafer test process (S2), a plurality of probe marks PM are formed on the pad electrode PD in a large number of semiconductor chips. As shown in FIG. 1, in the semiconductor device of the present embodiment, a wide variety of tests are performed by repeating the wafer test step (S2) a plurality of times. Therefore, a large number (for example, 10 or more) of probe marks PM are formed on the pad electrode PD of the semiconductor chip.

  FIG. 11 shows an example in which twelve probe marks PM are arranged inside the joint Wc. As shown in FIG. 11, adjacent probe marks PM are evenly arranged with a separation distance a. The concave portions CC of adjacent probe marks PM are also separated from each other. In order to arrange a large number of probe marks PM inside the joint Wc, it is necessary to make the separation distance a as small as possible. The separation distance a ≦ the diameter of the probe mark PM (2 × r2), or the separation distance a ≦ This is the radius (r2) of the probe mark PM. That is, according to the present embodiment, the distance a between adjacent probe marks PM is equal to or less than the diameter (2 × r2) of the probe marks PM or the radius (r2) of the probe marks PM in the joint portion Wc. The arrangement of the probe mark PM.

  Further, when the diameter of the joint portion Wc of the wire W is 42.5 μm and the diameter of the probe mark PM is 9 μm, the occupation ratio OC of the probe mark PM in the joint portion Wc (= the probe mark PM located in the joint portion Wc) The total area / the area of the junction Wc) is approximately 53%. The present embodiment relates to the arrangement of the probe marks PM when the occupation ratio OC of the probe marks PM in the joint portion Wc exceeds 50%.

  In other words, the present embodiment relates to the arrangement of the probe marks PM when a large number (for example, 10 or more) of the probe marks PM is arranged inside the joint portion Wc, and the occupation ratio OC of the probe marks PM. In the case of ≦ 50%, or when the separation distance a of the adjacent probe marks PM> the diameter of the probe marks PM (2 × r2), it is out of the scope of the present embodiment. This is because the above-described problem does not occur when the occupation ratio OC of the probe mark PM is small and the adjacent probe marks PM are arranged sufficiently apart from each other.

FIG. 12 is a cross-sectional view of a main part taken along line X2-X2 in FIG. FIG. 12 also shows the state of the pad electrode PD that has been subjected to the high-temperature storage test after the wire bonding step (S5) and the resin sealing step (S6), as in FIG. As shown in FIG. 11, when arranging a large number of probe marks PM inside the joint Wc, the concave portions CC of two adjacent probe marks PM are arranged so as to be separated from each other. The copper-rich alloy layer Cu ₉ Al ₄ is dispersed and formed in the pad electrode PD. This is because the formation position of the alloy layer Cu ₉ Al ₄ corresponds to the concave portion CC of the probe mark PM. Since adjacent probe marks PM (exactly, the recesses CC) are separated from each other, the wide and thick alloy layer Cu ₉ Al ₄ is formed, unlike the case where the probe marks PM are overlapped. Can be prevented. Therefore, the defect that the ball portion Wb of the wire W is peeled off from the pad electrode PD can be prevented.

  Next, the wafer dicing step (S3) shown in FIG. 1 is performed. As shown in FIG. 13, the semiconductor wafer WF is divided into a plurality of semiconductor chips C using a dicing blade DB.

  Next, the die bonding step (S4) shown in FIG. 1 is performed. As shown in FIG. 14, the separated semiconductor chip C is bonded onto the die pad 16 of the lead frame LF via an adhesive layer 17. In this die bonding step (S4), for example, a thermal load of about 175 ° C. for about 1 hour is applied to the pad electrode PD. Note that the lead frame LF of the present embodiment is made of a material mainly composed of copper, for example. Further, the base material on which the semiconductor chip C is mounted is not limited to the lead frame, but may be a wiring board (printed wiring board).

  Next, the wire bonding step (S5) shown in FIG. 1 is performed. As shown in FIG. 15, the pad electrode PD formed on the main surface of the semiconductor chip C is electrically connected to the lead 15 via the wire W. Specifically, a part of the wire W is connected to the plating layer 15 b formed on the surface of the lead 15. The wire W of the present embodiment is, for example, a wire containing copper (Cu) as a main component, and the wire W is formed using a ball bonding (also referred to as nail head bonding) method using both thermocompression bonding and ultrasonic vibration. Is connected to the pad electrode PD. That is, as shown in FIG. 12, the wire W has a ball portion Wb at its tip, and a bonding portion Wc including an alloy layer is formed at the interface between the ball portion Wb and the pad electrode PD, whereby the pad electrode Connected to PD. Here, as shown in FIG. 11, the bonding portion Wc is formed so as to cover the entire number of probe marks PM formed on the pad electrode PD. In the wire bonding step (S5), for example, a thermal load of about 2 to 5 minutes is applied to the pad electrode PD at 240 ° C.

  Next, the resin sealing step (S6) shown in FIG. 1 is performed. As shown in FIG. 16, the semiconductor chip C and the lead frame LF are installed in the cavity 19c formed on the mating surface of the upper mold 19a and the lower mold 19b of the mold 19, and the sealing resin ( Resin) 20 is filled to form a sealing body 18 shown in FIG. Here, the sealing resin 20 is made of, for example, an epoxy resin containing sulfur (S). Therefore, although the adhesion between the lead frame LF made of copper and the sealing resin 20 can be improved, the alloy layer CuAl formed at the joint between the wire W and the pad electrode PD may be damaged. However, in the present embodiment, as described above, the wafer test process is performed so that the concave portions CC of the two adjacent probe marks PM do not overlap each other. Therefore, since the bonding strength of the wire W to the pad electrode PD is improved as compared with the case where the wafer test process shown in the examination example is performed, even if damage is applied to the alloy layer CuAl, the wire from the pad electrode PD to the wire is improved. It is possible to suppress a defect that the ball portion Wb of W is peeled off. An epoxy resin that does not contain sulfur (S) can also be used as the sealing resin 20. In the resin sealing step (S6), for example, a thermal load of about 180 ° C. is applied to the pad electrode PD.

  Next, the configuration of the semiconductor device SD formed through the process flow shown in FIG. 1 will be described. FIG. 17 is a cross-sectional view of a QFP (Quad Flat Package) type semiconductor device, for example.

  In FIG. 17, a two-dot chain line represents a mounting surface of a mounting substrate on which the semiconductor device SD is mounted. The semiconductor device SD includes a semiconductor chip C, a plurality of wires W, a plurality of leads 15 and a sealing body 18.

  The semiconductor chip C is composed of, for example, a semiconductor substrate made of silicon (Si), and includes a plurality of semiconductor elements, a plurality of wirings, and a plurality of pad electrodes PD (terminals, external electrodes, external lead electrodes, electrode pads).

  The plurality of semiconductor elements are connected by a plurality of wirings to form circuit blocks such as the CPU 1, the RAM 2, the analog circuit 3, and the flash memory 4, and the circuit blocks are electrically connected to the pad electrode PD through the wirings. It is connected. The pad electrode PD is electrically connected to the lead 15 via the wire W. The pad electrode PD is connected to, for example, a lead 15 mainly composed of copper (Cu) by a wire (bonding wire) W mainly composed of copper (Cu). Specifically, a plating layer 15b made of a silver (Ag) plating layer is formed in a portion (area) to which the wire W is connected on the surface of the lead 15, and the plating layer 15b is used to form a plating layer 15b. The wire W is electrically connected to the lead 15. As shown in FIG. 6, the wire W has a ball portion Wb and is connected to the pad electrode PD at a joint portion Wc that is a part of the ball portion Wb.

  Here, the lead or wire mainly composed of copper (Cu) includes a copper alloy containing a trace amount of metal additive (1% or less). Here, examples of the metal additive include aluminum (Al), magnesium (Mg), titanium (Ti), manganese (Mn), iron (Fe), zinc (Zn), zirconium (Zr), and niobium (Nb). , Molybdenum (Mo), ruthenium (Ru), palladium (Pd), silver (Ag), gold (Au), In (indium), nickel (Ni), platinum (Pt), lanthanoid metal, actinoid metal, etc. Or several types of metals are mentioned. In addition, the wire to be used may be, for example, a surface of a wire made of copper (Cu) covered with a metal (for example, palladium) different from copper.

  For example, the sealing body 18 made of an epoxy resin covers the semiconductor chip C, the wires W, the plurality of leads 15, the die pad (chip mounting portion) 16, and the adhesive layer 17. The semiconductor chip C is bonded to the die pad 16 with an adhesive layer 17.

  The plurality of leads 15 includes an inner lead portion IL positioned inside the sealing body 18 and an outer lead portion OL connected to the inner lead portion 1L and positioned outside the sealing body 18. Although not shown in FIG. 17, the inner lead portions IL of the plurality of leads 15 are arranged around the semiconductor chip C and extend from the side surface of the sealing body 18 toward the semiconductor chip C. Further, the main surface and the back surface of the outer lead portion OL are covered with a plating layer 15a made of a solder material.

  Further, the outer lead portion OL has a gull wing shape, and is continuously extended from the inner lead portion IL and linearly protrudes outside the sealing body 18 and bends extending from the protruding portion toward the mounting surface. And a connecting portion that extends from the bent portion substantially parallel to the mounting surface and is connected to the mounting substrate via mounting solder.

  The present embodiment has the following features.

  The semiconductor device manufacturing method of the present embodiment includes a step of performing a plurality of wafer tests on the semiconductor wafer WF to form a plurality of probe marks PM on each of the plurality of pad electrodes PD, and a plurality of probes. Connecting the ball portion Wb of the wire W to the pad electrode PD so as to cover the mark PM with the ball portion Wb of the wire W. Each of the plurality of probe marks PM includes a convex portion CV protruding from the main surface PDa of the pad electrode PD and a concave portion CC recessed from the main surface PDa in a cross-sectional view. In the joint portion Wc between the portion Wb and the pad electrode PD, the concave portions CC of the plurality of probe marks PM are separated from each other.

In the joint portion Wc between the ball portion Wb of the wire W and the pad electrode PD, the recesses CC of the plurality of probe marks PM are separated from each other, whereby the pad electrode PD becomes high temperature after the wire bonding step (S5). The copper (Cu) -rich alloy layer Cu ₉ Al ₄ that grows in the above can be dispersed. That is, the alloy layer Cu ₉ Al ₄ can be prevented from being formed thick in a wide range. And the defect that the ball | bowl part Wb of the wire W peels from the pad electrode PD can be prevented. This is because the alloy layer Cu ₉ Al ₄ is formed at a position corresponding to the probe mark PM.

  In addition, the ball portion Wb of the wire W is connected to the region where the probe mark PM is formed without independently providing the contact region of the probe needle PB and the connection region of the wire W to the pad electrode PD. As a result, the pad electrode PD and the semiconductor chip C can be reduced in size.

  In a plan view, two adjacent probe marks PM can be arranged with a separation distance equal to or less than the diameter of the probe mark PM in the bonding part Wc between the ball Wb of the wire W and the pad electrode PD. A large number of probe marks PM can be arranged in Wc. Accordingly, various and various wafer tests can be performed, and a highly functional semiconductor device can be manufactured.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the above embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say. A plurality of modified examples are shown below, but it is also possible to implement a combination of each modified example as appropriate.

<Modification 1>
Modification 1 is a modification of FIG. 10 of the above embodiment. In FIG. 10, the adjacent probe marks PM are separated from each other, and the convex portions CV and the concave portions CC of the adjacent probe marks PM are also separated from each other. In the modification 1, as shown in FIG. 18, the convex parts CV of the adjacent probe marks PM are in contact with each other. That is, it is only necessary that the concave portions of the adjacent probe marks PM are separated from each other, and the convex portions CV of the adjacent probe marks PM may be brought into contact with each other. Similarly, the probe mark PM shown in FIG. 11 of the above embodiment can be arranged in the same manner as in the first modification.

<Modification 2>
Modification 2 is a modification of FIG. 10 of the above embodiment. In the second modification, as shown in FIG. 19, the convex portions CV of the adjacent probe marks PM partially overlap each other, and the concave portions CC of the adjacent probe marks PM are separated from each other. That is, it is only necessary that the concave portions CC of the adjacent probe marks PM are separated from each other, and the convex portions CV of the adjacent probe marks PM may be overlapped. Similarly, the probe mark PM shown in FIG. 11 of the above embodiment can be arranged in the same manner as in the second modification.

<Modification 3>
Modification 3 is a modification to FIG. 11 of the above embodiment. In FIG. 11, all the probe marks PM formed on the pad electrode PD are located inside the bonding portion Wc between the wire W and the pad electrode PD in plan view. In Modification 3, as shown in FIG. 20, all the probe marks PM are not necessarily located inside the joint portion Wc. That is, the probe mark PM located inside the joint part Wc and the probe mark PM straddling the inside and outside of the joint part Wc are mixed.

  In the above embodiment, the arrangement of a large number of probe marks PM located at the joint Wc is important. That is, it is important to separate the recesses CC of the adjacent probe marks PM among the many probe marks PM located at the joint Wc. Therefore, if this condition is satisfied, the probe mark PM can be arranged so as to straddle the inside and the outside of the joint portion Wc.

  In the third modification, the number of probe marks PM overlapping with the joint portion Wc can be increased. Further, the separation distance b between adjacent probe marks PM can be made larger than the separation distance a in the above embodiment.

<Modification 4>
Modification 4 is a further modification of Modification 3. In the modification 4, as shown in FIG. 21, the probe mark PM in which the whole is located is provided in the exterior (outside) of the junction part Wc. As shown in FIG. 21, when the entirety is located outside the joint Wc, the concave portions CC of the adjacent probe marks PM can be arranged to overlap each other. This is because the alloy layer Cu ₉ AL ₄ is not formed in the concave portion CC when the entirety is located outside the joint portion Wc.

  In the fourth modification, the number of probe marks PM can be further increased compared to the third modification.

AR1 region C, C11, C12 ··· C73 semiconductor chip CA1, CA2, CA3, CA4 inspection area CC recess CFA chip formation region _{CuAl, CuAl 2, Cu 9 AL} 4 alloy layer CV protrusion DB dicing blade IF1, IF2 insulating Membrane IL Inner lead LF Lead frame OL Outer lead OP Opening PA Peripheral area PB Probe needle PBt Tip PD pad electrode (bonding pad, external connection terminal)
PDa main surface PDc center PM probe mark PMc center PS peeling stress SB semiconductor substrate SBa main surface SBb back surface SD semiconductor device W wire (bonding wire)
Wb Ball part Wc Joint part (connection part)
WF Semiconductor wafer WFa Main surface WFb Inclined part WFt End part 1 CPU (circuit)
2 RAM (circuit)
3 Analog circuit 4 Flash memory (memory circuit)
5 Tester 6 Prober 7 Prober Substrate 8 XYZ Drive Table 9 Wafer Suction Table 10 Prop 11 Probe Card 12 Probe Card Support Part 13 Pogo Pin 14 Test Head 15 Lead 15a Plating Layer 15b Plating Layer 16 Die Pad (Chip Mounting Part)
17 Adhesive layer 18 Sealing body 19 Mold 19a Upper mold 19b Lower mold 19c Cavity 20 Sealing resin

Claims (17)

A semiconductor device manufacturing method including the following steps:
(A) preparing a semiconductor wafer on which a plurality of semiconductor chips having a plurality of pad electrodes are arranged;
(B) A wafer test for confirming the operation of each of the plurality of semiconductor chips by pressing a probe needle against each main surface of the plurality of pad electrodes and performing a plurality of times on the semiconductor wafer, Forming a plurality of probe marks on each of the plurality of pad electrodes;
(C) After the step (b), the semiconductor wafer is subjected to a dicing process to obtain the plurality of divided semiconductor chips;
(D) After the step (c), the ball of the wire is placed on each of the plurality of pad electrodes so that the plurality of probe marks formed on each of the plurality of pad electrodes are covered with a ball portion of the wire. Connecting the parts;
here,
In the step (b), each of the plurality of probe marks has a convex portion protruding from the main surface of the pad electrode and a concave portion recessed from the main surface in a cross-sectional view,
Of the main surfaces of each of the plurality of pad electrodes, in the first region where the ball portion of the wire contacts, two adjacent probe traces have a separation distance equal to or smaller than the diameter of the probe trace in plan view. And
In the first region, the concave portions of the plurality of probe marks are separated from each other. In the manufacturing method of the semiconductor device according to claim 1,
The said separation distance is below the radius of the said probe trace in planar view. In the manufacturing method of the semiconductor device according to claim 1,
The wire is made of a material mainly composed of copper. In the manufacturing method of the semiconductor device according to claim 3,
Each of the plurality of pad electrodes is made of a material mainly composed of aluminum. In the manufacturing method of the semiconductor device according to claim 1,
In the first region, the plurality of probe marks are arranged at equal intervals. In the manufacturing method of the semiconductor device according to claim 1,
further,
(E) The acquired semiconductor chip among the plurality of semiconductor chips is placed on the chip mounting portion of the base material having a chip mounting portion and a lead portion between the step (c) and the step (d). Mounting process;
(F) After the step (d), a step of sealing the obtained semiconductor chip, the wire, and a part of the base material with a resin containing sulfur;
Have
here,
In the step (d), after the wire is connected to the pad electrode, the wire is connected to the lead portion through a silver plating layer. A semiconductor device manufacturing method including the following steps:
(A) preparing a semiconductor wafer on which a plurality of semiconductor chips having a plurality of pad electrodes are arranged;
(B) A wafer test for confirming the operation of each of the plurality of semiconductor chips is performed a plurality of times on the semiconductor wafer by pressing a probe needle against each main surface of the plurality of pad electrodes. Forming a plurality of probe marks on each of the plurality of pad electrodes;
(C) After the step (b), the semiconductor wafer is subjected to a dicing process to obtain the plurality of divided semiconductor chips;
(D) After the step (c), the plurality of probe traces formed on each of the plurality of pad electrodes are covered with the ball portions of the wires so that the plurality of pad electrodes are covered with the wires. Connecting the ball portions;
here,
In the step (b), each of the plurality of probe marks has a convex portion protruding from the main surface of the pad electrode and a concave portion recessed from the main surface in a cross-sectional view,
The main surface of each of the plurality of pad electrodes has a first region in contact with the ball portion of the wire, and a second region adjacent to the first region and surrounding the first region,
The plurality of probe marks are a plurality of first probe marks arranged inside the first region, a plurality of second probe marks arranged to straddle the first region and the second region, Including
The recesses of each of the plurality of first probe marks and the plurality of second probe marks are separated from each other. The method of manufacturing a semiconductor device according to claim 7.
The wire is made of a material mainly composed of copper. The method of manufacturing a semiconductor device according to claim 8.
Each of the plurality of pad electrodes is made of a material mainly composed of aluminum. The method of manufacturing a semiconductor device according to claim 7.
further,
A plurality of third probe marks disposed in the second region;
The recesses of the plurality of third probe traces overlap each other. A semiconductor device manufacturing method including the following steps:
(A) preparing a semiconductor wafer having a plurality of chip formation regions;
here,
Each of the plurality of chip formation regions includes a first circuit and a second circuit different from the first circuit,
Each of the plurality of chip formation regions has a pad electrode,
The pad electrode is made of a material mainly composed of aluminum;
(B) After the step (a), under a first condition, a probe needle of a probe card is brought into contact with a main surface of the pad electrode provided in each of the plurality of chip formation regions, and the semiconductor wafer is Inspection process,
Here, the step of inspecting the semiconductor wafer under the first condition includes:
(B1) A step of inspecting a first inspection target region having a first chip formation region and a second chip formation region among the plurality of chip formation regions using the probe card;
(B2) After the step (b1), of the plurality of chip formation regions, a second chip that has a third chip formation region and a fourth chip formation region and is located next to the first inspection target region. A step of inspecting a region to be inspected using the probe card;
(B3) After the step (b2), of the plurality of chip formation regions, a fifth chip formation region different from the chip formation regions provided in the first inspection target region and the second inspection target region, respectively. And a step of inspecting a third inspection target region having the fourth chip formation region provided in the second inspection target region using the probe card,
Including:
(C) After the step (b), a step of mounting the first semiconductor chip corresponding to the fourth chip formation region obtained by cutting the semiconductor wafer on a substrate;
here,
The first semiconductor chip has a first pad electrode corresponding to the pad electrode,
A plurality of probe marks are formed on the main surface of the first pad electrode,
(D) After the step (c), the ball portion of the wire is moved to the first pad so that the plurality of probe marks formed on the main surface of the first pad electrode are covered with the ball portion of the wire. Connecting to the pad electrode;
here,
The wire is made of a copper-based material;
(E) a step of sealing the wire and the first semiconductor chip with a resin after the step (d);
here,
Of the main surface of the first pad electrode, the occupation ratio of the plurality of probe traces in the first region where the ball portion of the wire contacts is greater than 50%,
In the step (c), the plurality of probe marks arranged in the first region are recessed from the main surface and a convex portion protruding from the main surface of the first pad electrode in a cross-sectional view. A recess,
In the step (b3), the concave portion of the probe trace formed by the step (b3) of the plurality of probe traces is the same as that of the probe trace formed by the step (b2) of the plurality of probe traces. The probe needle is brought into contact with the main surface of the first pad electrode so as to be separated from the recess. The method of manufacturing a semiconductor device according to claim 11.
further,
(F) The pads provided in each of the plurality of chip formation regions under a second condition different from the first condition after the step (b) and before the step (c). Contacting the probe needle of the probe card with the main surface of the electrode and inspecting the semiconductor wafer;
Have In the manufacturing method of the semiconductor device according to claim 12,
The first circuit is a logic circuit;
The second circuit is a memory circuit;
In the step (b), the logic circuit is inspected,
In the step (f), the memory circuit is inspected. The method of manufacturing a semiconductor device according to claim 11.
The resin contains sulfur. The method of manufacturing a semiconductor device according to claim 11.
The semiconductor wafer has the plurality of chip formation regions, and a peripheral region located around the plurality of chip formation regions,
In a cross-sectional view, the thickness of the portion of the semiconductor wafer corresponding to the peripheral region is thinner than the thickness of the portion of the semiconductor wafer corresponding to the plurality of chip formation regions. The method of manufacturing a semiconductor device according to claim 11.
The semiconductor wafer has the plurality of chip formation regions, and a peripheral region located around the plurality of chip formation regions,
In a cross-sectional view, the surface of the portion of the semiconductor wafer corresponding to the peripheral region is inclined with respect to the surface of the portion of the semiconductor wafer corresponding to the plurality of chip formation regions. The method of manufacturing a semiconductor device according to claim 11.
Of the plurality of probe marks, the probe mark formed by the step (b2) and the plurality of probe marks formed by the step (b3) and the step (b2). The distance from the probe mark located next to the probe mark is a distance equal to or less than the diameter of each of the plurality of probe marks.

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