JP2019057589A - diode - Google Patents

Abstract

To provide a technique to alleviate electric field concentration between a two-dimensional hole gas layer of a semiconductor laminate and an n-type semiconductor region, in a diode having a hetero junction type super junction structure.SOLUTION: A diode 1 with a hetero junction type super junction structure is provided. A two-dimensional hole gas layer (2DHG) and an n-type semiconductor region 104 are configured not to directly contact with each other due to a first insulative region 202.SELECTED DRAWING: Figure 1

Description

  The technology disclosed herein relates to a diode having a heterojunction super junction structure.

  Non-Patent Document 1 and Non-Patent Document 2 disclose a diode having a heterojunction super junction structure. The diode includes a cathode electrode, an anode electrode, and a semiconductor laminate provided between the cathode electrode and the anode electrode. The semiconductor laminate has a first hetero junction having a two-dimensional electron gas layer near the junction surface and a second hetero junction having a two-dimensional hole gas layer near the junction surface, and the first hetero junction and the second hetero junction A heterojunction extends along the direction connecting the cathode electrode and the anode electrode. The two-dimensional electron gas layer and the two-dimensional hole gas layer may be generated by a carrier supply layer using an impurity doping technique such as, for example, spontaneous polarization, piezo polarization and / or δ doping.

  When this diode is reverse biased, the two-dimensional electron gas layer and the two-dimensional hole gas layer are depleted. The two-dimensional electron gas layer and the two-dimensional hole gas layer face each other in a direction perpendicular to the stacking direction of the semiconductor stack, that is, the direction connecting the cathode electrode and the anode electrode. Therefore, when the two-dimensional electron gas layer and the two-dimensional hole gas layer are depleted, an electric field is generated in the direction orthogonal to the direction connecting the cathode electrode and the anode electrode. The heterojunction-type super junction structure in which such an electric field is generated can make the field intensity between the anode electrode and the cathode electrode uniform, as in the conventional super junction structure using a pn junction. Thus, a diode having a heterojunction super junction structure can have a high breakdown voltage.

Bo Song, Mingda Zhu, Zongyang Hu, Erhard Kohn, Debdeep Jena and Huil (Grace) Xing, GaN lateral Polar SJs: Polarization-doped super junctions, IEEE 72nd 2014 Tomoyoshi Kushida, Masato Ohmori, Shota Osanai, Daisuke Kawamoto, Takeshi Noda and Hiroyuki Sakaki, Electrical characteristics of AlGaAs / GaAs heterostructures with a pair of 2-D electron and hole channels, IEEE TRANSACTIONS ON ELECTRON DEVICE S, VOL. 11, NO. , NOVEMBER 2015

  The diode having the heterojunction super junction structure includes an n-type semiconductor region provided between the cathode electrode and the semiconductor stack. The two-dimensional electron gas layer of the semiconductor laminate is in ohmic contact with the cathode electrode through the n-type semiconductor region.

  On the other hand, the two-dimensional hole gas layer of the semiconductor laminate constitutes a pn junction with the n-type semiconductor region. Therefore, the electric field concentration at the pn junction of the two-dimensional hole gas layer of the semiconductor laminate and the n-type semiconductor region becomes a problem.

  The present specification discloses a technique for relaxing electric field concentration between a two-dimensional hole gas layer and an n-type semiconductor region of a semiconductor stack in a diode having a heterojunction super junction structure.

  One embodiment of the diode disclosed herein is a semiconductor laminate provided between a cathode electrode, an anode electrode, the cathode electrode and the anode electrode, and generates a two-dimensional electron gas layer. A first heterojunction and a second heterojunction for generating a two-dimensional hole gas layer, wherein the first heterojunction and the second heterojunction extend along a direction connecting between the cathode electrode and the anode electrode. And an n-type semiconductor region provided between the cathode electrode and the semiconductor laminate, and a first insulating region. The two-dimensional electron gas layer and the n-type semiconductor region are configured to be in direct contact with each other. The two-dimensional hole gas layer and the n-type semiconductor region are configured not to be in direct contact with each other by the first insulating region.

  In the diode according to this embodiment, the two-dimensional hole gas layer and the n-type semiconductor region are not in direct contact with each other by providing the first insulating region. Thereby, the electric field concentration between the two-dimensional hole gas layer and the n-type semiconductor region is relaxed.

The principal part sectional view of the diode of a 1st embodiment is shown typically. The principal part sectional view of the diode of a 2nd embodiment is shown typically. The principal part sectional view of the diode of a 3rd embodiment is shown typically. The principal part sectional view of the diode of a 4th embodiment is shown typically. The principal part sectional view of the diode of a 5th embodiment is shown typically. The principal part sectional view of the diode of a 6th embodiment is shown typically. The principal part sectional view of the diode of a 7th embodiment is shown typically. The principal part sectional drawing of the diode of 8th Embodiment is shown typically. The principal part sectional view of the modification of the diode of a 1st embodiment is shown typically.

First Embodiment
As shown in FIG. 1, the diode 1 includes a cathode electrode 102, an anode electrode 108, and a semiconductor laminate 10 provided between the cathode electrode 102 and the anode electrode 108.

  The semiconductor laminate 10 includes a semi-insulating GaAs substrate 11, a buffer layer 12 of i-GaAs, a barrier layer 13 of i-AlGaAs, a hole supply layer 14 of p-InGaP, a channel layer 15 of i-GaAs, n An electron supply layer 16 of InGaP and a barrier layer 17 of i-AlGaAs; The buffer layer 12, the barrier layer 13, the hole supply layer 14, the channel layer 15, the electron supply layer 16, and the barrier layer 17 are made of the substrate 11 using metal organic chemical vapor deposition (MOCVD). It is formed by growing in this order from the surface of. On the surface of the semiconductor laminate 10, a protective film of silicon oxide is formed using a chemical vapor deposition (CVD) method.

  The diode 1 further includes an n-type semiconductor region 104 provided between the cathode electrode 102 and the semiconductor stack 10, and a p-type semiconductor region 106 provided between the anode electrode 108 and the semiconductor stack 10. ing. The n-type semiconductor region 104 is provided to cover most of the side surface and the bottom surface of the cathode electrode 102, and is in contact with both the cathode electrode 102 and the semiconductor stack 10. The n-type semiconductor region 104 is formed by introducing a n-type impurity into the side and bottom surfaces of the trench after forming the trench for forming the cathode electrode 102 using oblique ion implantation technology. The p-type semiconductor region 106 is provided to cover most of the side surface and the bottom surface of the anode electrode 108 and is in contact with both the anode electrode 108 and the semiconductor stack 10. The p-type semiconductor region 106 is formed by introducing a p-type impurity into the side surface and the bottom surface of the trench after forming the trench for forming the anode electrode 108 using oblique ion implantation technology.

  The diode 1 further includes a cathode side insulating region 202 and an anode side insulating region 204. The insulating regions 202 and 204 are formed as air gaps. In addition, as long as the cathode side insulating region 202 is configured so as not to directly contact the two-dimensional hole gas layer (2DHG) and the n-type semiconductor region 104, other alternative means may be adopted. For example, an insulator, a semi-insulator, or a high resistance semiconductor of a material that does not generate a two-dimensional hole gas layer (2DHG) in a region corresponding to the cathode-side insulating region 202 may be formed. Alternatively, an air gap, an insulator, a semi-insulator, or a high resistance semiconductor may be formed at a position where the two-dimensional hole gas layer (2DHG) and the n-type semiconductor region 104 are interposed. Similarly, as long as the anode-side insulating region 204 is configured not to be in direct contact with the two-dimensional electron gas layer (2DEG) and the p-type semiconductor region 106, other alternative means may be adopted. For example, an insulator, a semi-insulator, or a high resistance semiconductor of a material that does not generate a two-dimensional electron gas layer (2DEG) in a region corresponding to the anode-side insulating region 204 may be formed. Alternatively, an air gap, an insulator, a semi-insulator, or a high resistance semiconductor may be formed at a position where the two-dimensional electron gas layer (2DEG) and the p-type semiconductor region 106 are interposed.

  The cathode side insulating region 202 and the anode side insulating region 204 can be formed through the following steps. First, as part of a trench for forming the cathode electrode 102 and the anode electrode 108, a trench is formed to penetrate the barrier layer 17 from the surface of the semiconductor laminate 10 to reach the electron supply layer 16 using sulfuric acid etching. Do. Next, after filling the trench for the cathode electrode 102 with a protective film, the electron supply layer 16 is selectively etched using an etchant (for example, hydrochloric acid) having a faster etching rate of InGaP than GaAs and AlGaAs. Side insulating regions 204 are formed. The lateral width of the anode-side insulating region 204 is several μm. Next, after removing the protective film filling the trench for the cathode electrode 102, the trench is further deepened to penetrate the channel layer 15 to reach the hole supply layer 14 using sulfuric acid etching. Next, after the trench for the anode electrode 108 is filled with a protective film, the hole supply layer 14 is selectively etched using hydrochloric acid etching to form the cathode-side insulating region 202. The lateral width of the cathode side insulating region 202 is several μm. Thus, in the process for forming the cathode electrode 102 and the anode electrode 108, the cathode side insulating region 202 and the anode side insulating region 204 can be formed. The cathode electrode 102 and the anode electrode 108 can be further formed through the following steps. After removing the protective film filling the trench for the anode electrode 108, the trench is further deepened to penetrate the barrier layer 13 and the buffer layer 12 to reach the substrate 11 using sulfuric acid etching. Thereafter, as described above, after the n-type semiconductor region 104 and the p-type semiconductor region 106 are formed using oblique ion implantation technology, the cathode electrode 102 and the anode electrode are formed in the trench using sputtering or evaporation. Form 108.

  Next, the operation of the diode 1 will be described. When a voltage higher than that of the cathode electrode 102 is applied to the anode electrode 108, the diode 1 is in a forward bias state. At this time, holes are supplied from the hole supply layer 14 on the channel layer 15 side of the heterojunction surface of the hole supply layer 14 and the channel layer 15 to generate a two-dimensional hole gas layer (2DHG). . On the other hand, electrons are supplied from the electron supply layer 16 on the channel layer 15 side of the heterojunction surface of the channel layer 15 and the electron supply layer 16 to generate a two-dimensional electron gas layer (2DEG). Thereby, holes are injected from the p-type semiconductor region 106 into the channel layer 15 through the two-dimensional hole gas layer (2DHG), and from the n-type semiconductor region 104 through the two-dimensional electron gas layer (2DEG), the channel layer Electrons are injected into 15. The diode 1 has a PIN structure including a two-dimensional hole gas layer (2DHG), a channel layer 15 of i-GaAs, and a two-dimensional electron gas layer (2DEG), and can operate as a PIN diode. . The diode 1 can have low on-resistance because it can use a two-dimensional hole gas layer (2DHG) and a two-dimensional electron gas layer (2DEG) as a channel.

  When a voltage higher than the anode electrode 108 is applied to the cathode electrode 102, the diode 1 is in a reverse bias state. When the diode 1 is reverse biased, the two-dimensional electron gas layer (2DEG) and the two-dimensional hole gas layer (2DHG) are depleted. When the two-dimensional electron gas layer (2DEG) and the two-dimensional hole gas layer (2DHG) are depleted, positive fixed charges remain in the region where the two-dimensional electron gas layer (2DEG) is depleted, and two-dimensional holes A negative fixed charge remains in the region where the gas layer (2DHG) is depleted, and an electric field between these fixed charges is generated in a direction orthogonal to the direction connecting the cathode electrode 102 and the anode electrode 108. Thus, the diode 1 has a heterojunction-type super junction structure, and can make the electric field strength between the cathode electrode 102 and the anode electrode 108 uniform as in a normal super junction structure. Therefore, the diode 1 can have high withstand voltage characteristics.

  Furthermore, the diode 1 is provided with a cathode side insulating region 202. Since the cathode side insulating region 202 is provided, the two-dimensional hole gas layer (2DHG) is not formed in the channel layer 15 adjacent to the cathode side insulating region 202, and the two-dimensional hole gas layer (2DHG) The n-type semiconductor region 104 is configured not to be in direct contact with each other. For example, when the cathode side insulating region 202 is not provided, electric field concentration at the pn junction surface of the two-dimensional hole gas layer (2DHG) and the n-type semiconductor region 104 is concerned. On the other hand, in the diode 1, when the channel layer 15 of i-GaAs is interposed between the two-dimensional hole gas layer (2DHG) and the n-type semiconductor region 104, the electric field concentration in this portion is relaxed and the high withstand voltage characteristics Is realized.

  Furthermore, the diode 1 is provided with an anode side insulating region 204. Since the anode-side insulating region 204 is provided, the two-dimensional electron gas layer (2DEG) is not formed in the channel layer 15 adjacent to the anode-side insulating region 204, and the two-dimensional electron gas layer (2DEG) and the p-type The semiconductor region 106 is configured not to be in direct contact with each other. For example, when the anode-side insulating region 204 is not provided, electric field concentration at the pn junction of the two-dimensional electron gas layer (2DEG) and the p-type semiconductor region 106 is concerned. On the other hand, in the diode 1, the electric field concentration in this portion is relaxed by interposing the channel layer 15 of i-GaAs between the two-dimensional electron gas layer (2DEG) and the p-type semiconductor region 106, and high withstand voltage characteristics are obtained. To be realized.

  As described above, the diode 1 of the first embodiment can achieve both low on-resistance and high breakdown voltage.

Second Embodiment
The diode 2 of 2nd Embodiment is shown in FIG. In addition, about the component substantially the same as the diode 1 of 1st Embodiment, the same code | symbol may be attached | subjected and the description may be abbreviate | omitted.

  As shown in FIG. 2, the diode 2 includes a cathode electrode 102, an anode electrode 108, and a semiconductor laminate 20 provided between the cathode electrode 102 and the anode electrode 108.

  The semiconductor stack 20 includes a semi-insulating GaAs substrate 21, an i-GaAs buffer layer 22, an i-AlGaAs first barrier layer 23, an i-GaAs p-channel quantum well layer 24, and an i-InGaP positive A hole supply layer 25, a channel layer 26 of i-GaAs, an electron supply layer 27 of i-InGaP, an n-channel quantum well layer 28 of i-GaAs, and a second barrier layer 29 of i-AlGaAs are provided. In the hole supply layer 25, a p-type σ-doped layer containing a p-type impurity is formed at a position close to the p-channel quantum well layer 24. In the electron supply layer 27, an n-type σ-doped layer containing an n-type impurity is formed at a position close to the n-channel quantum well layer 28. The buffer layer 22, the first barrier layer 23, the p-channel quantum well layer 24, the hole supply layer 25, the channel layer 26, the electron supply layer 27, the n-channel quantum well layer 28 and the second barrier layer 29 It is grown and formed in this order from the surface of the substrate 21 using a vapor deposition method.

  The diode 2 further includes a cathode side insulating region 206 and an anode side insulating region 208. The insulating regions 206 and 208 are formed as air gaps. In addition, as long as the cathode side insulating region 206 is configured so as not to directly contact the two-dimensional hole gas layer (2DHG) and the n-type semiconductor region 104, other alternative means may be adopted. For example, an insulator, a semi-insulator, or a high-resistance semiconductor of a material that does not generate a two-dimensional hole gas layer (2DHG) in a region corresponding to the cathode-side insulating region 206 may be formed. Alternatively, an air gap, an insulator, a semi-insulator, or a high resistance semiconductor may be formed at a position where the two-dimensional hole gas layer (2DHG) and the n-type semiconductor region 104 are interposed. Similarly, as long as the anode-side insulating region 208 is configured so as not to directly contact the two-dimensional electron gas layer (2DEG) and the p-type semiconductor region 106, other alternative means may be adopted. For example, an insulator, a semi-insulator, or a high resistance semiconductor of a material that does not generate a two-dimensional electron gas layer (2DEG) in a region corresponding to the anode-side insulating region 208 may be formed. Alternatively, an air gap, an insulator, a semi-insulator, or a high resistance semiconductor may be formed at a position where the two-dimensional electron gas layer (2DEG) and the p-type semiconductor region 106 are interposed.

  The cathode side insulating region 206 and the anode side insulating region 208 can be formed through the following steps. First, as a part of a trench for forming the cathode electrode 102 and the anode electrode 108, the second barrier layer 29 and the n-channel quantum well layer 28 are penetrated from the surface of the semiconductor laminate 20 using sulfuric acid etching. A trench reaching the electron supply layer 27 is formed. Next, after filling the trench for the cathode electrode 102 with a protective film, the electron supply layer 27 is selectively etched using hydrochloric acid etching to form an anode-side insulating region 208. The lateral width of the anode-side insulating region 208 is several μm. Next, after removing the protective film filling the trench for the cathode electrode 102, the trench is further deepened to penetrate the channel layer 26 to reach the hole supply layer 25 using sulfuric acid etching. Next, after the trench for the anode electrode 108 is filled with a protective film, the hole supply layer 25 is selectively etched using hydrochloric acid etching to form a cathode-side insulating region 206. The lateral width of the cathode side insulating region 206 is several μm. Thus, in the process for forming the cathode electrode 102 and the anode electrode 108, the cathode side insulating region 206 and the anode side insulating region 208 can be formed. The cathode electrode 102 and the anode electrode 108 can be further formed through the following steps. After the protective film filling the trench for the anode electrode 108 is removed, sulfuric acid etching is used to penetrate the p channel quantum well layer 24, the first barrier layer 23 and the buffer layer 22 to reach the substrate 21. To make the trench deeper. Thereafter, as described above, after the n-type semiconductor region 104 and the p-type semiconductor region 106 are formed using oblique ion implantation technology, the cathode electrode 102 and the anode electrode are formed in the trench using sputtering or evaporation. Form 108.

  Next, the operation of the diode 2 will be described. When a voltage higher than that of the cathode electrode 102 is applied to the anode electrode 108, the diode 2 is in a forward bias state. At this time, holes are supplied from the p-type σ-doped layer of the hole supply layer 25 to the p-channel quantum well layer 24 side of the heterojunction surface of the p-channel quantum well layer 24 and the hole supply layer 25. Thus, a two-dimensional hole gas layer (2DHG) is generated. On the other hand, electrons are supplied from the n-type σ-doped layer of the electron supply layer 27 to the n-channel quantum well layer 28 side of the heterojunction surface of the electron supply layer 27 and the n-channel quantum well layer 28 to obtain two-dimensional electrons A gas layer (2 DEG) is produced. Thereby, holes are injected from the p-type semiconductor region 106 into the channel layer 26 through the two-dimensional hole gas layer (2DHG), and from the n-type semiconductor region 104 through the two-dimensional electron gas layer (2DEG), the channel layer Electrons are injected into 26. The diode 2 has a PIN structure including a two-dimensional hole gas layer (2DHG), a channel layer 26 of i-GaAs, and a two-dimensional electron gas layer (2DEG), and can operate as a PIN diode. . The diode 2 can use a two-dimensional hole gas layer (2DHG) and a two-dimensional electron gas layer (2DEG) as a channel, and thus can have low on-resistance. Furthermore, since a two-dimensional hole gas layer (2DHG) is generated in the p-channel quantum well layer 24 and a two-dimensional electron gas layer (2DEG) is generated in the n-channel quantum well layer 28, extremely low on-resistance is obtained. To be realized.

  When a voltage higher than that of the anode electrode 108 is applied to the cathode electrode 102, the diode 2 is in a reverse bias state. When the diode 2 is reverse biased, the two-dimensional electron gas layer (2DEG) and the two-dimensional hole gas layer (2DHG) are depleted. When the two-dimensional electron gas layer (2DEG) and the two-dimensional hole gas layer (2DHG) are depleted, positive fixed charges remain in the region where the two-dimensional electron gas layer (2DEG) is depleted, and two-dimensional holes A negative fixed charge remains in the region where the gas layer (2DHG) is depleted, and an electric field between these fixed charges is generated in a direction orthogonal to the direction connecting the cathode electrode 102 and the anode electrode 108. Thus, the diode 2 also has a heterojunction-type super junction structure, and the electric field strength between the cathode electrode 102 and the anode electrode 108 can be made uniform as in a normal super junction structure. Therefore, the diode 2 can have high withstand voltage characteristics.

  Furthermore, the diode 2 is provided with a cathode side insulating region 206. Since the cathode side insulating region 206 is provided, the two-dimensional hole gas layer (2DHG) is not formed in the p-channel quantum well layer 24 adjacent to the cathode side insulating region 206, and thus the two-dimensional hole gas layer 2DHG) and the n-type semiconductor region 104 are configured not to be in direct contact with each other. In the diode 2, when the p-channel quantum well layer 24 of i-GaAs is interposed between the two-dimensional hole gas layer (2DHG) and the n-type semiconductor region 104, the electric field concentration in this portion is relaxed and the high breakdown voltage Characteristics are realized.

  Furthermore, the diode 2 is provided with the anode side insulating region 208. Since the anode-side insulating region 208 is provided, the two-dimensional electron gas layer (2DEG) is not formed in the n-channel quantum well layer 28 adjacent to the anode-side insulating region 208, and the two-dimensional electron gas layer (2DEG) And the p-type semiconductor region 106 are not in direct contact with each other. In the diode 2, the n-channel quantum well layer 28 of i-GaAs intervenes between the two-dimensional electron gas layer (2DEG) and the p-type semiconductor region 106, whereby the electric field concentration in this portion is alleviated, and high withstand voltage is achieved. Characteristics are realized.

  As described above, the diode 2 of the second embodiment can achieve both low on-resistance and high withstand voltage.

Third Embodiment
The diode 3 of 3rd Embodiment is shown in FIG. In addition, about the component substantially the same as the diode 1 of 1st Embodiment, the same code | symbol is attached | subjected and the description is abbreviate | omitted.

  As shown in FIG. 3, the diode 3 includes a cathode electrode 102, an anode electrode 108, and a semiconductor laminate 30 provided between the cathode electrode 102 and the anode electrode 108.

  The semiconductor stack 30 includes a sapphire substrate 31, an i-GaAs buffer layer 32, an i-AlGaAs first barrier layer 33, an i-InGaP hole supply layer 34, an i-GaAs channel layer 35, and an i-InGaP layer. And the second barrier layer 37 of i-AlGaAs. In the channel layer 35, a p-type σ-doped layer containing a p-type impurity is formed at a position close to the hole supply layer 34, and an n-type σ-doped layer containing an n-type impurity at a position close to the electron supply layer 36. A layer is formed. The buffer layer 32, the first barrier layer 33, the hole supply layer 34, the channel layer 35, the electron supply layer 36 and the second barrier layer 37 are arranged in this order from the surface of the substrate 31 using metalorganic vapor phase epitaxy. Grow and form.

  The diode 3 further includes a cathode side insulating region 210 and an anode side insulating region 212. The insulating regions 210 and 212 are formed as air gaps. As long as the cathode side insulating region 210 is configured so as not to directly contact the two-dimensional hole gas layer (2DHG) and the n-type semiconductor region 104, other alternative means may be employed. For example, an insulator, a semi-insulator, or a high resistance semiconductor of a material that does not generate a two-dimensional hole gas layer (2DHG) in a region corresponding to the cathode-side insulating region 210 may be formed. Alternatively, an air gap, an insulator, a semi-insulator, or a high resistance semiconductor may be formed at a position where the two-dimensional hole gas layer (2DHG) and the n-type semiconductor region 104 are interposed. Similarly, as long as the anode-side insulating region 212 is configured so as not to directly contact the two-dimensional electron gas layer (2DEG) and the p-type semiconductor region 106, other alternative means may be adopted. For example, an insulator, a semi-insulator, or a high resistance semiconductor of a material that does not generate a two-dimensional electron gas layer (2DEG) in a region corresponding to the anode-side insulating region 212 may be formed. Alternatively, an air gap, an insulator, a semi-insulator, or a high resistance semiconductor may be formed at a position where the two-dimensional electron gas layer (2DEG) and the p-type semiconductor region 106 are interposed.

  Next, the operation of the diode 3 will be described. When a voltage higher than that of the cathode electrode 102 is applied to the anode electrode 108, the diode 3 is in a forward bias state. At this time, holes are supplied from the p-type σ-doped layer of the channel layer to the channel layer 35 side of the heterojunction surface of the hole supply layer 34 and the channel layer 35, and a two-dimensional hole gas layer (2DHG) is formed. It is generated. On the other hand, electrons are supplied from the n-type σ-doped layer of the channel layer 35 to the channel layer 35 side of the heterojunction surface of the channel layer 35 and the electron supply layer 36 to generate a two-dimensional electron gas layer (2DEG). . Thereby, holes are injected from the p-type semiconductor region 106 to the channel layer 35 via the two-dimensional hole gas layer (2DHG), and from the n-type semiconductor region 104 to the channel layer via the two-dimensional electron gas layer (2DEG). Electrons are injected into 35. The diode 3 has a PIN structure including a two-dimensional hole gas layer (2DHG), a channel layer 35 of i-GaAs, and a two-dimensional electron gas layer (2DEG), and can operate as a PIN diode. . The diode 3 can use a two-dimensional hole gas layer (2DHG) and a two-dimensional electron gas layer (2DEG) as a channel, and therefore can have low on-resistance.

  When a voltage higher than the anode electrode 108 is applied to the cathode electrode 102, the diode 3 is in a reverse bias state. When the diode 3 is reverse biased, the two-dimensional electron gas layer (2DEG) and the two-dimensional hole gas layer (2DHG) are depleted. When the two-dimensional electron gas layer (2DEG) and the two-dimensional hole gas layer (2DHG) are depleted, positive fixed charges remain in the region where the two-dimensional electron gas layer (2DEG) is depleted, and two-dimensional holes A negative fixed charge remains in the region where the gas layer (2DHG) is depleted, and an electric field between these fixed charges is generated in a direction orthogonal to the direction connecting the cathode electrode 102 and the anode electrode 108. Thus, the diode 3 also has a heterojunction-type super junction structure, and can make the electric field strength between the cathode electrode 102 and the anode electrode 108 uniform as in a normal super junction structure. Thus, the diode 3 can have high withstand voltage characteristics.

  Furthermore, the diode 3 includes a cathode side insulating region 210. Since the cathode side insulating region 210 is provided, the two-dimensional hole gas layer (2DHG) is not formed in the channel layer 35 adjacent to the cathode side insulating region 210, and the two-dimensional hole gas layer (2DHG) is formed. The n-type semiconductor region 104 is configured not to be in direct contact with each other. In the diode 3, when the channel layer 35 of i-GaAs is interposed between the two-dimensional hole gas layer (2DHG) and the n-type semiconductor region 104, the electric field concentration in this portion is relaxed and high withstand voltage characteristics are realized. Be done.

  Furthermore, the diode 3 includes an anode-side insulating region 212. Since the anode-side insulating region 212 is provided, the two-dimensional electron gas layer (2DEG) is not formed in the channel layer 35 adjacent to the anode-side insulating region 212, and the two-dimensional electron gas layer (2DEG) and the p-type The semiconductor region 106 is configured not to be in direct contact with each other. In the diode 3, the electric field concentration in this portion is relaxed by interposing the channel layer 35 of i-GaAs between the two-dimensional electron gas layer (2DEG) and the p-type semiconductor region 106, and high withstand voltage characteristics are realized. Ru.

  As described above, the diode 3 of the third embodiment can achieve both low on-resistance and high withstand voltage.

Fourth Embodiment
The diode 4 of 4th Embodiment is shown in FIG. In addition, about the component substantially the same as the diode 1 of 1st Embodiment, the same code | symbol is attached | subjected and the description is abbreviate | omitted.

  As shown in FIG. 4, the diode 4 includes a cathode electrode 102, an anode electrode 108, and a semiconductor laminate 40 provided between the cathode electrode 102 and the anode electrode 108.

The semiconductor laminate 40 includes a substrate 41 of silicon, a buffer layer 42 of i-AlGaN, a first barrier layer 43 of i-AlGaN, a hole supply layer 44 of p ⁺ -AlGaN, a channel layer 45 of i-GaN, n ⁺ An electron supply layer 46 of AlGaN and a second barrier layer 47 of i-AlGaN. The buffer layer 42, the first barrier layer 43, the hole supply layer 44, the channel layer 45, the electron supply layer 46, and the second barrier layer 47 are arranged in this order from the surface of the substrate 41 using metalorganic vapor phase epitaxy. Grow and form.

  The diode 4 further includes a cathode side insulating region 214 and an anode side insulating region 216. The insulating regions 214 and 216 are formed as air gaps. In addition, as long as the cathode side insulating region 214 is configured so as not to directly contact the two-dimensional hole gas layer (2DHG) and the n-type semiconductor region 104, other alternative means may be adopted. For example, an insulator, a semi-insulator, or a high resistance semiconductor of a material that does not generate a two-dimensional hole gas layer (2DHG) in a region corresponding to the cathode-side insulating region 214 may be formed. Alternatively, an air gap, an insulator, a semi-insulator, or a high resistance semiconductor may be formed at a position where the two-dimensional hole gas layer (2DHG) and the n-type semiconductor region 104 are interposed. Similarly, as long as the anode-side insulating region 216 is configured so as not to directly contact the two-dimensional electron gas layer (2DEG) and the p-type semiconductor region 106, other alternative means may be adopted. For example, an insulator, a semi-insulator, or a high resistance semiconductor of a material that does not generate a two-dimensional electron gas layer (2DEG) in a region corresponding to the anode-side insulating region 212 may be formed. Alternatively, an air gap, an insulator, a semi-insulator, or a high resistance semiconductor may be formed at a position where the two-dimensional electron gas layer (2DEG) and the p-type semiconductor region 106 are interposed.

  Next, the operation of the diode 4 will be described. When a voltage higher than that of the cathode electrode 102 is applied to the anode electrode 108, the diode 4 is in a forward bias state. At this time, the hole supply layer 44 is polarized such that negative fixed charge is induced at the interface on the channel layer 45 side by spontaneous polarization and piezoelectric polarization. The channel induced by the polarization charge of the hole supply layer 44 and the supply of holes from the acceptor impurity of the hole supply layer 44 makes the channel layer 45 side of the heterojunction surface of the hole supply layer 44 and the channel layer 45 A two-dimensional hole gas layer (2DHG) is generated. On the other hand, the electron supply layer 46 is polarized such that positive fixed charge is induced at the interface on the channel layer 45 side by spontaneous polarization and piezoelectric polarization. Due to the electron induction by the polarization charge of the electron supply layer 46 and the supply of electrons from the donor impurity of the electron supply layer 46, a two-dimensional electron gas is formed on the channel layer 45 side of the heterojunction surface of the channel layer 45 and the electron supply layer 46. A layer (2 DEG) is created. Thereby, holes are injected from the p-type semiconductor region 106 to the channel layer 45 via the two-dimensional hole gas layer (2DHG), and from the n-type semiconductor region 104 to the channel layer via the two-dimensional electron gas layer (2DEG). Electrons are injected into 45. The diode 4 has a PIN structure including a two-dimensional hole gas layer (2DHG), a channel layer 45 of i-GaN, and a two-dimensional electron gas layer (2DEG), and can operate as a PIN diode. . The diode 4 can have low on-resistance because it can use a two-dimensional hole gas layer (2DHG) and a two-dimensional electron gas layer (2DEG) as a channel.

  When a voltage higher than that of the anode electrode 108 is applied to the cathode electrode 102, the diode 4 is in a reverse bias state. When the diode 4 is reverse biased, the two-dimensional electron gas layer (2DEG) and the two-dimensional hole gas layer (2DHG) are depleted. In the diode 4, when reverse bias is applied, the positive fixed charge of the electron supply layer 46 and the negative fixed charge of the hole supply layer 44 remain, and the electric field between these fixed charges connects the cathode electrode 102 and the anode electrode 108. It occurs in the direction orthogonal to the direction. Thus, the diode 4 also has a heterojunction-type super junction structure, and can make the electric field strength between the cathode electrode 102 and the anode electrode 108 uniform as in a normal super junction structure. Thus, the diode 4 can have a high breakdown voltage.

  Furthermore, the diode 4 includes a cathode side insulating region 214. Since the cathode side insulating region 214 is provided, the two-dimensional hole gas layer (2DHG) is not formed in the channel layer 45 adjacent to the cathode side insulating region 214, and the two-dimensional hole gas layer (2DHG) is formed. The n-type semiconductor region 104 is configured not to be in direct contact with each other. In the diode 4, the i-GaN channel layer 45 intervenes between the two-dimensional hole gas layer (2DHG) and the n-type semiconductor region 104, whereby the electric field concentration in this portion is relaxed and high breakdown voltage characteristics are realized. Be done.

  Furthermore, the diode 4 includes an anode-side insulating region 216. Since the anode-side insulating region 216 is provided, the two-dimensional electron gas layer (2DEG) is not formed in the channel layer 45 adjacent to the anode-side insulating region 216, and the two-dimensional electron gas layer (2DEG) and the p-type The semiconductor region 106 is configured not to be in direct contact with each other. In the diode 4, the i-GaN channel layer 45 intervenes between the two-dimensional electron gas layer (2DEG) and the p-type semiconductor region 106, whereby the electric field concentration in this portion is relaxed and high withstand voltage characteristics are realized. Ru.

  As described above, the diode 4 of the fourth embodiment can achieve both low on-resistance and high withstand voltage.

Fifth Embodiment
The diode 5 of 5th Embodiment is shown in FIG. In addition, about the component substantially the same as the diode 1 of 1st Embodiment, the same code | symbol is attached | subjected and the description is abbreviate | omitted.

  As shown in FIG. 5, the diode 5 includes a cathode electrode 102, an anode electrode 108, and a semiconductor laminate 50 provided between the cathode electrode 102 and the anode electrode 108.

  The semiconductor stack 50 includes a silicon substrate 51, an i-AlGaN buffer layer 52, an i-GaN n-channel layer 53, an i-AlGaN channel layer 54, and an i-GaN p-channel layer 55. The buffer layer 52, the n-channel layer 53, the channel layer 54, and the p-channel layer 55 are formed by growing in this order from the surface of the substrate 51 using metal organic chemical vapor deposition.

  The diode 5 further includes an anode-side insulating region 218 and a cathode-side insulating region 220. The insulating regions 218 and 220 are formed as air gaps. Other alternative means may be adopted as the anode-side insulating region 218 as long as the two-dimensional electron gas layer (2DEG) and the p-type semiconductor region 106 are not in direct contact with each other. For example, an insulator, a semi-insulator, or a high-resistance semiconductor may be formed in a region corresponding to the anode-side insulating region 218. Similarly, as long as the cathode side insulating region 220 is configured so as not to directly contact the two-dimensional hole gas layer (2DHG) and the n-type semiconductor region 104, other alternative means may be adopted. For example, an insulator, a semi-insulator, or a high-resistance semiconductor may be formed in a region corresponding to the cathode-side insulating region 220.

  Next, the operation of the diode 5 will be described. When a voltage higher than that of the cathode electrode 102 is applied to the anode electrode 108, the diode 5 is in a forward bias state. At this time, the channel layer 54 is polarized such that positive fixed charge is induced at the interface on the n channel layer 53 side by spontaneous polarization and piezoelectric polarization, and negative fixed charge is induced at the interface on the p channel layer 55 side. ing. By the polarization action of the channel layer 54, a two-dimensional electron gas layer (2DEG) is generated on the n channel layer 53 side of the heterojunction surface of the n channel layer 53 and the channel layer 54. A two-dimensional hole gas layer (2DHG) is generated on the p channel layer 55 side of the heterojunction surface of Thereby, holes are injected from the p-type semiconductor region 106 to the channel layer 54 through the two-dimensional hole gas layer (2DHG), and from the n-type semiconductor region 104 to the channel layer through the two-dimensional electron gas layer (2DEG). Electrons are injected into 54. The diode 5 has a PIN structure including a two-dimensional hole gas layer (2DHG), a channel layer 54 of i-AlGaN, and a two-dimensional electron gas layer (2DEG), and can operate as a PIN diode. . The diode 5 can use a two-dimensional hole gas layer (2DHG) and a two-dimensional electron gas layer (2DEG) as a channel, and therefore can have low on-resistance.

  When a voltage higher than that of the anode electrode 108 is applied to the cathode electrode 102, the diode 5 is in a reverse bias state. When the diode 5 is reverse biased, the two-dimensional electron gas layer (2DEG) and the two-dimensional hole gas layer (2DHG) are depleted. In the diode 5, positive fixed charge and negative fixed charge of the channel layer 54 remain, and an electric field between these fixed charges is generated in a direction orthogonal to the direction connecting the cathode electrode 102 and the anode electrode 108. Thus, the diode 5 also has a heterojunction-type super junction structure, and can make the electric field strength between the cathode electrode 102 and the anode electrode 108 uniform, as in a normal super junction structure. Thus, the diode 5 can have a high breakdown voltage.

  Furthermore, the diode 5 is provided with an anode-side insulating region 218. Since the anode-side insulating region 218 is provided, the two-dimensional electron gas layer (2DEG) and the p-type semiconductor region 106 are configured not to be in direct contact with each other. In the diode 5, the anode-side insulating region 218 is interposed between the two-dimensional electron gas layer (2DEG) and the p-type semiconductor region 106, whereby the electric field concentration in this portion is alleviated and high withstand voltage characteristics are realized. .

  Furthermore, the diode 5 includes a cathode side insulating region 220. Since the cathode side insulating region 220 is provided, the two-dimensional hole gas layer (2DHG) and the n-type semiconductor region 104 are not in direct contact with each other. In the diode 5, the cathode-side insulating region 220 is interposed between the two-dimensional hole gas layer (2DHG) and the n-type semiconductor region 104, whereby the electric field concentration in this portion is alleviated and high withstand voltage characteristics are realized. Ru.

  As described above, the diode 5 of the fifth embodiment can achieve both low on-resistance and high withstand voltage.

Sixth Embodiment
The diode 6 of 6th Embodiment is shown in FIG. In addition, about the component substantially the same as the diode 1 of 1st Embodiment, the same code | symbol is attached | subjected and the description is abbreviate | omitted.

  As shown in FIG. 6, the diode 6 includes a cathode electrode 102, an anode electrode 108, and a semiconductor laminate 60 provided between the cathode electrode 102 and the anode electrode 108.

  The semiconductor laminate 60 includes a sapphire substrate 61, a buffer layer 62 of i-AlGaN, a first barrier layer 63 of i-AlGaN, a quantum well layer 64 of p-channel for i-InGaN, a channel layer 65 of i-GaN, i A quantum well layer 66 for n-channel InGaN and a second barrier layer 67 for i-AlGaN. The buffer layer 62, the first barrier layer 63, the p-channel quantum well layer 64, the channel layer 65, the n-channel quantum well layer 66, and the second barrier layer 67 are formed of the substrate 61 using metal organic chemical vapor deposition. It is formed by growing in this order from the surface of.

  The diode 6 further includes a cathode side insulating region 222 and an anode side insulating region 224. The insulating regions 222 and 224 are formed as air gaps. In addition, as long as the cathode side insulating region 222 is configured so as not to directly contact the two-dimensional hole gas layer (2DHG) and the n-type semiconductor region 104, other alternative means may be adopted. For example, an insulator, a semi-insulator, or a high-resistance semiconductor may be formed in a region corresponding to the cathode-side insulating region 222. Similarly, as long as the anode-side insulating region 224 is configured not to be in direct contact with the two-dimensional electron gas layer (2DEG) and the p-type semiconductor region 106, other alternative means may be adopted. For example, an insulator, a semi-insulator, or a high-resistance semiconductor may be formed in a region corresponding to the anode-side insulating region 224.

  Next, the operation of the diode 6 will be described. When a voltage higher than that of the cathode electrode 102 is applied to the anode electrode 108, the diode 6 is in a forward bias state. At this time, the first barrier layer 63 is polarized such that a negative fixed charge is induced at the interface on the p channel quantum well layer 64 side by spontaneous polarization and piezoelectric polarization. The polarization of the first barrier layer 63 generates a two-dimensional hole gas layer (2DHG) in the p-channel quantum well layer 64 formed on the heterojunction surface of the first barrier layer 63 and the channel layer 65. . On the other hand, the second barrier layer 67 is polarized such that positive fixed charge is induced at the interface on the n-channel quantum well layer 66 side by spontaneous polarization and piezoelectric polarization. Due to the polarization of the second barrier layer 67, a two-dimensional electron gas layer (2DEG) is generated in the n-channel quantum well layer 66 formed on the heterojunction surface of the channel layer 65 and the second barrier layer 67. Thereby, holes are injected from the p-type semiconductor region 106 to the channel layer 65 via the two-dimensional hole gas layer (2DHG), and from the n-type semiconductor region 104 to the channel layer via the two-dimensional electron gas layer (2DEG). Electrons are injected into 65. The diode 6 has a PIN structure including a two-dimensional hole gas layer (2DHG), a channel layer 65 of i-GaN, and a two-dimensional electron gas layer (2DEG), and can operate as a PIN diode. . The diode 6 can have low on-resistance because it can use a two-dimensional hole gas layer (2DHG) and a two-dimensional electron gas layer (2DEG) as a channel.

  When a voltage higher than that of the anode electrode 108 is applied to the cathode electrode 102, the diode 6 is in a reverse bias state. When the diode 6 is reverse biased, the two-dimensional electron gas layer (2DEG) and the two-dimensional hole gas layer (2DHG) are depleted. In the diode 6, the positive fixed charge of the second barrier layer 67 and the negative fixed charge of the first barrier layer 63 remain, and the electric field between these fixed charges is in the direction connecting the cathode electrode 102 and the anode electrode 108. It occurs in the orthogonal direction. Thus, the diode 6 also has a heterojunction-type super junction structure, and can make the electric field strength between the cathode electrode 102 and the anode electrode 108 uniform as in a normal super junction structure. Therefore, the diode 6 can have high withstand voltage characteristics.

  Furthermore, the diode 6 is provided with a cathode side insulating region 222. Since the cathode side insulating region 222 is provided, the two-dimensional hole gas layer (2DHG) and the n-type semiconductor region 104 are not in direct contact with each other. In the diode 6, the cathode-side insulating region 222 is interposed between the two-dimensional hole gas layer (2DHG) and the n-type semiconductor region 104, whereby the electric field concentration in this portion is alleviated and high withstand voltage characteristics are realized. Ru.

  Furthermore, the diode 6 includes an anode-side insulating region 224. Since the anode-side insulating region 224 is provided, the two-dimensional electron gas layer (2DEG) and the p-type semiconductor region 106 are not in direct contact with each other. In the diode 6, the anode-side insulating region 224 is interposed between the two-dimensional electron gas layer (2DEG) and the p-type semiconductor region 106, whereby the electric field concentration in this portion is alleviated and high withstand voltage characteristics are realized. .

  As described above, the diode 6 according to the sixth embodiment can achieve both low on-resistance and high withstand voltage.

Seventh Embodiment
The diode 7 of 7th Embodiment is shown in FIG. In addition, about the component substantially the same as the diode 1 of 1st Embodiment, the same code | symbol is attached | subjected and the description is abbreviate | omitted.

  As shown in FIG. 7, the diode 7 includes a cathode electrode 102, an anode electrode 108, and a semiconductor laminate 70 provided between the cathode electrode 102 and the anode electrode 108.

  The semiconductor laminate 70 includes a sapphire substrate 71, an i-GaAs buffer layer 72, an i-AlGaAs first barrier layer 73, a p-InGaP hole supply layer 74, an i-GaAs channel layer 75, and an n-InGaP layer. And the second barrier layer 77 of i-AlGaAs. The buffer layer 72, the first barrier layer 73, the hole supply layer 74, the channel layer 75, the electron supply layer 76, and the second barrier layer 77 are arranged in this order from the surface of the substrate 71 using metal organic chemical vapor deposition. Grow and form.

  Unlike the diode shown in FIGS. 1-6, in the diode 7, no p-type semiconductor region is formed between the anode electrode 108 and the semiconductor stack 70, and the anode electrode 108 is in Schottky contact with the channel layer 75. It is characterized by

  The diode 7 further includes a cathode side insulating region 226, an anode side p channel insulating region 228, and an anode side n channel insulating region 230. These insulating regions 226, 228, 230 are formed as air gaps. As long as the cathode side insulating region 226 is configured so that the two-dimensional hole gas layer (2DHG) and the n-type semiconductor region 104 are not in direct contact with each other, other alternative means may be adopted. For example, an insulator, a semi-insulator, or a high resistance semiconductor of a material that does not generate a two-dimensional hole gas layer (2DHG) in a region corresponding to the cathode-side insulating region 226 may be formed. Alternatively, an air gap, an insulator, a semi-insulator, or a high resistance semiconductor may be formed at a position where the two-dimensional hole gas layer (2DHG) and the n-type semiconductor region 104 are interposed. Similarly, as long as the two-dimensional hole gas layer (2DHG) and the anode electrode 108 are not in direct contact with each other, the anode side p-channel insulating region 228 may adopt other alternative means. For example, an insulator, a semi-insulator, or a high-resistance semiconductor of a material that does not generate a two-dimensional hole gas layer (2DHG) may be formed in a region corresponding to the anode-side p-channel insulating region 228. Alternatively, an air gap, an insulator, a semi-insulator, or a high resistance semiconductor may be formed at a position where the two-dimensional hole gas layer (2DHG) and the anode electrode 108 are interposed. Furthermore, similarly, as long as the two-dimensional electron gas layer (2DEG) and the anode electrode 108 are not in direct contact with each other, the anode n-channel insulating region 230 may adopt other alternative means. For example, an insulator, a semi-insulator, or a high resistance semiconductor of a material that does not generate a two-dimensional electron gas layer (2DEG) may be formed in a region corresponding to the anode-side n-channel insulating region 230. Alternatively, an air gap, an insulator, a semi-insulator, or a high resistance semiconductor may be formed at a position where the two-dimensional electron gas layer (2DEG) and the anode electrode 108 are interposed.

  Next, the operation of the diode 7 will be described. When a voltage higher than that of the cathode electrode 102 is applied to the anode electrode 108, the diode 7 is in a forward bias state. This lowers the Schottky barrier between the anode electrode 108 and the channel layer 75. At this time, electrons are supplied from the donor impurity of the electron supply layer 76 on the channel layer 75 side of the heterojunction surface of the channel layer 75 and the electron supply layer 76 to generate a two-dimensional electron gas layer (2DEG). Electrons are injected from the n-type semiconductor region 104 into the channel layer 75 via the two-dimensional electron gas layer (2DEG), and the electrons flow to the anode electrode 108 over the low Schottky barrier. Thus, the diode 7 can operate as a Schottky diode. The diode 7 can have a low on-resistance because a two-dimensional electron gas layer (2DEG) can be used as a channel. On the other hand, when the diode 7 is forward biased, holes are supplied from the hole supply layer 74 to the channel layer 75 side of the heterojunction surfaces of the hole supply layer 74 and the channel layer 75, and the two-dimensional hole gas layer (2 DHG) is generated. However, this two-dimensional hole gas layer (2DHG) is considered not to operate substantially as a channel.

  When a voltage higher than that of the anode electrode 108 is applied to the cathode electrode 102, the diode 7 is in a reverse bias state. At this time, the two-dimensional electron gas layer (2DEG) and the two-dimensional hole gas layer (2DHG) are depleted. When the two-dimensional electron gas layer (2DEG) and the two-dimensional hole gas layer (2DHG) are depleted, positive fixed charges remain in the region where the two-dimensional electron gas layer (2DEG) is depleted, and two-dimensional holes A negative fixed charge remains in the region where the gas layer (2DHG) is depleted, and an electric field between these fixed electric fields is generated in a direction orthogonal to the direction connecting the cathode electrode 102 and the anode electrode 108. Thus, the diode 7 also has a heterojunction-type super junction structure, and can make the electric field strength between the cathode electrode 102 and the anode electrode 108 uniform as in a normal super junction structure. Therefore, the diode 7 can have high withstand voltage characteristics.

  Furthermore, the diode 7 includes a cathode side insulating region 226. Since the cathode side insulating region 226 is provided, the two-dimensional hole gas layer (2DHG) is not formed in the channel layer 75 adjacent to the cathode side insulating region 226, and the two-dimensional hole gas layer (2DHG) is formed. The n-type semiconductor region 104 is configured not to be in direct contact with each other. In the diode 7, the electric field concentration in this portion is relaxed by interposing the channel layer 75 of i-GaAs between the two-dimensional hole gas layer (2DHG) and the n-type semiconductor region 104, and high withstand voltage characteristics are realized. Be done.

  Furthermore, the diode 7 is provided with an insulating region 228 for the anode side p-channel. Since the anode-side p-channel insulating region 228 is provided, the two-dimensional hole gas layer (2DHG) is not formed in the channel layer 75 adjacent to the anode-side p-channel insulating region 228; The gas layer (2DHG) and the anode electrode 108 are configured not to be in direct contact with each other. In the diode 7, by interposing the channel layer 75 of i-GaAs between the two-dimensional hole gas layer (2DHG) and the anode electrode 108, the electric field concentration in this portion is relaxed, and high withstand voltage characteristics are realized. .

  Furthermore, the diode 7 includes an insulating region 230 for the anode side n-channel. Since the anode-side n-channel insulating region 230 is provided, the two-dimensional electron gas layer (2DEG) is not formed in the channel layer 75 adjacent to the anode-side n-channel insulating region 230. (2DEG) and the anode electrode 108 are not in direct contact with each other. In the diode 7, by interposing the channel layer 75 of i-GaAs between the two-dimensional electron gas layer (2DEG) and the anode electrode 108, the electric field concentration in this portion is relaxed, and high withstand voltage characteristics are realized.

  As described above, the diode 7 of the seventh embodiment can achieve both low on resistance and high withstand voltage.

Eighth Embodiment
The diode 8 of 8th Embodiment is shown in FIG. Components substantially the same as those of the diode 8 according to the eighth embodiment are denoted by the same reference numerals, and the description thereof will be omitted.

  As shown in FIG. 8, the diode 8 includes a cathode electrode 102, an anode electrode 108, and a semiconductor laminate 80 provided between the cathode electrode 102 and the anode electrode 108.

  The semiconductor stack 80 includes a sapphire substrate 81, a buffer layer 82 of i-AlGaN, a first barrier layer 83 of i-AlGaN, a hole supply layer 84 of p-AlGaN, a channel layer 85 of i-GaN, n-AlGaN And the second barrier layer 87 of i-AlGaN. The buffer layer 82, the first barrier layer 83, the hole supply layer 84, the channel layer 85, the electron supply layer 86, and the second barrier layer 87 are arranged in this order from the surface of the substrate 81 using metal organic chemical vapor deposition. Grow and form.

  Unlike the diode shown in FIGS. 1-6, in the diode 8, no p-type semiconductor region is formed between the anode electrode 108 and the semiconductor stack 80, and the anode electrode 108 is in Schottky contact with the channel layer 85. It is characterized by

  The diode 8 further includes a cathode side insulating region 232, an anode side p channel insulating region 234, and an anode side n channel insulating region 236. These insulating regions 232, 234 and 236 are formed as air gaps. In addition, as long as the cathode side insulating region 232 is configured so as not to directly contact the two-dimensional hole gas layer (2DHG) and the n-type semiconductor region 104, other alternative means may be adopted. For example, an insulator, a semi-insulator, or a high resistance semiconductor of a material that does not generate a two-dimensional hole gas layer (2DHG) in a region corresponding to the cathode-side insulating region 232 may be formed. Alternatively, an air gap, an insulator, a semi-insulator, or a high resistance semiconductor may be formed at a position where the two-dimensional hole gas layer (2DHG) and the n-type semiconductor region 104 are interposed. Similarly, as long as the two-dimensional hole gas layer (2DHG) and the anode electrode 108 are not in direct contact with each other, the anode side p-channel insulating region 234 may adopt other alternative means. For example, an insulator, a semi-insulator, or a high resistance semiconductor of a material that does not generate a two-dimensional hole gas layer (2DHG) may be formed in the region corresponding to the anode-side p-channel insulating region 234. Alternatively, an air gap, an insulator, a semi-insulator, or a high resistance semiconductor may be formed at a position where the two-dimensional hole gas layer (2DHG) and the anode electrode 108 are interposed. Furthermore, similarly, as long as the two-dimensional electron gas layer (2DEG) and the anode electrode 108 are not in direct contact with each other, the anode n-channel insulating region 236 may adopt other alternative means. For example, an insulator, a semi-insulator, or a high resistance semiconductor of a material that does not generate a two-dimensional electron gas layer (2DEG) may be formed in a region corresponding to the anode-side n-channel insulating region 236. Alternatively, an air gap, an insulator, a semi-insulator, or a high resistance semiconductor may be formed at a position where the two-dimensional electron gas layer (2DEG) and the anode electrode 108 are interposed.

  Next, the operation of the diode 8 will be described. When a voltage higher than that of the cathode electrode 102 is applied to the anode electrode 108, the diode 8 is in a forward bias state. This lowers the Schottky barrier between the anode electrode 108 and the channel layer 85. At this time, the electron supply layer 86 is polarized such that a positive fixed charge is induced at the interface on the channel layer 85 side by spontaneous polarization and piezoelectric polarization. The two-dimensional electron gas on the channel layer 85 side of the heterojunction surface of the channel layer 85 and the electron supply layer 86 by the electron induction by the polarization charge of the electron supply layer 86 and the supply of electrons from the donor impurity of the electron supply layer 86 A layer (2 DEG) is created. Electrons are injected from the n-type semiconductor region 104 into the channel layer 85 through the two-dimensional electron gas layer (2DEG), and the electrons flow to the anode electrode 108 over the low Schottky barrier. Thus, the diode 8 can operate as a Schottky diode. The diode 8 can have a low on-resistance because a two-dimensional electron gas layer (2DEG) can be used as a channel. On the other hand, the hole supply layer 84 is also polarized such that a negative fixed charge is induced at the interface on the channel layer 85 side by spontaneous polarization and piezoelectric polarization. The channel induced by the polarization charge of the hole supply layer 84 and the supply of holes from the acceptor impurity of the hole supply layer 44 makes the channel layer 85 side of the heterojunction surface of the hole supply layer 84 and the channel layer 85. A two-dimensional hole gas layer (2DHG) is generated. However, this two-dimensional hole gas layer (2DHG) is considered not to operate substantially as a channel.

  When a voltage higher than that of the anode electrode 108 is applied to the cathode electrode 102, the diode 8 is in a reverse bias state. When the diode 8 is reverse biased, the two-dimensional electron gas layer (2DEG) and the two-dimensional hole gas layer (2DHG) are depleted. In diode 8, the positive fixed charge of electron supply layer 86 and the negative fixed charge of hole supply layer 84 remain, and the electric field between these fixed charges is orthogonal to the direction connecting cathode electrode 102 and anode electrode 108. Occurs in the Thus, the diode 8 also has a heterojunction-type super junction structure, and can make the electric field strength between the cathode electrode 102 and the anode electrode 108 uniform as in a normal super junction structure. Therefore, the diode 8 can have high withstand voltage characteristics.

  Furthermore, the diode 8 is provided with a cathode side insulating region 232. Since the cathode side insulating region 232 is provided, the two-dimensional hole gas layer (2DHG) is not formed in the channel layer 85 adjacent to the cathode side insulating region 232, and the two-dimensional hole gas layer (2DHG) The n-type semiconductor region 104 is configured not to be in direct contact with each other. In the diode 8, the electric field concentration in this portion is relaxed by interposing the channel layer 85 of i-GaAs between the two-dimensional hole gas layer (2DHG) and the n-type semiconductor region 104, and high withstand voltage characteristics are realized. Be done.

  Furthermore, the diode 8 includes an insulating region 234 for the anode side p-channel. Since the anode-side p-channel insulating region 234 is provided, the two-dimensional hole gas layer (2DHG) is not formed in the channel layer 85 adjacent to the anode-side p-channel insulating region 234. The gas layer (2DHG) and the anode electrode 108 are configured not to be in direct contact with each other. In the diode 8, by interposing the channel layer 85 of i-GaAs between the two-dimensional hole gas layer (2DHG) and the anode electrode 108, the electric field concentration in this portion is relaxed and high withstand voltage characteristics are realized. .

  Further, the diode 8 is provided with an anode-side n-channel insulating region 236. Since the anode-side n-channel insulating region 236 is provided, the two-dimensional electron gas layer (2DEG) is not formed in the channel layer 85 adjacent to the anode-side n-channel insulating region 236. (2DEG) and the anode electrode 108 are not in direct contact with each other. In the diode 8, by interposing the channel layer 85 of i-GaAs between the two-dimensional electron gas layer (2DEG) and the anode electrode 108, the electric field concentration in this portion is relaxed and high withstand voltage characteristics are realized.

  As described above, the diode 8 according to the eighth embodiment can achieve both low on-resistance and high withstand voltage.

  The technical elements disclosed in the present specification are listed below. The following technical elements are useful independently of one another.

  The diode disclosed herein can include a cathode electrode, an anode electrode, a semiconductor stack, an n-type semiconductor region, and a first insulating region. The semiconductor laminate is provided between the cathode electrode and the anode electrode. The semiconductor stack may have a first heterojunction that produces a two-dimensional electron gas layer and a second heterojunction that produces a two-dimensional hole gas. The first heterojunction and the second heterojunction extend along the direction connecting the cathode electrode and the anode electrode. The n-type semiconductor region is provided between the cathode electrode and the semiconductor laminate. The two-dimensional electron gas layer and the n-type semiconductor region are configured to be in direct contact with each other. The two-dimensional hole gas layer and the n-type semiconductor region are configured not to be in direct contact with each other by the first insulating region. Here, in the first insulating region, the two-dimensional hole gas layer may not be in direct contact with the n-type semiconductor region by preventing the two-dimensional hole gas layer from being generated in a partial region. . Alternatively, the first insulating region may be interposed between the two-dimensional hole gas layer and the n-type semiconductor region so that the two-dimensional hole gas layer and the n-type semiconductor region are not in direct contact with each other. The first insulating region may be formed of an air gap, an insulator, a semi-insulator, or a high resistance semiconductor.

  One embodiment of the diode may further include a p-type semiconductor region provided between the anode electrode and the semiconductor stack, and a second insulating region. In this case, the two-dimensional hole gas layer and the p-type semiconductor region are in direct contact with each other. The two-dimensional electron gas layer and the p-type semiconductor region are configured not to be in direct contact with each other by the second insulating region. This diode can operate as a PIN diode. Here, in the second insulating region, the two-dimensional electron gas layer may not be in direct contact with the p-type semiconductor region by preventing the two-dimensional electron gas layer from being generated in a partial region. Alternatively, the second insulating region may be interposed between the two-dimensional electron gas layer and the p-type semiconductor region so that the two-dimensional electron gas layer and the p-type semiconductor region are not in direct contact with each other. The second insulating region may be formed of an air gap, an insulator, a semi-insulator, or a high resistance semiconductor.

  In another embodiment of the diode, the semiconductor stack may be configured such that the semiconductor layer adjacent to the two-dimensional electron gas layer is in Schottky contact with the anode electrode. This diode can operate as a Schottky diode. The diode may further comprise a second insulating region and a third insulating region. The two-dimensional electron gas layer and the anode electrode are configured not to be in direct contact with each other by the second insulating region. The two-dimensional hole gas layer and the anode electrode are configured not to be in direct contact with each other by the third insulating region. Here, in the second insulating region, the two-dimensional electron gas layer may not be in direct contact with the anode electrode by preventing the two-dimensional electron gas layer from being generated in a partial region. Alternatively, the second insulating region may be interposed between the two-dimensional electron gas layer and the anode electrode so that the two-dimensional electron gas layer and the anode electrode are not in direct contact with each other. The second insulating region may be formed of an air gap, an insulator, a semi-insulator, or a high resistance semiconductor. In the third insulating region, the two-dimensional hole gas layer may not be in direct contact with the anode electrode so that the two-dimensional hole gas layer is not generated in a partial region. Alternatively, the third insulating region may be interposed between the two-dimensional hole gas layer and the anode electrode so that the two-dimensional hole gas layer and the anode electrode are not in direct contact with each other. The third insulating region may be formed of an air gap, an insulator, a semi-insulator, or a high resistance semiconductor.

  As mentioned above, although the specific example of this invention was described in detail, these are only an illustration and do not limit a claim. The art set forth in the claims includes various variations and modifications of the specific examples illustrated above.

  For example, the top and bottom of the two-dimensional electron gas layer and the two-dimensional hole gas layer may be interchanged, or a plurality of heterostructures having a pair of the two-dimensional electron gas layer and the two-dimensional hole gas layer are stacked in the thickness direction. May be Such a modification is illustrated in FIG. The diode 9 shown in FIG. 9 is a modification of the diode 1 of FIG. The semiconductor laminate 90 of the diode 9 includes a semi-insulating GaAs substrate 91, a buffer layer 92 of AlGaAs, a barrier layer 93 of i-AlGaAs, an electron supply layer 94 of n-InGaP, a channel layer 95 of i-GaAs, p-InGaP hole supply layer 96, i-AlGaAs barrier layer 97, n-InGaP electron supply layer 98, i-GaAs channel layer 99, p-InGaP hole supply layer 100, and i-AlGaAs The barrier layer 101 of Thus, in the diode 9 of FIG. 9, the top and bottom of the two-dimensional electron gas layer and the two-dimensional hole gas layer are interchanged as compared with the diode 1 of FIG. 1, and further, the two-dimensional electron gas layer and the two-dimensional positive. A plurality of heterostructures having a pair of porous gas layers are stacked in the thickness direction. Such a diode 9 also has a heterojunction-type super junction structure, and can make the electric field strength between the cathode electrode 102 and the anode electrode 108 uniform as in a normal super junction structure. Therefore, the diode 9 can have high withstand voltage characteristics. Furthermore, the diode 9 also includes cathode side insulating regions 238 and 240, and the channel layer 95 and 99 of i-GaAs is interposed between the two-dimensional hole gas layer (2DHG) and the n-type semiconductor region 104. Thus, the concentration of the electric field in this portion is alleviated, and high withstand voltage characteristics are realized. Furthermore, the diode 9 includes anode-side insulating regions 242 and 244, and the channel layers 95 and 99 of i-GaAs are interposed between the two-dimensional electron gas layer (2DEG) and the p-type semiconductor region 106. The electric field concentration in this portion is alleviated, and high withstand voltage characteristics are realized.

  The technical elements described in the present specification or the drawings exhibit technical usefulness singly or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Moreover, although the techniques illustrated in the present specification or the drawings can achieve a plurality of purposes simultaneously, achieving one of the purposes has technical utility in itself.

1: Diode 10: Semiconductor laminate 11: Substrate 12: Buffer layer 13: Barrier layer 14: Hole supply layer 15: Channel layer 16: Electron supply layer 17: Barrier layer 102: Cathode electrode 104: n-type semiconductor region 106: p-type semiconductor region 108: anode electrode 202: cathode side insulating region 204: anode side insulating region

Claims (4)

A cathode electrode,
An anode electrode,
A semiconductor laminate provided between the cathode electrode and the anode electrode, the first hetero junction having a two-dimensional electron gas layer in the vicinity of the junction interface and the first hetero junction having a two-dimensional hole gas layer in the vicinity of the junction interface A semiconductor laminate having two hetero junctions, wherein the first hetero junction and the second hetero junction extend along a direction connecting between the cathode electrode and the anode electrode;
An n-type semiconductor region provided between the cathode electrode and the semiconductor laminate;
And a first insulating region,
The two-dimensional electron gas layer and the n-type semiconductor region are configured to be in direct contact with each other,
The diode, wherein the two-dimensional hole gas layer and the n-type semiconductor region are not in direct contact with each other by the first insulating region. A p-type semiconductor region provided between the anode electrode and the semiconductor laminate;
And a second insulating region,
The two-dimensional hole gas layer and the p-type semiconductor region are configured to be in direct contact with each other,
The diode according to claim 1, wherein the two-dimensional electron gas layer and the p-type semiconductor region are configured not to be in direct contact with each other by the second insulating region.   The diode according to claim 1, wherein the semiconductor stack is configured such that a semiconductor layer adjacent to the two-dimensional electron gas layer is in Schottky contact with the anode electrode. A second insulating region,
And a third insulating region,
The two-dimensional electron gas layer and the anode electrode are configured not to be in direct contact with each other by the second insulating region,
The diode according to claim 3, wherein the two-dimensional hole gas layer and the anode electrode are not in direct contact with each other by the third insulating region.