JP2019050300A - Power semiconductor module - Google Patents

Abstract

To provide a power semiconductor module capable of achieving large current capacity and equal supply of control signals. A plurality of semiconductor elements are disposed along the periphery of a center C of a region 70 in which a plurality of submodules 10 are disposed, and have a plurality of switching elements S having a control input unit 13. The control wiring 50 surrounds the center C of the region 70 and is provided with an outer wiring 51 connected to the control input 13 of the switching element S, a lead-out wiring 55 extending outside the outer wiring 51 from the center C or its vicinity, It has the inside wiring 52 which is arranged inside the wiring 51 and which connects the outside wiring 51 and the lead-out wiring 55. [Selected figure] Figure 4

Description

  Embodiments of the present invention relate to a power semiconductor module on which a power semiconductor element is mounted.

  In order to construct a high-voltage / high-capacity power converter, it is required to increase the current capacity of the semiconductor device. Therefore, it has been proposed to mount a plurality of semiconductor elements in parallel in a device.

  Furthermore, a semiconductor element constituting a general power converter has a mixed structure of a switching element and a diode connected antiparallel to the switching element, and for the purpose of downsizing and simplification of the device, It is required to fit the switching element and the diode in one package.

Patent 3258200 gazette Patent No. 4385324

  In order to maximize current capacity by parallel mounting of a plurality of switching elements, it is desirable that control signals be equally supplied to the plurality of switching elements connected in parallel.

  Embodiments of the present invention provide a power semiconductor module that enables large current capacity and equal supply of control signals.

  According to the embodiment, the power semiconductor module includes the first metal member, the plurality of sub-modules disposed on the first metal member, and the control wiring. Each of the plurality of sub-modules includes a second metal member joined to the first metal member, a third metal member disposed above the second metal member, the second metal member, and the third metal member. And a semiconductor element disposed between the metal member and the second metal member and the third metal member. The control wiring is disposed on the first metal member. The plurality of semiconductor devices are disposed along the periphery of the center of the region in which the plurality of sub-modules are disposed, and include a plurality of switching devices having a control input unit. The control wiring surrounds the center of the region, and includes an outer wiring connected to the control input portion of the switching element, a lead-out wiring extending from the center or the vicinity thereof to the outside of the outer wiring, and the outer wiring. And an inner wire connecting the outer wire and the lead-out wire.

(A) is a schematic cross section of the power semiconductor module of embodiment, (b) is a schematic cross section of the control wiring board of embodiment. The schematic cross section of the submodule of an embodiment. The model top view of the chip top of the submodule of an embodiment. The schematic plan view which shows the layout of the internal element of the power semiconductor module of 1st Embodiment. The schematic plan view which shows the layout of the internal element of the power semiconductor module of 2nd Embodiment. The schematic plan view which shows the layout of the internal element of the power semiconductor module of 3rd Embodiment. The schematic plan view which shows the layout of the internal element of the power semiconductor module of 4th Embodiment. The schematic plan view which shows the layout of the internal element of the power semiconductor module of 5th Embodiment. BRIEF DESCRIPTION OF THE DRAWINGS The schematic cross section of the power semiconductor module of embodiment. (A) is a top view of the submodule mounted in the power semiconductor module of FIG. 9, (b) is a side view of the same submodule.

  Hereinafter, embodiments will be described with reference to the drawings. In the drawings, the same elements are denoted by the same reference numerals.

  FIG. 1A is a schematic cross-sectional view of a power semiconductor module (or power semiconductor device) of an embodiment.

  The power semiconductor module of the embodiment includes a metal member 21, a metal member 22, and a plurality of submodules 10 disposed between the metal member 21 and the metal member 22.

  The plate-like metal members 21 and the metal members 22 are disposed to face each other, and a plurality of sub-modules 10 are disposed in an area 70 between the metal members 21 and the metal members 22. The area 70 is an area where the plurality of submodules 10 are arranged on the metal member 21.

  A case 23 is attached to the side surface of the metal member 21, the side surface of the metal member 22, and the side of the region 70.

  FIG. 2 is a schematic cross-sectional view of the submodule 10.

  The sub module 10 includes a metal member 2, a metal member 3, one or more semiconductor elements (semiconductor chips) 1 disposed between the metal member 2 and the metal member 3, and an electrically insulating resin 6. Have.

  The semiconductor device 1 is, for example, a power semiconductor device used for power conversion, and is a switching device having a control input unit such as, for example, an IGBT (Insulated Gate Bipolar Transistor) or a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor).

  FIG. 3 is a schematic plan view of the top surface of the submodule 10. In the example shown in FIG. 3, two semiconductor elements 1 are mounted on one submodule 10.

  For example, a first main electrode 12 functioning as an emitter electrode or a source electrode is formed on one surface (surface) of the semiconductor element 1. The first main electrode 12 is bonded to the metal member 3 by a bonding material 5 shown in FIG.

  The metal member 3 has a plate-like portion 3 a and a plurality of convex portions (or columnar portions) 3 b. The plurality of convex portions 3 b are provided integrally with the plate-like portion 3 a on one surface of the plate-like portion 3 a. The first main electrode 12 (emitter electrode or source electrode) of the semiconductor element 1 is bonded to the convex portion 3 b of the metal member 3 by the bonding material 5.

  On the other surface (back surface) of the semiconductor element 1, for example, a second main electrode (not shown) functioning as a collector electrode or a drain electrode is formed. The second main electrode is joined to the metal member 2 by the joining material 4 shown in FIG.

  The semiconductor element 1 shown in FIG. 3 is a switching element, and on the surface of the switching element on which the first main electrode 12 is formed, a gate pad 13 is formed as a control input unit.

  When the semiconductor element 1 is a diode element such as, for example, a fast recovery diode (FRD), a cathode electrode is formed on the surface of the diode element, and an anode electrode is formed on the back surface. The cathode electrode is bonded to the metal member 3, and the anode electrode is bonded to the metal member 2.

  As shown in FIG. 2, the resin 6 covers the semiconductor element 1. In addition, the resin 6 covers the bonding portion between the semiconductor element 1 and the metal member 2 and the bonding portion between the semiconductor element 1 and the metal member 3.

  At least a part of the surface of the metal member 2 opposite to the surface bonded to the semiconductor element 1 is exposed without being sealed with the resin 6. At least a part of the surface of the plate-like portion 3 a of the metal member 3 opposite to the surface joined to the semiconductor element 1 is exposed without being sealed by the resin 6.

  The exposed portion of the metal member 2 is bonded to the metal member 21 by a bonding material 31 as shown in FIG. The exposed portion of the metal member 3 is bonded to the metal member 22 by a bonding material 32.

  The metal members 2, 3, 21, 22 are made of a material having excellent electrical conductivity and thermal conductivity. For example, the metal members 2, 3, 21, 22 contain copper or aluminum as a main component, and are made of copper, a copper alloy, aluminum, or an aluminum alloy.

  The bonding materials 4, 5, 31, 32 are, for example, solder, conductive adhesive, silver paste or the like.

  As a method of increasing the current of the power semiconductor module, there is a method in which a large number of semiconductor elements are arranged in parallel and pressure welding is performed at one time, but there is a problem that it is difficult to press the respective semiconductor elements evenly. On the other hand, there is a method to increase the reliability of bonding by soldering both sides of the semiconductor element, but when soldering a large number of semiconductor elements at once, the processing accuracy of the metal member and the temperature variation at the time of solder temperature rise Junction failure may occur. If even one semiconductor element has a junction failure, the semiconductor device becomes defective and the yield is deteriorated.

  On the other hand, according to the embodiment, the semiconductor device 1 of one or more small units is soldered to form a submodule 10 in which insulation by resin sealing is applied, and the submodule 10 is mounted on a large number of planes. Power semiconductor module (semiconductor device). Therefore, an electrical test of the semiconductor element 1 is performed in the state of the submodule 10, and a power semiconductor module can be manufactured using only non-defective products, and the yield can be improved. Further, by increasing the number of sub modules 10, the power semiconductor module can be easily made to have a large current capacity.

  FIG. 4 is a schematic plan view showing the layout of internal elements of the power semiconductor module of the first embodiment.

  The plurality of semiconductor elements 1 have a plurality of switching elements S and a plurality of diode elements D. In a region 70 between the metal member 21 and the metal member 22 shown in FIG. 1A, a plurality of submodules 10 are arranged in the layout illustrated in FIG.

  In the example shown in FIG. 4, the same two semiconductor elements 1 are mounted in one sub module 10. That is, the plurality of submodules 10 have a submodule 10 in which two switching elements S are mounted and a submodule 10 in which two diode elements D are mounted.

  The plurality of submodules 10 on which the switching element S is mounted, that is, the plurality of switching elements S are disposed along the periphery of the center C in the surface direction of the region 70. In FIG. 4, the peripheral circuit at the center C of the area 70 is virtually represented by a broken line. The plurality of switching elements S are disposed on the circuit. Each switching element S is disposed at a position approximately equidistant from the center C.

  A control wiring 50 is disposed in a region 70 between the metal member 21 and the metal member 22. The control wiring 50 has an outer wiring 51, an inner wiring 52, and a lead-out wiring 55.

  The outer wire 51 continuously surrounds the center C of the region 70 and is connected to the control input of the switching element S. The control input unit (gate pad) 13 shown in FIG. 3 in the switching element S is connected to the outer wiring 51 by, for example, a wire 14. Alternatively, the gate pad 13 may be connected to the outer wiring 51 by, for example, a connector.

  The inner wires 52 are arranged, for example, in a lattice pattern inside the outer wires 51, and connect the outer wires 51 and the lead-out wires 55.

  The lead-out interconnection 55 extends from the center C of the region 70 or its vicinity to the outside of the outer interconnection 51 and is led to the outside of the region 70.

  As shown in FIG. 1A, a substrate (for example, a printed wiring board) 41 is disposed in the area 70. The substrate 41 is supported on the metal member 21 by, for example, an insulating support column 42. The substrate 41 is disposed between the plurality of submodules 10 in the region 70 and in the region where the submodules 10 are not disposed.

  The outer wiring 51, the inner wiring 52, and the lead-out wiring 55 are conductor patterns (for example, copper patterns) integrally formed on the substrate 41 using the same material. The substrate 41 is, for example, a multilayer wiring substrate, and as shown in FIG. 1B, the inner wiring 52 and the lead-out wiring 55 are respectively formed in different layers. The outer wire 51 is formed, for example, in the same layer as the inner wire 52.

  As shown in FIG. 4, the plurality of submodules 10 on which the diode element D is mounted, that is, the plurality of diode elements D are arranged inside the outer wiring 51 and inside the arrangement circulation (dotted line) of the plurality of switching elements S. It is done.

  Each of the plurality of switching elements S is electrically connected to the lead-out wiring 55 at or near the center C of the region 70 through the outer wiring 51 and the inner wiring 52. The wiring lengths between each switching element S and the lead-out wiring 55 are approximately equal.

  Such a configuration makes it possible to equally supply the control signal (current) to each switching element S. This suppresses the switching variation of each switching element S and gives the power semiconductor module stable characteristics and high reliability.

  By forming the control wiring 50 including the outer wiring 51, the inner wiring 52, and the lead-out wiring 55 on the printed circuit board 41 as a conductor pattern, it is possible to improve the fixing property of the control wiring 50 and reduce the wiring. The diode element D having no control input unit can effectively utilize the space in the module by being disposed in the free space of the region 70.

  Hereinafter, other embodiments will be described. The description will be made focusing on the points different from the first embodiment, and the elements common to the first embodiment may be denoted by the same reference numerals, and the description thereof may be omitted.

  FIG. 5 is a schematic plan view showing the layout of internal elements of the power semiconductor module of the second embodiment.

  The plurality of switching elements S are disposed along the periphery of the center C of the region 70. In FIG. 5, the peripheral line at the center C of the area 70 is virtually represented by a broken line. In the example shown in FIG. 5, double circumferential circuits are formed. The plurality of switching elements S are disposed on the respective circulation lines.

  The outer wire 51 is formed between double circumferential lines (arrangement lines of the switching elements S). The inner wires 52 are arranged, for example, in a lattice pattern inside the outer wires 51, and connect the outer wires 51 and the lead-out wires 55.

  The lead-out interconnection 55 extends from the center C of the region 70 or its vicinity to the outside of the outer interconnection 51 and is led to the outside of the region 70.

  The plurality of diode elements D are disposed on the inside of the outer wiring 51 and the inside of the arrangement circulation (broken line) of the plurality of switching elements S. Furthermore, in the example shown in FIG. 5, the diode elements D are arranged also in the four corners of the region 70.

  Also in the second embodiment, each of the plurality of switching elements S is electrically connected to the lead-out wiring 55 at or near the center C of the region 70 through the outer wiring 51 and the inner wiring 52. The wiring lengths between each switching element S and the lead-out wiring 55 are approximately equal.

  Therefore, also in the second embodiment, it is possible to uniformly supply the control signal (current) to each switching element S. This suppresses the switching variation of each switching element S and gives the power semiconductor module stable characteristics and high reliability.

  In addition, by arranging the diode element D having no control input portion in the free space of the region 70, the space in the module can be effectively used.

  FIG. 6 is a schematic plan view showing the layout of internal elements of the power semiconductor module of the third embodiment.

  The power semiconductor module of the third embodiment has a submodule 10 in which the switching element S and the diode element D are mixedly mounted. In the example shown in FIG. 6, one switching element S and one diode element D are mounted on the same common submodule 10.

  The diode element D is disposed closer to the center C of the region 70 than the switching element S. The switching element S is disposed outside the region 70 as viewed from the center C than the diode element D.

  The plurality of switching elements S are arranged along the periphery of the center C of the region 70. In FIG. 6, the peripheral circuit at the center C of the area 70 is virtually represented by a broken line. The plurality of switching elements S are disposed on the circuit.

  The outer wires 51 continuously surround the center C of the region 70. The inner wires 52 are arranged, for example, in a lattice pattern inside the outer wires 51, and connect the outer wires 51 and the lead-out wires 55.

  The lead-out interconnection 55 extends from the center C of the region 70 or its vicinity to the outside of the outer interconnection 51 and is led to the outside of the region 70.

  Also in the third embodiment, each of the plurality of switching elements S is electrically connected to the lead-out wiring 55 at or near the center C of the region 70 through the outer wiring 51 and the inner wiring 52. The wiring lengths between each switching element S and the lead-out wiring 55 are approximately equal.

  Therefore, also in the third embodiment, it is possible to uniformly supply the control signal (current) to each switching element S. This suppresses the switching variation of each switching element S and gives the power semiconductor module stable characteristics and high reliability.

  FIG. 7 is a schematic plan view showing the layout of internal elements of the power semiconductor module of the fourth embodiment.

  The power semiconductor module of the fourth embodiment also has the submodule 10 in which the switching element S and the diode element D are mixedly mounted as in the third embodiment. In the example shown in FIG. 7, one switching element S and one diode element D are mounted on the same common submodule 10.

  In the third embodiment, the switching element S is disposed closer to the center C of the region 70 than the diode element D, contrary to the arrangement shown in FIG. The diode element D is disposed outside the region 70 as viewed from the center C than the switching element S.

  The control wiring 56 has a pad portion 58, a connection wiring 57, and a lead-out wiring 55.

  The pad portion 58 is disposed in an area inside the plurality of switching elements S (an area including the center C of the area 70).

  The lead-out wiring 55 is connected to the pad portion 58 at or near the center C of the region 70, extends from the connection portion to the outside of the outer wiring 51, and is led to the outside of the region 70.

  The pad portion 58 and the lead-out wiring 55 are conductor patterns (for example, copper patterns) integrally formed on the substrate 41 with the same material as in the above embodiment.

  The connection wiring 57 is a wire or a connector that connects the control input unit (gate pad) 13 of each switching element S to the pad unit 58.

  The plurality of switching elements S are arranged around the center C of the region 70 and around the pad portion 58. In FIG. 7, the peripheral circuit at the center C of the area 70 is virtually represented by a broken line. The plurality of switching elements S are disposed on the circuit.

  Each of the plurality of switching elements S is electrically connected to the lead-out wiring 55 at or near the center C of the region 70 through the connection wiring 57 and the pad portion 58. The wiring lengths between each switching element S and the lead-out wiring 55 are approximately equal.

  Therefore, also in the fourth embodiment, it is possible to equally supply the control signal (current) to each switching element S. This suppresses the switching variation of each switching element S and gives the power semiconductor module stable characteristics and high reliability.

  FIG. 8 is a schematic plan view showing the layout of internal elements of the power semiconductor module of the fifth embodiment.

  The configuration of the submodule 10 and the layout of the plurality of semiconductor devices 1 in the fifth embodiment are the same as those of the embodiment shown in FIG. That is, diode element D is arranged closer to center C of region 70 than switching element S. The switching element S is disposed outside the region 70 as viewed from the center C than the diode element D. The layout of the control wiring 50 is also the same as in FIG.

  In the embodiment shown in FIG. 8, a water cooling mechanism for cooling the semiconductor element 1 is provided. For example, the water cooling channel 61 is disposed in the area 70 so as to be in direct or indirect contact with the semiconductor element 1.

  In FIG. 8, the arrow A represents the inflow direction of water into the water cooling channel 61, and the arrow B represents the outflow direction of water from the water cooling channel 61.

  In the operation of the power converter, the heat generation density of the switching element S and the heat generation density of the diode element D may be different. For example, when the switching element S has a heat generation density higher than that of the diode element D, the switching element S should be disposed upstream of the water cooling channel 61 than the diode element D, as shown in FIG. Thus, the cooling performance of the switching element S having a high heat generation density can be improved, and soaking of heat as a package (module) becomes possible. Thereby, the utilization factor of each semiconductor element 1 can be increased, and a large current can be realized.

FIG. 9 is a schematic cross-sectional view of a power semiconductor module according to another embodiment.
Fig.10 (a) is a top view of the submodule mounted in the power semiconductor module of FIG. 9, FIG.10 (b) is a side view of the same submodule.

  The power semiconductor module shown in FIG. 9 connects the metal member 21, the plurality of submodules 10 mounted on the metal member 21, the main circuit wiring 80, and the plurality of submodules 10 to the main circuit wiring 80. And a case 100 made of an insulating resin.

  The metal member 21 has a plate-like portion 21 a and a plurality of convex portions (or columnar portions) 21 b. The plurality of convex portions 21 b are provided integrally with the plate-like portion 21 a on one surface of the plate-like portion 21 a. The sub module 10 is mounted on the convex portion 21 b.

  The lower end portion of the case 100 is bonded to the plate-like portion 21 a of the metal member 21, and a region 70 is formed inside the metal member 21 and the case 100 as a sealed space. In the area 70, a plurality of submodules 10, a plurality of bus bars 20, and a main circuit wiring 80 are disposed.

  The sub module 10 includes the metal member 4, the metal member 3 disposed above the metal member 4, and the semiconductor element 1 disposed between the metal member 4 and the metal member 3 as in the embodiment described above. And an electrically insulating resin 6.

  A main circuit wiring 80 is disposed between the plurality of submodules 10. The main circuit wiring 80 is a plate-like metal wiring, and is, for example, a copper wiring. The main circuit wiring 80 is provided in a resin 90 formed on the metal member 21, and is held on the metal member 21 by the resin 90. A portion of the main circuit wiring 80 protrudes outside the case 100 as a main electrode terminal.

  The bus bar 20 is joined to the plate-like portion 3 b of the metal member 3 of the sub module 10. Metal feet 20 a and 20 b are provided at both ends of the bus bar 20. The metal feet 20 a and 20 b are, for example, copper brazed to the bus bar 20.

  The metal foot portion 20 a at one end of the bus bar 20 is joined or screwed to the side surface of the metal member 3. Alternatively, the metal foot 20 a may be joined or screwed to the upper surface of the metal member 3.

  The metal foot portion 20 b at the other end of the bus bar 20 is joined or screwed to the main circuit wiring 80. The resin 90 covers and protects the junction between the main circuit wiring 80 and the metal foot 20b.

  The bus bar 20 is made of, for example, a conductive material such as copper, 42 alloy (alloy of nickel and iron), alloy of nickel and chromium, or the like. The bus bar 20 is formed in, for example, a plate-like shape or a shape obtained by bending a plate-like member in a zigzag manner.

The electrical resistance of the bus bar 20 is higher than the electrical resistance of the main circuit wiring 80. In bus bar 20, the cross-sectional area S [cm ² ] of the cross section perpendicular to the direction of current flow and the length (current path length) L [cm] are compared to the electrical resistance R [Ω] required for bus bar 20. It is determined by the following equation.
R = ρ ₀ × L / S [Ω] (ρ ₀ : volume resistivity [Ω cm])

  For example, by using a material having a volume resistivity higher than that of the main circuit wiring 80 as the material of the bus bar 20, the electric resistance of the bus bar 20 is made higher than the electric resistance of the main circuit wiring 80. The material of the main circuit wiring 80 is desirably a material having a volume resistivity smaller than that of the bus bar 20 in order to reduce the electrical resistance and the heat generation. For example, the material of the main circuit wiring 80 is copper, and the material of the bus bar 20 is a 42 alloy (an alloy of nickel and iron), or an alloy of nickel and chromium.

  One submodule 10 is electrically connected to the main circuit wiring 80 by at least one bus bar 20. The plurality of sub-modules 10 are electrically connected in parallel between the metal member 21 and the main circuit wiring 80 via the plurality of bus bars 20. The current flows in the vertical direction (stacking direction) of the submodule 10. The current flows between the metal member 21 and the main circuit wiring 80 through the submodule 10 and the bus bar 20.

  A short circuit current may flow in the semiconductor device 1 and the Joule heat generated at that time may destroy the semiconductor device 1 and lead to the rupture of the submodule 10 if the pressure in the submodule 10 is increased.

  Therefore, according to the embodiment shown in FIG. 9, by connecting the bus bar 20 having a high electric resistance value to the sub module 10 in series, energy consumption is shared between the bus bar 20 and the semiconductor element 1. Joule heat generated can be suppressed.

In normal operation (normal operation), since current flows in each bus bar 20, assuming that the total current flowing in the plurality of submodules 10 is Itotal, the Joule heat Q generated per one bus bar 20 is Q = R × (Itotal / number of parallel connections) ² [J] (R is the electrical resistance [Ω] of the bus bar 20).

A current flows in the submodule 10 including the failed semiconductor device 1 and no current flows in the normal submodule 10. The Joule heat Q ′ generated in the bus bar 20 connected to the failed submodule 10 is Q ′ = R × (Itotal) ² [J].

The loss generation effect on the current value flowing to the submodule 10 in normal operation is Q / Q ′ = (1 / parallel number) ² compared to the failure time, and the loss generation is reduced in normal operation more than the failure time. can do.

  Due to the parallel connection effect of the plurality of bus bars 20, the bus bar 20 connected to the failed sub module 10 consumes energy at the time of failure without deteriorating the efficiency of the sub module 10 at the time of normal operation. The generated Joule heat can be suppressed, and the rupture of the submodule 10 can be suppressed.

  That is, at the time of failure, a short circuit current flows only to the failed sub module 10 and the bus bar 20 connected in series to the sub module 10, and a large Joule heat can be generated in the bus bar 20. Thus, the Joule heat generated in the semiconductor element 1 through which the short circuit current flows is reduced, and the destruction can be suppressed.

  Since the plurality of bus bars 20 are connected in parallel between the metal member 21 and the main circuit wiring 80, the value of the current flowing through each of the bus bars 20 during normal operation is a value obtained by dividing the output current of the power semiconductor module by the number of parallel Joule heat during normal operation can be suppressed.

  While certain embodiments of the present invention have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and the gist of the invention, and are included in the invention described in the claims and the equivalent scope thereof.

  DESCRIPTION OF SYMBOLS 1 ... Semiconductor element, 2 ... Metal member, 3 ... Metal member, 10 ... Submodule, 21 ... Metal member, 22 ... Metal member, 50 ... Control wiring, 51 ... Outer wiring, 52 ... Inner wiring, 55 ... Extraction wiring, 56: control wiring, 57: connection wiring, 58: pad portion, 61: water cooling flow path, S: switching element, D: diode element

Claims (9)

A first metal member,
A plurality of sub-modules disposed on the first metal member, a second metal member joined to the first metal member, and a third metal member disposed above the second metal member; A plurality of sub-modules each having a semiconductor element disposed between the second metal member and the third metal member and joined to the second metal member and the third metal member;
Control wiring disposed on the first metal member;
Equipped with
The plurality of semiconductor elements are disposed along the periphery of the center of the region in which the plurality of sub-modules are disposed, and have a plurality of switching elements having a control input unit,
The control wiring is
An outer wire surrounding the center of the region and connected to the control input of the switching element;
A lead-out wire extending from the center or the vicinity thereof to the outside of the outer wire;
An inner wire disposed inside the outer wire and connecting the outer wire and the lead-out wire;
Power semiconductor module having a.   The power semiconductor module according to claim 1, wherein the plurality of semiconductor elements further include a diode element disposed inside the outer wiring. The switching element and the diode element are mounted on the same submodule as the plurality of semiconductor elements,
The power semiconductor module according to claim 1, wherein the diode element is disposed closer to the center of the region than the switching element.   The power semiconductor module according to claim 2 or 3, further comprising a water cooling mechanism arranged such that the switching element is upstream of the water cooling flow path than the diode element.   The power semiconductor module according to any one of claims 1 to 4, wherein the control wiring is a conductor pattern formed on a substrate. A first metal member,
A plurality of sub-modules disposed on the first metal member, a second metal member joined to the first metal member, and a third metal member disposed above the second metal member; A plurality of sub-modules each having a semiconductor element disposed between the second metal member and the third metal member and joined to the second metal member and the third metal member;
Control wiring disposed on the first metal member;
Equipped with
The plurality of semiconductor elements are disposed along the periphery of the center of the region in which the plurality of sub-modules are disposed, and have a plurality of switching elements having a control input unit,
The control wiring is
A pad portion disposed inside the plurality of switching elements;
A connection wire connecting the control input portion of the switching element and the pad portion;
A lead-out wire connected to the pad portion at or near the center;
Power semiconductor module having a.   The power semiconductor module according to claim 6, wherein the plurality of semiconductor elements further include a diode element disposed outside the switching element.   The power semiconductor module according to claim 7, wherein the switching element and the diode element are mounted on the same sub-module. Main circuit wiring disposed in the area;
A plurality of bus bars connected to the plurality of third metal members and the main circuit wiring, and having a higher electrical resistance than the main circuit wiring;
The power semiconductor module according to any one of claims 1 to 8, further comprising: