JP2019050237A - Manufacturing method for element chip - Google Patents

Abstract

An element chip manufacturing method that suppresses debris residue in plasma dicing is provided. In a manufacturing method of a semiconductor chip, a back surface of a semiconductor wafer is held on a dicing tape. Next, the surface 6A is covered with a mask 24 including a water-insoluble lower layer mask 24A and a water-soluble upper layer mask 24B. Next, the mask 24 is irradiated with laser light to form an opening in the mask 24 to expose the divided region 16. Next, the semiconductor wafer 12 is brought into contact with water, and the lower layer mask 24 </ b> A is left while removing the upper layer mask 24 </ b> B covering the element region 14. Next, the semiconductor wafer 12 is exposed to the first plasma, and the divided regions 16 exposed in the openings are etched until reaching the back surface 4A, whereby the semiconductor wafer 12 is separated into a plurality of semiconductor chips 2. Next, the lower layer mask 24A remaining on the surface 6A of the plurality of semiconductor chips 2 is removed. [Selection] Figure 1I

Description

  The present invention relates to a method for manufacturing an element chip.

  Plasma etching may be used to manufacture element chips. Applications of plasma etching are wide, and for example, a method called plasma dicing for separating a substrate into individual pieces is known as one of them. In plasma dicing, a substrate having a plurality of element regions defined by the divided regions is subjected to plasma etching of the divided regions from one surface of the substrate to the other surface, thereby dividing the substrate into individual device chips. Turn into. In such plasma dicing, it is necessary to plasma-etch only the divided regions, that is, the element region needs to be protected from plasma. Therefore, before plasma etching, a mask having plasma resistance is formed on the entire surface of the substrate, and the mask of the divided region is removed while leaving the mask of the element region, thereby forming the mask in a necessary region. At the same time, patterning is also performed in which a part of the protective film and a part of the divided region under the protective film is cut by laser processing or the like. Thus, a region to be plasma-etched is defined, and accurate plasma dicing is performed (see, for example, Patent Document 1).

U.S. Pat. No. 8,703,581

  When plasma dicing a substrate having a metal layer, processing dust called debris generated by the ablation phenomenon scatters when patterning (laser grooving) is performed in the protective film and the metal layer below it in patterning. There is. Most of the scattered debris can be removed by performing plasma cleaning or the like in a later process, but some debris having a large particle size remains without being removed, which may reduce device reliability and yield. There is.

  An object of the present invention is to provide a method for manufacturing an element chip in which debris remains in plasma dicing.

  The present invention provides a substrate including a plurality of element regions and divided regions defining the element regions, the substrate including a first surface and a second surface opposite to the first surface, and the substrate The second surface of the substrate is held by a holding sheet, the first surface of the substrate is covered with a mask including a water-insoluble lower layer and a water-soluble upper layer, and the mask is irradiated with laser light. Thereby forming an opening in the mask to expose a divided region of the substrate, contacting the substrate with water or an aqueous solution, leaving the lower layer while removing the upper layer of the mask covering the element region, The substrate is exposed to a first plasma, and the divided regions exposed to the openings are etched until reaching the second surface, whereby the plurality of element chips are separated into pieces, and the plurality of element chips are the holding sheet. In the state held in the Removing the mask remaining on the surface of the element chip, the plurality of element chips removed the mask comprises a state of being held by the holding sheet, to provide a manufacturing method of the element chip.

  According to this method, since the water-soluble upper layer is formed on the first surface of the substrate before the laser grooving process, even if debris scatters and adheres to the upper layer by the laser grooving process, At the same time, debris can be removed. Therefore, since the debris residue in plasma dicing can be suppressed, processing defects due to debris in plasma dicing can be suppressed, and the reliability of the element chip as a product can be improved.

  The removal of the mask from the surface of the plurality of element chips may include ashing with a second plasma.

  According to this method, the water-insoluble lower layer can be easily removed by ashing with the second plasma.

  The coating with the mask is performed by applying a water-soluble resin raw material liquid after applying a water-insoluble resin raw material liquid to the first surface of the substrate held by the holding sheet and forming the lower layer. Forming an upper layer may be included.

  According to this method, since the upper layer and the lower layer can be formed by applying the raw material liquid, the upper layer and the lower layer can be easily formed.

  Prior to the holding by the holding sheet, a protective tape comprising a base material and a water-insoluble adhesive layer is attached to the first surface via the adhesive layer, and the mask is covered with the protective tape. The base material may be peeled from the substrate, and the adhesive layer may be left on the first surface of the substrate to form the lower layer, and the upper layer may be formed on the lower layer.

  According to this method, since the adhesive layer of the protective tape can be used as a lower layer, the mask forming process can be simplified.

  According to the present invention, in the element chip manufacturing method, since the water-soluble upper layer is formed on the first surface of the substrate before the laser grooving process, the debris scatters and adheres to the upper layer by the laser grooving process. Even so, debris can be removed together with the upper layer by washing with water. Therefore, debris residue in plasma dicing can be suppressed.

Sectional drawing which shows the 1st preparatory process of the manufacturing method of the element chip which concerns on 1st Embodiment of this invention. Sectional drawing which shows the 2nd preparatory process of the manufacturing method of an element chip Sectional drawing which shows the protection process of the manufacturing method of an element chip Sectional drawing which shows the thinning process of the manufacturing method of an element chip Sectional drawing which shows the 1st holding process of the manufacturing method of an element chip Sectional drawing which shows the 2nd holding process of the manufacturing method of an element chip Sectional drawing which shows the 1st mask formation process of the manufacturing method of an element chip | tip. Sectional drawing which shows the 2nd mask formation process of the manufacturing method of an element chip | tip. Sectional drawing which shows the patterning process of the manufacturing method of an element chip Sectional drawing which shows the cleaning process of the manufacturing method of an element chip Sectional drawing which shows the isolation | separation process of the manufacturing method of an element chip Sectional drawing which shows the ashing process of the manufacturing method of an element chip Partial enlarged sectional view showing details of FIG. 1L Schematic diagram of dry etching equipment Schematic configuration diagram of a cluster apparatus that executes a method for manufacturing an element chip Sectional drawing which shows the 1st preparatory process of the manufacturing method of the element chip which concerns on 2nd Embodiment of this invention. Sectional drawing which shows the 2nd preparatory process of the manufacturing method of an element chip Sectional drawing which shows the protection process of the manufacturing method of an element chip Sectional drawing which shows the thinning process of the manufacturing method of an element chip Sectional drawing which shows the 1st holding process of the manufacturing method of an element chip Sectional drawing which shows the 1st mask formation process of the manufacturing method of an element chip | tip. Sectional drawing which shows the 2nd mask formation process of the manufacturing method of an element chip | tip. Sectional drawing which shows the patterning process of the manufacturing method of an element chip Sectional drawing which shows the cleaning process of the manufacturing method of an element chip Sectional drawing which shows the isolation | separation process of the manufacturing method of an element chip Sectional drawing which shows the ashing process of the manufacturing method of an element chip

  Embodiments of the present invention will be described below with reference to the accompanying drawings.

(First embodiment)
1A to 1L show a manufacturing process of the semiconductor chip (element chip) 2 according to the first embodiment of the present invention. Referring to FIG. 1L which is a final process drawing and FIG. 2 which is a detailed view of the semiconductor chip 2, the manufactured semiconductor chip 2 includes a semiconductor layer 4 and a wiring layer 6 formed on the semiconductor layer 4. And a protective film 8 formed on the wiring layer 6 and a bump 10 as an electrode. Although FIG. 2 is a cross-sectional view, hatching is omitted for clarity of illustration. Solder is generally used for the bump 10, and the solder is formed by a plating method, a printing method, or a vapor deposition method. A UBM film (under bump metal film) 9 is formed on the protective film 8 of the semiconductor chip 2, and the bumps 10 are formed on the UBM film 9. That is, the UBM film 9 is a base layer of the bump 10, basically has electrical conductivity, and is electrically connected to the metal wiring 6 </ b> B in the wiring layer 6. In the wiring layer 6, such metal wiring 6B, an insulating film 6C, and a transistor 6D are provided. The material of the metal wiring 6B can be, for example, Cu, Al, Al alloy, W, or the like. The material of the insulating film 6C can be SiO2 _, SiN, SiOC, Low-k material, or the like. The metal contained in the bump 10 may be Cu, an alloy of Cu, Sn, and Ag, an alloy of Ag, Sn, Au, Al, an Al alloy, or the like. The shape of the bump 10 is not particularly limited, and may be a prism, cylinder, mountain, ball, or the like. The arrangement and number of the bumps 10 are not particularly limited, and are appropriately set according to the purpose. Here, the convex bump 10 as the electrode may be a concave pad electrode. The wiring layer 6 is provided with a metal layer 6E called a TEG (Test Element Group). More specifically, the metal layer 6E has an element region 14 (see FIG. 1B) and a divided region 16 (see FIG. 1B). And is provided over.

In the present embodiment, the bump 10 is, for example, a Cu pillar having a diameter of 40 μm and a height of 50 μm. Further, the wiring layer 6 is a wiring layer having a thickness of about 5 μm including, for example, a Low-k material and Cu wiring. The semiconductor layer 4 is a semiconductor layer made of Si and having a thickness of 70 μm, for example. Further, an insulating film layer made of SiO _{2 having} a thickness of about 1 μm may be provided on the opposite side of the semiconductor layer 4 from the wiring layer 6, for example.

  In the first preparation step shown in FIG. 1A, a semiconductor wafer (substrate) 12 is prepared. As shown in FIG. 1A, the semiconductor wafer 12 includes a semiconductor layer 4 and a wiring layer 6 formed on the semiconductor layer 4.

  In the second preparation step shown in FIG. 1B, the protective film 8 and the bumps 10 are formed on the surface (first surface) 6A of the wiring layer 6 of the semiconductor wafer 12. The semiconductor wafer 12 that has undergone this process includes a plurality of element regions 14 on which bumps 10 are formed, and divided regions 16 that are adjacent to the periphery of each element region 14. In other words, the individual element regions 14 are defined by the divided regions 16.

  In the protection step shown in FIG. 1C, a BG (back grind) tape 20 is attached to the front surface 6A of the semiconductor wafer 12 for protection during grinding of the back surface (second surface) 4A. The BG tape 20 is a film including an adhesive layer 20A and a resin base layer 20B. That is, the adhesive layer 20A is attached to the surface 6A of the semiconductor wafer 12, and the surface 6A of the semiconductor wafer 12 is protected by the base material layer 20B. Since the BG tape 20 is cut according to the outer shape of the semiconductor wafer 12 after being attached to the semiconductor wafer 12 or before being attached, the handling property of the semiconductor wafer 12 is not impaired. The BG tape 20 is an example of a protective tape.

  1D, the semiconductor layer 4 is ground from the back surface (second surface) 4A side of the semiconductor wafer 12 by a grinding apparatus (not shown). The semiconductor wafer 12 is thinned to a predetermined thickness by grinding the semiconductor layer 4.

  In the first holding step shown in FIG. 1E, a dicing tape (holding sheet) 22 is attached to the back surface 4A of the semiconductor wafer 12. The dicing tape 22 of the present embodiment is a film composed of an adhesive layer 22A made of an acrylic pressure-sensitive adhesive and a resin base layer 22B. The adhesive layer 22A is attached to the back surface 4A of the semiconductor wafer 12, and the semiconductor wafer 12 is held by the base material layer 22B. Further, a frame 22C is attached to the dicing tape 22 from the viewpoint of handling properties.

  In the second holding step shown in FIG. 1F, the BG tape 20 is peeled from the semiconductor wafer 12. In the state where the BG tape 20 is peeled off, the bumps 10 are exposed on the surface 6 </ b> A of the semiconductor wafer 12.

  In the first mask formation step shown in FIG. 1G, a lower layer mask 24A having plasma resistance is formed on the surface 6A of the semiconductor wafer 12. The lower layer mask 24A prevents the surface of the element from being exposed to plasma when plasma dicing is performed in an individualization process described later. The lower layer mask 24A is made of a water-insoluble material and is not removed by water washing in a cleaning process described later. For example, the material of the lower layer mask 24A of this embodiment is polyolefin. Instead of this, for example, an ethylene vinyl acetate copolymer may be used. In the present embodiment, the lower layer mask 24A is formed by applying a raw material liquid to the surface 6A of the semiconductor wafer 12 by spin coating. However, the formation method of the lower layer mask 24A is not limited to the spin coating method, and may be a spray coating method in which the raw material liquid is sprayed on the surface 6A of the semiconductor wafer 12 in a mist form.

  In the second mask formation step shown in FIG. 1H, the upper layer mask 24B is formed on the upper surface of the lower layer mask 24A. The upper layer mask 24B prevents processing waste (debris) generated along with laser grooving in a patterning process described later from directly attaching to the surface of the element. The upper layer mask 24B is made of a water-soluble material, and is removed by washing in a washing process described later. For example, the material of the upper layer mask 24B of this embodiment is polyvinyl alcohol. Instead of this, for example, a water-soluble polyester may be used. In the present embodiment, the lower layer mask 24A is formed by applying a raw material liquid to the upper surface of the lower layer mask 24A by a spin coating method. However, the formation method of the lower layer mask 24A is not limited to the spin coating method, and may be a spray coating method in which the raw material liquid is sprayed on the upper surface of the lower layer mask 24A in a mist form. Hereinafter, the lower layer mask 24A and the upper layer mask 24B are also simply referred to as a mask 24.

  In the patterning step shown in FIG. 1I, the mask 24 and the semiconductor wafer 12 are cut by laser grooving to form an exposed portion 18 in a portion corresponding to the divided region 16 (see FIG. 1H). Specifically, the exposed portion 18 is formed by cutting the wiring layer 6, the protective film 8, and the mask 24. At this time, the semiconductor layer 4 may be partially cut or not cut, but not cut to the back surface 4A. The wiring layer 6 is provided with a metal layer such as an insulating film 6C and a metal layer (TEG) 6E, which are also removed by a laser to form an exposed portion 18.

  Specifically, processing by laser grooving can be performed under the following conditions. As the laser light source, a nanosecond laser having a UV wavelength (for example, 355 nm) is used. Then, the laser beam is irradiated twice to the divided region 16 (see FIG. 1H) at a pulse period of 40 kHz, an output of 0.3 W, and a scanning speed of 200 mm / second, and the mask 24 is removed. Thereafter, the divided region 16 is irradiated once with a pulse period of 25 kHz, an output of 1.7 W, and a scanning speed of 100 mm / second, and the protective film 8 and the wiring layer 6 are removed. By performing laser irradiation for removing the mask 24 twice under a low output condition, peeling (delamination) of the mask 24 from the semiconductor wafer 12 can be suppressed. Further, by performing laser irradiation for removing the wiring layer 6 under a high output condition, the wiring layer 6 can be removed even when the wiring layer 6 includes a metal layer (TEG) 6E made of Cu.

As shown in FIG. 1I, when processing a metal layer (TEG) 6E and an insulating film 6C (PI, PBO, SiN, SiO ₂ , low-k, etc.) by laser grooving, processing dust (debris) D is generated. The debris D includes the TEG metal, Si, SiOx, and the like. Therefore, the molten debris D may adhere to the exposed portion 18, and the scattered debris D may adhere to the surface of the upper mask 24B. In particular, a large amount of debris D tends to adhere to a portion where there is a lot of TEG metal and in the vicinity thereof. If the debris D adhering to the surface of the upper mask 24B by laser grooving remains without being removed, it will have an adverse effect in the subsequent plasma dicing process, causing a so-called micromask.

  In the cleaning step shown in FIG. 1J, debris D is removed together with upper layer mask 24B by washing with water. As described above, the two-layer structure of the lower layer mask 24A and the upper layer mask 24B is adopted, and the lower layer mask 24A does not dissolve in water. Therefore, the lower layer mask 24A can be left as a mask for the subsequent plasma etching after washing with water. By removing the debris D in this manner, the surface roughness of the semiconductor chip 2 in the plasma dicing process can be suppressed as will be described later. Preferably, the water washing is warm water, and more preferably performed while bubbling nitrogen in order to increase residue removal efficiency. An aqueous solution may be used instead of water.

  Similarly, in the drying step shown in FIG. 1J, blow drying with nitrogen or the like is performed after the cleaning step. Instead, spin drying in which a cleaning liquid such as water is shaken off by centrifugal force may be performed by spinning a mounting table (not shown) on which the semiconductor wafer 12 is mounted.

  In the singulation (plasma dicing) step shown in FIG. 1K, the semiconductor wafer 12 is singulated by plasma etching (plasma dicing) while the back surface 4A of the semiconductor wafer 12 is held by the dicing tape 22.

  FIG. 3 shows an example of the dry etching apparatus 50 used in this step. A dielectric window (not shown) is provided on the top of the chamber 52 of the dry etching apparatus 50, and an antenna 54 as an upper electrode is disposed above the dielectric window. The antenna 54 is electrically connected to the first high frequency power supply unit 56. On the other hand, a stage 60 on which the semiconductor wafer 12 is disposed is disposed on the bottom side of the processing chamber 58 in the chamber 52. The stage 60 has a coolant channel (not shown) formed therein, and the stage 60 is cooled by circulating the coolant through the coolant channel. The stage 60 also functions as a lower electrode and is electrically connected to the second high frequency power supply unit 62. The stage 60 includes an electrostatic chucking electrode (ESC electrode) (not shown) so that the dicing tape 22 (that is, the semiconductor wafer 12) placed on the stage 60 can be electrostatically chucked to the stage 60. The stage 60 is provided with a cooling gas hole (not shown) for supplying a cooling gas. By supplying a cooling gas such as helium from the cooling gas hole, the stage 60 is electrostatically attracted to the stage 60. The semiconductor wafer 12 can be cooled. The gas inlet 64 of the chamber 52 is fluidly connected to an etching gas source 66, and the exhaust port 68 is connected to a vacuum exhaust unit 70 including a vacuum pump for evacuating the chamber 52.

In this singulation process, the semiconductor wafer 12 is placed on the stage 60 via the dicing tape 22, the inside of the processing chamber 58 is evacuated by the evacuation unit 70, and, for example, SF is supplied from the etching gas source 66 into the processing chamber 58. _The etching gas which is ₆ is supplied. Then, the inside of the processing chamber 58 is maintained at a predetermined pressure, high-frequency power is supplied from the first high-frequency power supply unit 56 to the antenna 54, first plasma is generated in the processing chamber 58, and the semiconductor wafer 12 is irradiated. . At this time, the semiconductor layer 4 of the semiconductor wafer 12 exposed at the exposed portion 18 is removed by the physicochemical action of radicals and ions in the first plasma. The semiconductor wafer 12 is formed on each individual semiconductor chip 2 through this individualization step.

More specifically, the singulation process includes (1) chucking process, (2) cleaning process, (3) surface oxide removal process, (4) plasma dicing process, and (5) SiO ₂ etching process. Can be included.

(1) Chucking process In the chucking process, before the high energy plasma is generated in the chamber 52, the low energy plasma is generated, and the semiconductor wafer 12 and the dicing tape 22 placed on the stage 60 are The stage 60 is surely electrostatically attracted. As a result, the dicing tape 22 with poor heat resistance is less susceptible to thermal damage associated with plasma processing. For example, weak plasma may be generated for about 10 seconds by adjusting the chamber pressure to 8 Pa while supplying Ar gas at 100 sccm and applying RF power of 150 W to the antenna 54. At this time, while adjusting the temperature of the stage 60 to 20 ° C. or less, a DC voltage of 3 kV is applied to the ESC electrode, and He of 50 to 200 Pa is supplied between the dicing tape 22 and the stage 60 as a cooling gas. By doing so, the semiconductor wafer 12 and the dicing tape 22 can be cooled.

(2) Cleaning process Debris generated by laser grooving and not completely removed by the cleaning process (for example, metal debris), amorphous silicon layer or silicon oxide layer generated by melting Si by laser grooving, and the above-described lower mask ( For example, in order to remove a layer in which a melt of polyolefin or ethylene vinyl acetate copolymer) is mixed, a cleaning process using plasma may be performed. The plasma used in the cleaning process is preferably a gas species that can remove the silicon and silicon oxide layers. For example, while supplying a mixed gas of SF ₆ and O ₂ at 200 sccm, the chamber pressure is adjusted to 5 Pa, What is necessary is just to expose to the plasma produced | generated by applying 1000-2000W RF electric power to the antenna 54 for about 1-2 minutes. At this time, the cleaning effect can be enhanced by applying LF power of about 150 W to the lower electrode of the stage 60. In order to reduce thermal damage due to plasma generated in the cleaning process, it is preferable that the semiconductor wafer 12 and the dicing tape 22 are cooled in the cleaning process. For example, while adjusting the temperature of the stage 60 to 20 ° C. or less, a DC voltage of 3 kV is applied to the ESC electrode, and 50 to 200 Pa of He is supplied between the dicing tape 22 and the stage 60 as a cooling gas. Thus, the semiconductor wafer 12 and the dicing tape 22 can be cooled.

(3) Surface Oxide Removal Step When cleaning is performed with oxygen-containing plasma in the cleaning step, the cleaned silicon surface may be oxidized. Therefore, a surface oxide removal step may be provided in order to remove the oxide film layer on the silicon surface generated in the cleaning step. The plasma used in the surface oxide removal step is preferably a gas species that can remove the silicon oxide layer. For example, while supplying SF ₆ at 200 sccm, the chamber pressure is adjusted to 8 Pa, and the antenna 54 is set to 2000 to 2000. It may be exposed to plasma generated by applying RF power of 5000 W for about 2 to 10 seconds. At this time, the surface oxide removal effect can be enhanced by applying LF power of about 500 W to the lower electrode of the stage 60. Further, in order to reduce thermal damage due to plasma generated in the surface oxide removal step, it is preferable that the semiconductor wafer 12 and the dicing tape 22 are cooled in the surface oxide removal step. For example, while adjusting the temperature of the stage 60 to 20 ° C. or less, a DC voltage of 3 kV is applied to the ESC electrode, and 50 to 200 Pa of He is supplied between the dicing tape 22 and the stage 60 as a cooling gas. Thus, the semiconductor wafer 12 and the dicing tape 22 can be cooled.

(4) Plasma dicing process In the plasma dicing process, the semiconductor layer 4 made of silicon is removed by the BOSCH method. In the BOSCH method, plasma for depositing a protective film and plasma for etching silicon are alternately generated. The plasma for depositing the protective film is generated for about 2 to 10 seconds by adjusting the chamber pressure to 20 Pa and supplying RF power of 2000 to 5000 W to the antenna 54 while supplying C ₄ F ₈ at 300 sccm. Just do it. The plasma for etching silicon is, for example, adjusting the chamber pressure to 20 Pa while supplying SF ₆ at 600 sccm, applying RF power of 2000 to 5000 W to the antenna 54, and LF of 50 to 500 W to the lower electrode. What is necessary is just to generate electric power for about 5 to 20 seconds. In order to suppress notching in the processed shape of the semiconductor layer 4, the power applied to the lower electrode may be pulsed. The semiconductor layer 4 can be removed by repeating such generation of plasma for depositing a protective film and generation of plasma for etching silicon, for example, for about 20 cycles. In order to reduce thermal damage due to plasma generated in the plasma dicing process, it is preferable that the semiconductor wafer 12 and the dicing tape 22 be cooled in the plasma dicing process. For example, while adjusting the temperature of the stage 60 to 20 ° C. or less, a DC voltage of 3 kV is applied to the ESC electrode, and 50 to 200 Pa of He is supplied between the dicing tape 22 and the stage 60 as a cooling gas. Thus, the semiconductor wafer 12 and the dicing tape 22 can be cooled. In addition, when the semiconductor layer 4 has a predetermined thickness or less, silicon may be continuously etched without using the BOSCH method.

(5) SiO ₂ etching process When the semiconductor wafer 12 is provided with SiO ₂ or DAF (die attach film) in the lower layer of the semiconductor layer 4, after the plasma dicing process, the etching conditions are switched to process these SiO ₂ and DAF. May be. The plasma used in the SiO ₂ etching process is preferably a gas species that can remove the silicon oxide layer. For example, while supplying a mixed gas of Ar and C ₄ F ₈ at 300 sccm, the chamber pressure is adjusted to 1 Pa. Then, it may be exposed to plasma generated by applying RF power of 500 to 2000 W to the antenna 54 for about 2 to 8 minutes. At this time, the SiO ₂ etching effect can be enhanced by applying LF power of about 500 to 1500 W to the lower electrode provided in the stage 60. Further, in order to reduce the thermal damage by plasma to be generated in the SiO ₂ etching process, preferably the semiconductor wafer 12 and the dicing tape 22 it is cooled in the SiO ₂ etching process. For example, while adjusting the temperature of the stage 60 to 20 ° C. or less, a DC voltage of 3 kV is applied to the ESC electrode, and 50 to 200 Pa of He is supplied between the dicing tape 22 and the stage 60 as a cooling gas. Thus, the semiconductor wafer 12 and the dicing tape 22 can be cooled.

  In the ashing process shown in FIG. 1K, the inside of the processing chamber 58 shown in FIG. 3 is evacuated by the evacuation unit 70 and an etching gas containing, for example, oxygen is supplied from the etching gas source 66 into the processing chamber 58. Then, the inside of the processing chamber 58 is maintained at a predetermined pressure, high frequency power is supplied from the first high frequency power supply unit 56 to the antenna 54, second plasma is generated in the processing chamber 58, and the semiconductor wafer 12 is irradiated. That is, the surface of the lower layer mask 24A is exposed to the second plasma. At this time, the lower layer mask 24A is removed by the physicochemical action of radicals and ions in the second plasma.

In order to remove the remaining film and debris of the lower layer mask 24A in the ashing process, a reactive gas such as CF ₄ is added to an ashing gas such as oxygen to enhance the removal effect of Si, SiOx, and the mask cured layer. It is preferable. Further, in order to remove the metal component, it is preferable to perform plasma etching under conditions where the Bias power is increased and the ionicity (sputtering property) is increased. As the plasma used in the ashing process, it is preferable to use a gas species that can remove the hardened layer and the altered layer on the outermost layer of the lower layer mask 24. For example, a mixed gas of O ₂ and CF ₄ can be used. In this process, for example, plasma is generated by adjusting the chamber pressure to 1 Pa and supplying RF power of 2000 to 5000 W to the antenna 54 while supplying a mixed gas of O ₂ and CF ₄ at 300 sccm. Expose for about a minute. At this time, the ashing effect can be enhanced by applying LF power of about 100 W to the lower electrode of the stage 60. Further, in order to reduce thermal damage due to plasma generated in the ashing process, it is preferable that the semiconductor wafer 12 and the dicing tape 22 are cooled in the surface oxide removal process. For example, while adjusting the temperature of the stage 60 to 20 ° C. or less, a DC voltage of 3 kV is applied to the ESC electrode, and 50 to 200 Pa of He is supplied between the dicing tape 22 and the stage 60 as a cooling gas. Thus, the semiconductor wafer 12 and the dicing tape 22 can be cooled.

  After the ashing step, a dechucking step for reducing the electrostatic adsorption force between the semiconductor wafer 12 and the dicing tape 22 and the stage 60 may be provided. In the dechucking process, weak plasma is generated in the chamber 52 to remove residual charges from the semiconductor wafer 12 and the dicing tape 22 that are electrostatically attracted to the stage 60, thereby reducing the electrostatic attraction force between the stage 60 and the stage 60. Let For example, weak plasma may be generated for about 30 to 120 seconds by adjusting the chamber pressure to 12 Pa while supplying Ar gas at 100 sccm and applying 150 W of RF power to the antenna 54. At this time, it is preferable to generate weak plasma by stopping the application of voltage to the ESC electrode and the supply of the cooling gas while adjusting the temperature of the stage 60 to 20 ° C. or less.

  Through the above steps, a high-quality semiconductor chip 2 is manufactured as a product (see FIG. 1L).

  FIG. 4 is a schematic configuration diagram of the cluster apparatus 100 that executes the method for manufacturing the semiconductor chip 2. A transport mechanism 180 is provided at the center of the cluster apparatus 100, and clusters 110 to 170 corresponding to the aforementioned steps are provided around the transport mechanism 180. However, the arrangement and shape of the transport mechanism 180 and the clusters 110 to 170 shown in FIG. 4 are conceptual and do not necessarily match the actual arrangement and shape.

  The transport mechanism 180 transports the semiconductor wafer 12 or the semiconductor chip 2 obtained by dividing the semiconductor wafer 12 into individual clusters 110 to 170.

  The cluster 110 is for carrying in / out the semiconductor wafer 12 or the semiconductor chip 2 obtained by dividing the semiconductor wafer 12. Here, the semiconductor wafer 12 to be loaded is in a state where the second holding process has already been completed from the first preparation process (see FIG. 1F). Moreover, the semiconductor chip 2 to be carried out is in a state where all the above steps are completed (see FIG. 1L).

  The cluster 120 is a cluster in which the first mask formation process (see FIG. 1G) is executed. The cluster 130 is a cluster in which the second mask formation process (see FIG. 1H) is executed. The cluster 140 is a cluster in which a patterning process (see FIG. 1I) is performed. The cluster 150 is a cluster in which a cleaning process (see FIG. 1J) is performed. The cluster 160 is a cluster in which a drying process (also see FIG. 1J) is performed. The cluster 170 is a cluster in which the singulation process (see FIG. 1K) and the ashing process (see FIG. 1L) are performed. The classification of the clusters 110 to 170 is conceptual and is not necessarily limited to the above. For example, the cluster 120 that executes the first mask formation step and the cluster 130 that executes the second mask formation step may be the same cluster. Further, the cluster 150 for executing the water washing step and the cluster 160 for executing the drying step may be the same cluster.

  According to the present embodiment, since the water-soluble upper layer mask 24B is formed on the surface 6A of the semiconductor wafer 12 before the laser grooving process in the patterning step, the debris attached to the upper layer mask 24B in the subsequent laser grooving process. It can be removed by washing with the upper layer mask 24B. Therefore, since the debris residue in plasma dicing can be suppressed, processing defects caused by debris in plasma dicing can be suppressed, and the reliability of the semiconductor chip 2 as a product can be improved.

  Further, according to the present embodiment, in the ashing process, the water-insoluble lower layer mask 24A can be easily removed by ashing with the second plasma.

  Further, according to the present embodiment, the upper layer mask 24B and the lower layer mask 24A can be formed by applying the raw material liquid in the first mask forming step and the second mask forming step, so that the upper layer mask 24B and the lower layer mask 24A are easily formed. it can.

(Second Embodiment)
The manufacturing method of the semiconductor chip 2 of the present embodiment shown in FIGS. 5A to 5L is different from the first embodiment in the formation method of the lower layer mask 24. Except for this, it is substantially the same as the manufacturing method of the semiconductor chip 2 of the first embodiment. Therefore, description of the portions described in the first embodiment may be omitted.

  The first preparation step shown in FIG. 5A, the second preparation step shown in FIG. 5B, the protection step shown in FIG. 5C, the thinning step shown in FIG. 5D, and the first holding step shown in FIG. 5E are substantially the same as those in the first embodiment. Are the same. However, the BG tape 20 used in the present embodiment includes a base material 20B and a water-insoluble adhesive layer 20A, and the base material 20B can be peeled off while leaving the adhesive layer 20A. In particular, the pressure-sensitive adhesive layer 20A has plasma resistance, and can protect the element region 14 from plasma in the singulation process (see FIG. 5J).

  In the first mask forming step shown in FIG. 5F, only the base material 20B of the BG tape 20 is peeled off. That is, the adhesive layer 20A is left and used as the lower layer mask 24A (see FIG. 1G) of the first embodiment.

  In the second mask formation step shown in FIG. 5G, the upper layer mask 24B is formed on the upper surface of the adhesive layer 20A. The upper layer mask 24B is the same as that of the first embodiment, and the formation method thereof is the same as that of the first embodiment.

  The patterning step shown in FIG. 5H, the cleaning step shown in FIG. 5I, the singulation step shown in FIG. 5J, and the ashing step shown in FIG. 5K are other than the point that the lower layer mask 24A of the first embodiment is replaced with the adhesive layer 20A. This is substantially the same as the first embodiment.

  Through the above steps, a high-quality semiconductor chip 2 is manufactured as a product (see FIG. 5L).

  According to this embodiment, since the adhesive layer 20A of the BG tape 20 can be used as the lower layer mask 24A of the first embodiment, the mask forming process can be simplified.

  As mentioned above, although specific embodiment and its modification example of this invention were described, this invention is not limited to the said form, It can implement in various changes within the scope of this invention. For example, what combined suitably the content of each embodiment is good also as one Embodiment of this invention.

2 Semiconductor chip (element chip)
4 Semiconductor layer 4A Back surface (second surface)
6 Wiring layer 6A Surface (first surface)
6B Metal wiring 6C Insulating film 6D Transistor 6E Metal layer (TEG)
8 Protective film 9 UBM film 10 Bump 12 Semiconductor wafer (substrate)
14 Element area 16 Divided area 18 Exposed part 20 BG tape 20A Adhesive layer 20B Base material layer 22 Dicing tape (holding sheet)
22A Adhesive layer 22B Base material layer 22C Frame 24 Mask 24A Lower layer mask (lower layer)
24B Upper layer mask (upper layer)
DESCRIPTION OF SYMBOLS 50 Dry etching apparatus 52 Chamber 54 Antenna 56 1st high frequency power supply part 58 Processing chamber 60 Stage 62 2nd high frequency power supply part 64 Gas inlet 66 Etching gas source 68 Exhaust outlet 70 Vacuum exhaust part 100 Cluster apparatus 110,120,130,140 , 150, 160, 170 Cluster 180 Transport mechanism

Claims (4)

Providing a substrate comprising a plurality of element regions and divided regions defining the element regions, the substrate having a first surface and a second surface opposite to the first surface;
Holding the second surface of the substrate on a holding sheet;
Covering the first surface of the substrate with a mask comprising a water-insoluble lower layer and a water-soluble upper layer;
By irradiating the mask with laser light, an opening is formed in the mask to expose a divided region of the substrate,
Contacting the substrate with water or an aqueous solution, leaving the lower layer while removing the upper layer of the mask covering the element region,
The substrate is exposed to a first plasma, and the divided regions exposed to the openings are etched until reaching the second surface, whereby the plurality of element chips are separated into pieces, and the plurality of element chips are the holding sheet. Is held in the
A method of manufacturing an element chip, comprising: removing the mask remaining on the surface of the plurality of element chips, and setting the plurality of element chips from which the mask has been removed to be held by the holding sheet.   2. The element chip manufacturing method according to claim 1, wherein the removal of the mask from the surface of the plurality of element chips includes ashing by a second plasma.   The coating with the mask is performed by applying a water-soluble resin raw material liquid after applying a water-insoluble resin raw material liquid to the first surface of the substrate held by the holding sheet and forming the lower layer. The element chip manufacturing method according to claim 1, comprising forming an upper layer. Prior to holding by the holding sheet, a protective tape comprising a base material and a water-insoluble adhesive layer is attached to the first surface via the adhesive layer,
The covering with the mask is to peel off the base material of the protective tape from the substrate and leave the adhesive layer on the first surface of the substrate as the lower layer, and form the upper layer on the lower layer. The manufacturing method of the element chip of Claim 1 containing this.

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