JP2019050232A - Semiconductor device and manufacturing method for semiconductor device - Google Patents

Abstract

To improve characteristics of a semiconductor device. A method for manufacturing a semiconductor device according to the present invention includes a step of forming a gate insulating film GI on a nitride semiconductor layer. This step includes a step of forming a crystalline Al2O3 film on the nitride semiconductor layer, a step of forming a SiO2 film thereon, and a step of forming an amorphous Al2O3 film thereon. And The method further includes a step of forming a crystalline Al2O3 film by subjecting the amorphous Al2O3 film to a heat treatment and crystallization, and a step of forming a SiO2 film thereon. As described above, since the laminated film in which the crystalline Al2O3 film and the SiO2 film are alternately laminated from below is used as the gate insulating film GI, the threshold voltage (Vt) can be cumulatively improved. [Selection diagram] Fig. 1

Description

  The present invention relates to a method of manufacturing a semiconductor device and a semiconductor device, and can be suitably used, for example, in a semiconductor device using a nitride semiconductor.

  GaN-based nitride semiconductors have high electron mobility in a wide band gap compared to Si and GaAs, and are expected to be applied to transistors for high withstand voltage, high output, and high frequency applications. Development is in progress. Among such transistors, a transistor having a normally-off characteristic is useful, and a structure for providing the normally-off characteristic has been studied.

  For example, Patent Document 1 discloses a semiconductor device provided with an underlayer, an electron supply layer, a two-dimensional electron gas elimination layer, a first insulating film, and a gate electrode.

Further, Non-Patent Document 1 describes that in a so-called high-k / metal structure MOS device, the threshold voltage is increased by using a laminated film in which Al ₂ O ₃ is laminated on SiO ₂ as a gate insulating film. It is done.

Patent No. 5684574 gazette

K. Kita and A. Toriumi "Origin of electric dipolars formed at high-k / SiO2 interface," Applied Physics Letters vol. 94, 132902 (2009).

  The inventor of the present invention is engaged in research and development of a semiconductor device using a nitride semiconductor, and is diligently examining improvement of the characteristics of the semiconductor device. In particular, the transistor structure (mesa MOS structure) for providing the normally-off characteristic is examined.

  However, according to the study of the inventor of the present invention, the threshold voltage of the mesa MOS structure is low, for example, around 0 V, and a further increase in threshold voltage is desired to effectively exhibit normally-off characteristics.

In addition, in a MOS device (silicon device) formed on the main surface of a silicon substrate, as described in the above-mentioned non-patent document, a laminated film in which Al ₂ O ₃ is laminated on SiO ₂ is used as a gate insulating film. It is known that the threshold voltage rises.

From such a point of view, in the nitride semiconductor device, when the threshold voltage was examined using a laminated film in which Al ₂ O ₃ was laminated on SiO ₂ as the gate insulating film, the threshold voltage was significantly improved with good reproducibility. I could not do it. The inventor further studied, and examined various laminated films as a gate insulating film, and contrary to the case of silicon devices, laminated layers of SiO ₂ laminated on Al ₂ O ₃ as a gate insulating film When the film was used, the improvement effect of the threshold voltage could be confirmed in some nitride semiconductor devices. Then, when the analysis was advanced, it was found that the threshold improvement effect was obtained when the lower layer Al ₂ O ₃ was crystallized. Further, the relationship of Vt and SiO ₂ film thickness, threshold improvement was found to be explained by the dipole model.

  Therefore, based on the above findings, the inventor of the present invention has intensively studied the structure and manufacturing method of the nitride semiconductor device capable of further reducing the threshold voltage, and suppressing the reduction of the threshold voltage to obtain a semiconductor with a normally off characteristic. It has led to the realization of the device.

  Other problems and novel features will be apparent from the description of the present specification and the accompanying drawings.

  The outline of typical ones of the embodiments disclosed in the present application will be briefly described as follows.

  A method of manufacturing a semiconductor device according to an embodiment disclosed in the present application includes the step of forming a gate insulating film on a nitride semiconductor layer. Then, in this step, a step of forming a crystalline first metal oxide film on the nitride semiconductor layer, and a step of forming a second metal oxide film on the crystalline first metal oxide film And forming an amorphous oxide film of the first metal on the oxide film of the second metal.

  A semiconductor device described in an embodiment disclosed in the present application has a gate insulating film formed on a nitride semiconductor layer. Then, in the gate insulating film, a crystalline first metal oxide film, a second metal oxide film, a crystalline first metal oxide film, and a second metal oxide film are sequentially stacked from the bottom. Having a laminate.

  According to the method for manufacturing a semiconductor device disclosed in the present application and described in the following representative embodiments, a semiconductor device with good characteristics can be manufactured.

  According to the semiconductor device disclosed in the present application and shown in the following representative embodiments, the characteristics of the semiconductor device can be improved.

FIG. 1 is a cross sectional view showing a schematic configuration of a semiconductor device of a first embodiment. FIG. 2 is an energy band diagram of the semiconductor device of Embodiment 1; FIG. 7 is a cross-sectional view showing a step of forming a gate insulating film and a gate electrode according to Embodiment 1. FIG. 7 is a cross-sectional view showing a step of forming a gate insulating film and a gate electrode according to Embodiment 1. FIG. 7 is a cross-sectional view showing a step of forming a gate insulating film and a gate electrode according to Embodiment 1. FIG. 7 is a cross-sectional view showing a step of forming a gate insulating film and a gate electrode according to Embodiment 1. FIG. 7 is a cross-sectional view showing a step of forming a gate insulating film and a gate electrode according to Embodiment 1. FIG. 7 is a cross-sectional view showing a step of forming a gate insulating film and a gate electrode according to Embodiment 1. FIG. 7 is a cross-sectional view showing the structure of the semiconductor device of Comparative Example 1; FIG. 7 is an energy band diagram of the semiconductor device of Comparative Example 1; FIG. 18 is a cross-sectional view showing the structure of the semiconductor device of Comparative Example 2; FIG. 7 is an energy band diagram of a semiconductor device of Comparative Example 2; It is a sectional view showing the structure of a semiconductor device using a stacked film of crystallinity of the Al ₂ O ₃ film and the SiO ₂ film thereon as a gate insulating film. It is an energy band diagram of a semiconductor device using a stacked film of crystallinity of the Al ₂ O ₃ film and the SiO ₂ film thereon as a gate insulating film. FIG. 1 is a cross sectional view showing a configuration of a semiconductor device of a first embodiment. FIG. 1 is a plan view showing a configuration of a semiconductor device of a first embodiment. FIG. 7 is a cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 1; FIG. 7 is a cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 1; FIG. 7 is a cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 1; FIG. 7 is a cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 1; FIG. 7 is a cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 1; FIG. 7 is a cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 1; FIG. 7 is a cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 1; FIG. 7 is a cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 1; FIG. 7 is a cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 1; FIG. 7 is a cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 1; FIG. 7 is a cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 1; FIG. 7 is a cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 1; FIG. 7 is a cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 1; FIG. 7 is a cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 1; FIG. 7 is a cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 1; FIG. 7 is a cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 1; FIG. 7 is a cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 1; FIG. 7 is a cross-sectional view showing the configuration of the semiconductor device of Embodiment 2; FIG. 18 is a cross-sectional view showing the manufacturing process of the semiconductor device of Embodiment 2; FIG. 18 is a cross-sectional view showing the manufacturing process of the semiconductor device of Embodiment 2; FIG. 18 is a cross-sectional view showing the manufacturing process of the semiconductor device of Embodiment 2; FIG. 18 is a cross-sectional view showing the manufacturing process of the semiconductor device of Embodiment 2; FIG. 18 is a cross-sectional view showing the manufacturing process of the semiconductor device of Embodiment 2; FIG. 18 is a cross-sectional view showing the manufacturing process of the semiconductor device of Embodiment 2; FIG. 18 is a cross-sectional view showing the manufacturing process of the semiconductor device of Embodiment 2; FIG. 18 is a cross-sectional view showing the manufacturing process of the semiconductor device of Embodiment 2; FIG. 18 is a cross-sectional view showing the manufacturing process of the semiconductor device of Embodiment 2; FIG. 18 is a cross-sectional view showing the manufacturing process of the semiconductor device of Embodiment 2; FIG. 18 is a cross-sectional view showing the manufacturing process of the semiconductor device of Embodiment 2; FIG. 18 is a cross-sectional view showing the manufacturing process of the semiconductor device of Embodiment 2; FIG. 18 is a cross-sectional view showing the manufacturing process of the semiconductor device of Embodiment 2; FIG. 18 is a cross-sectional view showing the manufacturing process of the semiconductor device of Embodiment 2; FIG. 18 is a cross-sectional view showing the manufacturing process of the semiconductor device of Embodiment 2; FIG. 18 is a cross-sectional view showing the manufacturing process of the semiconductor device of Embodiment 2; FIG. 18 is a cross-sectional view showing the manufacturing process of the semiconductor device of Embodiment 2; FIG. 33 is a cross sectional view showing a configuration of a semiconductor device of an application example 1 of a third embodiment; FIG. 33 is a cross sectional view showing a configuration of a semiconductor device of application example 2 of embodiment 3;

  In the following embodiments, when it is necessary for the sake of convenience, it will be described by dividing into a plurality of sections or embodiments, but they are not unrelated to each other unless specifically stated otherwise, one is the other And some of all the modifications, applications, detailed explanation, supplementary explanation, and the like. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), it is particularly pronounced and clearly limited to a specific number in principle. It is not limited to the specific number except for the number, and may be more or less than the specific number.

  Furthermore, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily essential unless otherwise specified or if they are considered to be obviously essential in principle. Similarly, in the following embodiments, when referring to the shapes, positional relationships and the like of components etc., the shapes thereof are substantially the same unless particularly clearly stated and where it is apparently clearly not so in principle. It is assumed that it includes things that are similar or similar to etc. The same applies to the above-described numbers and the like (including the number, the numerical value, the amount, the range, and the like).

  Hereinafter, embodiments will be described in detail based on the drawings. In all the drawings for describing the embodiments, members having the same function are denoted by the same or related reference numerals, and the repetitive description thereof will be omitted. Also, when there are a plurality of similar members (portions), symbols may be added to the generic symbols to indicate individual or specific portions. Further, in the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly required.

  In the drawings used in the embodiments, hatching may be omitted to make the drawing easy to see even if it is a sectional view. Further, even a plan view may be hatched to make it easy to see the drawing.

  Further, in the cross-sectional view and the plan view, the size of each portion does not correspond to the actual device, and a specific portion may be displayed relatively large in order to make the drawing easy to understand. Further, even when the sectional view and the plan view correspond to each other, a specific part may be displayed relatively large in order to make the drawing easy to understand.

Embodiment 1
Hereinafter, the semiconductor device of the present embodiment will be described in detail with reference to the drawings.

  FIG. 1 is a cross-sectional view showing a schematic configuration of the semiconductor device of the present embodiment.

  The semiconductor device shown in FIG. 1 is a MOS type field effect transistor (MOSFET; also referred to as a metal-oxide-semiconductor field effect transistor, or MISFET) using a nitride semiconductor. In addition, it is also called a high electron mobility transistor (HEMT: High Electron Mobility Transistor). The semiconductor device shown in FIG. 1 is also referred to as a “mesa-type MOS structure” because it has a structure in which the gate electrode is disposed on the mesa portion via the gate insulating film as described later.

  In the semiconductor device of the present embodiment, as shown in FIG. 1, a first nitride semiconductor layer S1, a second nitride semiconductor layer S2, and a third nitride semiconductor layer S3 are sequentially formed on a substrate SUB. There is. Then, a mesa portion made of the fourth nitride semiconductor layer S4 is formed on a part of the third nitride semiconductor layer S3 (approximately the center in FIG. 1).

  The second nitride semiconductor layer S2 has an electron affinity equal to that of the first nitride semiconductor layer S1, or has a larger electron affinity than the first nitride semiconductor layer S1 (S1 ≦ S2).

  The third nitride semiconductor layer S3 has a smaller electron affinity than the first nitride semiconductor layer S1 (S1> S3).

  The fourth nitride semiconductor layer S4 has a larger electron affinity than the first nitride semiconductor layer S1 (S4> S1).

  The first nitride semiconductor layer S1 is also called a buffer layer, and is made of, for example, AlGaN. The second nitride semiconductor layer S2 is also called a channel layer, and is made of, for example, GaN. The third nitride semiconductor layer S3 is called a barrier layer (electron supply layer), and is made of, for example, AlGaN. However, the Al composition is larger than that of the first nitride semiconductor layer S1. The mesa portion formed of the fourth nitride semiconductor layer S4 is also called a 2DEG elimination layer (2DEG suppression layer, cap layer), and is made of, for example, GaN.

  The planar shape of the mesa portion formed of the fourth nitride semiconductor layer S4 is, for example, a rectangular shape having a long side in the depth direction of the drawing.

  A gate electrode GE is formed on the mesa portion formed of the fourth nitride semiconductor layer S4 via the gate insulating film GI. Further, the source electrode SE is formed on the third nitride semiconductor layer S3 on one side (the left side in FIG. 1) of the mesa portion formed of the fourth nitride semiconductor layer S4, and the other side (FIG. 1). In the above, the drain electrode DE is formed on the third nitride semiconductor layer S3 on the right side).

  The planar shape of the stacked body of the gate electrode GE and the gate insulating film (GI) is, for example, a rectangular shape having long sides in the depth direction in the drawing (see FIG. 16). The planar shapes of the source electrode SE and the drain electrode DE are also, for example, rectangular shapes having long sides in the depth direction of the drawing (see FIG. 16). The above-mentioned paper depth direction is the Y direction in FIG.

  Here, in the vicinity of the interface between the second nitride semiconductor layer (channel layer) S2 and the third nitride semiconductor layer (barrier layer) S3, on the side of the second nitride semiconductor layer S2, 2DEG (two-dimensional electron gas) ) Occurs. The fourth nitride semiconductor layer S4 has a function of suppressing the 2DEG. The function of suppressing 2DEG can be said to be a function of reducing the concentration of 2DEG (two-dimensional electron gas). For this reason, as described above, the fourth nitride semiconductor layer S4 is also referred to as a 2DEG elimination layer.

  Therefore, when a predetermined voltage (threshold voltage) is applied to the gate electrode GE, a channel is formed below the gate electrode GE, the channel between 2DEGs is conducted by this channel, and the transistor is turned on. That is, the normally off operation can be realized.

Further, in the present embodiment, as the gate insulating film GI, the first gate insulating film GIa formed on the mesa portion formed of the fourth nitride semiconductor layer S4 and the first gate insulating film GIa are formed. A second gate insulating film GIb, a third gate insulating film GIc formed over the second gate insulating film GIb, and a fourth gate insulating film GId formed over the third gate insulating film GIc. The first gate insulating film GIa and the third gate insulating film GIc are made of crystalline aluminum oxide (c-Al ₂ O ₃ ), and the second gate insulating film GIb and the fourth gate insulating film GId are silicon oxide (SiO 2) ₂ ) It consists of. In other words, in the present embodiment, a stacked film in which crystalline Al ₂ O ₃ films and SiO ₂ films are alternately stacked from the bottom is used as the gate insulating film GI. Furthermore, in other words, in the present embodiment, a _two- layer film of a crystalline Al ₂ O ₃ film and a SiO ₂ film provided thereon is repeatedly stacked as the gate insulating film GI. A film is used (a film in which two or more layers are stacked) is used. The composition ratio of Al or Si to oxygen (O) is not limited to the above.

As described above, in the present embodiment, since the laminated film in which the crystalline Al ₂ O ₃ film and the SiO ₂ film are alternately laminated from the bottom is used as the gate insulating film GI, the threshold voltage (Vt) can be calculated. It can shift in the positive direction. That is, the threshold voltage (Vt) can be improved.

The improvement effect of the threshold voltage (Vt) of the present embodiment will be described with reference to FIGS. 1 to 14. FIG. 2 is an energy band diagram of the semiconductor device of the present embodiment. FIGS. 3-8 is sectional drawing which shows the formation process of the gate insulating film and gate electrode of this Embodiment. FIG. 9 is a cross-sectional view showing the structure of the semiconductor device of Comparative Example 1, and FIG. 10 is an energy band diagram of the semiconductor device of Comparative Example 1. As shown in FIG. FIG. 11 is a cross-sectional view showing the structure of the semiconductor device of Comparative Example 2, and FIG. 12 is an energy band diagram of the semiconductor device of Comparative Example 2. As shown in FIG. FIG. 13 is a cross-sectional view showing a structure of a semiconductor device using a laminated film of a crystalline Al ₂ O ₃ film and an SiO ₂ film thereon as a gate insulating film, and FIG. 14 shows a crystal as a gate insulating film. FIG. 16 is an energy band diagram of a semiconductor device using a laminated film of a crystalline Al ₂ O ₃ film and an SiO ₂ film thereon. The energy band diagram corresponds to the gate electrode, the gate insulating film below it, and the nitride semiconductor layer.

When a single-layer amorphous Al ₂ O ₃ film is used as the gate insulating film GI as in the semiconductor device of Comparative Example 1 shown in FIG. 9, the designed band diagram is a gate as shown by a broken line in FIG. 10. The level of the electrode GE part is located below the Fermi level (Ef). However, in an actual device, the solid line in FIG. 10 is caused by the influence of the interface positive charge Q _int generated at the interface between the mesa portion formed of the fourth nitride semiconductor layer S4 and the gate insulating film (a-Al ₂ O ₃ film) GI. As shown in the above, the direction of the electric field applied to the gate insulating film (a-Al ₂ O ₃ film) GI is reversed, and the threshold voltage (Vt) is lowered.

Also, according to the study of the present inventor, the threshold voltage can be obtained even if a laminated film of a SiO ₂ film and a amorphous Al ₂ O ₃ film on which a threshold improvement effect is obtained in a silicon device is used as a gate insulating film. Has been found to not improve.

Then, when various laminated films were examined as a gate insulating film by further study of the present inventor, a laminated film in which SiO ₂ is laminated on Al ₂ O ₃ as a gate insulating film, contrary to the case of a silicon device. The effect of improving the threshold voltage has been confirmed in some of the nitride semiconductor devices. In addition, as a result of further analysis, it was found that the threshold improvement effect is obtained when the lower layer Al ₂ O ₃ is crystallized.

For example, when a laminated film of an amorphous Al ₂ O ₃ film and an SiO ₂ film thereon is used as the gate insulating film GI as in the semiconductor device of Comparative Example 2 shown in FIG. It will be shown by. That is, since the interface positive charge Q _int generated at the interface between the mesa portion formed of the fourth nitride semiconductor layer S4 and the gate insulating film (a-Al ₂ O ₃ film) GI does not change, the direction of the electric field remains reversed. Because the electron affinity is lower in SiO ₂ than in Al ₂ O ₃ , and the electric field strength is high because the relative dielectric constant is low, the threshold voltage (Vt) is higher than in the case of Comparative Example 1 (FIGS. 9 and 10). ) Is further reduced.

On the other hand, as shown in FIG. 13, the crystalline Al ₂ O ₃ film to be the first gate insulating film GIa as the gate insulating film GI and the SiO ₂ film to be the second gate insulating film GIb thereon In the case of using the laminated film of the above, as shown in FIG. 14, the threshold voltage (Vt) can be improved more than in the case of Comparative Example 2 (FIG. 11, FIG. 12). That is, the threshold voltage (Vt) can be shifted in the positive direction.

  The improvement effect of the threshold voltage (Vt) can be described by the “dipole model” shown below from the comparison of the semiconductor devices shown in Comparative Examples 1 and 2 and FIG.

That is, in the laminated film of the crystalline of the _Al 2 _{O 3} film and the SiO ₂ film thereon, dipole is generated in the boundary portion of the crystalline of the _Al 2 _{O 3} film and the SiO ₂ film. This dipole has a negative charge (−) on the side of the crystalline Al ₂ O ₃ film and a positive charge (+) on the side of the SiO ₂ film (see FIG. 14). The distance of these charges is 1 nm or less. In the vicinity of the boundary between the crystalline Al ₂ O ₃ film and the SiO ₂ film in which the dipole (charge pair) exists, the mesa portion formed of the crystalline Al ₂ O ₃ film and the fourth nitride semiconductor layer S 4 An electric field is applied in the direction to cancel the electric field due to the interface positive charge Q _int generated at the interface (see thick arrows in FIG. 14). Therefore, the threshold voltage (Vt) can be improved as compared with the comparative examples 1 and 2. As described above, the range in which the electric field is applied is as narrow as 1 nm or less, but the charge amount in this range (the respective charge amounts of positive charge and negative charge) is about one digit higher than the amount of interface positive charge Q _int. A change of potential energy effective for improvement can be obtained.

Further, as in the present embodiment (FIG. 1), in the case of using a film in which a two-layer film of a crystalline Al ₂ O ₃ film and a SiO ₂ film provided thereon is repeatedly laminated, As shown in FIG. 2, the threshold voltage (Vt) can be further improved. Here, from the lower side of the film constituting the gate insulating film GI, the crystalline Al ₂ O ₃ film (GIa), the SiO ₂ film (GIb), the crystalline Al ₂ O ₃ film (GIc), the SiO ₂ film It is described as (GId).

As described above, even if a dipole is generated at the boundary between the crystalline Al ₂ O ₃ film (GIa) and the SiO ₂ film (GIb), the SiO ₂ film (GIb) and the crystalline Al ₂ thereon are produced. If a dipole consisting of a reverse dipole, ie, a positive charge (+) on the SiO ₂ film side and a negative charge (−) on the Al ₂ O ₃ film side, is generated at the boundary with the O ₃ film (GIc) , The above-mentioned dipole threshold improvement effect is canceled. However, when the amorphous Al ₂ O ₃ film is formed on the SiO ₂ film (GIb), the above-mentioned reverse dipole does not occur. Then, after forming an amorphous Al ₂ O ₃ film, crystallization is performed by heat treatment, and the above-mentioned reverse dipole is not generated even as a crystalline Al ₂ O ₃ film (GIc).

Therefore, every time a two-layer film of a crystalline Al ₂ O ₃ film and an SiO ₂ film provided thereon is stacked, the threshold voltage is cumulatively improved, and the threshold voltage (Vt) is made positive. be able to. Also, the threshold voltage (Vt) can be easily adjusted. FIG. 2A shows a band diagram in the case where two layers of a crystalline Al ₂ O ₃ film and an SiO ₂ film provided thereon are laminated in two layers (a total of four layers). FIG. 2 (b) shows a band diagram in the case where three layers are stacked (total six layers). In the case shown in FIG. 2, the level of the gate electrode GE is located below the Fermi level (Ef).

Thus, with the dipole at the boundary between the crystalline Al ₂ O ₃ film and the SiO ₂ film, the mesa portion made of the fourth nitride semiconductor layer S 4 and the gate insulating film (a-Al ₂ O ₃ film) GI and The threshold voltage (Vt) can be improved even if interface positive charge _Qint occurs during the period. Furthermore, in the case where a laminated film of a crystalline Al ₂ O ₃ film and a SiO ₂ film is repeatedly laminated, if an amorphous Al ₂ O ₃ film is laminated on the SiO ₂ film, an inverse dipole cancels the effect of the dipole. Does not occur, and even after crystallization of the amorphous Al ₂ O ₃ film, no inverse dipole occurs. For this reason, the threshold voltage can be cumulatively improved and the threshold voltage (Vt) can be made positive by repeatedly stacking the laminated film of the crystalline Al ₂ O ₃ film and the SiO ₂ film. Also, the threshold voltage (Vt) can be easily adjusted.

Further, when forming the SiO ₂ film on the _Al 2 _{O 3} film, when forming the SiO ₂ film in an atmosphere of more than 800 ° C., even lower of the _Al 2 _{O 3} film is an amorphous Good. In this case, the dipole is formed because the SiO ₂ film is formed on the crystallized Al ₂ O ₃ film while at least the surface portion is crystallized by being exposed to the above atmosphere to the Al ₂ O ₃ film. Be done.

Here, the threshold improvement effect by the dipole will be described quantitatively from the viewpoint of charge. For example, assuming that the film thickness of Al ₂ O ₃ on the interface where the interface positive charge Q _int = 1 × 10 ¹² cm ⁻² is 60 nm, a threshold voltage drop of 1.2 V occurs. On the other hand, the dipole charge generated at the interface between the crystalline Al ₂ O ₃ film and the SiO ₂ film of the present embodiment is 3.5 × 10 ¹³ cm ^−2, which is one digit higher than the interface positive charge Q _int. In many cases, a threshold improvement effect of 0.7 V is achieved. Therefore, it is possible to obtain a threshold improvement effect of 1.4 V if this is repeated twice and 2.1 V if it is repeated three times. In this case, by overlapping two or more times, it is possible to obtain a threshold improvement effect that exceeds the influence of the threshold reduction by the interface positive charge Q _int .

Hereinafter, the manufacturing process of the gate insulating film, the gate electrode and the like of the semiconductor device of the present embodiment will be described with reference to FIGS. 3 to 8, and the laminated state of Al ₂ O ₃ film and SiO ₂ film, Al The crystallinity of the ₂ O ₃ film and the generation of a dipole will be described.

  The substrate SUB shown in FIG. 3 is prepared, and the first to third nitride semiconductor layers (S1 to S3) are sequentially formed. For example, a semiconductor substrate made of silicon (Si) is used as the substrate SUB. Next, on the substrate SUB, an AlGaN layer (Al composition ratio 5%) is used as a first nitride semiconductor layer (buffer layer) S1, a GaN layer is used as a second nitride semiconductor layer (channel layer) S2, and As the nitride semiconductor layer (barrier layer) S3, an AlGaN layer (Al composition ratio 22%) is epitaxially grown sequentially. Next, a GaN layer is epitaxially grown as the fourth nitride semiconductor layer S4 on the third nitride semiconductor layer S3, and then a mask film (not shown) is formed in the formation region of the mesa portion, and this mask film is formed. The fourth nitride semiconductor layer S4 is etched as a mask. Thereby, the mesa portion is formed.

Next, the gate insulating film GI and the gate electrode GE are formed over the mesa portion formed of the fourth nitride semiconductor layer S4. For example, as shown in FIG. 3, on the mesa portion and the third nitride semiconductor layer S3 changes from the fourth nitride semiconductor layer S4, a first gate insulating film GIa, crystalline aluminum oxide (c-Al ₂ O ₃ ) form. First, amorphous aluminum oxide (a-Al ₂ O ₃ ) is deposited to a film thickness of 5 nm at a deposition temperature of 300 ° C. using an atomic layer deposition (ALD) method. Next, the amorphous aluminum oxide (a-Al ₂ O ₃ ) is subjected to heat treatment at 800 ° C. for 10 minutes in an inert gas (for example, nitrogen) atmosphere. By this heat treatment, amorphous aluminum oxide (a-Al ₂ O ₃ ) is crystallized to form crystalline aluminum oxide (c-Al ₂ O ₃ ).

Here, the crystallization and refers to the process of grain (crystal grain) occurs, the crystallinity of the aluminum oxide (c-Al 2 _{O 3)} has a plurality of grains (crystal grains). Therefore, it is also called polycrystalline aluminum oxide. The average grain size of the grains (crystal grains) is preferably about the same (± 80%) as the film thickness of the aluminum oxide film (a-Al ₂ O ₃ , c-Al ₂ O ₃ ).

Here, the film thickness of the aluminum oxide film (a-Al ₂ O ₃ , c-Al ₂ O ₃ ) is about 5 nm, but this film thickness is 2 nm or more and 20 nm or less, more preferably 5 nm or more and 10 nm or less The range can be adjusted. By setting the film thickness to 2 nm or more, a dipole can be generated. In order to obtain a sufficient dipole (increase the charge amount), the film thickness is preferably 5 nm or more. Although there is no upper limit to this film thickness, 20 nm or less is sufficient when repeatedly laminating a two-layer film of a crystalline Al ₂ O ₃ film and a SiO ₂ film provided thereon. Further, in order to suppress the influence of the interface positive charge Q _int , it is more preferable to set the film thickness to 10 nm or less.

Next, as shown in FIG. 4, a silicon oxide film (SiO ₂ film) is formed on the first gate insulating film GIa as a second gate insulating film GIb. For example, a silicon oxide film (SiO ₂ film) is formed to have a film thickness of 10 nm at a film forming temperature of 400 ° C. using a low pressure chemical vapor deposition (LPCVD) method. Here, the film thickness of the silicon oxide film (SiO ₂ film) is about 10 nm, but this film thickness can be adjusted in the range of 5 nm or more and 20 nm or less, more preferably 5 nm or more and 10 nm or less. By setting the film thickness to 5 nm or more, a dipole can be generated. Although there is no upper limit to this film thickness, 20 nm or less is sufficient when repeatedly laminating a two-layer film of a crystalline Al ₂ O ₃ film and a SiO ₂ film provided thereon. Further, in order to suppress the influence of the interface positive charge Q _int , it is more preferable to set the film thickness to 10 nm or less.

Here, as the second gate insulating film GIb, a silicon oxide film (SiO ₂ film) is formed on crystalline aluminum oxide (c-Al ₂ O ₃ ), so an interface of these films is obtained. A dipole is produced.

Next, as shown in FIGS. 5 and 6, over the second gate insulating film GIb, crystalline aluminum oxide (c-Al ₂ O ₃ ) is formed as a third gate insulating film GIc. First, as shown in FIG. 5, amorphous aluminum oxide (a-Al ₂ O ₃ ) is deposited to a film thickness of 10 nm at a deposition temperature of 300 ° C. using an ALD method.

Here, since amorphous aluminum oxide (a-Al ₂ O ₃ ) is formed on the silicon oxide film (SiO ₂ film) which is the second gate insulating film GIb, the interface of these films is formed. , A dipole does not occur.

Next, the amorphous aluminum oxide (a-Al ₂ O ₃ ) is subjected to heat treatment at 800 ° C. for 10 minutes in an inert gas (for example, nitrogen) atmosphere. By this heat treatment, amorphous aluminum oxide (a-Al ₂ O ₃ ) is crystallized to be crystalline aluminum oxide (c-Al ₂ O ₃ ) (FIG. 6). The heat treatment conditions are an example. However, for crystallization of amorphous aluminum oxide (a-Al ₂ O ₃ ), heat treatment at 800 ° C. or higher is preferably performed.

Here, even after the heat treatment (crystallization), the silicon oxide film (SiO ₂ film) which is the _second gate insulating film GIb and the crystalline aluminum oxide (c-Al ₂ O ₃ ) which is the third gate insulating film GIc. There is no dipole at the interface with). That is, the state in which no dipole occurs is maintained even after heat treatment (crystallization).

The thickness of the aluminum oxide film (a-Al ₂ O ₃ , c -Al ₂ O ₃ ) to be the third gate insulating film GIc is adjusted in the range of 2 nm to 20 nm, more preferably 5 nm to 10 nm. can do. By setting the film thickness to 2 nm or more, a dipole can be generated. In order to obtain a sufficient dipole (increase the charge amount), the film thickness is preferably 5 nm or more. Although there is no upper limit to this film thickness, 20 nm or less is sufficient when repeatedly laminating a two-layer film of a crystalline Al ₂ O ₃ film and a SiO ₂ film provided thereon. Further, in order to suppress the influence of the interface positive charge Q _int , it is more preferable to set the film thickness to 10 nm or less.

Next, as shown in FIG. 7, a silicon oxide film (SiO ₂ film) is formed over the third gate insulating film GIc as a fourth gate insulating film GId. For example, a silicon oxide film (SiO ₂ film) is deposited to a thickness of 10 nm at a deposition temperature of 400 ° C. by using the LPCVD method. The thickness of the silicon oxide film (SiO ₂ film) to be the fourth gate insulating film GId can be adjusted in the range of 5 nm to 20 nm, more preferably 5 nm to 10 nm. By setting the film thickness to 5 nm or more, a dipole can be generated. Although there is no upper limit to this film thickness, 20 nm or less is sufficient when repeatedly laminating a two-layer film of a crystalline Al ₂ O ₃ film and a SiO ₂ film provided thereon. Further, in order to suppress the influence of the interface positive charge Q _int , it is more preferable to set the film thickness to 10 nm or less.

Here, as the fourth gate insulating film GId, a silicon oxide film (SiO ₂ film) is formed on crystalline aluminum oxide (c-Al ₂ O ₃ ). A dipole is produced.

As described above, when the Al ₂ O ₃ film and the SiO ₂ film are in contact with each other, a dipole is not generated, and the crystallinity and the stacking order of the Al ₂ O ₃ film are involved in the generation of the dipole.

That is, "when forming the silicon oxide film (SiO ₂ film) on a crystalline aluminum oxide _(c-Al 2 _{O 3)} dipoles occurred", and "amorphous on the silicon oxide film (SiO ₂ film) aluminum oxide (a-Al 2 _{O 3)} is deposited, dipole when crystallized using experimental fact that does not occur "in the gate insulating film, the top of the crystalline of the Al ₂ O ₃ film It is important to newly discover that the threshold voltage can be cumulatively improved by repeatedly laminating a two-layer film with an SiO ₂ film. In other words, it is a new finding that “a dipole does not necessarily occur if the Al ₂ O ₃ film and the SiO ₂ film are in contact with each other,” and the Al ₂ O ₃ film used in silicon devices The threshold voltage can be improved by new knowledge unique to nitride semiconductors, which is different from the technique in which a positive charge is generated on the side and a negative charge is generated on the SiO ₂ film side.

  Here, although the gate insulating film GI has four layers (GIa to GId), the gate insulating film GI may have six, eight, or ten or more layers.

In addition, here, from the lower side of the film constituting the gate insulating film GI, a 5 nm crystalline Al ₂ O ₃ film (GIa), a 10 nm SiO ₂ film (GIb), a 10 nm crystalline Al ₂ O ₃ Although the film (GIc) is a 10 nm SiO ₂ film (GId), it has a capacitance value to obtain a gate drive capability equivalent to the case where the gate insulating film GI is a single-layer 60 nm Al ₂ O ₃ film. Is an example designed to be the same. Therefore, the gate insulating film GI is not limited to this film thickness configuration. A design example in which the gate insulating film GI has six layers is shown below. From the bottom side, 5 nm crystalline Al ₂ O ₃ film, 5 nm SiO ₂ film, 5 nm crystalline Al ₂ O ₃ film, 5 nm SiO ₂ film, 5 nm crystalline Al ₂ O ₃ film, 10 nm A film formed by sequentially stacking SiO ₂ films may be used as a gate insulating film.

  Then, as shown in FIG. 8, a TiN (titanium nitride) film, for example, as a conductive film for the gate electrode GE is formed on the gate insulating film (fourth gate insulating film GId) GI using a sputtering method or the like. Deposit with a film thickness of about 100 nm. Next, a photoresist film (not shown) is formed in the formation region of the gate electrode GE, and using this photoresist film as a mask, the conductive film for the gate electrode GE and the gate insulating film GI (GIa to GId) therebelow Etch. Thus, the gate electrode GE is formed, and the gate insulating film GI (GIa to GId) having a planar shape equivalent to that of the gate electrode GE is formed in the lower layer thereof (see FIG. 1). Then, the photoresist film is removed.

  Next, the source electrode SE and the drain electrode DE are formed. For example, the source electrode SE and the drain electrode DE are formed using a lift-off method or the like. For example, a region other than the formation regions of the source electrode SE and the drain electrode DE is covered with a photoresist film (not shown), and a conductive film is formed above the substrate SUB. For example, an aluminum film is deposited using a sputtering method or the like. Next, the photoresist film is removed, and the conductive film in the region other than the regions where the source electrode SE and the drain electrode DE are formed is removed.

  Thus, the semiconductor device shown in FIG. 1 can be formed.

  Next, the semiconductor device of the present embodiment will be described in more detail with reference to FIGS.

[Structure explanation]
FIG. 15 is a cross-sectional view showing the configuration of the semiconductor device of the present embodiment. FIG. 16 is a plan view showing the configuration of the semiconductor device of this embodiment. The cross-sectional view of FIG. 15 corresponds to, for example, the AA part of FIG.

  In the semiconductor device of the present embodiment, as shown in FIG. 15, the first nitride semiconductor layer S1, the second nitride semiconductor layer S2, and the third nitride semiconductor layer S3 are sequentially formed on the substrate SUB. There is. Then, a mesa portion formed of the fourth nitride semiconductor layer S4 is formed on a part of the third nitride semiconductor layer S3. The nucleation layer and the high-resistance buffer layer thereon may be formed on the substrate SUB, and then the first nitride semiconductor layer S1 and the like may be formed.

  As the substrate SUB, for example, a semiconductor substrate made of silicon (Si) in which the (111) plane is exposed can be used. As the substrate SUB, in addition to the above silicon, a substrate made of SiC, sapphire or the like may be used. Also, a substrate made of GaN may be used, and in this case, the nucleation layer may be omitted.

  The nucleation layer is made of a nitride semiconductor layer. For example, an aluminum nitride (AlN) layer can be used as the nucleation layer. The high resistance buffer layer is composed of one or more nitride semiconductor layers doped with an impurity that forms a deep level in the nitride semiconductor. For example, as a superlattice structure (also referred to as a superlattice layer) including a plurality of nitride semiconductor layers, a stacked film (AlN / GaN film) of a gallium nitride (GaN) layer and an aluminum nitride (AlN) layer is repeated. The stacked superlattice structure can be used as a high resistance buffer layer.

  In general, the nitride semiconductor layers (the compound semiconductor layers of group III-V) on the substrate SUB are all formed by group III element surface growth.

  As described above, the first nitride semiconductor layer S1, the second nitride semiconductor layer S2, and the third nitride semiconductor layer S3 are sequentially formed on the substrate SUB. A mesa portion formed of the fourth nitride semiconductor layer S4 is formed on a portion of the third nitride semiconductor layer S3.

  The second nitride semiconductor layer S2 has an electron affinity equal to that of the first nitride semiconductor layer S1, or has a larger electron affinity than the first nitride semiconductor layer S1 (S1 ≦ S2).

  The third nitride semiconductor layer S3 has a smaller electron affinity than the first nitride semiconductor layer S1 (S1> S3).

  The fourth nitride semiconductor layer S4 has a larger electron affinity than the first nitride semiconductor layer S1 (S4> S1).

  As described above, the first nitride semiconductor layer S1 is also called a buffer layer, and is made of, for example, AlGaN. The second nitride semiconductor layer S2 is also called a channel layer, and is made of, for example, GaN. The third nitride semiconductor layer S3 is called a barrier layer (electron supply layer), and is made of, for example, AlGaN. However, the Al composition is larger than that of the first nitride semiconductor layer S1. For example, the Al composition of the first nitride semiconductor layer S1 is 0 to 10%, and more preferably 3 to 8%. Also, for example, the Al composition of the third nitride semiconductor layer S3 is 15 to 30%, and more preferably 18 to 22%. Further, the fourth nitride semiconductor layer (2DEG elimination layer) S4 is a non-doped layer and is made of, for example, i-GaN, but AlGaN having a lower Al composition than the first nitride semiconductor layer S1 may be used. Also, InGaN may be used as the fourth nitride semiconductor layer S4.

  In addition, over the mesa portion formed of the fourth nitride semiconductor layer S4, the gate electrode GE is formed via the gate insulating film GI. The planar shape of the mesa portion is a rectangular shape having long sides in the depth direction of the drawing.

  The planar shape of the stacked body of the gate insulating film (GI) and the gate electrode GE is a rectangular shape having long sides in the depth direction (Y direction) in the drawing (see FIG. 16). The width (length in the X direction, the direction in which current flows from the drain electrode to the source electrode, ie, the length in the gate length direction) of the gate electrode GE is larger than the width (length in the X direction) of the mesa portion.

Here, in the present embodiment, four layers of films (GIa to GId) are formed as the gate insulating film GI. Specifically, a gate insulating film is provided in which two layers of crystalline aluminum oxide (Al ₂ O ₃ ) located in the lower layer and silicon oxide (SiO ₂ ) located in the upper layer are stacked in two layers. ing.

As described above, in the present embodiment, as the gate insulating film GI, a film in which a two-layered film of a crystalline Al ₂ O ₃ film and a SiO ₂ film provided thereon is repeatedly stacked is used. Then, the Al ₂ O ₃ film formed on the SiO ₂ film is a film formed in an amorphous state and then crystallized. By using such a laminated film as the gate insulating film GI, as described above, the threshold voltage (Vt) can be improved.

  In addition, a field plate insulating film FP is formed on the third nitride semiconductor layer S3 on both sides of the mesa portion. In other words, a field plate insulating film FP having an opening is formed on the third nitride semiconductor layer S3, and a mesa is disposed inside the opening. Then, the gate insulating film GI and the gate electrode GE are disposed so as to cover the opening of the field plate insulating film FP. Therefore, the width (length in the X direction) of the opening of the field plate insulating film FP is smaller than the width (length in the X direction) of the gate electrode GE and larger than the width (length in the X direction) of the mesa. As described above, the breakdown voltage of the semiconductor device can be improved by providing the field plate insulating film FP under the end of the gate electrode GE.

  Further, over the gate electrode GE, an interlayer insulating film IL1 is formed. Further, the source electrode SE or the drain electrode DE is formed on the third nitride semiconductor layer S3 on both sides of the mesa portion (S4). For example, in the interlayer insulating film IL1, a contact hole (connection hole) C1 is formed, and the source electrode SE and the drain electrode DE are disposed in and on the contact hole C1. An insulating film IL2 is formed over the source electrode SE and the drain electrode DE. The insulating film IL2 is a laminated film of the lower film IL2a and the upper film IL2b.

  As shown in FIG. 16, the planar shape of the drain electrode DE is a rectangular shape having a long side in the Y direction. The planar shape of the source electrode SE is a rectangular shape having long sides in the Y direction. Under the drain electrode DE, a contact hole C1 to be a connection portion (connection region) between the drain electrode DE and the third nitride semiconductor layer S3 is disposed. The planar shape of the contact hole C1 is a rectangular shape having long sides in the Y direction. Under the source electrode SE, a contact hole C1 to be a connection portion (connection region) between the source electrode SE and the third nitride semiconductor layer S3 is disposed. The planar shape of the contact hole C1 is a rectangular shape having long sides in the Y direction.

  The gate electrode GE is disposed between the drain electrode DE and the source electrode SE. As described above, the gate electrode GE has a rectangular shape having a long side in the Y direction.

  Further, as shown in FIG. 16, the drain electrode DE, the gate electrode GE, and the source electrode SE are repeatedly disposed in a plurality.

  That is, the planar shape of the drain electrode DE is a rectangular shape having long sides in the Y direction. A plurality of linear drain electrodes DE are arranged at regular intervals in the X direction. The planar shape of the source electrode SE is a rectangular shape having long sides in the Y direction. A plurality of linear source electrodes SE are arranged at regular intervals in the X direction. The plurality of source electrodes SE and the plurality of drain electrodes DE are alternately arranged along the X direction. The gate electrode GE is disposed between the contact hole C1 below the drain electrode DE and the contact hole C1 below the source electrode SE.

  Further, the plurality of drain electrodes DE are connected by a drain pad (also referred to as a terminal portion) DP. The drain pad DP is arranged to extend in the X direction on one end side (e.g., the upper part in FIG. 16) of the drain electrode DE. In other words, the plurality of drain electrodes DE are arranged to protrude in the Y direction from the drain pad DP extending in the X direction. Such a shape may be referred to as a comb shape.

  The plurality of source electrodes SE are connected by source pads (also referred to as terminals) SP. The source pad SP is arranged to extend in the X direction on the other end side (for example, the lower portion in FIG. 16) of the source electrode SE. In other words, the plurality of source electrodes SE are arranged to protrude in the Y direction from the source pad SP extending in the X direction. Such a shape may be referred to as a comb shape.

  The plurality of gate electrodes GE are connected by the gate line GL. The gate line GL is arranged to extend in the X direction on one end side (for example, the lower portion in FIG. 16) of the gate electrode GE. In other words, the plurality of gate electrodes GE are arranged to protrude in the Y direction from the gate line GL extending in the X direction. The gate line GL is connected to, for example, gate pads GP provided on both sides (for example, right and left sides in FIG. 16) of the gate line GL in the X direction.

  Under the gate electrode GE and the gate line GL, the mesa portion of the fourth nitride semiconductor layer S4 is disposed via the gate insulating film (GI).

  The source electrode SE, the drain electrode DE and the gate electrode GE are mainly disposed on the active region AC surrounded by the element isolation region ISO. The planar shape of the active region AC is a substantially rectangular shape having long sides in the X direction. On the other hand, the drain pad DP, the gate line GL, and the source pad SP are disposed on the element isolation region ISO. Gate line GL is arranged between active region AC and source pad SP. The element isolation region ISO is a region in which crystallinity is destroyed in the nitride semiconductor layer by implanting ion species such as boron (B) and nitrogen (N) by ion implantation or the like.

[Description of manufacturing method]
Next, the method of manufacturing the semiconductor device of the present embodiment will be described with reference to FIGS. 17 to 33, and the configuration of the semiconductor device will be clarified more. 17 to 33 are cross-sectional views showing the manufacturing process of the semiconductor device of the present embodiment.

  As shown in FIG. 17, a substrate SUB is prepared, and first to fourth nitride semiconductor layers (S1 to S4) are sequentially formed. As the substrate SUB, for example, a semiconductor substrate made of silicon (Si) in which the (111) plane is exposed is used. A substrate made of SiC, sapphire or the like may be used as the substrate SUB in addition to the above silicon. Alternatively, a substrate made of GaN may be used. Generally, all nitride semiconductor layers (compound semiconductor layers of group III-V) formed later on the substrate SUB are grown by III-group element surface growth (that is, gallium surface growth or aluminum surface growth in this case). Form. After the nucleation layer and the high resistance buffer layer are formed on the substrate SUB, the first to fourth nitride semiconductor layers (S1 to S4) may be sequentially formed. For example, an aluminum nitride (AlN) layer can be used as a nucleation layer, and this layer can be formed by epitaxial growth using, for example, metal organic chemical vapor deposition (MOCVD). it can. In addition, a superlattice structure in which a stacked film (AlN / GaN film) of a gallium nitride (GaN) layer and an aluminum nitride (AlN) layer is repeatedly stacked can be used as the high resistance buffer layer. The body can be formed, for example, by epitaxially growing a gallium nitride (GaN) layer and an aluminum nitride (AlN) layer alternately using metal organic vapor phase epitaxy.

Then, an AlGaN layer (Al composition ratio: 5%) is epitaxially grown to about 1 μm on the substrate SUB as a first nitride semiconductor layer (buffer layer) S1 using an organic metal vapor phase growth method or the like. For example, in the case of Al _x Ga _1-x N, the component ratio of the AlGaN layer is 0 or more and 0.1 or less (0 ≦ X ≦ 0.1), more preferably 0.03 or more. It can adjust in the range of 08 or less (0.03 <= X <= 0.08). When the Al composition ratio is 5%, X = 0.05. The AlGaN layer is, for example, a non-doped layer. That is, intentional doping of n-type impurities or p-type impurities is not performed.

  Next, on the first nitride semiconductor layer S1, a GaN layer is epitaxially grown to a thickness of about 40 nm as the second nitride semiconductor layer (channel layer) S2 by using the metal organic chemical vapor deposition method or the like.

Then, an AlGaN layer (Al composition ratio 22%) is epitaxially grown about 14 nm on the second nitride semiconductor layer S2 as the third nitride semiconductor layer (barrier layer) S3 using the metal organic chemical vapor deposition method or the like. . As to the component ratio of the AlGaN layer, for example, in the case of Al _Z Ga _1-Z N, Z is larger than X, 0.15 or more and less than 0.3 (0.15 ≦ Z <0.3). Preferably, 0.18 or more and 0.22 or less (0.18 ≦ X ≦ 0.22) are set.

  Here, as described above, on the second nitride semiconductor layer S2 side, which is the interface between the second nitride semiconductor layer (channel layer) S2 and the third nitride semiconductor layer (barrier layer) S3. 2DEG (two-dimensional electron gas) is generated.

  Next, on the third nitride semiconductor layer S3, a GaN layer is epitaxially grown to a thickness of about 25 nm as the fourth nitride semiconductor layer S4 using metal organic vapor phase epitaxy or the like. By the film formation of the fourth nitride semiconductor layer S4, the 2DEG disappears.

  The first to fourth nitride semiconductor layers S1 to S4 grow layers while introducing, for example, a carrier gas and a source gas into the apparatus. As a source gas, a gas containing a constituent element of a nitride semiconductor layer (here, an AlGaN layer or a GaN layer) is used. For example, when forming an AlGaN layer, trimethylaluminum (TMAl), trimethylgallium (TMG), and ammonia are used as source gases for Al, Ga, and N, respectively. Further, for example, in forming a GaN layer, trimethylgallium (TMG) and ammonia are used as source gases for Ga and N, respectively. As described above, according to the epitaxial growth method, the component ratio of each layer can be easily and accurately adjusted by adjusting the flow rate of the source gas. In addition, according to the epitaxial growth method, it is possible to easily and continuously form layers having different elemental compositions by switching the source gas.

  Next, an element isolation region (ISO) not appearing in the cross section shown in FIG. 17 is formed (see FIG. 16). For example, the fourth nitride semiconductor layer S4 is covered with a protective film such as an insulating film, and a photoresist film (not shown) in which an element isolation region is opened is formed on the protective film by photolithography. Then, using the photoresist film as a mask, boron ions are implanted through the protective film to form an element isolation region (ISO). Thus, by implanting an ion species such as boron (B) or nitrogen (N), crystallinity is destroyed in the nitride semiconductor layer, and an element isolation region (ISO) is formed.

For example, boron ions are implanted at a density of about 1 × 10 ¹⁴ to 4 × 10 ¹⁴ cm ⁻² into a part of the laminate including the first to fourth nitride semiconductor layers S1 to S4. The implantation energy is, for example, about 100 to 200 keV. The boron ion implantation conditions are adjusted so that the implantation depth, that is, the bottom of the element isolation region (ISO) is located below the bottom surface of the third nitride semiconductor layer (barrier layer) S3, for example. . Thus, the element isolation region (ISO) is formed. A region surrounded by the element isolation region (ISO) is an active region AC. As shown in FIG. 16, this active region AC is substantially rectangular. Thereafter, the photoresist film is removed by plasma peeling treatment or the like, and the protective film is further removed.

  Next, as shown in FIG. 18, a silicon oxide film, for example, is formed as the mask film MK to a film thickness of 100 nm using the LPCVD method or the like on the fourth nitride semiconductor layer S4. Next, a photoresist film PR1 is formed by photolithography in the mesa formation region on the mask film MK. Then, using this photoresist film as a mask, the mask film MK is etched (FIG. 19). For example, when a silicon oxide film is used as the mask film MK, dry etching using a fluorine-based gas is performed, for example. Thereafter, the photoresist film PR1 is removed by plasma peeling treatment or the like.

  Next, as shown in FIG. 20, a mesa portion made of the fourth nitride semiconductor layer S4 is formed. For example, the fourth nitride semiconductor layer S4 is removed by dry etching using a chlorine-based gas using the mask film MK as a mask. At this stage, the mesa portion is formed partially (for example, in a rectangular shape having a long side in the Y direction) on the third nitride semiconductor layer (barrier layer) S3, and below that, the 2DEG remains lost. And 2DEG reoccurs on both sides of the mesa. Thereafter, the mask film MK is removed by etching. When, for example, a silicon oxide film is used as the mask film MK, the mask film is removed by wet etching using buffered hydrofluoric acid, for example.

  Next, as shown in FIGS. 21 and 22, a field plate insulating film FP is formed on the third nitride semiconductor layer S3 on both sides of the mesa portion. For example, as shown in FIG. 21, on the third nitride semiconductor layer S3 and the fourth nitride semiconductor layer S4, a silicon nitride film is used as a film for the field plate insulating film FP by plasma CVD or the like to a thickness of about 90 nm. accumulate. Next, over the silicon nitride film, a photoresist film PR2 having an opening over the mesa portion is formed. Using this photoresist film PR2 as a mask, the film for field plate insulating film FP is etched. For example, the film for the field plate insulating film FP is etched by dry etching using a hydrofluoric acid-based gas (FIG. 22). Thereafter, the photoresist film PR2 is removed by plasma peeling treatment or the like. Thereby, as shown in FIG. 22, it is possible to form the field plate insulating film FP having an opening wider than the width of the mesa portion.

Next, as shown in FIGS. 23 to 28, the gate insulating film GI and the gate electrode GE are formed on the mesa portion formed of the fourth nitride semiconductor layer S4. For example, amorphous aluminum oxide (a-Al ₂ O ₃ ) is formed on the mesa portion made of the fourth nitride semiconductor layer S4, the third nitride semiconductor layer S3 and the field plate insulating film FP using the ALD method. The film is formed to have a film thickness of 5 nm at a film formation temperature of 300.degree. Next, the amorphous aluminum oxide (a-Al ₂ O ₃ ) is subjected to heat treatment at 800 ° C. for 10 minutes in an inert gas (for example, nitrogen) atmosphere. By this heat treatment, amorphous aluminum oxide (a-Al ₂ O ₃ ) is crystallized to be crystalline aluminum oxide (c-Al ₂ O ₃ ) (FIG. 23). As described above, the film thickness of amorphous aluminum oxide (a-Al ₂ O ₃ ) or crystalline aluminum oxide (c-Al ₂ O ₃ ) is 2 nm or more and 20 nm or less, more preferably 5 nm or more and 10 nm or less It can be adjusted in the range of

Next, as shown in FIG. 24, a silicon oxide film (SiO ₂ film) is formed over the first gate insulating film GIa as a second gate insulating film GIb. For example, a silicon oxide film (SiO ₂ film) is deposited to a thickness of 10 nm at a deposition temperature of 400 ° C. by using the LPCVD method. As described above, the thickness of the silicon oxide film (SiO ₂ film) can be adjusted in the range of 5 nm or more and 20 nm or less, more preferably 5 nm or more and 10 nm or less.

Here, as the second gate insulating film GIb, a silicon oxide film (SiO ₂ film) is formed on crystalline aluminum oxide (c-Al ₂ O ₃ ), so an interface of these films is obtained. A dipole is produced.

Next, on the second gate insulating film GIb, amorphous aluminum oxide (a-Al ₂ O ₃ ) is deposited to a thickness of 10 nm at a deposition temperature of 300 ° C. using an ALD method. Next, the amorphous aluminum oxide (a-Al ₂ O ₃ ) is subjected to heat treatment at 800 ° C. for 10 minutes in an inert gas (for example, nitrogen) atmosphere. By this heat treatment, amorphous aluminum oxide (a-Al ₂ O ₃ ) is crystallized to be crystalline aluminum oxide (c-Al ₂ O ₃ ) (FIG. 25). The heat treatment conditions are an example. However, for crystallization of amorphous aluminum oxide (a-Al ₂ O ₃ ), heat treatment at 800 ° C. or higher is preferably performed.

Here, before and after the heat treatment (crystallization), the interface between the silicon oxide film (SiO ₂ film) GIb and aluminum oxide thereon _{(a-Al 2 O 3,} c-Al 2 O 3), dipole It does not occur. As described above, the film thickness of amorphous aluminum oxide (a-Al ₂ O ₃ ) or crystalline aluminum oxide (c-Al ₂ O ₃ ) to be the third gate insulating film GIc is 2 nm or more and 20 nm or less More preferably, it can adjust in 5 nm or more and 10 nm or less of range.

Next, as shown in FIG. 26, over the third gate insulating film GIc, a silicon oxide film (SiO ₂ film) is formed as a fourth gate insulating film GId. For example, a silicon oxide film (SiO ₂ film) is deposited to a thickness of 10 nm at a deposition temperature of 400 ° C. by using the LPCVD method. As described above, the thickness of the silicon oxide film (SiO ₂ film) to be the fourth gate insulating film GId can be adjusted in the range of 5 nm to 20 nm, more preferably 5 nm to 10 nm. Thus, the gate insulating film GI formed of the four layers of insulating films (GIa to GId) can be formed. As described above, when forming the SiO ₂ film on the _Al 2 _{O 3} film, and a SiO ₂ film in an atmosphere of more than 800 ° C., subjected to crystallization of the lower of the _Al 2 _{O 3} film Alternatively, a SiO ₂ film may be formed.

Here, as the fourth gate insulating film GId, a silicon oxide film (SiO ₂ film) is formed on crystalline aluminum oxide (c-Al ₂ O ₃ ). A dipole is produced.

Thus, the threshold voltage can be cumulatively improved by repeatedly laminating the two-layer film of the crystalline Al ₂ O ₃ film and the SiO ₂ film provided thereon (see FIG. 2). ). Here, although the gate insulating film GI has four layers (GIa to GId), the gate insulating film GI may have six, eight, or ten or more layers. For example, from the lower side, the 5 nm crystalline Al ₂ O ₃ film (GIa), the 10 nm SiO ₂ film (GIb), the 10 nm crystalline Al ₂ O ₃ film (GIc), the 10 nm SiO ₂ from the lower side A film in which films (GId) are sequentially stacked may be used as a gate insulating film. In addition, from the lower side, a 5 nm crystalline Al ₂ O ₃ film, a 5 nm SiO ₂ film, a 5 nm crystalline Al ₂ O ₃ film, a 5 nm SiO ₂ film, a 5 nm crystalline Al ₂ O ₃ film A film formed by sequentially laminating 10 nm SiO ₂ films may be used as a gate insulating film.

  Then, for example, as shown in FIG. 27, a TiN (titanium nitride) film is formed on the insulating film for the gate insulating film GI as the conductive film 10 for the gate electrode GE by sputtering or the like to a thickness of 100 nm. Deposit with a certain thickness. The constituent material and film thickness of the conductive film can be appropriately adjusted. In addition to TiN, polycrystalline silicon to which a dopant such as B or P is added may be used as a conductive film for the gate electrode GE. In addition, Ti, Al, Ni, Pt, Au, and Si compounds or N compounds thereof may be used. Alternatively, a multilayer film in which these material films are stacked may be used. For example, as the conductive film, a film in which an Au film is stacked on the Ni film may be used.

  Next, a photoresist film (not shown) is formed in the formation region of the gate electrode GE on the conductive film for the gate electrode GE by photolithography. Using the photoresist film as a mask, the conductive film for the gate electrode GE and the gate insulating film GI are etched. For example, the TiN film and the aluminum oxide film are etched by dry etching using a chlorine-based gas, and the silicon oxide film is etched by dry etching using a fluorine-based gas. Note that a patterned insulating film (eg, a silicon oxide film) or the like may be used as the mask. Thereafter, the photoresist film is removed by plasma peeling treatment or the like. Thereby, as shown in FIG. 28, the gate electrode GE is formed on the fourth nitride semiconductor layer S4 via the gate insulating film GI.

  Then, as shown in FIG. 29, over the gate electrode GE, the interlayer insulating film IL1 is formed. For example, a silicon oxide film is deposited to about 1 μm as the interlayer insulating film IL1 using the CVD method or the like. Note that a silicon nitride film of about 100 nm may be formed under the silicon oxide film. As the silicon oxide film, a so-called TEOS film may be used which also uses tetraethyl orthosilicate (Tetraethyl orthosilicate) as a raw material.

  Next, as shown in FIG. 30, contact holes C1 are formed in the interlayer insulating film IL1 using photolithography and etching techniques. For example, over the interlayer insulating film IL1, a photoresist film PR3 having an opening in each of the source electrode connection region and the drain electrode connection region is formed. Then, using the photoresist film PR3 as a mask, the interlayer insulating film IL1 is etched to form a contact hole C1. Thereafter, the photoresist film PR3 is removed by plasma peeling treatment or the like.

  Next, as shown in FIGS. 31 and 32, the source electrode SE and the drain electrode DE are formed in the contact hole C1 and over the interlayer insulating film IL1. For example, as shown in FIG. 31, the conductive film 20 is formed on the interlayer insulating film IL1 including the inside of the contact hole C1. For example, an Al film is formed as the conductive film 20. For example, an Al film is formed on the interlayer insulating film IL1 including the inside of the contact hole C1 to a film thickness of about 5 μm using a sputtering method or the like.

Next, as shown in FIG. 32, on the conductive film (Al film), a photoresist film PR4 is formed in the formation region of the source electrode SE and the drain electrode DE, and the conductive film is used as a mask. (Al film) 20 is etched. For example, the conductive film (Al film) 20 is etched by dry etching using a gas containing Cl ₂ as a main component. Thereafter, the photoresist film PR4 is removed by plasma peeling treatment or the like. Thus, the source electrode SE and the drain electrode DE can be formed. After patterning the conductive film (Al film) 10, heat treatment is performed. For example, heat treatment is performed at 550 ° C. for 30 minutes. Thereby, ohmic contact can be established between the conductive film (Al film) 20 and the layer therebelow.

  The conductive film (Al film) 20 may be patterned after the heat treatment. Alternatively, an Al / Ti film may be used as the conductive film 20. In this case, for example, a Ti film is formed to a thickness of about 16 nm by sputtering or the like, and an Al film is further formed thereon to a thickness of about 2 μm by sputtering or the like. By using the Al / Ti film, a further favorable ohmic contact can be obtained. Alternatively, an Al / Cu film may be used as the conductive film 20. As described above, the constituent material and the film thickness of the conductive film constituting the source electrode SE and the drain electrode DE can be appropriately adjusted. As such a conductive film, it is preferable to use a material in ohmic contact with the nitride semiconductor layer.

  Next, as shown in FIG. 33, over the interlayer insulating film IL1 including over the source electrode SE and the drain electrode DE, an insulating film (protective film) IL2 is formed. For example, of the insulating film (protective film) IL2, a silicon nitride film is deposited to a thickness of about 90 nm as the lower film (also referred to as a passivation film) IL2a using a CVD method or the like. Next, on the silicon nitride film, a polyimide film is deposited to a thickness of about 7 μm as the upper film IL2 b using a coating method or the like.

  Note that after forming a multilayer wiring connected to the source electrode SE and the drain electrode DE, an insulating film (protective film) having the above-mentioned polyimide film or the like may be formed on the uppermost layer wiring. Thereafter, the insulating film (laminated film of a polyimide film and a silicon nitride film) is removed in a region requiring electrical connection with the outside of the gate pad GP, the source pad SP, the drain pad DP, etc. (see FIG. 16). And exposing a part of the lower conductive film (wiring) to form a pad portion (not shown).

  Through the above steps, the semiconductor device of this embodiment can be formed. Note that the above process is an example, and the semiconductor device of the present embodiment may be manufactured by processes other than the above process.

Second Embodiment
Hereinafter, the semiconductor device of the present embodiment will be described in detail with reference to the drawings. In the second embodiment, the configuration other than the components of the gate electrode and the gate insulating film is the same as that of the first embodiment, and can be formed by the same manufacturing method as that of the first embodiment.

[Structure explanation]
FIG. 34 is a cross-sectional view showing the configuration of the semiconductor device of the present embodiment. The semiconductor device shown in FIG. 34 is a MOS type field effect transistor using a nitride semiconductor. The semiconductor device of this embodiment is a so-called recess gate type semiconductor device. In addition, about the structure similar to Embodiment 1, the same code | symbol is attached | subjected and the detailed description is abbreviate | omitted. The plan view of the semiconductor device of this embodiment is the same as that of FIG. 16, and FIG. 34 corresponds to the AA part of FIG.

  In the semiconductor device of the present embodiment, as shown in FIG. 34, a first nitride semiconductor layer S1, a second nitride semiconductor layer S2 and a third nitride semiconductor layer S3 are sequentially formed on a substrate SUB. There is. The nucleation layer and the high-resistance buffer layer thereon may be formed on the substrate SUB, and then the first nitride semiconductor layer S1 and the like may be formed. The substrate SUB, the first to third nitride semiconductor layers (S1 to S3), the nucleation layer, and the high resistance buffer layer may be formed of the same material as in the first embodiment and have the same film thickness. it can.

  The second nitride semiconductor layer S2 has an electron affinity equal to that of the first nitride semiconductor layer S1, or has a larger electron affinity than the first nitride semiconductor layer S1 (S1 ≦ S2).

  The third nitride semiconductor layer S3 has a smaller electron affinity than the first nitride semiconductor layer S1 (S1> S3).

  Here, in the present embodiment, the gate electrode GE penetrates the field plate insulating film FP and the third nitride semiconductor layer S3, and is a groove (trench, recess formed by slightly digging the second nitride semiconductor layer S2). Also, it is formed inside the gate insulating film GI in the inside of T).

  Therefore, the 2DEG generated near the interface between the second nitride semiconductor layer (channel layer) S2 and the third nitride semiconductor layer (barrier layer) S3 on the second nitride semiconductor layer S2 side is divided by the trench T. It is done. Therefore, when a predetermined voltage (threshold voltage) is applied to the gate electrode GE, a channel is formed below the gate electrode GE, the channel between 2DEGs is conducted by this channel, and the transistor is turned on. That is, the normally off operation can be realized.

  The planar shape of the groove T is a rectangular shape having long sides in the depth direction in the drawing (Y direction in FIG. 16). The planar shape of the stacked body of the gate insulating film (GI) and the gate electrode GE is a rectangular shape having long sides in the Y direction (see FIG. 16). The width (length in the X direction, the direction in which current flows from the drain electrode to the source electrode, ie, the length in the gate length direction) of the gate electrode GE is larger than the width (length in the X direction) of the trench T.

Here, in the present embodiment, four layers of films (GIa to GId) are formed as the gate insulating film GI. Specifically, a gate insulating film is provided in which two layers of crystalline aluminum oxide (Al ₂ O ₃ ) located in the lower layer and silicon oxide (SiO ₂ ) located in the upper layer are stacked in two layers. ing.

As described above, in the present embodiment, as the gate insulating film GI, a film in which a two-layered film of a crystalline Al ₂ O ₃ film and a SiO ₂ film provided thereon is repeatedly stacked is used. Then, the Al ₂ O ₃ film formed on the SiO ₂ film is a film formed in an amorphous state and then crystallized. By using such a laminated film as the gate insulating film GI, as described above, the threshold voltage (Vt) can be improved.

  The field plate insulating film FP described above is formed on the third nitride semiconductor layer S3 on both sides of the trench T. As described above, the breakdown voltage of the semiconductor device can be improved by providing the field plate insulating film FP under the end of the gate electrode GE.

  Further, as in the case of the first embodiment, the interlayer insulating film IL1 is formed over the gate electrode GE. Further, the source electrode SE or the drain electrode DE is formed on the third nitride semiconductor layer S3 on both sides of the mesa portion. For example, in the interlayer insulating film IL1, a contact hole (connection hole) C1 is formed, and the source electrode SE and the drain electrode DE are disposed in and on the contact hole C1. An insulating film IL2 is formed over the source electrode SE and the drain electrode DE. The insulating film IL2 is a laminated film of the lower film IL2a and the upper film IL2b.

[Description of manufacturing method]
Next, a method of manufacturing the semiconductor device of the present embodiment will be described with reference to FIGS. 35 to 51, and the configuration of the semiconductor device will be clarified more. 35 to 51 are cross-sectional views showing the manufacturing process of the semiconductor device of the present embodiment. In addition, the detailed description is abbreviate | omitted about the structure and process similar to Embodiment 1. FIG.

  As shown in FIG. 35, a substrate SUB is prepared, and first to third nitride semiconductor layers (S1 to S3) are sequentially formed. As the substrate SUB, the same one as in the case of the first embodiment can be used. The first to third nitride semiconductor layers (S1 to S3) can be formed in the same manner using the same material as that of the first embodiment. Here, at the interface between the second nitride semiconductor layer (channel layer) S2 and the third nitride semiconductor layer (barrier layer) S3, on the side of the second nitride semiconductor layer S2, 2DEG (two-dimensional electron) Gas) is generated. Then, an element isolation region (ISO) not appearing in the cross section shown in FIG. 35 is formed in the same manner as in the first embodiment (see FIG. 16).

  Next, as shown in FIGS. 36 to 39, over the third nitride semiconductor layer S3, a field plate insulating film FP having an opening is formed. For example, as shown in FIG. 36, a silicon nitride film is deposited to a thickness of about 90 nm on the third nitride semiconductor layer S3 as a film for the field plate insulating film FP using a plasma CVD method or the like. Next, over the silicon nitride film, a photoresist film PR21 having an opening in the formation region of the trench T is formed (FIG. 37). Using this photoresist film PR21 as a mask, the film for field plate insulation film FP is etched. For example, the film for the field plate insulating film FP is etched by dry etching using a fluorine-based gas (FIG. 38). Thereafter, the photoresist film PR21 is removed by plasma peeling treatment or the like. Thereby, as shown in FIG. 39, field plate insulating film FP having an opening in the formation region of trench T can be formed.

  Then, as shown in FIG. 40, the field plate insulating film FP and the third nitride semiconductor are etched by etching the third nitride semiconductor layer S3 and the second nitride semiconductor layer S2 using the field plate insulating film FP as a mask. A trench T is formed through the layer S3 to expose the second nitride semiconductor layer S2. For example, the groove T is formed by dry etching using a chlorine-based gas. After this etching, heat treatment (annealing) may be performed to recover etching damage.

Then, as shown in FIG. 41 to FIG. 46, the gate insulating film GI and the gate electrode GE are formed on the field plate insulating film FP and in the trench T in which the second nitride semiconductor layer (channel layer) S2 is exposed at the bottom. Form First, for example, amorphous aluminum oxide (a-Al ₂ O ₃ ) is formed on the bottom and side surfaces of the trench T and the field plate insulating film FP shown in FIG. 41 using an ALD method at a film forming temperature of 300 ° C. The film is formed to have a thickness of 5 nm. Next, the amorphous aluminum oxide (a-Al ₂ O ₃ ) is subjected to heat treatment at 800 ° C. for 10 minutes in an inert gas (for example, nitrogen) atmosphere. By this heat treatment, amorphous aluminum oxide (a-Al ₂ O ₃ ) is crystallized to be crystalline aluminum oxide (c-Al ₂ O ₃ ) (FIG. 41). As described above, the film thickness of amorphous aluminum oxide (a-Al ₂ O ₃ ) or crystalline aluminum oxide (c-Al ₂ O ₃ ) is 2 nm or more and 20 nm or less, more preferably 5 nm or more and 10 nm or less It can be adjusted in the range of

Then, as shown in FIG. 42, over the first gate insulating film GIa, a silicon oxide film (SiO ₂ film) is formed as a second gate insulating film GIb. For example, a silicon oxide film (SiO ₂ film) is deposited to a thickness of 10 nm at a deposition temperature of 400 ° C. by using the LPCVD method. As described above, the thickness of the silicon oxide film (SiO ₂ film) can be adjusted in the range of 5 nm or more and 20 nm or less, more preferably 5 nm or more and 10 nm or less.

Here, as the second gate insulating film GIb, a silicon oxide film (SiO ₂ film) is formed on crystalline aluminum oxide (c-Al ₂ O ₃ ), so an interface of these films is obtained. A dipole is produced.

Next, on the second gate insulating film GIb, amorphous aluminum oxide (a-Al ₂ O ₃ ) is deposited to a thickness of 10 nm at a deposition temperature of 300 ° C. using an ALD method. Next, the amorphous aluminum oxide (a-Al ₂ O ₃ ) is subjected to heat treatment at 800 ° C. for 10 minutes in an inert gas (for example, nitrogen) atmosphere. By this heat treatment, amorphous aluminum oxide (a-Al ₂ O ₃ ) is crystallized to be crystalline aluminum oxide (c-Al ₂ O ₃ ) (FIG. 43). The heat treatment conditions are an example. However, for crystallization of amorphous aluminum oxide (a-Al ₂ O ₃ ), heat treatment at 800 ° C. or higher is preferably performed.

Here, before and after the heat treatment (crystallization), the interface between the silicon oxide film (SiO ₂ film) GIb and aluminum oxide thereon _{(a-Al 2 O 3,} c-Al 2 O 3), dipole It does not occur. As described above, the film thickness of amorphous aluminum oxide (a-Al ₂ O ₃ ) or crystalline aluminum oxide (c-Al ₂ O ₃ ) to be the third gate insulating film GIc is 2 nm or more and 20 nm or less More preferably, it can adjust in 5 nm or more and 10 nm or less of range.

Then, as shown in FIG. 44, over the third gate insulating film GIc, a silicon oxide film (SiO ₂ film) is formed as a fourth gate insulating film GId. For example, a silicon oxide film (SiO ₂ film) is deposited to a thickness of 10 nm at a deposition temperature of 400 ° C. by using the LPCVD method. As described above, the thickness of the silicon oxide film (SiO ₂ film) to be the fourth gate insulating film GId can be adjusted in the range of 5 nm to 20 nm, more preferably 5 nm to 10 nm. Thus, the gate insulating film GI formed of the four layers of insulating films (GIa to GId) can be formed. As described above, when forming the SiO ₂ film on the _Al 2 _{O 3} film, and a SiO ₂ film in an atmosphere of more than 800 ° C., subjected to crystallization of the lower of the _Al 2 _{O 3} film Alternatively, a SiO ₂ film may be formed.

Here, as the fourth gate insulating film GId, a silicon oxide film (SiO ₂ film) is formed on crystalline aluminum oxide (c-Al ₂ O ₃ ). A dipole is produced.

Thus, the threshold voltage can be cumulatively improved by repeatedly laminating the two-layer film of the crystalline Al ₂ O ₃ film and the SiO ₂ film provided thereon (see FIG. 2). ). Here, although the gate insulating film GI has four layers (GIa to GId), the gate insulating film GI may have six, eight, or ten or more layers. For example, from the lower side, the 5 nm crystalline Al ₂ O ₃ film (GIa), the 10 nm SiO ₂ film (GIb), and the 10 nm crystalline Al ₂ O ₃ film (GIc) described in the first embodiment A film formed by sequentially stacking 10 nm SiO ₂ films (GId) may be used as a gate insulating film. In addition, from the lower side, a 5 nm crystalline Al ₂ O ₃ film, a 5 nm SiO ₂ film, a 5 nm crystalline Al ₂ O ₃ film, a 5 nm SiO ₂ film, a 5 nm crystalline Al ₂ O ₃ film A film formed by sequentially laminating 10 nm SiO ₂ films may be used as a gate insulating film.

  Then, for example, a TiN (titanium nitride) film is deposited, for example, as a conductive film 10 for the gate electrode GE on the insulating film for the gate insulating film GI to a film thickness of about 100 nm using a sputtering method or the like. (Figure 45). As in the case of the first embodiment, a film other than the TiN film may be used as the conductive film 10 for the gate electrode GE.

  Next, a photoresist film (not shown) is formed in the formation region of the gate electrode GE on the conductive film for the gate electrode GE by photolithography. Using the photoresist film as a mask, the conductive film for the gate electrode GE and the gate insulating film GI are etched. For example, the TiN film and the aluminum oxide film are etched by dry etching using a chlorine-based gas, and the silicon oxide film is etched by dry etching using a fluorine-based gas. Note that a patterned insulating film (eg, a silicon oxide film) or the like may be used as the mask. Thereafter, the photoresist film is removed by plasma peeling treatment or the like. Thereby, as shown in FIG. 46, the gate electrode GE is formed on the fourth nitride semiconductor layer S4 via the gate insulating film GI.

  The interlayer insulating film IL1, the source electrode SE, the drain electrode DE, and the insulating film (protective film) IL2 described below can be formed in the same manner as in the first embodiment.

  Briefly, as shown in FIG. 47, the interlayer insulating film IL1 is formed over the gate electrode GE. Next, as shown in FIG. 48, contact holes C1 are formed in the interlayer insulating film IL1 using photolithography and etching techniques. For example, the contact hole C1 is formed by etching the interlayer insulating film IL1 using the photoresist film PR22 as a mask. Next, as shown in FIG. 49, conductive film 20 is formed on interlayer insulating film IL1 including the inside of contact hole C1, and as shown in FIG. 50, photoresist film PR23 on the conductive film (Al film) is formed. As a mask, the conductive film (Al film) 20 is etched to form the source electrode SE and the drain electrode DE. Next, after removing the photoresist film PR23 by plasma peeling treatment or the like, as shown in FIG. 51, an insulating film (protective film) IL2 is formed over the interlayer insulating film IL1 including over the source electrode SE and the drain electrode DE. .

  Note that after forming a multilayer wiring connected to the source electrode SE and the drain electrode DE, an insulating film (protective film) having the above-mentioned polyimide film or the like may be formed on the uppermost layer wiring. Thereafter, the insulating film (laminated film of a polyimide film and a silicon nitride film) is removed in a region requiring electrical connection with the outside of the gate pad GP, the source pad SP, the drain pad DP, etc. (see FIG. 16). And exposing a part of the lower conductive film (wiring) to form a pad portion (not shown).

  Through the above steps, the semiconductor device of this embodiment can be formed. Note that the above process is an example, and the semiconductor device of the present embodiment may be manufactured by processes other than the above process.

Third Embodiment
In the first and second embodiments, the gate insulating film is formed of four or more layers, but may be formed of two layers. In the first embodiment and the like, the laminated film of crystalline aluminum oxide (Al ₂ O ₃ ) and silicon oxide (SiO ₂ ) has been described as an example, but the first metal oxide film (M 1 O) and the second metal oxide film A laminated film of metal oxide film (M2O) may be used.

(Application example 1)
FIG. 52 is a cross-sectional view showing the configuration of the semiconductor device of the application 1 of the present embodiment. In the semiconductor device of this application example, the configuration other than the gate insulating film GI is the same as that of the semiconductor device shown in the first embodiment (FIG. 1).

That is, in the semiconductor device of the first embodiment (FIG. 1), the gate insulating film GI made of four insulating films (GIa to GId) is used, but in the present embodiment, two insulating films The gate insulating film GI made of (GIa, GIb) is used. Specifically, a first gate insulating film GIa made of crystalline aluminum oxide (Al ₂ O ₃ ) and a second gate insulating film GIb made of silicon oxide (SiO ₂ ) thereon as the gate insulating film GI The laminated film of

Also in this case, as described with reference to FIGS. 13 and 14 in the first embodiment, a dipole is generated at the boundary between the crystalline Al ₂ O ₃ film and the SiO ₂ film, and this dipole has an interface It cancels the electric field due to the positive charge Q _int . Therefore, the threshold voltage (Vt) can be improved.

As described above, the threshold voltage (Vt) can be improved also when a two-layer film of a crystalline Al ₂ O ₃ film and a SiO ₂ film provided thereon is used as the gate insulating film GI. it can. However, when the film thickness of the second gate insulating film GIb made of silicon oxide (SiO ₂ ) in the upper layer is large, the threshold voltage (Vt) is lowered more than the effect of the dipole (see FIG. 13). Therefore, when using a two-layered film of a crystalline Al ₂ O ₃ film and a SiO ₂ film provided thereon as the gate insulating film GI, the second layer made of silicon oxide (SiO ₂ ) in the upper layer is used. The thickness of the gate insulating film GIb is preferably 5 nm or more and 10 nm or less. In addition, as the first gate insulating film GIa made of crystalline aluminum oxide (Al ₂ O ₃ ) in the lower layer, as described above, the lower limit of the film thickness is preferably 2 nm or more, more preferably 5 nm or more . As a design example of the film thickness in the case of using a two-layer film, for example, aluminum oxide GIa can be 37.5 nm and silicon oxide GIb can be 10 nm.

  Also, the two-layer gate insulating film of this application example may be applied to the semiconductor device of the mesa MOS structure (FIG. 15) or the recess gate type semiconductor device (FIG. 34) described in the first and second embodiments.

  In the method of manufacturing a semiconductor device of this application example, in the method of manufacturing the semiconductor device of the first and second embodiments, the upper two insulating films (GIc, GIc) among the four insulating films (GIa to GId) are used. The formation process of GId) may be omitted.

(Application example 2)
FIG. 53 is a cross sectional view showing a configuration of a semiconductor device of application example 2 of the present embodiment. In the semiconductor device of this application example, the configuration other than the gate insulating film GI is the same as that of the semiconductor device shown in the first embodiment (FIG. 1).

That is, in the semiconductor device of the first embodiment (FIG. 1), the crystalline Al ₂ O ₃ film (GIa), the SiO ₂ film (GIb), the crystal is formed from the lower side from the lower side from the gate insulating film GI. The gate insulating film GI may be formed by using an oxide film of various metals (elements) although it is composed of a crystalline Al ₂ O ₃ film (GIc) and a SiO ₂ film (GId).

  Specifically, as the gate insulating film GI, from the lower side, the oxide film (M1O, GIa) of the crystalline first metal, the oxide film (M2O, GIb) of the second metal, the oxidation of the crystalline first metal A four-layer film of a film (M1O, GIc) and an oxide film of a second metal (M2O, GId) is used. The first metal (M1) has lower electronegativity than the second metal (M2). Needless to say, the composition ratio of M1 to O and the composition ratio of M2 to O change depending on the selected element.

  Then, the gate insulating film GI is formed by the following steps. A crystalline first film is formed on the mesa portion, and a first film made of an oxide of a first metal is formed, and a second film made of an oxide of a second metal is formed on the crystalline first film. Form a film. Then, a third film which is an amorphous third film made of an oxide of the first metal is formed on the second film, and the amorphous third film is subjected to a heat treatment to be crystallized. A crystalline third film which is formed of an oxide of a first metal; Further, a fourth film made of an oxide of a second metal is formed on the crystalline third film.

In the first and second embodiments, the first metal is Al, and the second metal (element) is Si. The first film (GIa) and the third film (GIc) are aluminum oxide films (Al ₂ O ₃ ), and the second film (GIb) and the fourth film (GId) are silicon oxide films (SiO ₂₎ ).

  Also in such a stacking relationship, as described in the first embodiment, “the second metal oxide film (M 2 O) is formed on the crystalline first metal oxide film (c—M 1 O) A dipole is generated, and an event that "amorphous first metal oxide film (a-M1O) is formed on the second metal oxide film (M2O) and crystallized, no dipole is generated" In the gate insulating film, the threshold voltage is obtained by repeatedly stacking a two-layer film of crystalline first metal oxide film (M1O, GIa) and second metal oxide film (M2O, GIb). Can be cumulatively improved (see FIG. 2).

  The first metal M1 and the second metal are selected from Group 2, Group 3, Group 4, Group 5, and Group 13 shown in Table 1 below (Porning's electronegativity). . As the first metal M1 and the second metal, in particular, it is preferable that the oxide is present as a solid at a device operating range temperature (for example, <200 ° C.) and has a good insulating property in a thin film. Among these metals, a combination of the lower oxide film and the upper oxide film may be selected from the relationship of electronegativity.

  As mentioned above, although the invention made by the present inventor was concretely explained based on an embodiment, the present invention is not limited to the above-mentioned embodiment, and can be variously changed in the range which does not deviate from the gist. Needless to say.

  For example, the gate insulating film of the application example 2 may be a two-layer film and applied to the semiconductor device described in the application example 1.

[Supplementary Note 1]
A first nitride semiconductor layer,
A second nitride semiconductor layer formed on the first nitride semiconductor layer;
A third nitride semiconductor layer formed on the second nitride semiconductor layer;
A groove penetrating through the third nitride semiconductor layer and reaching the second nitride semiconductor layer;
A gate electrode disposed in the groove via a gate insulating film;
Have
The electron affinity of the second nitride semiconductor layer is equal to or higher than the electron affinity of the first nitride semiconductor layer,
The electron affinity of the third nitride semiconductor layer is smaller than the electron affinity of the first nitride semiconductor layer. The gate insulating film is a crystalline first film, and is made of an oxide of a first metal. A second film made of an oxide of a second metal, and a crystalline third film, the third film made of an oxide of the first metal and a fourth film made of an oxide of the second metal The semiconductor device which has a laminated body laminated | stacked in order from the bottom.

[Supplementary Note 2]
In the semiconductor device according to appendix 1,
The semiconductor device, wherein the first metal has lower electronegativity than the second metal.

[Supplementary Note 3]
In the semiconductor device according to appendix 1,
The first film and the third film are aluminum oxide films,
The semiconductor device, wherein the second film and the fourth film are silicon oxide films.

[Supplementary Note 4]
(A) forming a second nitride semiconductor layer on the first nitride semiconductor layer;
(B) forming a third nitride semiconductor layer on the second nitride semiconductor layer;
(C) forming a mesa portion of the fourth nitride semiconductor layer on the third nitride semiconductor layer;
(D) forming a gate insulating film above the mesa portion;
(E) forming a gate electrode on the gate insulating film;
Have
The electron affinity of the second nitride semiconductor layer is equal to or higher than the electron affinity of the first nitride semiconductor layer,
The electron affinity of the third nitride semiconductor layer is smaller than the electron affinity of the first nitride semiconductor layer,
The electron affinity of the fourth nitride semiconductor layer is greater than the electron affinity of the first nitride semiconductor layer,
In the step (d),
(D1) forming a crystalline aluminum oxide film on the mesa portion;
(D2) forming a silicon oxide film on the aluminum oxide film;
Have
The aluminum oxide film has a thickness of 2 nm or more and 20 nm or less,
The method for manufacturing a semiconductor device, wherein the silicon oxide film has a thickness of 5 nm or more and 20 nm or less.

[Supplementary Note 5]
In the method of manufacturing a semiconductor device according to appendix 4,
The method of manufacturing a semiconductor device, wherein the step (d1) is a step of forming the crystalline aluminum oxide film by performing a heat treatment on the amorphous aluminum oxide film to crystallize it.

[Supplementary Note 6]
(A) forming a second nitride semiconductor layer on the first nitride semiconductor layer;
(B) forming a third nitride semiconductor layer on the second nitride semiconductor layer;
(C) forming a groove which penetrates the third nitride semiconductor layer and reaches the second nitride semiconductor layer by etching the third nitride semiconductor layer and the second nitride semiconductor layer ,
(D) forming a gate insulating film on the bottom and side walls of the groove;
(E) forming a gate electrode on the gate insulating film;
Have
The electron affinity of the second nitride semiconductor layer is equal to or higher than the electron affinity of the first nitride semiconductor layer,
The electron affinity of the third nitride semiconductor layer is smaller than the electron affinity of the first nitride semiconductor layer,
In the step (d),
(D1) forming a crystalline aluminum oxide film on the bottom and side walls of the groove;
(D2) forming a silicon oxide film on the aluminum oxide film;
Have
The aluminum oxide film has a thickness of 2 nm or more and 20 nm or less,
The silicon oxide film has a thickness of 5 nm or more and 20 nm or less.
Semiconductor device manufacturing method.

[Supplementary Note 7]
In the method of manufacturing a semiconductor device according to appendix 6,
The method of manufacturing a semiconductor device, wherein the step (d1) is a step of forming the crystalline aluminum oxide film by performing a heat treatment on the amorphous aluminum oxide film to crystallize it.

[Supplementary Note 8]
A first nitride semiconductor layer,
A second nitride semiconductor layer formed on the first nitride semiconductor layer;
A third nitride semiconductor layer formed on the second nitride semiconductor layer;
A mesa portion formed of the fourth nitride semiconductor layer formed on the third nitride semiconductor layer;
A gate electrode disposed on the mesa portion via a gate insulating film;
Have
The electron affinity of the second nitride semiconductor layer is equal to or higher than the electron affinity of the first nitride semiconductor layer,
The electron affinity of the third nitride semiconductor layer is smaller than the electron affinity of the first nitride semiconductor layer,
The electron affinity of the fourth nitride semiconductor layer is greater than the electron affinity of the first nitride semiconductor layer,
The gate insulating film has a stacked body in which a crystalline aluminum oxide film and a silicon oxide film are sequentially stacked from the bottom,
The aluminum oxide film has a thickness of 2 nm or more and 20 nm or less,
The semiconductor device, wherein the silicon oxide film has a thickness of 5 nm or more and 10 nm or less.

[Supplementary Note 9]
A first nitride semiconductor layer,
A second nitride semiconductor layer formed on the first nitride semiconductor layer;
A third nitride semiconductor layer formed on the second nitride semiconductor layer;
A groove penetrating through the third nitride semiconductor layer and reaching the second nitride semiconductor layer;
A gate electrode disposed in the groove via a gate insulating film;
Have
The electron affinity of the second nitride semiconductor layer is equal to or higher than the electron affinity of the first nitride semiconductor layer,
The electron affinity of the third nitride semiconductor layer is smaller than the electron affinity of the first nitride semiconductor layer,
The gate insulating film has a stacked body in which a crystalline aluminum oxide film and a silicon oxide film are sequentially stacked from the bottom,
The aluminum oxide film has a thickness of 2 nm or more and 20 nm or less,
The semiconductor device, wherein the silicon oxide film has a thickness of 5 nm or more and 10 nm or less.

2DEG 2D electron gas 10 conductive film 20 conductive film AC active region C1 contact hole DE drain electrode DP drain pad FP field plate insulating film GE gate electrode GI gate insulating film GIa first gate insulating film GIb second gate insulating film GIc Third gate insulating film GId Fourth gate insulating film GL Gate line GP Gate pad IL1 Interlayer insulating film IL2 Insulating film (protective film)
IL2a lower layer film IL2b upper layer film ISO element isolation region MK mask film PR1 photoresist film PR2 photoresist film PR21 photoresist film PR22 photoresist film PR23 photoresist film PR3 photoresist film PR4 photoresist film S1 first nitride semiconductor layer (buffer layer)
S2 Second nitride semiconductor layer (channel layer)
S3 Third nitride semiconductor layer (barrier layer)
S4 Fourth nitride semiconductor layer (2DEG elimination layer, mesa)
SE Source electrode SP Source pad SUB Substrate T Groove

Claims (20)

(A) forming a second nitride semiconductor layer on the first nitride semiconductor layer;
(B) forming a third nitride semiconductor layer on the second nitride semiconductor layer;
(C) forming a mesa portion of the fourth nitride semiconductor layer on the third nitride semiconductor layer;
(D) forming a gate insulating film above the mesa portion;
(E) forming a gate electrode on the gate insulating film;
Have
The electron affinity of the second nitride semiconductor layer is equal to or higher than the electron affinity of the first nitride semiconductor layer,
The electron affinity of the third nitride semiconductor layer is smaller than the electron affinity of the first nitride semiconductor layer,
The electron affinity of the fourth nitride semiconductor layer is greater than the electron affinity of the first nitride semiconductor layer,
In the step (d),
(D1) forming a first film which is a crystalline first film and is made of an oxide of a first metal on the mesa portion;
(D2) forming a second film comprising an oxide of a second metal on the crystalline first film;
(D3) A method of manufacturing a semiconductor device, comprising: forming a third film made of an oxide of the first metal, which is an amorphous third film, on the second film. In the method of manufacturing a semiconductor device according to claim 1,
In the step (d), after the step (d3),
(D4) a step of forming a third film which is a crystalline third film by subjecting the amorphous third film to a heat treatment to be crystallized, the third film being made of an oxide of the first metal;
(D5) forming a fourth film of an oxide of the second metal on the crystalline third film;
A method of manufacturing a semiconductor device, comprising: In the method of manufacturing a semiconductor device according to claim 2,
In the step (d1), the amorphous first film is subjected to heat treatment to be crystallized, thereby forming the first crystalline film and the first film made of an oxide of the first metal. A method of manufacturing a semiconductor device, which is a process of In the method of manufacturing a semiconductor device according to claim 3,
The method of manufacturing a semiconductor device, wherein the first metal has lower electronegativity than the second metal. In the method of manufacturing a semiconductor device according to claim 3,
The first film and the third film are aluminum oxide films,
The method of manufacturing a semiconductor device, wherein the second film and the fourth film are silicon oxide films. In the method of manufacturing a semiconductor device according to claim 5,
The heat treatment of the step (d4) is performed in an atmosphere of 800 ° C. or higher. In the method of manufacturing a semiconductor device according to claim 5,
The method of manufacturing a semiconductor device, wherein the steps (d4) and (d5) are steps of forming the silicon oxide film in an atmosphere of 800 ° C. or more. In the method of manufacturing a semiconductor device according to claim 5,
The aluminum oxide film has a thickness of 2 nm or more and 20 nm or less,
The method for manufacturing a semiconductor device, wherein the silicon oxide film has a thickness of 5 nm or more and 20 nm or less. In the method of manufacturing a semiconductor device according to claim 8,
The aluminum oxide film has a thickness of 5 nm or more and 10 nm or less,
The method for manufacturing a semiconductor device, wherein the silicon oxide film has a thickness of 5 nm or more and 10 nm or less. (A) forming a second nitride semiconductor layer on the first nitride semiconductor layer;
(B) forming a third nitride semiconductor layer on the second nitride semiconductor layer;
(C) forming a groove which penetrates the third nitride semiconductor layer and reaches the second nitride semiconductor layer by etching the third nitride semiconductor layer and the second nitride semiconductor layer ,
(D) forming a gate insulating film on the bottom and side walls of the groove;
(E) forming a gate electrode on the gate insulating film;
Have
The electron affinity of the second nitride semiconductor layer is equal to or higher than the electron affinity of the first nitride semiconductor layer,
The electron affinity of the third nitride semiconductor layer is smaller than the electron affinity of the first nitride semiconductor layer,
In the step (d),
(D1) forming a first film of crystalline first film comprising a first metal oxide on bottom and side walls of the groove;
(D2) forming a second film comprising an oxide of a second metal on the crystalline first film;
(D3) A method of manufacturing a semiconductor device, comprising: forming a third film made of an oxide of the first metal, which is an amorphous third film, on the second film. In the method of manufacturing a semiconductor device according to claim 10,
In the step (d), after the step (d3),
(D4) a step of forming a third film made of an oxide of the first metal, which is a crystalline third film by applying heat treatment to the amorphous third film to crystallize it;
(D5) forming a fourth film of an oxide of the second metal on the crystalline third film;
A method of manufacturing a semiconductor device, comprising: In the method of manufacturing a semiconductor device according to claim 11,
The method of manufacturing a semiconductor device, wherein the step (d1) is a step of forming the crystalline first film by performing heat treatment on the amorphous first film to crystallize it. In the method of manufacturing a semiconductor device according to claim 12,
The method of manufacturing a semiconductor device, wherein the first metal has lower electronegativity than the second metal. In the method of manufacturing a semiconductor device according to claim 12,
The first film and the third film are aluminum oxide films,
The method of manufacturing a semiconductor device, wherein the second film and the fourth film are silicon oxide films. In the method of manufacturing a semiconductor device according to claim 14,
The method of manufacturing a semiconductor device, wherein the step (d4) is performed under an atmosphere of 800 ° C. or higher. In the method of manufacturing a semiconductor device according to claim 14,
The method of manufacturing a semiconductor device, wherein the steps (d4) and (d5) are steps of forming the silicon oxide film in an atmosphere of 800 ° C. or more. In the method of manufacturing a semiconductor device according to claim 16,
The aluminum oxide film has a thickness of 5 nm or more and 10 nm or less,
The method for manufacturing a semiconductor device, wherein the silicon oxide film has a thickness of 5 nm or more and 10 nm or less. A first nitride semiconductor layer,
A second nitride semiconductor layer formed on the first nitride semiconductor layer;
A third nitride semiconductor layer formed on the second nitride semiconductor layer;
A mesa portion formed of the fourth nitride semiconductor layer formed on the third nitride semiconductor layer;
A gate electrode disposed on the mesa portion via a gate insulating film;
Have
The electron affinity of the second nitride semiconductor layer is equal to or higher than the electron affinity of the first nitride semiconductor layer,
The electron affinity of the third nitride semiconductor layer is smaller than the electron affinity of the first nitride semiconductor layer,
The electron affinity of the fourth nitride semiconductor layer is greater than the electron affinity of the first nitride semiconductor layer,
The gate insulating film is a crystalline first film, and is a first film made of an oxide of a first metal, a second film made of an oxide of a second metal, and a crystalline third film. A semiconductor device, comprising: a stacked body in which a third film made of an oxide of the first metal and a fourth film made of an oxide of the second metal are sequentially stacked from the bottom. In the semiconductor device according to claim 18,
The semiconductor device, wherein the first metal has lower electronegativity than the second metal. In the semiconductor device according to claim 18,
The first film and the third film are aluminum oxide films,
The semiconductor device, wherein the second film and the fourth film are silicon oxide films.

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