JP2019047383A - Imaging device and solid imaging element control method - Google Patents

Abstract

To provide an imaging device for imaging feature amount images in which the image quality of the feature amount images is improved.SOLUTION: The imaging device comprises a plurality of pixel circuits, and a feature amount extracting unit. In this imaging device, each of the plurality of pixel circuits generates an analog signal corresponding to the amount of received light and outputs the analog signal as a pixel signal. Furthermore, the feature amount extracting unit in the imaging device extracts, for each neighboring pixel circuit near a pixel circuit of interest among the plurality of pixel circuits, a feature amount representing by multiple values the magnitude of the difference between the pixel signal from the neighboring pixel circuit and the pixel signal from the pixel circuit of interest.SELECTED DRAWING: Figure 19

Description

  The present technology relates to an imaging apparatus and a control method for a solid-state imaging device. Specifically, the present invention relates to an imaging device that extracts a feature amount of an image and a control method of a solid-state imaging device.

  Conventionally, LBP (Local Binary Pattern) has been used in systems that perform image processing such as image recognition, texture division, and real-time video analysis. The LBP is a feature amount that represents the magnitude relationship between the pixel values of the neighboring pixels and the target pixel for each neighboring pixel in the vicinity of the target pixel in binary (1 bit). This LBP has a characteristic that it is robust against changes in the brightness of the entire image. For example, a recognition system has been proposed in which an 8-bit LBP is calculated for each pixel with eight neighboring pixels, and image recognition is performed using an image in which these LBPs are arranged in a two-dimensional grid (for example, non-pixels). (See Patent Document 1). Hereinafter, an image in which feature quantities such as LBP are arranged in a two-dimensional grid is referred to as a “feature quantity image”. A general image in which pixel data having a value corresponding to the amount of received light is arranged in a two-dimensional grid is referred to as a “normal image”.

Timo Ojala, et al., Multiresolution Gray-Scale and Rotation invariant Texture Classification with Local Binary Patterns, IEEE Transactions on Pattern Analysis and Machine Intelligence, vol. 24, no. 7, July 2002

  In the above-described conventional technology, image recognition is performed using a feature image composed of an LBP that is robust against changes in brightness of the entire image, and thus fluctuations in recognition results of image recognition due to changes in brightness are suppressed. can do. However, the feature amount image made of LBP has a problem that the image quality is generally lower than that of a normal image. If the image quality is low, the accuracy of image recognition decreases, so it is desirable to improve the image quality of the feature image.

  The present technology has been created in view of such a situation, and an object thereof is to improve the image quality of a feature image in an imaging apparatus that captures a feature image.

  The present technology has been made to solve the above-described problems. The first aspect of the present technology includes a plurality of pixel circuits that each generate an analog signal corresponding to the amount of received light and output it as a pixel signal. A feature value representing the magnitude of the difference between the pixel signals from the neighboring pixel circuit in the vicinity of the focused pixel circuit of interest and the focused pixel circuit among the plurality of pixel circuits for each of the neighboring pixel circuits. An imaging apparatus including a feature amount extraction unit to be extracted and a control method thereof. Thereby, there is an effect that a feature value representing the magnitude of the difference between the pixel signals from each of the neighboring pixel circuit and the target pixel circuit is extracted for each of the neighboring pixel circuits.

  The first aspect may further include a reference signal supply unit that sequentially supplies a plurality of reference signals having different offset voltages, and the feature amount extraction unit includes each of the pixel signal and the plurality of reference signals. It is also possible to extract the feature amount based on the comparison result obtained by comparing. This brings about the effect that the feature amount is extracted from the comparison result obtained by comparing the pixel signal and each of the plurality of reference signals.

  In the first aspect, the feature amount extraction unit compares the pixel signal with each of the plurality of reference signals and outputs the comparison result, and a plurality of features based on the comparison result. You may provide the memory | storage part which produces | generates and stores a local bit pattern in order, and the feature-value conversion part which converts the data which consist of said several local bit pattern into the said feature-value. This brings about the effect that data consisting of a plurality of local bit patterns is converted into feature quantities.

  In the first aspect, the storage unit includes a plurality of data storage units that generate and store different local bit patterns, and the feature amount conversion unit includes the data storage unit in all of the plurality of data storage units. After the local bit pattern is stored, each of the local bit patterns can be read and converted into the feature amount. Accordingly, there is an effect that each local bit pattern is read after the local bit pattern is stored in all of the plurality of data storage units.

  In the first aspect, the storage unit may further store a time code indicating a time when the comparison result is inverted. As a result, the normal image is generated from the time code.

  In the first aspect, the comparison unit outputs the comparison result between the pixel signal from the target pixel circuit and each of the plurality of reference signals as a target pixel comparison result, and from the neighboring pixel circuit. The comparison result between each of the plurality of reference signals and the plurality of reference signals is output as a neighboring pixel comparison result, and the data storage unit includes a latch circuit that holds the neighboring pixel comparison result and the target pixel comparison result. A latch control circuit for holding the neighboring pixel comparison result in the latch circuit when inverted, and delaying one of the target pixel comparison result and the neighboring pixel comparison result for a predetermined time to cause the latch circuit and the latch control to be delayed A delay circuit for outputting to any of the circuits. This brings about the effect that one of the target pixel comparison result and the neighboring pixel comparison result is delayed.

  In the first aspect, the delay circuit may delay the target pixel comparison result and output the delayed pixel comparison result to the latch control circuit. This brings about the effect that the target pixel comparison result is delayed.

  In the first aspect, the delay circuit may delay the neighborhood pixel comparison result and output the result to the latch circuit. This brings about the effect that the neighboring pixel comparison result is delayed.

  Further, according to the first aspect, the comparison unit that compares each of the pixel signals with a predetermined reference signal and outputs the comparison result, the time when the comparison result corresponding to the pixel circuit of interest is inverted, and the vicinity It is also possible to provide a counting unit that counts a count value over a period between the time when the comparison result corresponding to the pixel circuit is inverted and outputs the counted value as the feature amount. Thus, the count value is counted over a period between the time when the comparison result corresponding to the target pixel circuit is inverted and the time when the comparison result corresponding to the neighboring pixel circuit is inverted.

  Further, in this first aspect, the counting unit may perform the above operation when one of the comparison result corresponding to the pixel circuit of interest and the comparison result corresponding to the neighboring pixel circuit is inverted before the other. The count value can be incremented, and the count value can be decremented when the other is reversed before the one. Accordingly, there is an effect that the count value is incremented or decremented depending on which of the comparison result corresponding to the pixel circuit of interest and the comparison result corresponding to the neighboring pixel circuit is inverted first.

  In the first aspect, the plurality of pixel circuits are arranged in each of a plurality of area blocks, and each of the plurality of area blocks is supplied by the plurality of pixel circuits and the plurality of pixel circuits. A floating diffusion layer may be provided. Thereby, there is an effect that a feature amount representing a magnitude of a difference between pixel signals from each of a plurality of pixel circuits sharing a floating diffusion layer is extracted.

  In the first aspect, the neighboring pixel circuit includes a pair of neighboring pixel circuits that are point-symmetric with respect to the target pixel circuit, and the feature amount extraction unit is one of the pair of neighboring pixel circuits. It is also possible to extract the feature quantity that represents the magnitude of the difference between the pixel signals from the pixel circuit and the pixel circuit of interest by a multivalue. This brings about the effect that the feature quantity representing the magnitude of the difference between the pixel signals from one of the pair of neighboring pixel circuits and the target pixel circuit is extracted in multiple values.

  In the first aspect, the image processing unit may further include a process for recognizing a predetermined object based on the feature amount. This brings about the effect that a predetermined object is recognized.

  According to the present technology, in an imaging device that captures a feature amount image, an excellent effect that the image quality of the feature amount image can be improved can be achieved. Note that the effects described here are not necessarily limited, and may be any of the effects described in the present disclosure.

It is a block diagram showing an example of 1 composition of an imaging device in a 1st embodiment of this art. It is a block diagram showing an example of 1 composition of a solid imaging device in a 1st embodiment of this art. It is a block diagram showing an example of 1 composition of a pixel in a 1st embodiment of this art. It is a block diagram showing an example of 1 composition of ADC (Analog to Digital Converter) in a 1st embodiment of this art. It is a figure which shows an example of the connection form between the pixels in 1st Embodiment of this technique. It is a circuit diagram showing an example of 1 composition of a comparison circuit in a 1st embodiment of this art. 6 is a timing chart illustrating an example of the operation of the comparison circuit according to the first embodiment of the present technology. It is a circuit diagram showing an example of 1 composition of a pixel circuit in a 1st embodiment of this art. It is a circuit diagram showing an example of 1 composition of a data storage part in a 1st embodiment of this art. 3 is a circuit diagram illustrating a configuration example of a buffer circuit according to the first embodiment of the present technology. FIG. 6 is a timing chart illustrating an example of a reset level sampling operation according to the first embodiment of the present technology. 6 is a timing chart illustrating an example of a signal level sampling operation according to the first embodiment of the present technology. 6 is a timing chart illustrating an example of the operation of the solid-state imaging device when the low level is latched in the LBP extraction mode according to the first embodiment of the present technology. 6 is a timing chart illustrating an example of an operation of the solid-state imaging device when a high level is latched in the LBP extraction mode according to the first embodiment of the present technology. It is a figure for demonstrating LBP in 1st Embodiment of this technique. It is a figure showing an example of LBP for every reference signal in a 1st embodiment of this art. It is a block diagram showing an example of 1 composition of an output part in a 1st embodiment of this art. It is a figure for demonstrating the conversion process by the feature-value conversion part in 1st Embodiment of this technique. It is the figure which put together the processing flow in the imaging device in 1st Embodiment of this technique. 7 is a flowchart illustrating an example of an operation of the imaging device according to the first embodiment of the present technology. 3 is a flowchart illustrating an example of an LBP generation process according to the first embodiment of the present technology. It is a block diagram showing an example of 1 composition of ADC in a 2nd embodiment of this art. It is a circuit diagram showing an example of 1 composition of a counting circuit in a 2nd embodiment of this art. It is a circuit diagram showing an example of 1 composition of an up-down counter in a 2nd embodiment of this art. 12 is a timing chart illustrating an example of an operation for performing up-counting in the second embodiment of the present technology. 12 is a timing chart illustrating an example of an operation of performing a down count in the second embodiment of the present technology. It is the figure which put together the processing flow in the imaging device in 2nd Embodiment of this technique. It is a block diagram showing an example of 1 composition of ADC in a 3rd embodiment of this art. It is a circuit diagram showing an example of 1 composition of a data storage part in a 4th embodiment of this art. It is a block diagram showing an example of 1 composition of ADC in a 5th embodiment of this art. It is a top view showing an example of 1 composition of a pixel array part in a 6th embodiment of this art. It is a circuit diagram showing an example of 1 composition of an area block in a 6th embodiment of this art. It is a circuit diagram showing an example of 1 composition of a data storage part in a 7th embodiment of this art. It is a circuit diagram showing an example of 1 composition of an LBP latch circuit in a 7th embodiment of this art. It is a circuit diagram showing an example of 1 composition of a time code latch circuit in a 7th embodiment of this art. It is a figure for demonstrating the wiring connection of the signal wire | line in the 8th Embodiment of this technique. It is a circuit diagram showing an example of 1 composition of a data storage part in an 8th embodiment of this art. It is a block diagram showing an example of 1 composition of an output part in an 8th embodiment of this art. It is a block diagram which shows the schematic structural example of a vehicle control system. It is explanatory drawing which shows an example of the installation position of an imaging part.

Hereinafter, modes for carrying out the present technology (hereinafter referred to as embodiments) will be described. The description will be made in the following order.
1. First Embodiment (Exemplary feature amount extracting pixel signal difference expressed in multiple values)
2. Second Embodiment (Example of Extracting Feature Quantity Representing Difference of Pixel Signal by Multi-value Using Counter)
3. Third Embodiment (Example in which a plurality of LBPs are held and feature values representing pixel signal differences expressed by multiple values are extracted from those LBPs)
4). Fourth embodiment (example of extracting feature amount by delaying comparison result of target pixel)
5. Fifth embodiment (example of extracting feature quantity by delaying comparison result of neighboring pixels)
6). Sixth Embodiment (Example of extracting feature values representing pixel signal differences in multiple values in a pixel-sharing element)
7). Seventh Embodiment (Example in which a time code and LBP are held, a feature value representing a difference between pixel signals in multiple values is extracted from the LBP, and a normal image is generated from the time code)
8). Eighth Embodiment (Example of Extracting Feature Value Representing Difference of Pixel Signals by Multivalue in Solid-State Imaging Device with Reduced Number of Wiring)
9. Application examples for moving objects

<1. First Embodiment>
[Configuration example of imaging device]
FIG. 1 is a block diagram illustrating a configuration example of the imaging apparatus 100 according to the first embodiment of the present technology. The imaging device 100 captures image data, and includes an optical unit 110, a solid-state imaging device 200, a digital signal processor 120, a display unit 130, an operation unit 140, a bus 150, a frame memory 160, a recording unit 170, and a power supply unit 180. Is provided. As the imaging device 100, a digital camera such as a digital still camera or a digital video camera, or an electronic device having an imaging function such as a mobile phone is assumed.

  The optical unit 110 captures incident light (image light) from a subject and forms an image on the imaging surface of the solid-state imaging device 200.

  The solid-state image sensor 200 captures image data. The solid-state imaging device 200 captures image data in synchronization with a vertical synchronization signal VSYNC having a predetermined frequency (for example, 30 Hz), and supplies the image data to the digital signal processor 120 via a signal line 209.

  Further, the enable signal LBP_EN is input to the solid-state imaging device 200 via the signal line 208. This enable signal LBP_EN is a signal for instructing whether or not to enable a function of extracting a feature amount and generating a feature amount image. When the enable signal LBP_EN is set to enable, the solid-state imaging device 200 generates a feature amount image and outputs the image data to the digital signal processor 120. On the other hand, when the enable signal LBP_EN is disabled, the solid-state imaging device 200 generates a normal image including pixel data corresponding to the amount of received light, and outputs the image data to the digital signal processor 120. Hereinafter, the state of the imaging device 100 when the enable signal LBP_EN is enabled is referred to as “feature amount extraction mode”, and the state of the imaging device 100 when the enable signal LBP_EN is disabled is referred to as “imaging mode”.

  The digital signal processor 120 performs predetermined signal processing on the image data. The digital signal processor 120 causes the frame memory 160 to hold image data as necessary in signal processing. The digital signal processor 120 sets the enable signal LBP_EN based on the type of signal processing to be executed. For example, when performing image recognition, the digital signal processor 120 sets the enable signal LBP_EN to enable. On the other hand, when performing signal processing on a normal image such as demosaic processing or white balance processing, the digital signal processor 120 disables the enable signal LBP_EN. The digital signal processor 120 supplies an enable signal LBP_EN to the solid-state imaging device 200 via the signal line 208.

  The display unit 130 displays image data. As the display unit 130, for example, a liquid crystal panel or an organic EL (Electro Luminescence) panel is used.

  The operation unit 140 issues operation commands for various functions of the imaging apparatus 100 in accordance with user operations. The bus 150 is a common path for the solid-state imaging device 200, the digital signal processor 120, the display unit 130, the operation unit 140, the frame memory 160, the recording unit 170, and the power supply unit 180 to exchange information with each other.

  The frame memory 160 temporarily holds image data. The recording unit 170 records image data. As the recording unit 170, a recording medium such as a hard disk or a semiconductor memory is used. The power supply unit 180 supplies power to each unit in the imaging apparatus 100.

[Configuration example of solid-state image sensor]
FIG. 2 is a block diagram illustrating a configuration example of the solid-state imaging device 200 according to the first embodiment of the present technology. The solid-state imaging device 200 includes a DAC (Digital to Analog Converter) 211, a plurality of time code generators 212, a vertical drive circuit 213, and a pixel array unit 220. The solid-state imaging device 200 includes a pixel driving circuit 214, a timing generation circuit 215, and an output unit 250. These circuits are provided on a single semiconductor substrate.

  The DAC 211 generates a reference signal by DA (Digital to Analog) conversion and supplies the reference signal to the pixel array unit 220. As the reference signal, for example, a ramp signal whose level monotonously decreases with the passage of time is used. The DAC 211 is an example of the reference signal supply unit described in the claims.

  The pixel array unit 220 includes a plurality of pixels 230 arranged in a two-dimensional grid and a plurality of time code transfer units 221. Hereinafter, a set of pixels 230 arranged in a predetermined direction (such as a horizontal direction) is referred to as “row”, and a set of pixels 230 arranged in a direction perpendicular to the row is referred to as “column”.

  The timing generation circuit 215 controls the operation timing of the DAC 211, the vertical drive circuit 213, and the pixel drive circuit 214 in synchronization with the vertical synchronization signal VSYNC. The timing generation circuit 215 is constituted by a timing generator, for example. Further, the enable signal LBP_EN is input to the timing generation circuit 215. When the enable signal LBP_EN is enabled, the timing generation circuit 215 controls the offset voltage of the reference signal by the control signal to the DAC 211.

  The time code generator 212 generates a time code indicating a relative time within the period of the vertical synchronization signal VSYNC. The time code generator 212 is arranged for each time code transfer unit 221 and supplies the generated time code to the corresponding time code transfer unit 221. The time code transfer unit 221 transfers a time code.

  The pixel drive circuit 214 generates analog pixel signals by driving the pixels 230 in a predetermined order. The vertical drive circuit 213 drives the pixels 230 in a predetermined order, converts the pixel signals into digital signals, and outputs them.

  The pixel 230 generates an analog pixel signal corresponding to the amount of received light. The pixel 230 converts the pixel signal into a digital signal and supplies the digital signal to the output unit 250 via the time code transfer unit 221.

  Note that although the DAC 211, the time code generation unit 212, the vertical drive circuit 213, the pixel array unit 220, the pixel drive circuit 214, the timing generation circuit 215, and the output unit 250 are provided on a single semiconductor substrate, the present invention is not limited to this configuration. . For example, these circuits can be distributed and arranged on a plurality of stacked semiconductor substrates.

[Pixel configuration example]
FIG. 3 is a block diagram illustrating a configuration example of the pixel 230 according to the first embodiment of the present technology. The pixel 230 includes a pixel circuit 240 and an ADC 300.

  The pixel circuit 240 generates an analog signal corresponding to the amount of received light as the pixel signal SIG_ (i, j) according to the control of the pixel driving circuit 214. Here, i is an integer indicating the vertical coordinate of the pixel 230, and j is an integer indicating the horizontal coordinate. The pixel circuit 240 supplies the pixel signal SIG_ (i, j) to the ADC 300.

  The ADC 300 converts the pixel signal SIG_ (i, j) into a digital signal according to the control of the vertical drive circuit 213. The ADC 300 compares the reference signal REF from the DAC 211 and the pixel signal SIG_ (i, j), and generates a digital signal based on the comparison result VCO_ (i, j). Then, the ADC 300 supplies the generated digital signal to the time code transfer unit 221.

  Further, the ADC 300 outputs the comparison result VCO_ (i, j) to the neighboring pixel 230 (hereinafter referred to as “neighboring pixel”). Also, ADC 300 receives VCO_IN that is a comparison result of each neighboring pixel.

  Here, “neighboring” means that the Euclidean distance from the coordinates of a certain pixel to the coordinates of other pixels is within a certain distance. In the pixel array unit 220, for example, a pixel whose Euclidean distance from the focused pixel of interest is less than “2” is set as a neighboring pixel. In this case, the neighboring pixels are eight pixels, that is, up, down, left, right, upper left, upper right, lower left, and lower right of the target pixel. That is, the pixel at the coordinate (i, j) is represented by the coordinates (i-1, j-1), (i-1, j), (i-1, j + 1), (i, j-1), (i, The comparison result VCO_ (i, j) is output to the neighboring pixels of (j + 1), (i + 1, j-1), (i + 1, j) and (i + 1, j + 1). Further, 8-bit VCO_IN consisting of the comparison results of each of the eight neighboring pixels is input to the pixel at the coordinate (i, j).

  Note that the number of neighboring pixels is not limited to eight. For example, four pixels on the upper, lower, left, and right sides may be used as neighboring pixels.

  Further, the pixel circuit 240 of the target pixel is an example of the target pixel circuit described in the claims, and the pixel circuit 240 of the neighboring pixels is an example of the neighboring pixel circuit described in the claims.

[Configuration example of ADC]
FIG. 4 is a block diagram illustrating a configuration example of the ADC 300 according to the first embodiment of the present technology. The ADC 300 includes a comparison circuit 310, a data storage unit 350, and a buffer circuit 360. The comparison circuit 310 includes a differential input circuit 320, a voltage conversion circuit 330, and a positive feedback circuit 340. The circuit including the comparison circuits 310 of all the pixels is an example of a comparison unit described in the claims.

  The differential input circuit 320 compares the reference signal REF from the DAC 211 with the pixel signal SIG_ (i, j) from the pixel circuit 240. The differential input circuit 320 outputs a predetermined differential output signal HVO to the voltage conversion circuit 330 when the pixel signal SIG_ (i, j) is higher than the reference signal REF.

  The voltage conversion circuit 330 converts the voltage of the differential output signal HVO into a low potential at which the positive feedback circuit 340 can operate, and supplies it to the positive feedback circuit 340 as a conversion signal LVI.

  Based on the conversion signal LVI, the positive feedback circuit 340 generates a comparison result VCO_ (i, j) that is inverted when the pixel signal SIG_ (i, j) is higher than the reference signal REF, and the neighboring pixel 230. And output to The positive feedback circuit 340 is initialized by the initialization signal INI from the vertical drive circuit 213.

  The data storage unit 350 generates and stores LBP_ (i, j) based on the comparison results VCO_ (i, j) and VCO_IN when the enable signal LBP_EN is enabled. On the other hand, when the enable signal LBP_EN is disabled, the data storage unit 350 stores the time code when the comparison result VCO_ (i, j) is inverted as pixel data. The data storage unit 350 supplies these digital signals (LBP_ (i, j) or pixel data) to the buffer circuit 360 via the local bit line LBL. The data storage unit 350 is an example of a storage unit described in the claims.

  The buffer circuit 360 transfers a time code from the time code transfer unit 221 to the data storage unit 350, and transfers LBP_ (i, j) or pixel data from the data storage unit 350 to the time code transfer unit 221.

  Note that although the buffer circuit 360 is disposed in the pixel 230, this circuit may be disposed in the time code transfer unit 221.

  FIG. 5 is a diagram illustrating an example of a connection form between pixels according to the first embodiment of the present technology. In the figure, a pixel surrounded by a thick frame is a pixel of interest, and its coordinates are (i, j). Further, for example, coordinates (i-1, j-1), (i-1, j), (i-1, j + 1), (i, j-1), (i, j + 1), (i + 1, j- 1) Eight pixels of (i + 1, j) and (i + 1, j + 1) are set as neighboring pixels.

  The target pixel is connected to each of the eight neighboring pixels via the eight input signal lines. The 8-bit comparison result VCO_IN is input to the target pixel via these input signal lines. Further, the target pixel is connected to each of the neighboring pixels via one output signal line branched into eight. The target pixel outputs a 1-bit comparison result VCO_ (i, j) to each of the neighboring pixels via the output signal line.

[Configuration example of comparison circuit]
FIG. 6 is a circuit diagram illustrating a configuration example of the comparison circuit 310 according to the first embodiment of the present technology. The differential input circuit 320 in the comparison circuit 310 includes pMOS (p-channel metal-oxide-semiconductor) transistors 321 to 323 and nMOS (n-channel MOS) transistors 324 to 326.

  The pMOS transistors 321 and 322 constitute a current mirror circuit. The power supply voltage VDD1 is applied to the sources of the pMOS transistors 321, 322 and 323. The drain of the pMOS transistor 321 is commonly connected to the gates of the pMOS transistors 321 and 322 and the drain of the nMOS transistor 324. The drain of the pMOS transistor 322 is commonly connected to the drain of the nMOS transistor 325 and the gate of the pMOS transistor 323. The potential at this connection point is VO. The drain of the pMOS transistor 323 is connected to the voltage conversion circuit 330.

  nMOS transistors 324 and 325 constitute a differential pair, and the sources of these transistors are connected in common to the drain of nMOS transistor 326. The source of the nMOS transistor 326 is connected to a predetermined reference potential VSS. Further, the reference signal REF from the DAC 211 is input to the gate of the nMOS transistor 324, and the pixel signal SIG_ (i, j) from the pixel circuit 240 is input to the gate of the nMOS transistor 325.

  A predetermined bias voltage Vb is applied to the gate of the nMOS transistor 326, and a predetermined reference potential VSS is applied to the source of the nMOS transistor 326.

  The voltage conversion circuit 330 includes an nMOS transistor 331. A predetermined bias voltage VBIAS is applied to the gate of the nMOS transistor 331. The drain of the nMOS transistor 331 is connected to the drain of the pMOS transistor 323, and the source is connected to the positive feedback circuit 340.

  Here, the bias voltage VBIAS may be a value that can be converted into a voltage that does not destroy the transistors in the positive feedback circuit 340 that operates at a constant voltage. For example, the bias voltage VBIAS can be the same voltage as the power supply voltage of the positive feedback circuit 340.

  Positive feedback circuit 340 includes pMOS transistors 341, 342, and 343 and nMOS transistors 344 and 345. The pMOS transistors 341 and 342 and the nMOS transistor 344 are connected in series to the power supply voltage VDD2. The pMOS transistor 342 and the nMOS transistor 345 are connected in series to the power supply voltage VDD2.

Here, the magnitude relationship between the reference potential VSS and the power supply voltages VDD1 and VDD2 is expressed by the following equation. Note that, as described above, the bias voltage VBIAS is set to the same value as the power supply voltage VDD2, for example.
VSS <VDD2 <VDD1

  The initialization signal INI from the vertical drive circuit 213 is input to the gates of the pMOS transistor 341 and the nMOS transistor 344. The gate of the pMOS transistor 343 is connected to the connection point between the pMOS transistor 342 and the nMOS transistor 345. The gates of the pMOS transistor 342 and the nMOS transistor 345 are connected in common to the voltage conversion circuit 330 and the connection node of the pMOS transistor 343 and the nMOS transistor 344. The potential at the connection point of the pMOS transistor 342 and the nMOS transistor 345 is output as the comparison result VCO_ (i, j) to the data storage unit 350 or the like.

  Note that each of the differential input circuit 320, the voltage conversion circuit 330, and the positive feedback circuit 340 is not limited to the circuit illustrated in FIG. 6 as long as it has the function described in FIG.

  FIG. 7 is a timing chart illustrating an example of the operation of the comparison circuit 310 according to the first embodiment of the present technology. In the figure, a is a timing chart showing an example of the operation of the differential input circuit 320 in the comparison circuit 310. B in the figure is a timing chart showing an example of the operation of the voltage conversion circuit 330. C in the figure is a timing chart showing an example of the operation of the positive feedback circuit 340. In the figure, the vertical axis represents voltage, and the horizontal axis represents time.

  First, the reference signal REF is set to a voltage higher than the pixel signals SIG of all the pixels 230 by the DAC 211, and the comparison circuit 310 is initialized by the high level initialization signal INI.

  The reference signal REF is input to one gate of the differential pair nMOS transistors 324 and 325, and the pixel signal SIG_ (i, j) is input to the other gate. Consider a case where the voltage of the reference signal REF is higher than the voltage of the pixel signal SIG_ (i, j). At this time, most of the current output from the nMOS transistor 326 as the current source flows to the diode-connected pMOS transistor 321 via the nMOS transistor 324 on the reference signal REF side. The channel resistance of the pMOS transistor 322 having a common gate with the pMOS transistor 321 is sufficiently low, and the gate of the pMOS transistor 323 is kept substantially at the power supply voltage VDD1, and the pMOS transistor 323 is cut off.

  Therefore, even if the nMOS transistor 331 in the voltage conversion circuit 330 is conductive, the positive feedback circuit 340 as a charging circuit does not charge the conversion signal LVI. On the other hand, since the high-level initialization signal INI is supplied, the nMOS transistor 344 on the reference potential VSS side becomes conductive, and the positive feedback circuit 340 discharges the conversion signal LVI. Further, since the pMOS transistor 341 on the power supply side is cut off, the positive feedback circuit 340 does not charge the conversion signal LVI via the pMOS transistor 343. As a result, the conversion signal LVI is discharged to the reference potential VSS. The positive feedback circuit 340 outputs a high-level comparison result VCO_ (i, j) by the pMOS transistor 342 and the nMOS transistor 345 in the output stage constituting the inverter, and the comparison circuit 310 is initialized.

  At the timing Ts at the end of initialization, the vertical drive circuit 213 sets the initialization signal INI to a low level. After timing Ts, sweeping of the reference signal REF is started.

  In a period in which the reference signal REF is higher than the pixel signal SIG_ (i, j), the pMOS transistor 323 is turned off because it is turned off, and the comparison result VCO is a high level signal, so the pMOS transistor 343 is also turned off and turned off. Is done. The nMOS transistor 344 is also cut off because the initialization signal INI is at a low level. The conversion signal LVI maintains the reference potential VSS in a high impedance state, and a high level comparison result VCO is output.

  When the reference signal REF becomes lower than the pixel signal SIG_ (i, j) at the timing Tv, the output current of the nMOS transistor 326 as the current source does not flow through the nMOS transistor 324 on the reference signal REF side. As a result, the gate potentials of the pMOS transistors 321 and 322 constituting the current mirror circuit are increased, and the channel resistance of the pMOS transistor 322 is increased. The gate potential of the pMOS transistor 323 decreases due to the voltage drop caused by the current flowing through the nMOS transistor 325 on the pixel side, and the nMOS transistor 331 in the voltage conversion circuit 330 becomes conductive. The differential output signal HVO output from the pMOS transistor 323 is converted into a conversion signal LVI by the nMOS transistor 331 in the voltage conversion circuit 330 and supplied to the positive feedback circuit 340. A positive feedback circuit 340 as a charging circuit charges the conversion signal LVI and gradually increases the potential from the reference potential VSS to the power supply voltage VDD2.

  When the voltage of the conversion signal LVI exceeds the threshold voltage of the inverter constituted by the pMOS transistor 342 and the nMOS transistor 345, the comparison result VCO becomes low level, and the pMOS transistor 343 as the feedback destination becomes conductive. The pMOS transistor 341 is also turned on by the low level initialization signal INI. Therefore, the positive feedback circuit 340 rapidly charges the conversion signal LVI via the pMOS transistor 342 and the nMOS transistor 345, and raises the potential to the power supply voltage VDD2 at once.

  Since the bias voltage VBIAS is applied to the gate of the nMOS transistor 331 in the voltage conversion circuit 330, the nMOS transistor 331 is cut off when the voltage of the conversion signal LVI reaches a voltage value lowered by the threshold value of the transistor from the bias voltage VBIAS. Even if the pMOS transistor 323 remains conductive, the conversion signal LVI is not charged any further, and the voltage conversion circuit 330 also functions as a voltage clamp circuit.

  Charging of the conversion signal LVI due to the conduction of the pMOS transistor 343 is a positive feedback operation that starts from the fact that the conversion signal LVI has risen to the threshold value of the inverter and accelerates its movement. The nMOS transistor 326, which is a current source in the differential input circuit 320, has an enormous number of circuits that operate in parallel in the solid-state imaging device 200. Therefore, the current per circuit is set to be extremely small. Furthermore, the reference signal REF is swept very slowly because the voltage that changes during the unit time at which the time code switches becomes the LSB (Least Significant Bit) step of AD conversion. Therefore, the change in the gate potential of the pMOS transistor 323 is slow, and the change in the output current of the pMOS transistor 323 driven thereby is slow. However, by applying positive feedback to the conversion signal LVI charged with the output current from the subsequent stage, the comparison result VCO can transition sufficiently rapidly. Desirably, the transition time of the comparison result VCO is a fraction of the unit time of the time code, and is typically 1 nanosecond (ns) or less. In the comparison circuit 310, this output transition time can be achieved by setting a small current of, for example, 0.1 microampere (μA) to the nMOS transistor 326 of the current source.

[Configuration example of pixel circuit]
FIG. 8 is a circuit diagram illustrating a configuration example of the pixel circuit 240 according to the first embodiment of the present technology. The pixel circuit 240 includes a reset transistor 241, a transfer transistor 242, a floating diffusion layer 243, a photodiode 244, and a discharge transistor 245. For example, nMOS transistors are used as the reset transistor 241, the transfer transistor 242, the photodiode 244, and the discharge transistor 245.

  The photodiode 244 generates charges by photoelectrically converting incident light. The discharge transistor 245 discharges the charge of the photodiode 244 in accordance with the discharge control signal OFG from the pixel drive circuit 214.

  The transfer transistor 242 transfers charge from the photodiode 244 to the floating diffusion layer 243 in accordance with the transfer signal TX from the pixel drive circuit 214.

  The floating diffusion layer 243 accumulates the transferred charges and generates a voltage corresponding to the amount of accumulated charges. This voltage signal is output to the differential input circuit 320 as a pixel signal SIG_ (i, j).

  The reset transistor 241 initializes the charge amount of the floating diffusion layer 243 in accordance with the reset signal RST from the pixel drive circuit 214.

[Configuration example of data storage unit]
FIG. 9 is a circuit diagram illustrating a configuration example of the data storage unit 350 according to the first embodiment of the present technology. The data storage unit 350 includes a multiplexer 351, a latch control circuit 352, a plurality of switches 355, and a plurality of latch circuits 356. The switch 355 and the latch circuit 356 are provided for each neighboring pixel. When there are eight neighboring pixels, eight switches 355 and eight latch circuits 356 are provided.

  The multiplexer 351 switches the output destination of the comparison result VCO_ (i, j) according to the enable signal LBP_EN. The multiplexer 351 outputs the comparison result VCO_ (i, j) to all the switches 355 when the enable signal LBP_EN is enabled. On the other hand, when the enable signal LBP_EN is disabled, the multiplexer 351 outputs the comparison result VCO_ (i, j) to the latch control circuit 352.

  The latch control circuit 352 controls each operation of the latch circuit 356. The latch control circuit 352 includes an OR (logical sum) gate 353 and an inverter 354.

  The OR gate 353 calculates a logical sum of the WORD signal for controlling the pixel data read timing and the comparison result VCO_ (i, j). The WORD signal is supplied from the vertical drive circuit 213. The OR gate 353 supplies a logical sum signal as a control signal T to all the latch circuits 356.

  The inverter 354 inverts the comparison result VCO_ (i, j). The inverter 354 supplies the inverted signal as a control signal L to all the latch circuits 356.

  The switch 355 inputs the comparison result VCO from the corresponding neighboring pixel to the corresponding latch circuit 356 over the period until the comparison result VCO_ (i, j) from the multiplexer 351 is inverted.

  The latch circuit 356 holds 1-bit data. The latch circuit 356 includes inverters 357 and 358 and a switch 359. In the imaging mode, the n-th latch circuit 356 holds the nth bit of the time code. On the other hand, in the LBP extraction mode, the nth latch circuit 356 holds the nth bit in the local bit pattern.

  The inverter 357 inverts the signal from the inverter 358 and outputs the inverted signal to the input terminal of the inverter 358 and the switch 359 when the control signal L is at a high level.

  The inverter 358 inverts any of the comparison result VCO of the corresponding neighboring pixels, the signal from the inverter 357, and the signal from the switch 359 and outputs the result to the input terminal of the inverter 357. These loop inverters 357 and 358 hold (latch) a 1-bit signal.

  The switch 359 opens and closes a path between the buffer circuit 360 and the loop circuit including the inverters 357 and 358 in accordance with the control signal T. When the control signal T is at a high level, the switch 359 is controlled to be in a closed state, and when the control signal T is at a low level, it is controlled to be in an open state.

  When the enable signal LBP_EN is disabled (imaging mode), writing of the time code to the data storage unit 350 and reading are sequentially performed. The latch control circuit 352 latches the time code updated every unit time from the time code transfer unit 221 into eight latches while the high-level comparison result VCO_ (i, j) is input in the write operation. The data is stored in the circuit 356. When the reference signal REF and the pixel signal SIG_ (i, j) have the same voltage and the comparison result VCO is inverted to a low level, the latch control circuit 352 stops writing (updating) the time code. The latch control circuit 352 causes the latch circuit 356 to hold the time code last stored in the latch circuit 356. The time code stored in the eight latch circuits 356 represents the time when the pixel signal SIG_ (i, j) and the reference signal REF are equal, and the pixel signal SIG_ (i, j) is the reference for that time. It represents pixel data indicating a voltage, that is, a digitized light amount value.

  After the sweep of the reference signal REF is completed and the time code is stored in all the pixels 230 in the pixel array unit 220, reading of the time code (that is, pixel data) is started.

  In the read operation, the latch control circuit 352 causes the time code transfer unit 221 to output the stored time code when the read timing is reached based on the WORD signal that controls the read timing. The time code transfer unit 221 sequentially transfers the supplied time code in the column direction (vertical direction) and supplies it to the output unit 250.

  When the enable signal LBP_EN is enabled (LBP extraction mode), VCO_IN when the comparison result VCO_ (i, j) is inverted is written in the eight latch circuits 356. The written data corresponds to LBP. This LBP is read according to the WORD signal.

  Further, the DAC 211 sequentially supplies a plurality of reference signals REF having different offset voltages, and the data storage unit 350 sequentially executes LBP writing and reading each time the reference signal REF is supplied. For example, when four reference signals REF are supplied, LBP is written and read four times.

  In addition, although the bit number of pixel data and the bit number of LBP are made the same, the structure from which these bit numbers differ may be sufficient. In this case, the same number of latch circuits 356 as the larger of the number of bits of pixel data and the number of bits of LBP are provided, and the number of switches 355 greater than the number of bits of LBP is provided. For example, when the pixel data is 16 bits and the LBP is 8 bits, 16 latch circuits 356 and 8 or more switches 355 are provided.

[Configuration example of buffer circuit]
FIG. 10 is a circuit diagram illustrating a configuration example of the buffer circuit 360. The buffer circuit 360 includes a bidirectional buffer 361 for each latch circuit 356. When there are eight latch circuits 356, eight bidirectional buffers 361 are provided.

  The bidirectional buffer 361 transfers data bidirectionally according to the WR signal instructing writing and the RD signal instructing reading from the vertical drive circuit 213. The bidirectional buffer 361 includes a buffer 362 and an inverter 363.

  The buffer 362 outputs the nth bit of the time code to the data storage unit 350 via the local bit line LBL according to the WR signal.

  The inverter 363 inverts the nth bit of the digital signal (pixel data or LBL) from the data storage unit 350 according to the RD signal and supplies it to the time code transfer unit 221.

  FIG. 11 is a timing chart illustrating an example of a reset level sampling operation according to the first embodiment of the present technology. This operation is started when the enable signal LBP_EN is disabled (that is, the imaging mode) and imaging is instructed.

  First, at time t1 immediately before the end of exposure, the reference signal REF is set to the reset voltage Vrst from the standby voltage Vstb so far. As a result, the floating diffusion layer 243 is reset. At time t1, the initialization signal INI to the positive feedback circuit 340 is set to a high level, and thereby the positive feedback circuit 340 is initialized.

  Next, at time t2, the reference signal REF is raised to a predetermined voltage Vu, and comparison between the reference signal REF and the pixel signal SIG_ (i, j) is started. At this time, since the reference signal REF is larger than the pixel signal SIG_ (i, j), the comparison result VCO_ (i, j) is at a high level.

  At time t3 when the reference signal REF and the pixel signal SIG_ (i, j) become the same, the comparison result VCO_ (i, j) is inverted from the high level to the low level. When the comparison result VCO_ (i, j) is inverted, the data storage unit 350 stores the time code (that is, pixel data) at the time of the inversion.

  At time t4 after the completion of the time code writing, the voltage of the reference signal REF is lowered to the standby voltage Vstb enough to turn off the nMOS transistor 324 in the comparison circuit 310. Thereby, the current consumption of the comparison circuit 310 during the reading period is suppressed.

  At time t <b> 5, the WORD signal that controls the read timing becomes high level, and, for example, 8-bit pixel data is output from the data storage unit 350. The data acquired here is P-phase data at a reset level when performing CDS (Correlated Double Sampling) processing.

  FIG. 12 is a timing chart illustrating an example of a signal level sampling operation according to the first embodiment of the present technology.

  At time t6 after the reset level is read, the reference signal REF is raised to the predetermined voltage Vu, the initialization signal INI is set to the high level, and the positive feedback circuit 340 is initialized again.

  At time t7, the charge generated by the photodiode 244 is transferred to the floating diffusion layer 243 by the high-level transfer signal TX.

  After the initialization signal INI is returned to the low level, the comparison between the reference signal REF and the pixel signal SIG_ (i, j) is started. Then, at the time t8 when the reference signal REF and the pixel signal SIG_ (i, j) become the same, the comparison result VCO_ (i, j) is inverted, and the time code (i.e. Pixel data) is stored.

  At time t9 after the completion of the time code writing, the voltage of the reference signal REF is lowered to the standby voltage Vstb enough to turn off the nMOS transistor 324 in the comparison circuit 310.

  At time t <b> 10, the WORD signal that controls the read timing becomes high level, and, for example, 8-bit pixel data is output from the data storage unit 350. The data acquired here is D-phase data at a signal level when performing CDS processing.

  The above-described sampling of the reset level and the signal level is performed every period of the vertical synchronization signal VSYNC. Each pixel 230 in the solid-state imaging device 200 can perform a global shutter operation in which all the pixels are reset at the same time and all the pixels are exposed at the same time. Since all the pixels can be exposed and read out at the same time, it is usually unnecessary to provide a holding portion that is provided in the pixel and holds the charge until the charge is read out. Further, the pixel 230 does not require a selection transistor or the like for selecting a pixel to be driven, which is necessary for the column parallel readout type solid-state imaging device.

  FIG. 13 is a timing chart illustrating an example of the operation of the solid-state imaging device 200 when the low level is latched in the LBP extraction mode according to the first embodiment of the present technology. This operation is started when the enable signal LBP_EN is enabled (that is, LBP extraction mode) and imaging is instructed. In the figure, the vertical axis represents voltage, and the horizontal axis represents time.

  The DAC 211 sequentially supplies a plurality of reference signals REF having different offset voltages for each period of the vertical synchronization signal VSYNC. Here, the offset voltage is a fixed voltage applied to the entire reference signal REF. Two reference signals REF having different offset voltages have the same slope, but have a difference in potential at a predetermined phase of the slope (for example, sweep start time). For example, it is assumed that the DAC 211 sequentially generates four reference signals within the period of the vertical synchronization signal VSYNC, which are REFa, REFb, REFc, and REFd, respectively. The shape of these reference signals is assumed to be stepped.

  For example, the offset voltage of the reference signal REFa is “0” volts (V), and the offset voltage of the reference signal REFb is the negative voltage ofs1. The offset voltage of the reference signal REFc is a negative voltage ofs2 having an absolute value greater than that of ofs1, and the offset voltage of the reference signal REFd is a negative voltage ofs3 having an absolute value greater than of ofs2.

  The DAC 211 supplies the reference signal REFa at time TL1, and supplies the reference signal REFb at time TL2. The DAC 211 supplies the reference signal REFc at time TL3 and the reference signal REFd at time TL4.

  At time T11 immediately before the start of the sweep of the reference signal REFa, the pixel driving circuit 214 causes each pixel to output a pixel signal by the transfer signal TX. Here, it is assumed that the potential of the pixel signal SIG_ (i, j) of the target pixel is equal to or lower than the potential of the pixel signal SIG_ (i−1, j−1) of the upper left neighboring pixel.

  In this case, the comparison result VCO_ (i−1, j−1) of the neighboring pixels is inverted and becomes a low level at time T12. After that time, for example, the comparison result VCO_ (i, j) of the target pixel at time T13. Is reversed.

  Until the time T13 when the comparison result VCO_ (i, j) of the pixel of interest is inverted, the switch 355 is closed, and the comparison result VCO_ (i-1, j-1) is written in the corresponding latch circuit 356. This bit is, for example, a latch L7. The latch L7 corresponds to a bit corresponding to a neighboring pixel in the LBP.

  At time T13 when the comparison result VCO_ (i, j) is inverted, since the comparison result VCO_ (i-1, j-1) has already been inverted, the latch L356 holds the low level latch L7. The As described above, when the potential of the pixel signal of the target pixel is equal to or lower than the neighboring pixel, a low level bit is held in the corresponding latch circuit 356.

  Further, if the accumulated charge is electrons, the greater the amount of light received by the pixel, the greater the amount of accumulated electrons and the lower the potential of the pixel signal. Therefore, the lower the potential of the pixel signal, the larger the pixel value. Therefore, when the pixel value of the target pixel is equal to or greater than the neighboring pixel, a low level bit is held in the corresponding latch circuit 356.

  FIG. 14 is a timing chart illustrating an example of the operation of the solid-state imaging device 200 when the high level is latched in the LBP extraction mode according to the first embodiment of the present technology. In the figure, the vertical axis represents voltage, and the horizontal axis represents time.

  Here, the potential of the pixel signal SIG_ (i, j) of the target pixel is assumed to be higher than the pixel signal SIG_ (i + 1, j + 1) of the lower right neighboring pixel.

  In this case, the comparison result VCO_ (i, j) of the target pixel is inverted first at time T12 to become a low level, and then the comparison result VCO_ (i + 1, j + 1) of the neighboring pixel is inverted at time T13.

  Until time T12 when the comparison result VCO_ (i, j) of the target pixel is inverted, the switch 355 is closed, and the comparison result VCO_ (i + 1, j + 1) is written in the corresponding latch circuit 356. This bit is, for example, a latch L3.

  At time T12 when the comparison result VCO_ (i, j) is inverted, the comparison result VCO_ (i + 1, j + 1) is not inverted, so that the latch L356 holds the high level latch L3. As described above, when the potential of the pixel signal of the target pixel is higher than that of the neighboring pixel, a high level bit is held in the corresponding latch circuit 356. That is, when the pixel value of the target pixel is smaller than the neighboring pixel, a high level bit is held in the corresponding latch circuit 356.

  FIG. 15 is a diagram for describing the LBP in the first embodiment of the present technology. A in the same figure is a figure which shows the pixel value of an analog pixel signal for every pixel. B in the figure is a diagram representing the magnitude relationship of the pixel signals of the neighboring pixel and the target pixel by binary values.

  In the pixel of 3 rows × 3 columns, the center is the target pixel, and the remaining 8 pixels are the neighboring pixels. The pixel-of-interest data storage unit 350 holds a low-level LBP value when the pixel value of the pixel of interest is greater than or equal to a neighboring pixel, and holds a high-level bit otherwise. For example, since the pixel values of the neighboring pixels at the upper left, upper and lower, and right positions of the target pixel are equal to or lower than the target pixel, a bit of “0” is held for these pixels. For other neighboring pixels, a bit of “1” is held.

  The target pixel outputs the retained 8 bits, for example, arranged clockwise from the bit corresponding to the left neighboring pixel. As described above, the feature value representing the comparison result of the pixel value between the neighboring pixel and the target pixel in binary is called LBP.

  In the LBP extraction mode, noise cannot be reduced in principle by the CDS process performed in the imaging mode. Therefore, it is effective to reduce the noise by a method that does not depend on the CDS process. For example, when the pixel driving circuit 214 resets, a method of causing the pulse of the reset signal RST to the reset transistor 241 to transition to a low level more slowly than in the imaging mode can be applied. In addition, a method of applying band limitation by inserting a low-pass filter or the like can be applied.

  FIG. 16 is a diagram illustrating an example of the LBP for each reference signal according to the first embodiment of the present technology. As described above, in the LBP extraction mode, the DAC 211 sequentially supplies four reference signals having different offset voltages to all the pixels. In the figure, the vertical axis represents voltage, and the horizontal axis represents time. A solid straight line indicates a pixel signal of the pixel of interest, and a dotted straight line indicates a pixel signal of a neighboring pixel.

When the potential of the pixel signal of the target pixel becomes lower than the reference signal REFa at time TL5, the comparison result VCO_ (i, j) of the target pixel is inverted. If the potential of the neighboring pixel is higher than the reference signal REFa at this time TL5, the LBP value of “0” is held for the neighboring pixel. In this example, since the potentials of the six neighboring pixels are higher than the potential −dV _{var of the} target pixel, “0” bits are held for them, and the remaining two bits are “1”. As a result, “00000011” is generated as the first LBPa_ (i, j).

  Next, the DAC 211 supplies a reference signal REFb to which a negative offset voltage is added. This offset voltage changes the timing at which the comparison result VCO is inverted for each pixel. For example, when the potential of the pixel signal of the target pixel becomes lower than the reference signal REFb at time TL6, the target pixel comparison result VCO_ (i, j) is inverted. At this time TL6, the potentials of the three neighboring pixels are higher than the reference signal REFb, and the LBP value of “0” is held for those neighboring pixels. As a result, “00011111” is generated as LBPb_ (i, j).

  Subsequently, the DAC 211 supplies a reference signal REFc to which an offset voltage having a larger absolute value than the reference signal REFb is added. This offset voltage changes the timing at which the comparison result VCO is inverted for each pixel. For example, when the potential of the pixel signal of the target pixel becomes lower than the reference signal REFc at time TL7, the target pixel comparison result VCO_ (i, j) is inverted. At this time TL7, the potentials of the four neighboring pixels are higher than the reference signal REFb, and the LBP value of “0” is held for those neighboring pixels. As a result, “00001111” is generated as LBPc_ (i, j).

  The DAC 211 supplies the reference signal REFd to which an offset voltage having a larger absolute value than the reference signal REFc is added. This offset voltage changes the timing at which the comparison result VCO is inverted for each pixel. For example, when the potential of the pixel signal of the target pixel becomes lower than the reference signal REFd at time TL8, the target pixel comparison result VCO_ (i, j) is inverted. At this time TL8, the potentials of the five neighboring pixels are higher than the reference signal REFb, and the LBP value of “0” is held for those neighboring pixels. As a result, “00000111” is generated as LBPd_ (i, j).

  As described above, when the offset voltage of the reference signal REF is changed, the timing at which the comparison result VCO_ (i, j) of the target pixel is inverted, that is, the timing at which the comparison result VCO of the neighboring pixel is latched is changed. With this change in timing, the comparison result VCO is likely to change in neighboring pixels where the potential difference from the target pixel is small. For example, a neighboring pixel at coordinates (i + 1, j + 1) has the smallest potential difference from the target pixel. In this neighboring pixel, the comparison result VCO_ (i + 1, j + 1) is at the low level at time TL5, but the comparison result VCO_ (i + 1, j + 1) is changed to the high level at time TL6.

  On the other hand, in a neighboring pixel having a large potential difference from the target pixel, the comparison result VCO hardly changes even if the offset voltage is changed. For example, a neighboring pixel at coordinates (i−1, j−1) has the largest potential difference from the target pixel. In this neighboring pixel, the comparison result VCO_ (i−1, j−1) remains at the high level from time TL5 to TL8. In addition, the comparison result VCO does not change for neighboring pixels whose potential is equal to or higher than the potential of the target pixel regardless of the potential difference. For example, the neighboring pixel at the coordinate (i + 1, j) has a potential equal to or higher than the potential of the pixel of interest. In this neighboring pixel, the comparison result VCO_ (i + 1, j) remains at the low level from time TL5 to TL8.

  Therefore, for the neighboring pixels whose potential is lower than the target pixel, the larger the potential difference from the target pixel, the greater the number of bits of “1” in the corresponding bits of LBPa to LBPd.

  Note that the DAC 211 supplies four reference signals with different offset voltages, but can also supply a number of reference signals other than four. The DAC 211 applies a negative offset voltage, but may apply a positive offset voltage. In this case, the magnitude of the potential difference can be expressed by the number of bits of “1” for neighboring pixels whose potential is greater than or equal to the target pixel. Further, the DAC 211 can sequentially supply a reference signal to which a negative offset voltage is added and a reference signal to which a positive offset voltage is added.

[Configuration example of output unit]
FIG. 17 is a block diagram illustrating a configuration example of the output unit 250 according to the first embodiment of the present technology. The output unit 250 includes a switch 251, a feature amount conversion unit 252, a signal processing unit 253, and an output circuit 254.

  The switch 251 switches the output destination of data from the pixel array unit 220 according to the enable signal LBP_EN. When the enable signal LBP_EN is enabled, the switch 251 outputs LBPa_ (i, j) to LBPd_ (i, j) from the pixel array unit 220 to the feature amount conversion unit 252. On the other hand, when the enable signal LBP_EN is disabled, the switch 251 outputs the pixel data PIX_ (i, j) from the pixel array unit 220 to the signal processing unit 253.

  The feature amount conversion unit 252 converts LBPa_ (i, j) to LBPd_ (i, j) into a feature amount Fv_ (i, j) that represents the difference in pixel signal from the pixel of interest for each neighboring pixel by a multivalue. Is. The feature amount conversion unit 252 counts the number of “1” for each digit of LBPa_ (i, j) to LBPd_ (i, j). Then, the feature amount conversion unit 252 outputs the data in which those count values are arranged to the output circuit 254 as the feature amount Fv_ (i, j).

  Since there are four LBPs, the range of the count value of the number “1” in a certain digit is “0” to “4”. As described above, the larger the potential difference between the neighboring pixel and the target pixel, the greater the number of bits “1” in the corresponding bits of LBPa to LBPd, and thus the count value represents the magnitude of the potential difference. When 3 bits are assigned to the count values “0” to “4”, 8-bit LBPa_ (i, j) to LBPd_ (i, j) are converted into 24-bit feature quantity Fv_ (i, j), respectively. The

  The signal processing unit 253 performs predetermined signal processing such as black level correction processing for correcting the black level and CDS processing on the pixel data PIX_ (i, j). In the CDS process, the signal processing unit 253 subtracts the D-phase data from the P-phase data, so that the variation of the comparison circuit 310, the charge injection of the reset operation, the feedthrough, and the like can be canceled. The signal processing unit 253 supplies the pixel data after the signal processing to the output circuit 254.

  The output circuit 254 outputs data from the feature amount conversion unit 252 or the signal processing unit 253 to the digital signal processor 120 according to the control of the timing generation circuit 215.

  Note that the output unit 250 performs conversion into the feature value Fv_ (i, j). However, instead of the output unit 250, a subsequent circuit (such as the digital signal processor 120) performs the feature value Fv_ (i, j). ).

  FIG. 18 is a diagram for describing the conversion process by the feature amount conversion unit 252 according to the first embodiment of the present technology. In the figure, a shows an example of LBPa_ (i, j), and b in the figure shows an example of LBPb_ (i, j). C in the figure shows an example of LBPc_ (i, j), and d in the figure shows an example of LBPd_ (i, j). E in the figure shows an example of the feature amount Fv_ (i, j).

  The feature quantity conversion unit 252 counts the number of “1” for each digit of LBPa_ (i, j) to LBPd_ (i, j). For example, the digits corresponding to the upper left neighboring pixel are all “1” in LBPa_ (i, j) to LBPd_ (i, j). Therefore, “4” is set in the digit corresponding to the upper left neighboring pixel of the feature amount Fv_ (i, j). The digits corresponding to the lower left neighboring pixel are all “0” in LBPa_ (i, j) to LBPd_ (i, j). Accordingly, “0” is set in the digit corresponding to the lower left neighboring pixel of the feature amount Fv_ (i, j).

  This feature amount Fv_ (i, j) represents the difference in pixel signal from the target pixel in multiple values for each neighboring pixel. Therefore, the amount of information of the feature amount Fv_ (i, j) is large and the image quality of the feature amount image is improved as compared with the LBP in which the magnitude relationship of the pixel signal with the pixel of interest for each neighboring pixel is expressed in binary. For this reason, the digital signal processor 120 performs image recognition using the feature amount image made up of the feature amount Fv_ (i, j), thereby improving the recognition accuracy compared to the case where the feature amount image made up of LBP is used. Can be made.

  FIG. 19 is a diagram summarizing the processing flow in the imaging apparatus 100 according to the first embodiment of the present technology. The pixel circuit 240 generates an analog signal corresponding to the amount of received light as a pixel signal and supplies it to the ADC 300.

  The ADC 300 generates LBPa_ (i, j) to LBPd_ (i, j) using four reference signals REF having different offset voltages, and supplies them to the feature amount conversion unit 252. The feature amount conversion unit 252 represents LBPa_ (i, j) to LBPd_ (i, j) for each pixel, and a feature amount Fv_ (i, j) that represents the difference in pixel signal from the pixel of interest for each neighboring pixel by a multivalue. And is supplied to the digital signal processor 120. In other words, the feature amount Fv_ (i, j) is extracted for each pixel. The circuit including the ADC 300 and the feature amount conversion unit 252 is an example of a feature amount extraction unit described in the claims.

  Then, the digital signal processor 120 performs image recognition processing or the like on the feature amount image including the feature amount Fv_ (i, j).

  In a general imaging device, a solid-state imaging device AD converts a pixel signal to generate a normal image, and an external processor extracts an LBP from the normal image. On the other hand, in the solid-state image sensor 200, the LBP is extracted directly from the pixel signal inside the solid-state image sensor 200, not in the external processor. For this reason, it is not necessary to perform AD conversion of the pixel signal, and the power consumption of the imaging apparatus 100 can be reduced correspondingly.

[Operation example of imaging device]
FIG. 20 is a flowchart illustrating an example of the operation of the imaging device 100 according to the first embodiment of the present technology. This operation is started, for example, when a predetermined application for capturing image data is executed in the imaging apparatus 100.

  The imaging apparatus 100 determines whether or not the feature amount extraction mode is set (step S901). When the feature amount extraction mode is set (step S901: Yes), the imaging apparatus 100 executes an LBP generation process for generating an LBP (step S910). Then, the imaging apparatus 100 converts the LBP into the feature amount Fv_ (i, j) for each pixel (step S902), and performs image recognition on the feature amount image (step S903).

  When the feature amount extraction mode is not set (step S901: No), the imaging apparatus 100 performs AD conversion on the pixel signal for each pixel to generate a normal image (step S904), and various changes are made to the normal image. Image processing is executed (step S905). After step S903 or S905, the imaging apparatus 100 repeatedly executes step S901 and subsequent steps.

  FIG. 21 is a flowchart illustrating an example of the LBP generation process according to the first embodiment of the present technology. The solid-state imaging device 200 in the imaging apparatus 100 generates LBPa_ (i, j) for each pixel using the reference signal REFa (step S911). Then, the solid-state imaging device 200 changes the offset voltage of the reference signal (step S912), and generates LBPb_ (i, j) for each pixel using the changed reference signal REFb (step S913).

  Subsequently, the solid-state imaging device 200 changes the offset voltage of the reference signal (step S914), and generates LBPc_ (i, j) for each pixel using the changed reference signal REFc (step S915). Then, the solid-state imaging device 200 changes the offset voltage of the reference signal (Step S916), and generates LBPd_ (i, j) for each pixel using the changed reference signal REFd (Step S917). After step S917, the solid-state imaging device 200 ends the LBP generation process.

  As described above, in the first embodiment of the present technology, the solid-state imaging device 200 extracts the feature amount Fv_ (i, j) that represents the difference between the pixel signals of the neighboring pixel and the target pixel in multiple values. Therefore, the information amount of the feature amount can be increased as compared with the LBP that expresses the difference as a binary value. Thereby, the image quality of the feature amount image can be improved and the recognition accuracy of the image recognition can be increased.

<2. Second Embodiment>
In the first embodiment described above, the solid-state imaging device 200 extracts the feature value Fv_ (i, j) using a plurality of reference signals generated in order. However, as the number of reference signals increases, the ADC 300 increases. The conversion time becomes longer. When the conversion time becomes longer, the time for the pixel circuit 240 to hold the analog pixel signal SIG_ (i, j) becomes longer, and the possibility that the signal level fluctuates due to the influence of a leakage current or the like increases. As a result, the accuracy of AD conversion decreases. In order to shorten the AD conversion time, only one reference signal is used and AD conversion is performed using a counter. The solid-state imaging device 200 according to the second embodiment is different from the first embodiment in that AD conversion is performed using a counter.

  FIG. 22 is a block diagram illustrating a configuration example of the ADC 300 according to the second embodiment of the present technology. The ADC 300 according to the second embodiment is different from the first embodiment in that a counting unit 370 is provided instead of the data storage unit 350.

  The counting unit 370 includes a counting circuit 371 for each neighboring pixel. The counting circuit 371 counts the count value over a period between the time when the comparison result VCO_ (i, j) of the target pixel is inverted and the time when the comparison result VCO of the corresponding neighboring pixel is inverted. . The counting unit 370 outputs data consisting of these count values to the buffer circuit 360 via the local bit line LBL as the feature amount Fv_ (i, j).

  Further, since the ADC 300 extracts the feature amount Fv_ (i, j), the feature amount conversion unit 252 is not provided in the output unit 250 of the second embodiment.

  FIG. 23 is a circuit diagram illustrating a configuration example of the counting circuit 371 according to the second embodiment of the present technology. The counting circuit 371 includes a NAND (negative logical product) gate 372, a NOR (negative logical sum) gate 373, and an up / down counter 380.

  The NAND gate 372 uses the negative logical product of the comparison result (VCO_ (i, j−1) etc.) of the corresponding neighboring pixel and the comparison result VCO_ (i, j) of the target pixel as a start flag STA, and the up / down counter 380 Is output. The start flag STA is set to the high level when the comparison result between the target pixel and the corresponding neighboring pixel is inverted by the negative logical product operation, and counting of the up / down counter 380 is started.

  The NOR gate 373 outputs a negative logical sum of the comparison result of the corresponding neighboring pixel and the comparison result VCO_ (i, j) of the target pixel to the up / down counter 380 as a stop flag STP. When the comparison result of both the target pixel and the corresponding neighboring pixel is inverted by the negative OR operation, the stop flag STP is set to the high level, and the counting of the up / down counter 380 is ended.

  The up / down counter 380 counts the count value of the code according to the comparison result of the corresponding neighboring pixels. The up / down counter 380 receives the comparison result of the corresponding neighboring pixels as an up / down flag UD. Further, the clock signal CLK from the vertical drive circuit 213 is input to the up / down counter 380.

  When the start flag STA becomes high level, the up / down counter 380 increments the count value (that is, counts up) in synchronization with the clock signal CLK if the up / down flag UD is high level. On the other hand, if the up / down flag UD is at a low level, the up / down counter 380 decrements the count value (ie, counts down) in synchronization with the clock signal CLK. When the stop flag STP becomes high level, the up / down counter 380 stops counting. Then, the up / down counter 380 outputs the count value to the buffer circuit 360. Here, the count value is multivalued and is represented by a bit string of 2 bits or more. However, the number of bits may be smaller than the number of bits (10 bits or more) of the pixel data in the imaging mode. For example, when the count value range is “−3” to “+3”, 3 bits including 1 bit indicating the sign and 2 bits indicating the absolute value are output as the count value.

  Further, the frequency of the clock signal CLK in the LBP extraction mode may be lower than the frequency of the clock signal in the imaging mode. For example, the imaging mode is set to several tens to several hundreds of megahertz (MHz), whereas the LBP extraction mode is set to several kilohertz (kHz) to several tens of hertz (Hz).

  FIG. 24 is a circuit diagram illustrating a configuration example of the up / down counter 380 according to the second embodiment of the present technology. The up / down counter 380 includes an inverter 381, a NAND gate 382, a NOR gate 383, and a JK flip-flop 384. The up / down counter 380 includes XOR (exclusive OR) gates 385 and 387, JK flip-flops 386 and 389, and an AND (logical product) gate 388.

  The inverter 381 inverts the up / down flag UD. The inverter 381 supplies the inverted inverted signal to the XOR gates 385 and 387.

  The NAND gate 382 outputs a negative logical product of the clock signal CLK and the start flag STA to the NOR gate 383.

  The NOR gate 383 outputs a negative logical sum of the signal from the NAND gate 382 and the stop flag STP to the JK flip-flops 384, 386 and 389.

  The JK flip-flop 384 holds the 0th bit of the count value. The high level is input to the input terminals J and K of the JK flip-flop 384, and the inverted value of the signal from the NOR gate 383 is input to the clock terminal. The JK flip-flop 384 outputs the hold value from the output terminal Q to the XOR gate 385 and the buffer circuit 360.

  The XOR gate 385 outputs an exclusive OR of the signal from the inverter 381 and the signal from the flip-flop 384 to the JK flip-flop 386 and the AND gate 388.

  The JK flip-flop 386 holds the first bit of the count value. A signal from the XOR gate 385 is input to the input terminals J and K of the JK flip-flop 386, and an inverted value of the signal from the NOR gate 383 is input to the clock terminal. Further, the JK flip-flop 386 outputs the hold value from the output terminal Q to the XOR gate 387 and the buffer circuit 360.

  The XOR gate 387 outputs an exclusive OR of the signal from the inverter 381 and the signal from the flip-flop 386 to the AND gate 388.

  The AND gate 388 outputs a logical product of signals from the XOR gates 385 and 387 to the JK flip-flop 389.

  The JK flip-flop 389 holds the second bit of the count value. A signal from the AND gate 388 is input to the input terminals J and K of the JK flip-flop 389, and an inverted value of the signal from the NOR gate 383 is input to the clock terminal. Further, the JK flip-flop 389 outputs the retained value to the buffer circuit 360.

  Note that the circuit in the up / down counter 380 is not limited to the configuration illustrated in FIG. 24 as long as the function described in FIG. 23 can be realized.

  FIG. 25 is a timing chart illustrating an example of an operation for performing up-counting according to the second embodiment of the present technology. As illustrated in the figure, the DAC 211 of the second embodiment supplies the slope-shaped reference signal REF only once.

  Here, it is assumed that the potential of the pixel signal SIG_ (i−1, j−1) of the pixel near the coordinate (i−1, j−1) is higher than the potential of the pixel signal SIG_ (i, j) of the target pixel. To do. In this case, the comparison result VCO_ (i−1, j−1) of the neighboring pixels is inverted first at time T51, and then the comparison result VCO_ (i, j) of the target pixel is inverted at time T52.

  The up / down counter 380 counts up from time T51 to time T52, and acquires a count value of “+1”, for example. As described above, when the potential of the pixel signal of the neighboring pixel is higher than the potential of the pixel signal of the target pixel, up-counting is performed. As the potential difference between the target pixel and the neighboring pixel is larger, the counting period is longer and the counted value is larger. Therefore, the count value indicates the magnitude of the potential difference between the pixel signals of the target pixel and the neighboring pixels.

  FIG. 26 is a timing chart illustrating an example of an operation for performing a down-count in the second embodiment of the present technology.

  Here, it is assumed that the potential of the pixel signal SIG_ (i + 1, j + 1) of the neighboring pixel at the coordinate (i + 1, j + 1) is lower than the potential of the pixel signal SIG_ (i, j) of the target pixel. In this case, the target pixel comparison result VCO_ (i, j) is inverted first at time T53, and then the target pixel comparison result VCO_ (i + 1, j + 1) is inverted at time T54.

  The up / down counter 380 counts down from time T53 to time T54, and acquires a count value of “−3”, for example. As described above, when the potential of the pixel signal of the neighboring pixel is lower than the potential of the pixel signal of the target pixel, down-counting is performed.

  As illustrated in FIGS. 25 and 26, the sign of the count value indicates which of the pixel signal of the target pixel and the pixel signal of the neighboring pixel is greater. When the values of these pixel signals substantially match, the count value is “0”.

  Further, as described above, in the second embodiment, the DAC 211 does not need to supply a plurality of reference signals. For this reason, the conversion time of the ADC 300 can be shortened as compared with the first embodiment.

  FIG. 27 is a diagram summarizing the processing flow in the imaging apparatus 100 according to the second embodiment of the present technology. Similar to the first embodiment, the pixel circuit 240 generates an analog signal corresponding to the amount of received light as a pixel signal, and supplies the pixel signal to the ADC 300.

  The ADC 300 counts the count value based on the comparison result between the pixel signal and the reference signal, and extracts the feature amount Fv_ (i, j) similar to that of the first embodiment for each pixel. The ADC 300 is an example of a feature amount extraction unit described in the claims.

  Then, the digital signal processor 120 performs image recognition processing or the like on the feature amount image including the feature amount Fv_ (i, j). The feature amount Fv_ (i, j) is different from the LBP that indicates only the magnitude relationship between the pixel signals of the target pixel and the neighboring pixels, and indicates the magnitude of the difference between the pixel signals. Therefore, by using the feature amount Fv_ (i, j), whether the difference between the pixel signals is a value that is buried in various noises such as kTC noise and an offset of the comparison circuit 310, or a significant value. Can be determined. Therefore, the recognition accuracy of image recognition can be improved.

  As described above, in the second embodiment of the present technology, the ADC 300 sequentially supplies a plurality of reference signals in order to extract a feature value by counting a count value based on a comparison result between a pixel signal and a reference signal. Compared to the first embodiment, the conversion time of the ADC 300 can be shortened. Thereby, the precision of AD conversion can be improved.

<3. Third Embodiment>
In the first embodiment described above, the ADC 300 performs LBP writing and reading each time a reference signal is supplied. However, as the number of reference signals increases, the number of times of reading increases. Resulting in. If the number of times of reading increases, the conversion time of the ADC 300 becomes longer, and the accuracy of AD conversion may decrease. The solid-state imaging device 200 of the third embodiment is different from the first embodiment in that the number of data reading is reduced by reading a plurality of data collectively.

  FIG. 28 is a block diagram illustrating a configuration example of the ADC 300 according to the third embodiment of the present technology. The ADC 300 according to the third embodiment is different from the first embodiment in that it includes a plurality of data storage units 350. The number of data storage units 350 is the same as the number of reference signals (four), for example. Further, the number of buffer circuits 360 is the same as that of the data storage unit 350.

  The vertical drive circuit 213 supplies the enable signal LBPa_EN to the data storage unit 350 corresponding to the reference signal REFa when supplying the reference signal REFa. The data storage unit 350 holds LBPa.

  Next, when the reference signal REFb is supplied, the vertical drive circuit 213 supplies the enable signal LBPb_EN to the data storage unit 350 corresponding to the reference signal REFb. The data storage unit 350 holds the LBPb.

  Similarly, the vertical drive circuit 213 sequentially supplies enable signals LBPc_EN and LBPd_EN, and the corresponding data storage unit 350 holds LBPc and LBPd.

  When the LBP is held in all the data storage units 350, the vertical drive circuit 213 supplies the WORD signal to all the data storage units 350 to execute the reading operation of LBPa to LBPd. As a result, when the data storage unit 350 holds all LBPa to LBPd, the vertical drive circuit 213 can collectively read the data.

  As described above, in the third embodiment of the present technology, since the solid-state imaging device 200 reads the plurality of LBPs after writing all the plurality of LBPs to the plurality of data storage units 350, the solid-state imaging device 200 is compared with the case where the LBP is read each time writing is performed. Thus, the conversion time of the ADC 300 can be shortened. Thereby, the accuracy of AD conversion can be improved without using the up / down counter 380.

<4. Fourth Embodiment>
In the first embodiment described above, the solid-state imaging device 200 holds a high-level bit when the potential of the pixel signal is higher than that of a neighboring pixel. However, when noise occurs in the pixel 230, a high-level bit may be held even if the relationship is not satisfied. For example, when the potential difference between the pixel signals of the pixel of interest and the neighboring pixels is less than a certain value, it is determined that the potential difference is caused by noise, and the pixel 230 holds a high level bit when the potential difference is greater than a certain value. , Noise effects can be reduced. The ADC 300 of the fourth embodiment is different from that of the first embodiment in that the pixel 230 holds a high-level bit when the potential difference is larger than a certain value.

  FIG. 29 is a circuit diagram illustrating a configuration example of the data storage unit 350 according to the fourth embodiment of the present technology. The data storage unit 350 of the fourth embodiment is different from that of the first embodiment in that it further includes a delay circuit 390.

  The delay circuit 390 delays the comparison result VCO_ (i, j) of the target pixel over a certain delay time dT. The delay circuit 390 supplies the delayed comparison result VCO_ (i, j) to the latch control circuit 352.

The fluctuation amount of the reference signal during the delay time dT is fixed. If the fluctuation amount is dV _fix , the high-level bit is held when the potential difference between the pixel signals of the target pixel and the neighboring pixel is larger than dV _fix. Is done.

Thus, in the fourth embodiment of the present technology, since the delay circuit 390 delays the comparison result VCO_ (i, j) of the target pixel, the target pixel is more than the fixed value dV _fix corresponding to the delay time. In addition, when the potential difference between neighboring pixels is large, “1” can be reliably held. Thereby, the influence of noise can be reduced.

<5. Fifth embodiment>
In the first embodiment described above, the ADC 300 holds the high-level bit when the potential of the pixel signal is higher than that of the neighboring pixels. However, when noise occurs in the pixel 230, a high-level bit may be held even if the relationship is not satisfied. For example, when the potential difference between the pixel signals of the pixel of interest and the neighboring pixels is less than a certain value, it is determined that the potential difference is caused by noise, and the pixel 230 holds a high level bit when the potential difference is greater than a certain value. , Noise effects can be reduced. The ADC 300 of the fifth embodiment is different from the first embodiment in which the pixel 230 holds a high-level bit when the potential difference is larger than a certain value.

  FIG. 30 is a block diagram illustrating a configuration example of the ADC 300 according to the fifth embodiment of the present technology. The ADC 300 of the fifth embodiment is different from that of the first embodiment in that it further includes a delay circuit 390.

  The delay circuit 390 delays the comparison result VCO of neighboring pixels over a certain delay time dT. The delay circuit 390 supplies the delayed comparison result VCO to each data storage unit 350 of the neighboring pixels.

Thus, in the fifth embodiment of the present technology, since the delay circuit 390 delays the comparison result VCO of the neighboring pixels, the potential difference between the target pixel and the neighboring pixels is more than the fixed value dV _fix corresponding to the delay time. When “1” is large, “1” can be reliably held. Thereby, the influence of noise can be reduced without delaying the comparison result VCO_ (i, j) of the target pixel.

<6. Sixth Embodiment>
In the first embodiment described above, the ADC 300 is arranged for each pixel in the pixel array unit 220. However, as the miniaturization progresses, the circuit scale per pixel may increase. For example, if a pixel sharing type configuration in which a plurality of pixels share a floating diffusion layer and a transistor, the circuit scale per pixel can be reduced. The pixel array unit 220 of the sixth embodiment is different from the first embodiment in that a plurality of pixels share a floating diffusion layer.

  FIG. 31 is a plan view illustrating a configuration example of the pixel array unit 220 according to the sixth embodiment of the present technology. In the pixel array unit 220 of the sixth embodiment, a plurality of area blocks 400 are arranged in a two-dimensional lattice pattern. Each area block 400 has a plurality of pixels. For example, in the area block 400, four pixels are arranged in 2 rows × 2 columns. Pixels in the area block 400 share the floating diffusion layer and the ADC 300.

  FIG. 32 is a circuit diagram illustrating a configuration example of the area block 400 according to the sixth embodiment of the present technology. The area block 400 includes pixel circuits 410, 420, 430 and 440, a floating diffusion layer 450, and an ADC 300.

  The pixel circuit 410 includes a discharge transistor 411, a transfer transistor 412, and a photodiode 413. The pixel circuit 420 includes a discharge transistor 421, a transfer transistor 422, and a photodiode 423. The pixel circuit 430 includes a discharge transistor 431, a transfer transistor 432, and a photodiode 433. The pixel circuit 440 includes a discharge transistor 441, a transfer transistor 442, and a photodiode 443.

  The photodiode 413 generates charges by photoelectrically converting incident light. The discharge transistor 411 discharges the charge of the photodiode 413 in accordance with the discharge control signal OFG. The transfer transistor 412 transfers charges from the photodiode 413 to the floating diffusion layer 450 in accordance with the transfer signal TX0.

  The functions of the elements in the pixel circuits 420, 430, and 440 are the same as the elements of the same name in the pixel circuit 410. However, transfer signals TX1, TX2, and TX3 are supplied to the pixel circuits 420, 430, and 440. The pixel drive circuit 214 sequentially supplies the transfer signals TX0, TX1, TX2, and TX3 to transfer the charges in order.

  Note that although four pixels share the floating diffusion layer 450 and the ADC 300, the number of pixels to be shared is not limited to four pixels. For example, a configuration in which eight pixels share the floating diffusion layer 450 or the like may be used.

  As described above, in the sixth embodiment of the present technology, since four pixels share the floating diffusion layer 450 and the ADC 300, the circuit per pixel is compared with the configuration in which the floating diffusion layer 450 and the like are arranged for each pixel. Can reduce the scale.

<7. Seventh Embodiment>
In the above-described first embodiment, the solid-state imaging device 200 performs exposure for each image when capturing both a normal image and a feature amount image. That is, it was necessary to perform exposure at least twice. However, if one of the normal image and the feature amount image is generated and held by exposure and then the other is also generated and held, there is no need to perform the exposure again. The solid-state imaging device 200 according to the seventh embodiment is different from the first embodiment in that both a normal image and a feature amount image are generated by a single exposure.

  FIG. 33 is a circuit diagram illustrating a configuration example of the data storage unit 350 according to the seventh embodiment of the present technology. The data storage unit 350 according to the seventh embodiment includes a latch control circuit 352, a plurality of LBP latch circuits 460, and a plurality of time code latch circuits 470. The LBP latch circuit 460 is arranged for each neighboring pixel. The number of time code latch circuits 470 is the same as the number of bits of the time code. For example, when there are 8 neighboring pixels and the time code is 8 bits, eight LBP latch circuits 460 and eight time code latch circuits 470 are arranged.

  The LBP latch circuit 460 holds the comparison result VCO of the corresponding neighboring pixels according to the control of the latch control circuit 352. The time code latch circuit 470 holds the corresponding bit in the time code in accordance with the control of the latch control circuit 352.

  FIG. 34 is a circuit diagram illustrating a configuration example of the LBP latch circuit 460 according to the seventh embodiment of the present technology. The LBP latch circuit 460 includes a switch 355 and a latch circuit 356. These functions are the same as those of the circuit of the same name in the first embodiment.

  FIG. 35 is a circuit diagram illustrating a configuration example of the time code latch circuit 470 according to the seventh embodiment of the present technology. This time code latch circuit 470 includes inverters 461 and 462 and a switch 463.

  The inverter 461 inverts the signal from the inverter 462 according to the control signal L and outputs it to the input terminal of the inverter 462 and the switch 463.

  The inverter 462 inverts the signal from the switch 463 or the inverter 461 and outputs it to the input terminal of the inverter 461.

  The switch 463 opens and closes a path between the loop circuit including the inverters 461 and 462 and the buffer circuit 360 according to the control signal T.

  At the end of exposure, the vertical drive circuit 213 holds the LBP in the eight LBP latch circuits 460, and then holds the time code as pixel data in the eight time code latch circuits 470. The vertical drive circuit 213 sequentially outputs LBPa to LBPd and a normal image composed of pixel data.

  As described above, in the seventh embodiment of the present technology, since the data storage unit 350 further holds the time code in addition to the LBP, it is possible to generate both the feature amount image and the normal image by one exposure. it can.

<8. Eighth Embodiment>
In the first embodiment described above, in the pixel array unit 220, the target pixel outputs the comparison result VCO_ (i, j) to all eight neighboring pixels. Therefore, it is desirable to reduce the number of wires. However, in order to reduce the number of wires, it is necessary to perform processing for restoring the LBP whose number of bits has decreased with the reduction of the number of wires to the original number of bits. The solid-state imaging device 200 according to the eighth embodiment is different from the first embodiment in that the number of wires for transmitting the comparison result is reduced and the LBP is restored.

  FIG. 36 is a diagram for describing wiring connection of signal lines in the eighth embodiment of the present technology. A in the same figure is a figure which shows the connection relation of the attention pixel and neighboring pixel in 1st Embodiment. B in the figure is a diagram showing a connection relationship between a pixel of interest and a neighboring pixel in the eighth embodiment. In the figure, a thick arrow represents a wiring of a neighboring pixel connected to the latch of the target pixel, and a thin solid arrow represents a wiring connected to a latch of the neighboring pixel. The direction of the arrow represents the connection direction.

  In the first embodiment, there are a plurality of sets of arrows that overlap in opposite directions. This indicates that the relative relationship between the pixel value of the target pixel and the pixel values of neighboring pixels is acquired in an overlapping manner. The LBP values acquired by the pixels associated with the pair of arrows pointing in the opposite directions are equivalent as information (= the magnitude relationship between the two pixels), and the LBP value itself is the other bit inverted value. is there.

  Therefore, as illustrated in b in FIG. 36, the wiring connection between neighboring pixels can be reduced by half. In this example, the target pixel is connected to one of a pair of neighboring pixels that are point-symmetric with respect to the target pixel. For example, since the upper left neighboring pixel and the lower right neighboring pixel of the target pixel are point-symmetric with respect to the target pixel, the upper left neighboring pixel is connected, and the lower right neighboring pixel is not connected. As a result, the number of bits of the LBP acquired by each pixel is halved (eg, 4 bits), but the desired LBP can be completely restored by the arithmetic processing described later.

  FIG. 37 is a circuit diagram illustrating a configuration example of the data storage unit 350 according to the eighth embodiment of the present technology. In the data storage unit 350, the number of each of the switch 355 and the latch circuit 356 is reduced to half (for example, four) compared to the first embodiment.

  FIG. 38 is a circuit diagram illustrating a configuration example of the output unit 250 according to the eighth embodiment of the present technology. The output unit 250 of the eighth embodiment differs from the first embodiment in that it further includes an interpolation processing unit 255.

  The interpolation processing unit 255 interpolates the bit corresponding to the other in the LBP consisting of the bit corresponding to one of a pair of neighboring pixels that are point-symmetric with respect to the target pixel. For example, the interpolation processing unit 255 performs interpolation by the following processing.

  First, the 0th bit of the LBP value obtained at the pixel of interest is directly used as the value of the 0th bit of the pixel of interest. The first bit of the LBP value obtained at the target pixel is also used as the value of the first bit of the target pixel. Similarly, the second bit of the LBP value obtained at the target pixel is set as the second bit value of the target pixel, and the third bit of the LBP value obtained at the target pixel is set as the third bit value of the target pixel. To do.

  Further, the 0th bit of the LBP value obtained at the neighboring pixel at the coordinates (i + 1, j + 1) is inverted to obtain the value of the 4th bit of the target pixel. The first bit of the LBP value obtained at the pixel near the coordinate (i + 1, j) is inverted to obtain the value of the fifth bit of the target pixel. Further, the second bit of the LBP value obtained at the neighboring pixel is inverted to (i−1, j + 1) of the target pixel to obtain the value of the sixth bit of the target pixel. The third bit of the LBP value obtained at the pixel near the coordinate (i, j-1) is inverted to obtain the value of the seventh bit of the target pixel.

  In addition, although the imaging apparatus 100 performs the interpolation process in the solid-state image sensor 200, it may be performed outside the solid-state image sensor 200 (such as the digital signal processor 120).

  Thus, in the eighth embodiment of the present technology, when one of a pair of neighboring pixels that are point-symmetric with respect to the target pixel and the target pixel are connected to restore the LBP, the entire pixel is connected. As compared with the above, the number of wirings of the pixel array unit 220 can be reduced. In addition, the circuit scale of the data storage unit 350 can be reduced.

<9. Application example to mobile objects>
The technology according to the present disclosure (present technology) can be applied to various products. For example, the technology according to the present disclosure is realized as a device that is mounted on any type of mobile body such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, and a robot. May be.

  FIG. 39 is a block diagram illustrating a schematic configuration example of a vehicle control system that is an example of a mobile control system to which the technology according to the present disclosure can be applied.

  The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in FIG. 39, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside vehicle information detection unit 12030, an in-vehicle information detection unit 12040, and an integrated control unit 12050. As a functional configuration of the integrated control unit 12050, a microcomputer 12051, an audio image output unit 12052, and an in-vehicle network I / F (interface) 12053 are illustrated.

  The drive system control unit 12010 controls the operation of the device related to the drive system of the vehicle according to various programs. For example, the drive system control unit 12010 includes a driving force generator for generating a driving force of a vehicle such as an internal combustion engine or a driving motor, a driving force transmission mechanism for transmitting the driving force to wheels, and a steering angle of the vehicle. It functions as a control device such as a steering mechanism that adjusts and a braking device that generates a braking force of the vehicle.

  The body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a keyless entry system, a smart key system, a power window device, or a control device for various lamps such as a headlamp, a back lamp, a brake lamp, a blinker, or a fog lamp. In this case, the body control unit 12020 can be input with radio waves transmitted from a portable device that substitutes for a key or signals from various switches. The body system control unit 12020 receives input of these radio waves or signals, and controls a door lock device, a power window device, a lamp, and the like of the vehicle.

  The vehicle outside information detection unit 12030 detects information outside the vehicle on which the vehicle control system 12000 is mounted. For example, the imaging unit 12031 is connected to the vehicle exterior information detection unit 12030. The vehicle exterior information detection unit 12030 causes the imaging unit 12031 to capture an image outside the vehicle and receives the captured image. The vehicle outside information detection unit 12030 may perform an object detection process or a distance detection process such as a person, a car, an obstacle, a sign, or a character on a road surface based on the received image.

  The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of received light. The imaging unit 12031 can output an electrical signal as an image, or can output it as distance measurement information. Further, the light received by the imaging unit 12031 may be visible light or invisible light such as infrared rays.

  The vehicle interior information detection unit 12040 detects vehicle interior information. For example, a driver state detection unit 12041 that detects a driver's state is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that images the driver, and the vehicle interior information detection unit 12040 determines the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041. It may be calculated or it may be determined whether the driver is asleep.

  The microcomputer 12051 calculates a control target value of the driving force generator, the steering mechanism, or the braking device based on the information inside / outside the vehicle acquired by the vehicle outside information detection unit 12030 or the vehicle interior information detection unit 12040, and the drive system control unit A control command can be output to 12010. For example, the microcomputer 12051 realizes an ADAS (Advanced Driver Assistance System) function including vehicle collision avoidance or impact mitigation, vehicle-following travel based on inter-vehicle distance, vehicle speed maintenance travel, vehicle collision warning, or vehicle lane departure warning. It is possible to perform cooperative control for the purpose.

  Further, the microcomputer 12051 controls the driving force generator, the steering mechanism, the braking device, and the like based on the information around the vehicle acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040. It is possible to perform cooperative control for the purpose of automatic driving that autonomously travels without depending on the operation.

  Further, the microcomputer 12051 can output a control command to the body system control unit 12020 based on information outside the vehicle acquired by the vehicle outside information detection unit 12030. For example, the microcomputer 12051 controls the headlamp according to the position of the preceding vehicle or the oncoming vehicle detected by the outside information detection unit 12030, and performs cooperative control for the purpose of anti-glare, such as switching from a high beam to a low beam. It can be carried out.

  The sound image output unit 12052 transmits an output signal of at least one of sound and image to an output device capable of visually or audibly notifying information to a vehicle occupant or the outside of the vehicle. In the example of FIG. 39, an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are illustrated as output devices. The display unit 12062 may include at least one of an on-board display and a head-up display, for example.

  FIG. 40 is a diagram illustrating an example of an installation position of the imaging unit 12031.

  In FIG. 40, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

  The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as a front nose, a side mirror, a rear bumper, a back door, and an upper part of a windshield in the vehicle interior of the vehicle 12100. The imaging unit 12101 provided in the front nose and the imaging unit 12105 provided in the upper part of the windshield in the vehicle interior mainly acquire an image in front of the vehicle 12100. The imaging units 12102 and 12103 provided in the side mirror mainly acquire an image of the side of the vehicle 12100. The imaging unit 12104 provided in the rear bumper or the back door mainly acquires an image behind the vehicle 12100. The imaging unit 12105 provided on the upper part of the windshield in the passenger compartment is mainly used for detecting a preceding vehicle or a pedestrian, an obstacle, a traffic light, a traffic sign, a lane, or the like.

  Note that FIG. 40 shows an example of the imaging range of the imaging units 12101 to 12104. The imaging range 12111 indicates the imaging range of the imaging unit 12101 provided in the front nose, the imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided in the side mirrors, respectively, and the imaging range 12114 The imaging range of the imaging part 12104 provided in the rear bumper or the back door is shown. For example, by superimposing the image data captured by the imaging units 12101 to 12104, an overhead image when the vehicle 12100 is viewed from above is obtained.

  At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera including a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

  For example, the microcomputer 12051, based on the distance information obtained from the imaging units 12101 to 12104, the distance to each three-dimensional object in the imaging range 12111 to 12114 and the temporal change in this distance (relative speed with respect to the vehicle 12100). In particular, it is possible to extract, as a preceding vehicle, a three-dimensional object that travels at a predetermined speed (for example, 0 km / h or more) in the same direction as the vehicle 12100, particularly the closest three-dimensional object on the traveling path of the vehicle 12100. it can. Further, the microcomputer 12051 can set an inter-vehicle distance to be secured in advance before the preceding vehicle, and can perform automatic brake control (including follow-up stop control), automatic acceleration control (including follow-up start control), and the like. Thus, cooperative control for the purpose of autonomous driving or the like autonomously traveling without depending on the operation of the driver can be performed.

  For example, the microcomputer 12051 converts the three-dimensional object data related to the three-dimensional object to other three-dimensional objects such as a two-wheeled vehicle, a normal vehicle, a large vehicle, a pedestrian, and a utility pole based on the distance information obtained from the imaging units 12101 to 12104. It can be classified and extracted and used for automatic avoidance of obstacles. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 as obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 determines the collision risk indicating the risk of collision with each obstacle, and when the collision risk is equal to or higher than the set value and there is a possibility of collision, the microcomputer 12051 is connected via the audio speaker 12061 or the display unit 12062. By outputting an alarm to the driver and performing forced deceleration or avoidance steering via the drive system control unit 12010, driving assistance for collision avoidance can be performed.

  At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether a pedestrian is present in the captured images of the imaging units 12101 to 12104. Such pedestrian recognition is, for example, whether or not the user is a pedestrian by performing a pattern matching process on a sequence of feature points indicating the outline of an object and a procedure for extracting feature points in the captured images of the imaging units 12101 to 12104 as infrared cameras. It is carried out by the procedure for determining. When the microcomputer 12051 determines that there is a pedestrian in the captured images of the imaging units 12101 to 12104 and recognizes the pedestrian, the audio image output unit 12052 has a rectangular contour line for emphasizing the recognized pedestrian. The display unit 12062 is controlled so as to be superimposed and displayed. Moreover, the audio | voice image output part 12052 may control the display part 12062 so that the icon etc. which show a pedestrian may be displayed on a desired position.

  Heretofore, an example of a vehicle control system to which the technology according to the present disclosure can be applied has been described. Of the configurations described above, the technology according to the present disclosure may be applied to the imaging unit 12031, for example. Specifically, the imaging device 100 illustrated in FIG. 1 can be applied to the imaging unit 12031. By applying the technology according to the present disclosure to the imaging unit 12031, the accuracy of image recognition of an obstacle or the like can be improved, and thus the safety of the vehicle control system can be improved.

  The above-described embodiment shows an example for embodying the present technology, and the matters in the embodiment and the invention-specific matters in the claims have a corresponding relationship. Similarly, the invention specific matter in the claims and the matter in the embodiment of the present technology having the same name as this have a corresponding relationship. However, the present technology is not limited to the embodiment, and can be embodied by making various modifications to the embodiment without departing from the gist thereof.

  Further, the processing procedure described in the above embodiment may be regarded as a method having a series of these procedures, and a program for causing a computer to execute these series of procedures or a recording medium storing the program. You may catch it. As this recording medium, for example, a CD (Compact Disc), an MD (MiniDisc), a DVD (Digital Versatile Disc), a memory card, a Blu-ray disc (Blu-ray (registered trademark) Disc), or the like can be used.

  In addition, the effect described in this specification is an illustration to the last, Comprising: It does not limit and there may exist another effect.

In addition, this technique can also take the following structures.
(1) a plurality of pixel circuits each generating an analog signal corresponding to the amount of received light and outputting it as a pixel signal;
A feature amount representing a difference value of the pixel signal from each of a neighboring pixel circuit in the vicinity of the noticed pixel circuit of interest and the noticed pixel circuit among the plurality of pixel circuits by a multivalue for each neighboring pixel circuit. An imaging apparatus comprising a feature amount extraction unit for extraction.
(2) a reference signal supply unit that sequentially supplies a plurality of reference signals having different offset voltages;
The imaging apparatus according to (1), wherein the feature amount extraction unit extracts the feature amount based on a comparison result obtained by comparing the pixel signal and each of the plurality of reference signals.
(3) The feature amount extraction unit
A comparison unit that compares the pixel signal with each of the plurality of reference signals and outputs the comparison result;
A storage unit that sequentially generates and stores a plurality of local bit patterns based on the comparison result;
The imaging apparatus according to (2), further comprising: a feature amount conversion unit that converts the data including the plurality of local bit patterns into the feature amount.
(4) The storage unit includes a plurality of data storage units that generate and store different local bit patterns.
The imaging device according to (3), wherein the feature amount conversion unit reads each of the local bit patterns and converts the local bit patterns into the feature amounts after the local bit patterns are stored in all of the plurality of data storage units.
(5) The imaging device according to (3) or (4), wherein the storage unit further stores a time code indicating a time when the comparison result is inverted.
(6) The comparison unit outputs the comparison result between the pixel signal from the pixel-of-interest circuit and each of the plurality of reference signals as a pixel-of-interest comparison result, and the pixel signal from the neighboring pixel circuit and the pixel signal Outputting the comparison result with each of a plurality of reference signals as a neighboring pixel comparison result;
The data storage unit
A latch circuit for holding the neighboring pixel comparison result;
A latch control circuit for holding the neighboring pixel comparison result in the latch circuit when the target pixel comparison result is inverted;
(3) to (5) including a delay circuit that delays one of the target pixel comparison result and the neighboring pixel comparison result over a predetermined time and outputs the delayed result to either the latch circuit or the latch control circuit. The imaging device according to any one of the above.
(7) The imaging device according to (6), wherein the delay circuit delays the pixel-of-interest comparison result and outputs the result to the latch control circuit.
(8) The imaging device according to (6), wherein the delay circuit delays the neighborhood pixel comparison result and outputs the result to the latch circuit.
(9) The feature quantity extraction unit
A comparison unit that compares each of the pixel signals with a predetermined reference signal and outputs a comparison result;
A count that counts a count value over a period between the time when the comparison result corresponding to the pixel circuit of interest inverts and the time when the comparison result corresponding to the neighboring pixel circuit is inverted, and outputs the counted value as the feature amount The imaging device according to (1), further including:
(10) The counting unit increments the count value when one of the comparison result corresponding to the target pixel circuit and the comparison result corresponding to the neighboring pixel circuit is inverted before the other, The imaging apparatus according to (9), wherein the count value is decremented when the other is inverted before the one.
(11) The plurality of pixel circuits are arranged in each of a plurality of area blocks,
Each of the plurality of area blocks is
The imaging device according to any one of (1) to (10), comprising the plurality of pixel circuits and a floating diffusion layer supplied by the plurality of pixel circuits.
(12) The neighboring pixel circuit includes a pair of neighboring pixel circuits that are point-symmetric with respect to the target pixel circuit,
The feature amount extraction unit extracts the feature amount that expresses the magnitude of the difference between the pixel signals from one of the pair of neighboring pixel circuits and the target pixel circuit by a multi-value (1) to (1) The imaging device according to any one of 11).
(13) The imaging apparatus according to any one of (1) to (12), further including an image processing unit that performs processing for recognizing a predetermined object based on the feature amount.
(14) An output procedure in which each of the plurality of pixel circuits generates an analog signal corresponding to the amount of received light and outputs it as a pixel signal;
A feature amount representing a difference value of the pixel signal from each of a neighboring pixel circuit in the vicinity of the noticed pixel circuit of interest and the noticed pixel circuit among the plurality of pixel circuits by a multivalue for each neighboring pixel circuit. A method for controlling an imaging apparatus, comprising: a feature amount extraction procedure for extraction.

DESCRIPTION OF SYMBOLS 100 Image pick-up device 110 Optical part 120 Digital signal processor 130 Display part 140 Operation part 150 Bus 160 Frame memory 170 Recording part 180 Power supply part 200 Solid-state image sensor 211 DAC
212 Time code generation unit 213 Vertical drive circuit 214 Pixel drive circuit 215 Timing generation circuit 220 Pixel array unit 221 Time code transfer unit 230 Pixel 240, 410, 420, 430, 440 Pixel circuit 241 Reset transistor 242, 412, 422, 432, 442 Transfer transistor 243, 450 Floating diffusion layer 244, 413, 423, 433, 443 Photodiode 245, 411, 421, 431, 441 Discharge transistor 250 Output unit 251, 355, 359, 463 Switch 252 Feature amount conversion unit 253 Signal processing Unit 254 output circuit 255 interpolation processing unit 300 ADC
310 Comparison circuit 320 Differential input circuit 321, 322, 323, 341, 342, 343 pMOS transistor 324, 325, 326, 331, 344, 345 nMOS transistor 330 Voltage conversion circuit 340 Positive feedback circuit 350 Data storage unit 351 Multiplexer 352 Latch Control circuit 353 OR (logical sum) gate 354, 357, 358, 363, 381, 461, 462 Inverter 356 Latch circuit 360 Buffer circuit 361 Bidirectional buffer 362 Buffer 370 Count unit 371 Count circuit 372, 382 NAND (Negative logical product) Gate 373, 383 NOR (negative OR) gate 380 Up / down counter 384, 386, 389 JK flip-flop 385, 387 XOR (exclusive OR) gate 38 AND (logical product) gate 390 delay circuit 400 Area block 460 LBP latch circuit 470 time code latch circuit 12031 imaging unit

Claims (14)

A plurality of pixel circuits each generating an analog signal corresponding to the amount of received light and outputting it as a pixel signal;
A feature amount representing a difference value of the pixel signal from each of a neighboring pixel circuit in the vicinity of the noticed pixel circuit of interest and the noticed pixel circuit among the plurality of pixel circuits by a multivalue for each neighboring pixel circuit. An imaging apparatus comprising a feature amount extraction unit for extraction. A reference signal supply unit that sequentially supplies a plurality of reference signals having different offset voltages,
The imaging apparatus according to claim 1, wherein the feature amount extraction unit extracts the feature amount based on a comparison result obtained by comparing the pixel signal and each of the plurality of reference signals. The feature amount extraction unit includes:
A comparison unit that compares the pixel signal with each of the plurality of reference signals and outputs the comparison result;
A storage unit that sequentially generates and stores a plurality of local bit patterns based on the comparison result;
The imaging apparatus according to claim 2, further comprising: a feature amount conversion unit that converts the data including the plurality of local bit patterns into the feature amount. The storage unit includes a plurality of data storage units that generate and store different local bit patterns,
The imaging device according to claim 3, wherein the feature amount conversion unit reads each of the local bit patterns and converts the local bit patterns into the feature amounts after the local bit patterns are stored in all of the plurality of data storage units.   The imaging apparatus according to claim 3, wherein the storage unit further stores a time code indicating a time when the comparison result is inverted. The comparison unit outputs the comparison result between the pixel signal from the pixel-of-interest circuit and each of the plurality of reference signals as a pixel-of-interest comparison result, and the pixel signal from the neighboring pixel circuit and the plurality of references Outputting the comparison result with each of the signals as a neighboring pixel comparison result,
The data storage unit
A latch circuit for holding the neighboring pixel comparison result;
A latch control circuit for holding the neighboring pixel comparison result in the latch circuit when the target pixel comparison result is inverted;
The imaging apparatus according to claim 3, further comprising: a delay circuit that delays one of the target pixel comparison result and the neighboring pixel comparison result for a predetermined time and outputs the delayed result to either the latch circuit or the latch control circuit.   The imaging device according to claim 6, wherein the delay circuit delays the pixel-of-interest comparison result and outputs the result to the latch control circuit.   The imaging device according to claim 6, wherein the delay circuit delays the neighborhood pixel comparison result and outputs the delayed result to the latch circuit. The feature amount extraction unit includes:
A comparison unit that compares each of the pixel signals with a predetermined reference signal and outputs a comparison result;
A count that counts a count value over a period between the time when the comparison result corresponding to the pixel circuit of interest inverts and the time when the comparison result corresponding to the neighboring pixel circuit is inverted, and outputs the counted value as the feature amount The imaging device according to claim 1, further comprising: The counting unit increments the count value when one of the comparison result corresponding to the target pixel circuit and the comparison result corresponding to the neighboring pixel circuit is inverted before the other, and the other is The imaging apparatus according to claim 9, wherein the count value is decremented when inverted before the one. The plurality of pixel circuits are arranged in each of a plurality of area blocks,
Each of the plurality of area blocks is
The imaging device according to claim 1, comprising: the plurality of pixel circuits; and a floating diffusion layer supplied by the plurality of pixel circuits. The neighboring pixel circuit includes a pair of neighboring pixel circuits that are point-symmetric with respect to the target pixel circuit,
2. The imaging according to claim 1, wherein the feature amount extraction unit extracts the feature amount that represents a magnitude of a difference between the pixel signals from one of the pair of neighboring pixel circuits and the target pixel circuit by a multi-value. apparatus. The imaging apparatus according to claim 1, further comprising an image processing unit that performs a process of recognizing a predetermined object based on the feature amount. An output procedure in which each of a plurality of pixel circuits generates an analog signal corresponding to the amount of received light and outputs it as a pixel signal;
A feature amount representing a difference value of the pixel signal from each of a neighboring pixel circuit in the vicinity of the noticed pixel circuit of interest and the noticed pixel circuit among the plurality of pixel circuits by a multivalue for each neighboring pixel circuit. A method for controlling an imaging apparatus, comprising: a feature amount extraction procedure for extraction.

Images