JP2019047349A - Electronic component - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress deterioration of a piezoelectric substrate. SOLUTION: A support substrate 10a, a piezoelectric substrate bonded on the support substrate, a functional element 12 provided on the piezoelectric substrate, and a side surface provided on the support substrate so as to surround the functional element. Is provided on the piezoelectric substrate and the first metal layer so as to overlap the first metal layer in contact with the side surface of the piezoelectric substrate and the interface 74 in which the piezoelectric substrate and the first metal layer are in contact in a plan view. Between the second metal layer 34, the piezoelectric substrate, the first metal layer, and the second metal layer, at least a part of the side surface 76 of the second metal layer on the functional element side and the interface thereof in a plan view. An electronic component comprising a protective film 35 provided so as to overlap at least a part of the above, and a cover member provided so as to be joined to the second metal layer and to seal the functional element in a gap. [Selection diagram] FIG. 7

Description

  The present invention relates to an electronic component, and to an electronic component having a piezoelectric substrate.

  An elastic wave device is known in which frequency temperature characteristics are improved by using a bonding substrate in which a piezoelectric substrate is bonded to the upper surface of a supporting substrate (for example, Patent Document 1). Further, in the configuration in which the piezoelectric substrate is bonded to a part of the upper surface of the support substrate and the wiring extends from the region of the upper surface of the support substrate to which the piezoelectric substrate is not bonded, the side surface of the piezoelectric substrate is an inclined surface It is known to suppress the disconnection of wiring by doing (For example, patent document 2).

JP 2004-343359 A JP, 2013-21387, A

  Since the piezoelectric substrate is fragile, when a metal layer or the like is provided on the piezoelectric substrate, a crack may be introduced into the piezoelectric substrate due to thermal stress or the like of the support substrate, the piezoelectric substrate, and the metal layer.

  The present invention is made in view of the above-mentioned subject, and it aims at controlling degradation of a piezoelectric substrate.

  The present invention is provided so as to surround a support substrate, a piezoelectric substrate bonded onto the support substrate, a functional element provided on the piezoelectric substrate, and the functional element on the support substrate, and the side surface is A second metal provided on a first metal layer in contact with a side surface of a piezoelectric substrate, and on the piezoelectric substrate and the first metal layer so as to overlap an interface where the piezoelectric substrate and the first metal layer are in contact in plan view Layer, between the piezoelectric substrate and the first metal layer and the second metal layer, at least a portion of the side surface of the second metal layer on the functional element side and at least a portion of the interface in plan view It is an electronic component provided with the protective film provided so that it might overlap and the cover member which joined with the said 2nd metal layer, and was provided so that the said functional element might be sealed in a space | gap.

  In the above configuration, the Young's modulus of the protective film can be smaller than the Young's modulus of a layer in contact with the protective film of the second metal layer.

  According to the present invention, a supporting substrate, a piezoelectric substrate bonded onto the supporting substrate, a functional element provided on the piezoelectric substrate, and a supporting substrate provided on the supporting substrate so as to surround the functional element. A first metal layer, a part of which is opposed to at least a part of the side surface of the piezoelectric substrate with a first air gap, a second metal layer provided on the first metal layer to surround the functional element, and And a cover member provided so as to be bonded to the second metal layer and sealing the functional element in the second air gap.

  In the above configuration, the linear thermal expansion coefficient of the support substrate may be smaller than the linear thermal expansion coefficient of the piezoelectric substrate.

  In the above configuration, the first metal layer and the support substrate can be in contact with each other.

  In the above configuration, the thickness of the first metal layer and the thickness of the piezoelectric substrate may be substantially the same.

  In the above configuration, the piezoelectric substrate may be a lithium tantalate substrate or a lithium niobate substrate.

  In the above configuration, the first metal layer may be configured to contain copper as a main component.

  In the above configuration, the cover member may have a device chip facing the functional element with an air gap therebetween.

  In the above configuration, the cover member encloses the device chip and is joined to the second metal layer, and has a metal sealing portion having a melting point lower than the melting points of the first metal layer and the second metal layer. be able to.

  According to the present invention, deterioration of the piezoelectric substrate can be suppressed.

FIG. 1 is a cross-sectional view of an electronic component according to Comparative Example 1. FIG. 2A is a plan view of the functional element 12 used in the comparative example and the example, and FIG. 2B is a cross-sectional view of the functional element 22. FIG. 3 is a schematic view of a cross-sectional SEM image of Comparative Example 1. 4 (a) and 4 (b) are a plan view and a cross-sectional view of a simulated structure. FIG. 5A and FIG. 5B are diagrams showing the stress in the XX cross section and the YY cross section. 6 (a) is an enlarged view of the region A of FIG. 5 (a), and FIG. 6 (b) is a diagram showing the magnitude of stress in the piezoelectric substrate of FIG. 5 (a). FIG. 7A is a cross-sectional view of the electronic component according to the first embodiment, and FIG. 7B is a plan view of the substrate 10. FIGS. 8A to 8D are cross-sectional views (part 1) illustrating the method of manufacturing the electronic component according to the first embodiment. 9 (a) to 9 (c) are cross-sectional views (part 2) showing the method of manufacturing the electronic component according to the first embodiment. FIGS. 10A and 10B are cross-sectional views of the electronic component according to the first and second modifications of the first embodiment. FIG. 11 is a plan view of a substrate of the electronic component according to the third modification of the first embodiment. 12 (a) and 12 (b) are cross-sectional views of electronic parts according to Modifications 4 and 5 of Embodiment 1. FIG. 13 (a) is a cross-sectional view of the electronic component according to the second embodiment, and FIG. 13 (b) is an enlarged view of the vicinity of the air gap 37 of FIG. 13 (a). 14 (a) to 14 (d) are cross-sectional views showing a method of manufacturing an electronic component according to the second embodiment.

Comparative Example 1
FIG. 1 is a cross-sectional view of an electronic component according to Comparative Example 1. As shown in FIG. 1, the substrate 10 has a support substrate 10a and a piezoelectric substrate 10b. The support substrate 10a is, for example, a sapphire substrate, an alumina substrate, a spinel substrate, a quartz substrate, or a silicon substrate. The piezoelectric substrate 10 b is, for example, a tantalum lithium substrate or a lithium niobate substrate. The piezoelectric substrate 10 b is bonded to the upper surface of the support substrate 10 a. The linear thermal expansion coefficient of the support substrate 10a is smaller than that of the piezoelectric substrate 10b.

  The functional element 12 and the wiring 14 are provided on the upper surface of the substrate 10. Terminals 18 are provided on the lower surface of the substrate 10. The terminal 18 is a foot pad for connecting the functional elements 12 and 22 to the outside. A penetrating electrode 16 penetrating the substrate 10 is provided. The through electrode 16 electrically connects the terminal 18 and the wiring 14.

  The piezoelectric substrate 10 b is removed at the outer edge of the substrate 10, and the annular metal layer 32 is provided on the support substrate 10 a. The wiring 14, the through electrode 16, the terminal 18 and the annular metal layer 32 are metal layers such as a copper layer, an aluminum layer or a gold layer, for example. An annular electrode 34 is provided on the annular metal layer 32. The annular electrode 34 includes, for example, a lower layer 34a, a middle layer 34b, and an upper layer 34c. The lower layer 34a is, for example, a titanium layer and is an adhesive layer with the annular metal layer 32 and the piezoelectric substrate 10b. The middle layer 34 b is, for example, a nickel layer and is a barrier layer that suppresses interdiffusion between the sealing portion 30 and the annular metal layer 32. The upper layer 34 c is, for example, a gold layer and a gold layer having good wettability with the sealing portion 30.

  The device chip 21 has a substrate 20, a functional element 22 and a wiring 24. The functional element 22 and the wiring 24 are provided on the lower surface of the substrate 20. The substrate 20 is, for example, an insulating substrate or a semiconductor substrate such as a silicon substrate, a glass substrate, a sapphire substrate, an alumina substrate, a spinel substrate, or a quartz substrate. The wiring 24 is, for example, a metal layer such as a copper layer, an aluminum layer, or a gold layer. The substrate 20 is flip-chip mounted (face-down mounting) on the substrate 10 via the bumps 28. The bumps 28 bond to the wires 14 and 24. The bumps 28 are, for example, gold bumps, solder bumps or copper bumps.

  A sealing portion 30 is provided on the substrate 10 so as to surround the substrate 20. The sealing unit 30 is a metal or resin such as solder. The sealing portion 30 is joined to the annular electrode 34. A flat lid 36 is provided on the upper surface of the substrate 20 and the upper surface of the sealing portion 30. The lid 36 is, for example, a metal plate such as a Kovar plate or an insulating plate. A protective film 38 is provided to cover the lid 36 and the sealing portion 30. The protective film 38 is a metal film such as a nickel film or an insulating film.

  The functional element 12 is opposed to the substrate 20 via the air gap 26. The functional element 22 is opposed to the piezoelectric substrate 10 b via the air gap 26. The functional elements 12 and 22 are sealed by the sealing portion 30, the substrate 10, the substrate 20 and the lid 36. The bumps 28 are surrounded by the air gap 26. The terminal 18 is electrically connected to the functional element 12 through the through electrode 16 and the wiring 14, and is further electrically connected to the functional element 22 through the bump 28 and the wiring 24.

  FIG. 2A is a plan view of the functional element 12 used in the comparative example and the example, and FIG. 2B is a cross-sectional view of the functional element 22. As shown in FIG. 2A, the functional element 12 is a surface acoustic wave resonator. An IDT (Interdigital Transducer) 40 and a reflector 42 are formed on the piezoelectric substrate 10 b of the substrate 10. The IDT 40 has a pair of comb electrodes 40a facing each other. The comb-shaped electrode 40 a has a plurality of electrode fingers 40 b and a bus bar 40 c connecting the plurality of electrode fingers 40 b. The reflectors 42 are provided on both sides of the IDT 40. The IDT 40 excites a surface acoustic wave on the piezoelectric substrate 10b. The IDT 40 and the reflector 42 are formed of, for example, an aluminum film or a copper film.

  The arrangement direction of the electrode fingers 40b is the direction in which the elastic wave propagates, and is the X direction. The extension direction of the electrode finger 40b is taken as a Y direction. The normal direction of the substrate 10 is taken as the Z direction. The X direction, the Y direction, and the Z direction do not necessarily coincide with the X axis, the Y axis, and the Z direction of the crystal orientation of the piezoelectric substrate 10b. In the rotated Y-cut X-propagating lithium tantalate substrate and the rotated Y-cut X-propagating lithium niobate substrate, the X direction is the X-axis direction of the crystal orientation.

  As shown in FIG. 2B, the functional element 22 is a piezoelectric thin film resonator. A piezoelectric film 46 is provided on the substrate 20. A lower electrode 44 and an upper electrode 48 are provided to sandwich the piezoelectric film 46. An air gap 45 is formed between the lower electrode 44 and the substrate 20. The lower electrode 44 and the upper electrode 48 excite the elastic wave in the thickness longitudinal vibration mode in the piezoelectric film 46. The lower electrode 44 and the upper electrode 48 are metal films, such as a ruthenium film, for example. The piezoelectric film 46 is, for example, an aluminum nitride film. The substrate 20 is an insulating substrate or a semiconductor substrate.

  The functional elements 12 and 22 include electrodes for exciting elastic waves. For this reason, the functional elements 12 and 22 are covered by the air gap 26 so as not to limit the elastic wave.

  The reason why the annular metal layer 32 is provided in the first comparative example is as follows. The piezoelectric substrate 10 b has lower thermal conductivity than the support substrate 10 a and the metal layer. Therefore, by removing at least a part of the piezoelectric substrate 10b and providing the annular metal layer 32, the thermal resistance between the sealing portion 30 and the support substrate 10a is reduced. As a result, heat is easily conducted to the entire electronic component, and the heat dissipation efficiency is enhanced. Further, there is a possibility that a crack or the like is introduced into the piezoelectric substrate 10b due to the thermal stress of the support substrate 10a, the piezoelectric substrate 10b, the sealing portion 30, and the like. Therefore, by providing the annular metal layer 32 on the outer edge of the piezoelectric substrate 10b where thermal stress tends to be concentrated, stress concentration on the piezoelectric substrate 10b can be suppressed, and deterioration of the piezoelectric substrate 10b can be suppressed.

  However, also in the comparative example 1, a crack may be introduced into the piezoelectric substrate 10 b. FIG. 3 is a schematic view of a cross-sectional SEM (Scanning Electron Microscope) image of Comparative Example 1. The supporting substrate 10a is a sapphire substrate, the piezoelectric substrate 10b is a lithium tantalate substrate, the annular metal layer 32 is copper, the lower layer 34a of the annular electrode 34 is titanium, the middle layer 34b is nickel, and the sealing portion 30 is tin silver. The upper layer 34c is a gold layer, but reacts with tin silver of the sealing portion 30 to form an alloy, and can not be confirmed by the SEM image.

  As shown in FIG. 3, a crack 60 is introduced from a region 70 where the side surface of the annular electrode 34 is in contact with the piezoelectric substrate 10 b to a region 72 of the interface between the piezoelectric substrate 10 b and the support substrate 10 a.

[Simulation of Comparative Example 1]
In the comparative example 1, it simulated about the location where stress concentrates. 4 (a) and 4 (b) are a plan view and a cross-sectional view of a simulated structure. As shown in FIG. 4A, a plurality of annular electrodes 34 are formed on the substrate 10. The substrate 20 is flip-chip mounted in each of the plurality of annular electrodes 34. Each annular electrode 34 and the substrate 20 are provided in the area 62 to be an electronic component. A plurality of regions 62 are arranged in the X direction and the Y direction. The X direction is the arrangement direction of the electrode fingers in FIG. Between the areas 62, there are provided cutting areas 64 to be cut when the electronic component is singulated.

  FIG.4 (b) is corresponded to the XX cross section and YY cross section in FIG. 4 (a). The simulation used a two-dimensional finite element method for the range of FIG. 4 (b). As shown in FIG. 4B, the range in which the simulation was performed is from the substrate 20 to the adjacent annular electrode 34 sandwiching the cutting region 64. The simulated range includes the through electrodes 16 and the bumps 28. In the simulation, it is assumed that the wiring 14 is not present.

Other simulation conditions are as follows.
Support substrate 10a: Sapphire substrate piezoelectric substrate 10b having a thickness of 100 μm: 42 ° rotated Y-cut X-propagation lithium tantalate substrate penetrating electrode 16 having a thickness of 20 μm: copper layer terminal 18 having a diameter of 40 μm: copper having a film thickness of 2 μm Layer and film thickness 5 μm nickel layer substrate 20: 150 μm thick silicon substrate bump 28: height 15 μm, diameter 80 μm gold bump annular metal layer 32: thickness 20 μm, width 67.5 μm copper Lower layer 34a of the layer annular electrode 34: titanium layer middle layer 34b having a film thickness of 100 nm: nickel layer upper layer 34c having a film thickness of 2500 nm: gold layer having a film thickness of 200 nm

表１に示すように、ＬＴおよびサファイアはヤング率が大きい、ＴｉおよびＮｉはＣｕおよびＡｕよりヤング率が大きい。サファイアはＬＴより線熱膨張係数が小さく、ＣｕはＬＴより線熱膨張係数が大きい。 Table 1 shows Young's modulus and linear thermal expansion coefficient of main materials. LT is lithium tantalate, and X and Y indicate the X-axis direction and the Y-axis direction of the crystal orientation.

As shown in Table 1, LT and sapphire have large Young's modulus, Ti and Ni have larger Young's modulus than Cu and Au. Sapphire has a smaller linear thermal expansion coefficient than LT, and Cu has a larger linear thermal expansion coefficient than LT.

  FIG. 5A and FIG. 5B are diagrams showing the stress in the XX cross section and the YY cross section. The direction of the arrow indicates the direction of stress, and the size of the arrow indicates the strength of stress. As shown in FIG. 5A, in the X-X cross section, stress in the X direction is applied near the piezoelectric substrate 10b in the support substrate 10a. Stress in the Z direction is applied to the piezoelectric substrate 10 b near the annular metal layer 32. As shown in FIG. 5B, the stress in the support substrate 10a is smaller than that in FIG. 5A in the Y-Y cross section. Stress in the Z direction is applied to the interface between the piezoelectric substrate 10 b and the annular metal layer 32.

  6 (a) is an enlarged view of the region A of FIG. 5 (a), and FIG. 6 (b) is a diagram showing the magnitude of stress in the piezoelectric substrate of FIG. 5 (a). As shown in FIG. 6A, in the region 66, stress in the X direction is applied in the support substrate 10a, and stress in the Z direction is applied in the piezoelectric substrate 10b. Stress is concentrated in this way. The area 72 of FIG. 3 is substantially at the same position as the area 66 of FIG. 6 (a). Thus, the crack 60 in FIG. 3 is considered to be the region 66 as a starting point.

In FIG. 6B, a region 68 is a region in which the magnitude of stress in the piezoelectric substrate 10b is 1.0 × 10 ⁻⁸ Pa or more. There is a large stress area in the Z direction near the annular metal layer 32. As shown in FIG. 3, stress is applied to the piezoelectric substrate 10b in a region 70 where the side surface of the annular electrode 34 is in contact with the piezoelectric substrate 10b. Therefore, it is considered that the crack 60 may be introduced into the area 70 of FIG. 3 through the area 68 of FIG. 6 (b) starting from the area 66 of FIG. 6 (a).

  In order to suppress concentration of stress on the piezoelectric substrate 10 b at the end of the annular electrode 34, it is also conceivable to position the end of the annular electrode 34 on the annular metal layer 32. However, in this case, when the annular metal layer 32 is exposed, contamination with copper or the like occurs. Further, in order to strengthen the bonding of the sealing portion 30 to the annular electrode 34, the width of the annular electrode 34 is preferably large. For the reasons described above, it is difficult to provide the end of the annular electrode 34 on the annular metal layer 32.

  Hereinafter, the Example which solves the problem of the comparative example 1 is described.

FIG. 7A is a cross-sectional view of the electronic component according to the first embodiment, and FIG. 7B is a plan view of the substrate 10. As shown in FIG. 7A, a protective film 35 is provided between the upper surfaces of the piezoelectric substrate 10b and the annular metal layer 32 and the annular electrode 34. The protective film 35 is, for example, an insulating film such as silicon oxide (SiO ₂ ). The protective film 35 overlaps the interface 74 at which the side surface of the annular metal layer 32 and the piezoelectric substrate 10 b are in contact with each other in plan view, and the side surface 76 of the annular electrode 34 on the functional element 12 side. The other configuration is the same as that of Comparative Example 1, and the description thereof is omitted.

  In FIG. 7B, the annular metal layer 32, the annular electrode 34 and the protective film 35 are illustrated. The interface 74 at which the piezoelectric substrate 10 b contacts the annular metal layer 32 is indicated by a broken line, and the inner side surface 76 of the annular electrode 34 is indicated by a dotted line. The outer end 35 a (contour or inner periphery) of the protective film 35 is located outside the interface 74, and the inner end 35 b (contour or outer periphery) of the protective film 35 is located inside the side 76 of the annular electrode 34. ing. Thus, the protective film 35 overlaps the interface 74 and the side surface 76 in plan view.

  The width W32 of the annular metal layer 32 is, for example, 50 μm to 65 μm. The width W 34 of the annular electrode 34 is, for example, 65 μm to 70 μm. The width W 35 of the protective film 35 is, for example, 75 μm to 100 μm. The distance L35a between the interface 74 and the end 35a is, for example, 25 μm to 50 μm. The distance L35b between the side surface 76 and the end 35b is, for example, 10 μm to 35 μm. The thickness of the piezoelectric substrate 10 b is, for example, 1 μm to 20 μm.

[Manufacturing Method of Example 1]
FIG. 8A to FIG. 9C are cross-sectional views showing a method of manufacturing an electronic component according to the first embodiment. As shown in FIG. 8A, the lower surface of the piezoelectric substrate 10b is bonded to the upper surface of the support substrate 10a. The support substrate 10a and the piezoelectric substrate 10b may be directly bonded via an amorphous layer of several nm or the like, or may be bonded by an adhesive or the like.

  As shown in FIG. 8B, the piezoelectric substrate 10b is removed by etching, for example, to form an opening 31. The through holes 15 are formed in the piezoelectric substrate 10b and the support substrate 10a by, for example, laser beam irradiation. At this time, the through hole 15 does not penetrate the support substrate 10a. The annular metal layer 32 is formed in the opening 31, and the through electrode 16 is formed in the through hole 15. The annular metal layer 32 and the through electrode 16 are, for example, copper layers, and are formed using a plating method. The upper surfaces of the piezoelectric substrate 10b, the through electrode 16, and the annular metal layer 32 are planarized using, for example, a CMP (Chemical Mechanical Polishing) method. The annular metal layer 32 and the through electrode 16 preferably have low electrical resistance and low thermal conductivity. From this viewpoint, the annular metal layer 32 and the through electrode 16 preferably contain copper as a main component.

  As shown in FIG. 8C, the functional element 12 and the wiring 14 are formed on the piezoelectric substrate 10b. A mask layer 50 having an opening 51 is formed on the substrate 10. The mask layer 50 is, for example, a photoresist. A protective film 35 is formed in the opening 51 and on the mask layer 50. The protective film 35 is a silicon oxide film, and is formed using, for example, a vacuum evaporation method.

  As shown in FIG. 8D, the mask layer 50 is removed. Thereby, the protective film 35 on the mask layer 50 is lifted off.

  As shown in FIG. 9A, an annular electrode 34 is formed on the protective film 35 and the annular metal layer 32. The annular electrode 34 is formed by, for example, a vacuum evaporation method and a lift-off method. The lower layer 34a, the middle layer 34b and the upper layer 34c of the annular electrode 34 are, for example, a titanium layer, a nickel layer and a gold layer.

  As shown in FIG. 9B, the device chip 21 is flip-chip mounted on the substrate 10 via the bumps 28. Thus, the functional elements 12 and 22 face each other with the air gap 26 therebetween.

  As shown in FIG. 9C, the sealing portion 30 made of, for example, tin-silver solder is formed so as to surround the device chip 21. The sealing portion 30 is joined to the upper layer 34 c of the annular electrode 34. A lid 36 is provided on the sealing portion 30 and the device chip 21. The upper surface of the device chip 21 may be covered with the sealing portion 30. The lid 36 may not be provided.

  Thereafter, the lower surface of the support substrate 10a is polished using a CMP method or the like. Thereby, the penetration electrode 16 is exposed to the lower surface of the support substrate 10a. A terminal 18 is formed in contact with the through electrode 16. The substrate 10 is cut at the cutting area 64. Thereby, the electronic component is singulated. A protective film 38 surrounding the sealing portion 30 and the lid 36 is formed. Thereby, the electronic component of FIG. 7 (a) and FIG.7 (b) is manufactured.

Modification of First Embodiment
FIGS. 10A and 10B are cross-sectional views of the electronic component according to the first and second modifications of the first embodiment. As shown in FIG. 10A, the protective film 35 is provided up to the outer periphery 77 of the annular metal layer 32. Thus, the annular metal layer 32 and the annular electrode 34 are not in contact with each other. Thus, the protective film 35 may completely cover the upper surface of the annular metal layer 32. The other configuration is the same as that of the first embodiment, and the description is omitted. In order to electrically connect the annular metal layer 32 and the annular electrode 34, it is preferable that the annular metal layer 32 and the annular electrode 34 be partially in contact as in the first embodiment.

  As shown in FIG. 10B, the inner end 78 of the protective film 35 overlaps the device chip 21 in plan view. As described above, the protective film 35 may extend just under the device chip 21. The other configuration is the same as that of the first embodiment, and the description is omitted. In order to prevent the protective film 35 from coming into contact with the wiring 14, it is preferable that the inner end 78 of the protective film 35 does not overlap the device chip 21 in plan view as in the first embodiment.

  FIG. 11 is a plan view of a substrate of the electronic component according to the third modification of the first embodiment. As shown in FIG. 11, the protective film 35 is provided on the side extending in the Y direction out of the interface 74 and the side surface 76 having a rectangular planar shape, and is not provided on the side extending in the X direction. As shown in Table 1, when the linear thermal expansion coefficient of the piezoelectric substrate 10b has crystal orientation dependency, as shown in FIG. 5A, stress is exerted in the direction in which the linear thermal expansion coefficient of the piezoelectric substrate 10b and the support substrate 10a is larger. Is easy to add. Therefore, the protective film 35 may be provided so as to overlap a part of the interface 74 and a part of the side surface 76 in plan view, and may not overlap the remaining part of the interface 74 and the remaining part of the side surface 76.

  12 (a) and 12 (b) are cross-sectional views of electronic parts according to Modifications 4 and 5 of Embodiment 1. FIG. As shown in FIG. 12A, a cover member 80 is bonded onto the annular electrode 34. As shown in FIG. The cover member 80 is, for example, a silicon cap. As shown in FIG. 12 (b), a lid 82 is provided on the annular electrode 84 as a cover member. The annular electrode 84 contains, for example, copper or solder. The lid 82 is a metal plate or an insulator plate. As in the fourth and fifth modifications of the first embodiment, the electronic component may not include the device chip.

[Effects of Embodiment 1 and its Modifications]
According to the first embodiment and its modification, the annular metal layer 32 (first metal layer) is provided on the support substrate 10a so as to surround the functional element 12, and the side surface is in contact with the side surface of the piezoelectric substrate 10b. The annular electrode 34 (second metal layer) is provided on the piezoelectric substrate 10 b and the annular metal layer 32 so as to overlap with the interface 74 at which the piezoelectric substrate 10 b and the annular metal layer 32 contact in plan view. In the first embodiment and the first to third modifications, the sealing portion 30, the device chip 21 and the lid 36 function as a cover member, and the sealing portion 30 is joined to the annular electrode 34 to seal the functional element 12 in the air gap 26. Do. In the fourth and fifth modified examples of the first embodiment, the cover member not including the device chip is joined to the annular electrode 34 or 84 to seal the functional element 12 in the air gap 26.

  In such an electronic component, as shown in FIG. 3, a crack 60 may be formed between the side surface of the annular electrode 34 and the piezoelectric substrate 10 b. Therefore, at least a portion of the side surface 76 on the functional element 12 side of the annular electrode 34 and at least a portion of the interface 74 between the piezoelectric substrate 10 b and the annular metal layer 32 and the annular electrode 34 in the protective film 35. To overlap with the Thereby, concentration of stress in the piezoelectric substrate 10 b on the side surface of the annular electrode 34 is suppressed. Therefore, the deterioration of the piezoelectric substrate 10b such as the introduction of a crack to the piezoelectric substrate 10b can be suppressed.

  When the interface 74 between the piezoelectric substrate 10 b and the annular metal layer 32 is inclined, the protective film 35 preferably overlaps at least a part of the interface 74 in plan view, and the upper surface of the piezoelectric substrate 10 b and the annular metal layer 32 It preferably overlaps the interface 74. When the annular electrode 34 is inclined, the protective film 35 preferably overlaps at least a part of the side surface 76 in plan view, and preferably overlaps the side surface 76 of the lower surface of the annular electrode 34.

  The Young's modulus of the protective film 35 is preferably smaller than that of the lower layer 34 a of the annular electrode 34 in contact with the protective film 35. Thereby, the stress at the end of the annular electrode 34 in the piezoelectric substrate 10 b can be relaxed. As the protective film, an insulating film such as a silicon oxide film or a metal film can be used.

  13 (a) is a cross-sectional view of the electronic component according to the second embodiment, and FIG. 13 (b) is an enlarged view of the vicinity of the air gap 37 of FIG. 13 (a). As shown in FIG. 13A, an air gap 37 is provided between the side surface of the piezoelectric substrate 10b and the side surface of the annular metal layer 32. The width W 37 of the air gap 37 is, for example, 100 nm, and preferably 10 μm to 200 μm. The other configuration is the same as in Comparative Example 1 and Example 1, and the description is omitted.

  14 (a) to 14 (d) are cross-sectional views showing a method of manufacturing an electronic component according to the second embodiment. As shown in FIG. 14A, the opening 31 is formed in the piezoelectric substrate 10b bonded to the support substrate 10a. As shown in FIG. 14B, the sacrificial layer 37a is formed in contact with the side surface of the piezoelectric substrate 10b in the opening 31. The sacrificial layer 37a is, for example, a silicon oxide film, and is formed using a vacuum evaporation method and a lift-off method. As shown in FIG. 14C, through holes 15 are formed in the piezoelectric substrate 10b and the support substrate 10a. The through electrode 16 is formed in the through hole 15, and the annular metal layer 32 is formed in the opening 31. The upper surfaces of the piezoelectric substrate 10b, the through electrode 16, the annular metal layer 32, and the sacrificial layer 37a are planarized using a CMP method or the like. As shown in FIG. 14D, the sacrificial layer 37 a is removed to form a void 37. Thereafter, the processes of FIG. 8 (d) to FIG. 9 (c) of the first embodiment are performed.

[Effect of Example 2]
According to the second embodiment, at least a part of the side surface of the annular metal layer 32 opposes at least a part of the side surface of the piezoelectric substrate 10b with the air gap 37 (first air gap) interposed therebetween. As a result, concentration of stress in the region 66 (see FIG. 6A) can be suppressed. Therefore, the introduction of the crack 60 starting from the region 66 can be suppressed.

  As in the third modification of the first embodiment, the air gap 37 may be provided on the side of the interface 74 extending in the Y direction and may not be provided on the side extending in the X direction. As in the fourth and fifth modifications of the first embodiment, the cover member may not include the device chip. As in the first embodiment, the protective film 35 may be provided and the air gap 37 may be provided.

  By making the linear thermal expansion coefficient of the support substrate 10a smaller than the linear thermal expansion coefficient of the piezoelectric substrate 10b, the frequency temperature characteristic of the functional element 12 can be suppressed. However, as in Comparative Example 1, the crack 60 is easily introduced to the piezoelectric substrate 10 b. Therefore, the crack 60 and the like can be suppressed by providing the protective film 35 and / or the air gap 37 as in the first and second embodiments.

  The annular metal layer 32 may not be in contact with the support substrate 10a. When the annular metal layer 32 is in contact with the support substrate 10a, stress tends to be concentrated on the region 66 as shown in FIG. 6A. Therefore, as in Comparative Example 1, the crack 60 is easily introduced to the piezoelectric substrate 10 b. Therefore, the crack 60 and the like can be suppressed by providing the protective film 35 and / or the air gap 37 as in the first and second embodiments.

  When the annular metal layer 32 is in contact with the support substrate 10 a and the thicknesses of the annular metal layer 32 and the piezoelectric substrate 10 b are substantially the same, stress is likely to be concentrated in the region 66. Therefore, the protective film 35 and / or the air gap 37 is provided. Thereby, the crack 60 etc. of the piezoelectric substrate 10b can be suppressed.

  When the piezoelectric substrate 10 b is a lithium tantalate substrate or a lithium niobate substrate, the piezoelectric substrate 10 b is brittle and a crack is easily introduced. Therefore, the protective film 35 and / or the air gap 37 is provided. Thereby, the crack 60 etc. of the piezoelectric substrate 10b can be suppressed.

  When the annular metal layer 32 contains copper as a main component, the provision of the annular metal layer 32 can reduce the electrical resistance and the thermal resistance of the annular metal layer 32. Thus, the heat dissipation efficiency of the electronic component is increased. However, a crack is easily introduced into the piezoelectric substrate 10b. Therefore, the protective film 35 and / or the air gap 37 is provided. Thereby, the crack 60 etc. of the piezoelectric substrate 10b can be suppressed.

  As in the first and second embodiments, the cover member has the device chip 21 facing the functional element 12 with the air gap 26 therebetween. The cover member has a sealing portion 30 (a metal sealing portion having a melting point lower than the melting points of the annular metal layer 32 and the annular electrode 34) made of solder which surrounds the device chip 21 and is joined to the annular electrode 34. In such a case, the annular electrode 34 includes a barrier layer. Since the barrier layer is made of metal having a high Young's modulus, stress is likely to be concentrated in the piezoelectric substrate 10 b at the end of the annular electrode 34. Furthermore, the Young's modulus of the alloy formed by the gold and solder of the upper layer 34c of the annular electrode 34 is high. Therefore, it is preferable to provide the protective film 35 and / or the air gap 37.

  Although the elastic wave element has been described as an example of the functional elements 12 and 22, the functional element 22 may be a passive element such as an inductor or a capacitor, an active element including a transistor, or a MEMS (Micro Electro Mechanical Systems) element.

  The functional elements 12 and 22 may each form an elastic wave filter. The functional elements 12 and 22 may form a multiplexer such as a duplexer, triplexer or quadplexer.

  As mentioned above, although the embodiment of the present invention has been described in detail, the present invention is not limited to such a specific embodiment, and various modifications may be made within the scope of the subject matter of the present invention described in the claims. Changes are possible.

10, 20 substrate 10a support substrate 10b piezoelectric substrate 12, 22 functional element 21 device chip 30 sealing portion 32 annular metal layer 34 annular electrode 36 lid 74 interface 76 side surface

Claims (10)

A supporting substrate,
A piezoelectric substrate bonded onto the support substrate;
A functional element provided on the piezoelectric substrate;
A first metal layer provided on the support substrate so as to surround the functional element, the side surface being in contact with the side surface of the piezoelectric substrate;
A second metal layer provided on the piezoelectric substrate and the first metal layer so as to overlap an interface at which the piezoelectric substrate and the first metal layer are in contact with each other in plan view;
Between the piezoelectric substrate and the first metal layer and the second metal layer, at least a portion of the side surface of the second metal layer on the functional element side and at least a portion of the interface in plan view A protective film provided,
A cover member provided so as to bond to the second metal layer and seal the functional element in an air gap;
Electronic components comprising   The electronic component according to claim 1, wherein a Young's modulus of the protective film is smaller than a Young's modulus of a layer in contact with the protective film among the second metal layers. A supporting substrate,
A piezoelectric substrate bonded onto the support substrate;
A functional element provided on the piezoelectric substrate;
A first metal layer provided on the support substrate so as to surround the functional element, at least a portion of the side surface of the piezoelectric substrate facing the at least a portion of the side surface of the piezoelectric substrate and facing the first gap;
A second metal layer provided on the first metal layer so as to surround the functional element;
A cover member provided so as to bond to the second metal layer and seal the functional element in a second air gap;
Electronic components comprising   The electronic component according to any one of claims 1 to 3, wherein a linear thermal expansion coefficient of the support substrate is smaller than a linear thermal expansion coefficient of the piezoelectric substrate.   The electronic component according to any one of claims 1 to 4, wherein the first metal layer and the support substrate are in contact with each other.   The electronic component according to claim 5, wherein a thickness of the first metal layer and a thickness of the piezoelectric substrate are substantially the same.   The electronic component according to any one of claims 1 to 6, wherein the piezoelectric substrate is a lithium tantalate substrate or a lithium niobate substrate.   The electronic component according to claim 7, wherein the first metal layer contains copper as a main component.   The electronic component according to any one of claims 1 to 8, wherein the cover member has a device chip opposed to the functional element via an air gap.   10. The electronic component according to claim 9, wherein the cover member encloses the device chip and is joined to the second metal layer, and has a metal sealing portion having a melting point lower than the melting points of the first metal layer and the second metal layer. .

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