JP2019040943A - Multilayer ceramic capacitor - Google Patents

Abstract

To provide a multilayer ceramic capacitor in which solder crack does not occur at the mounting part, while restraining crack of the multilayer ceramic capacitor, especially in mounting under high temperature environment.SOLUTION: A multilayer ceramic capacitor 10 includes a laminate 12 formed by laminating multiple dielectric layers 14 and multiple internal electrode layers 16, and a pair of external electrodes 24a, 24b formed on both end faces 12e, 12f of the laminate 12 so as to be connected electrically with the internal electrode layers 16. Each of the external electrodes 24a, 24b has a base electrode layer 26, a conductive resin layer 28 placed on the surface of the base electrode layer 26, and containing thermosetting resin and a metal composition, a Cu plating layer 30 placed on the surface of the conductive resin layer 28, and a metal layer 32 placed on the surface of the Cu plating layer 30. The Cu plating layer has a thickness of 4.56-37.31 μm.SELECTED DRAWING: Figure 4

Description

  The present invention relates to a multilayer ceramic capacitor, and more particularly to a multilayer ceramic capacitor provided with an external electrode having a multilayer structure.

In recent years, a ceramic electronic component represented by a multilayer ceramic capacitor has been used in a harsh environment as compared to the conventional case.
For example, multilayer ceramic capacitors used in mobile devices such as mobile phones and portable music players are required to withstand impacts such as dropping. Specifically, it is necessary that the multilayer ceramic capacitor does not fall off from the mounting substrate even when subjected to an impact such as dropping, and does not cause a crack. In addition, multilayer ceramic capacitors used for in-vehicle devices such as ECUs are required to withstand impacts such as thermal cycles. Specifically, multilayer ceramic capacitors need to be free from cracks even when subjected to thermal stress and bending stress generated by linear expansion / contraction of the mounting board or tensile stress applied to external electrodes. is there.

  For the purpose of meeting the above requirements, a multilayer ceramic capacitor having an external electrode including a thermosetting resin layer is known. In Patent Document 1, an epoxy thermosetting resin layer is formed between a conventional electrode layer and Ni plating, and measures are taken to prevent cracks in the capacitor body (laminate) even under harsh environments. (Improved deflection resistance).

  In the structure of the multilayer ceramic capacitor shown in Patent Document 1, when a stress due to an impact at the time of dropping or a bending stress generated due to thermal expansion / contraction of the mounting substrate due to a thermal cycle is generated, the stress transmitted to the mounting substrate The stress is released by peeling the (mounting substrate distortion) between the electrode layer and the epoxy thermosetting resin layer with the tip of the epoxy thermosetting resin layer as the starting point, and there is a crack in the capacitor body of the multilayer ceramic capacitor. I try not to enter.

Japanese Patent Laid-Open No. 11-162771

  However, in the structure of the multilayer ceramic capacitor as in Patent Document 1, the capacitor body is cracked due to the stress due to the impact at the time of dropping or the flexural stress generated by the thermal expansion / contraction of the mounting substrate in response to the thermal cycle. However, when used in a high temperature environment, the difference in the linear expansion coefficient between the multilayer ceramic capacitor and the mounting board becomes significant. Mechanical failure sometimes occurred. In particular, when solder is used as a mounting material, mechanical breakdown (solder cracks) easily occurs inside the solder or at the joint interface between the solder and the adherend, and the solder cracks cause deterioration of the conductivity of the external electrode. In addition, the adhesion force between the external electrode and the mounting substrate is reduced, which is a problem for mounting the multilayer ceramic capacitor in a high temperature environment.

  Therefore, a main object of the present invention is to provide a multilayer ceramic capacitor that suppresses cracks in the multilayer ceramic capacitor and does not cause solder cracks in the mounting portion, particularly in mounting in a high temperature environment.

A multilayer ceramic capacitor according to the present invention includes a plurality of stacked dielectric layers and a stacked internal electrode layer, and is orthogonal to the first and second main surfaces opposite to the stacking direction. A laminated body including a first side face and a second side face opposed to the width direction, and a first end face and a second end face opposed to the length direction perpendicular to the lamination direction and the width direction, and an internal electrode In a multilayer ceramic capacitor having a pair of external electrodes disposed on the end face and on the first and second main faces, and a pair of external electrodes arranged on the first and second side faces, connected to the layer, Each of the external electrodes includes a base electrode layer containing a conductive metal and a glass component, a conductive resin layer containing a thermosetting resin and a metal component disposed on the surface of the base electrode layer, and a surface of the conductive resin layer Cu plating layer disposed on A metal layer disposed on the surface of the Cu plating layer, the thickness of the Cu plating layer is not less than 4.56μm 37.31μm less, a laminated ceramic capacitor.
In the multilayer ceramic capacitor according to the present invention, the metal layer is preferably a Ni plating layer and a Sn plating layer disposed on the surface of the Ni plating layer.

In the multilayer ceramic capacitor according to the present invention, since the thickness of the Cu plating layer is not less than 4.56 μm and not more than 37.31 μm, the material of the linear expansion coefficient between the multilayer ceramic capacitor and the glass epoxy substrate during reflow mounting is a resin electrode. By being present on the surface without being mechanically bonded to the multilayer ceramic capacitor, the stress due to the difference in linear expansion coefficient during reflow can be relieved and the residual stress after mounting can be reduced. Therefore, it is possible to suppress the occurrence of solder cracks caused by the sum of the linear expansion coefficient difference and the residual stress during the thermal shock cycle.
In addition, the conductive resin layer and the metal layer are formed by forming a metal plating in the base electrode layer and a Cu plating layer compatible with the Ni plating between the conductive resin layer and the Ni plating layer as the metal layer. Can be reduced (that is, the conductivity of the entire external electrode can be improved), and the ESR can be lowered.
Further, in the multilayer ceramic capacitor according to the present invention, when a plated layer made of Ni plating is provided in the metal layer, when mounting the multilayer ceramic capacitor, the ground electrode layer and the conductive resin layer are formed by solder used for mounting. It can be prevented from being eroded. Moreover, when a plated layer made of Sn plating is further provided on the surface of the plated layer made of Ni, when mounting a multilayer ceramic capacitor, the wettability of the solder used for mounting is improved and mounting is easy. Can do.

  According to the present invention, it is possible to provide a multilayer ceramic capacitor in which solder cracks do not occur in the mounting portion while suppressing cracks in the multilayer ceramic capacitor, particularly in mounting in a high temperature environment.

  The above-described object, other objects, features, and advantages of the present invention will become more apparent from the following description of embodiments for carrying out the invention with reference to the drawings.

1 is an external perspective view showing a multilayer ceramic capacitor according to an embodiment of the present invention. It is sectional drawing in the II-II line of FIG. 1 which shows the laminated ceramic capacitor which concerns on one embodiment of this invention. FIG. 3 is a cross-sectional view taken along line III-III in FIG. 1 showing a multilayer ceramic capacitor according to an embodiment of the present invention. FIG. 3 is an enlarged view of an external electrode and its vicinity in the cross-sectional view of FIG.

1. Multilayer Ceramic Capacitor A multilayer ceramic capacitor according to the present invention will be described. FIG. 1 is an external perspective view showing a multilayer ceramic capacitor according to an embodiment of the present invention. 2 is a cross-sectional view taken along the line II-II of FIG. 1 showing a multilayer ceramic capacitor according to one embodiment of the present invention, and FIG. 3 is a diagram showing the multilayer ceramic capacitor according to one embodiment of the present invention. 3 is a cross section taken along line III-III in FIG. 4 is an enlarged view of the external electrode and its vicinity in the cross-sectional view of FIG. 2 showing the multilayer ceramic capacitor according to one embodiment of the present invention.

  As shown in FIGS. 1 to 3, the multilayer ceramic capacitor 10 includes a rectangular parallelepiped multilayer body 12.

  The stacked body 12 includes a plurality of dielectric layers 14 and a plurality of internal electrode layers 16 that are stacked. Furthermore, the laminate 12 includes a first main surface 12a and a second main surface 12b that are opposed to the lamination direction x, and a first side surface 12c and a second side surface that are opposed to the width direction y orthogonal to the lamination direction x. 12d, and a first end surface 12e and a second end surface 12f that are opposed to a length direction z orthogonal to the stacking direction x and the width direction y. The laminated body 12 has rounded corners and ridges. In addition, a corner | angular part is a part where three adjacent surfaces of a laminated body cross, and a ridgeline part is a part where two adjacent surfaces of a laminated body intersect. Further, unevenness or the like is formed on part or all of the first main surface 12a and the second main surface 12b, the first side surface 12c and the second side surface 12d, and the first end surface 12e and the second end surface 12f. May be.

  The dielectric layer 14 of the stacked body 12 includes an outer layer portion 14a and an inner layer portion 14b. The outer layer portion 14a is located on the first main surface 12a side and the second main surface 12b side of the laminate 12, and is formed between the first main surface 12a and the internal electrode layer 16 closest to the first main surface 12a. The dielectric layer 14 is located between the second main surface 12b and the internal electrode layer 16 closest to the second main surface 12b. The region sandwiched between both outer layer portions 14a is the inner layer portion 14b. The outer layer portion 14a preferably has a thickness of 50 μm or more and 300 μm or less.

  The number of dielectric layers 14 to be laminated is not particularly limited, but is preferably 15 or more and 200 or less including the outer layer portion 14a.

  Although the dimension of the laminated body 12 is not specifically limited, The dimension of the length direction z is 1.5 mm or more and 5.6 mm or less, The dimension of the width direction y is 0.7 mm or more and 4.9 mm or less, The dimension of the lamination direction x Is preferably 0.7 mm or more and 2.9 mm or less.

The dielectric layer 14 can be formed of a dielectric material, for example. As such a dielectric material, for example, a dielectric ceramic containing a main component such as BaTiO ₃ , CaTiO ₃ , SrTiO ₃ , or CaZrO ₃ can be used. When the above-described dielectric material is included as a main component, depending on the desired characteristics of the laminated body 12, for example, a secondary material having a lower content than the main component such as an Mn compound, Fe compound, Cr compound, Co compound, or Ni compound. You may use what added the component.

  The thickness of the dielectric layer 14 after firing is preferably 0.5 μm or more and 20 μm or less.

  The multilayer body 12 includes, as the plurality of internal electrode layers 16, for example, a plurality of first internal electrode layers 16a and a plurality of second internal electrode layers 16b each having a substantially rectangular shape. The plurality of first internal electrode layers 16 a and the plurality of second internal electrode layers 16 b are embedded so as to be alternately arranged at equal intervals along the stacking direction x of the stacked body 12 with the dielectric layers 14 interposed therebetween. ing.

The first internal electrode layer 16a is located on one end side of the first internal electrode layer 16a and the first counter electrode portion 18a facing the second internal electrode layer 16b, and from the first counter electrode portion 18a. It has the 1st extraction electrode part 20a to the 1st end surface 12e of the laminated body 12. As shown in FIG. The end portion of the first extraction electrode portion 20a is drawn out to the first end surface 12e and exposed.
The second internal electrode layer 16b is located on one end side of the second counter electrode portion 18b facing the first internal electrode layer 16a and the second internal electrode layer 16b, and from the second counter electrode portion 18b. It has the 2nd extraction electrode part 20b to the 2nd end surface 12f of the laminated body 12. As shown in FIG. The end portion of the second extraction electrode portion 20b is drawn out to the second end face 12f and exposed.

  The stacked body 12 includes a first counter electrode portion 18a and a second counter electrode portion between one end in the width direction y of the first counter electrode portion 18a and the second counter electrode portion 18b and the first side surface 12c, and the first counter electrode portion 18a and the second counter electrode portion. The side part (henceforth "W gap") 22a of the laminated body 12 formed between the other end of the width direction y of 18b, and the 2nd side surface 12d is included. Further, the multilayer body 12 includes the second internal surface of the second internal electrode layer 16b between the end of the first internal electrode layer 16a opposite to the first extraction electrode portion 20a and the second end surface 12f. It includes an end portion (hereinafter referred to as “L gap”) 22b of the laminated body 12 formed between the end portion on the opposite side to the extraction electrode portion 20b and the first end face 12e.

  The internal electrode layer 16 can be made of an appropriate conductive material such as a metal such as Ni, Cu, Ag, Pd, or Au, or an alloy containing at least one of these metals such as an Ag—Pd alloy. . The internal electrode layer 16 may further include dielectric particles having the same composition as the ceramics included in the dielectric layer 14.

  The thickness of the internal electrode layer 16 is preferably 0.2 μm or more and 2.0 μm or less. The number of internal electrode layers 16 is preferably 15 or more and 200 or less.

External electrodes 24 are disposed on the first end surface 12 e side and the second end surface 12 f side of the multilayer body 12. The external electrode 24 includes a first external electrode 24a and a second external electrode 24b.
The first external electrode 24a is disposed on the surface of the first end surface 12e of the multilayer body 12, and extends from the first end surface 12e to form the first main surface 12a, the second main surface 12b, and the first side surface. 12c and second side surface 12d are formed so as to cover each part. In this case, the first external electrode 24a is electrically connected to the first extraction electrode portion 20a of the first internal electrode layer 16a.
The second external electrode 24b is disposed on the surface of the second end surface 12f of the multilayer body 12, and extends from the second end surface 12f to the first main surface 12a, the second main surface 12b, and the first side surface. 12c and second side surface 12d are formed so as to cover each part. In this case, the second external electrode 24b is electrically connected to the second extraction electrode portion 20b of the second internal electrode layer 16b.

  In the stacked body 12, the first counter electrode portion 18a of the first internal electrode layer 16a and the second counter electrode portion 18b of the second internal electrode layer 16b are opposed to each other with the dielectric layer 14 therebetween. Thus, a capacitance is formed. Therefore, a capacitance can be obtained between the first external electrode 24a to which the first internal electrode layer 16a is connected and the second external electrode 24b to which the second internal electrode layer 16b is connected. The characteristics of the capacitor are manifested.

  The first external electrode 24a and the second external electrode 24b include a base electrode layer 26 containing a conductive metal and a glass component, a conductive resin layer 28 containing a thermosetting resin and a metal component, and a Cu plating layer 30. And a metal layer 32.

The base electrode layer 26 includes a first base electrode layer 26a and a second base electrode layer 26b.
The first base electrode layer 26a is disposed on the surface of the first end surface 12e of the multilayer body 12, and extends from the first end surface 12e to form the first main surface 12a, the second main surface 12b, and the first main surface 12e. It is formed so as to cover a part of each of the side surface 12c and the second side surface 12d.
The second base electrode layer 26b is disposed on the surface of the second end surface 12f of the multilayer body 12, and extends from the second end surface 12f to extend the first main surface 12a, the second main surface 12b, and the second main surface 12b. The first side face 12c and the second side face 12d are formed so as to cover a part thereof.
The first base electrode layer 26a may be disposed only on the surface of the first end face 12e of the multilayer body 12, and the second base electrode layer 26b may be disposed on the second end face 12f of the multilayer body 12. It may be arranged only on the surface.

  The base electrode layer 26 includes a conductive metal and a glass component. The metal of the base electrode layer 26 includes, for example, at least one selected from Cu, Ni, Ag, Pd, Ag—Pd alloy, Au, and the like. Further, the glass of the base electrode layer 26 includes at least one selected from B, Si, Ba, Mg, Al, Li, and the like. The base electrode layer 26 may be a plurality of layers. The base electrode layer 26 is obtained by applying and baking a conductive paste containing glass and metal on the laminate 12, and may be fired simultaneously with the dielectric layer 14 and the internal electrode layer 16. The internal electrode layer 16 may be baked after being baked. The thickness of the thickest portion of the base electrode layer 26 is preferably 10 μm or more and 150 μm or less.

  The base electrode layer 26 located on the first end face 12e and the second end face 12f has a shape with a thicker central part than the other parts. As a result, the contact angle of the solder to the plating on the external electrode 24 becomes an acute angle, and the component of the stress applied from the solder to the plating during the thermal shock cycle is parallel to the plating plane. An effect of reducing the occurrence probability can be obtained. The thickness of the external electrode 24 on the first main surface 12a and the second main surface 12b of the base electrode layer 26 and on the first side surface 12c and the second side surface 12f is preferably 5 μm or more and 20 μm or less. .

The conductive resin layer 28 includes a first conductive resin layer 28a and a second conductive resin layer 28b.
The first conductive resin layer 28a is disposed so as to cover the first base electrode layer 26a. Specifically, the first conductive resin layer 28a is disposed on the first end surface 12e on the surface of the first base electrode layer 26a, and the first main surface 12a on the surface of the first base electrode layer 26a. It is preferable that the second main surface 12b and the first side surface 12c and the second side surface 12d are also provided. The first conductive resin layer 28a may be disposed only on the surface of the first base electrode layer 26a disposed on the first end surface 12e, or the first conductive resin layer 28a disposed on the first end surface 12e. Covers the surface of the base electrode layer 26a, the first main surface 12a and the second main surface 12b, and part of the surface of the first base electrode layer 26a disposed on the first side surface 12c and the second side surface 12d. It may be arranged as follows.
Similarly, the second conductive resin layer 28b is disposed so as to cover the second base electrode layer 26b. Specifically, the second conductive resin layer 28b is disposed on the second end face 12f on the surface of the second base electrode layer 26b, and the first main surface 12a on the surface of the second base electrode layer 26b. It is preferable that the second main surface 12b and the first side surface 12c and the second side surface 12d are also provided. The second conductive resin layer 28b may be disposed only on the surface of the second base electrode layer 26b disposed on the second end surface 12f, or the second conductive resin layer 28b disposed on the second end surface 12f. A part of the surface of the base electrode layer 26b, the first main surface 12a and the second main surface 12b, and the surface of the second conductive resin layer 28b disposed on the first side surface 12c and the second side surface 12d You may arrange | position so that it may cover.

  The thickness of the conductive resin layer 28 is preferably 10 μm or more and 200 μm or less, for example. The conductive resin layer 28 includes a thermosetting resin and a metal component. Since the conductive resin layer 28 contains a thermosetting resin, it is more flexible than the base electrode layer 26 made of a fired product of a plating film or a conductive paste, for example. For this reason, even when a physical impact or an impact due to a thermal cycle is applied to the multilayer ceramic capacitor 10, the conductive resin layer 28 functions as a buffer layer and prevents cracks in the multilayer ceramic capacitor 10. be able to.

  As specific examples of the thermosetting resin contained in the conductive resin layer 28, various known thermosetting resins such as an epoxy resin, a phenol resin, a urethane resin, a silicone resin, and a polyimide resin can be used. . Among them, an epoxy resin excellent in heat resistance, moisture resistance, adhesion and the like is one of the most appropriate resins. The conductive resin layer 28 preferably contains a curing agent together with the thermosetting resin. As the curing agent, when an epoxy resin is used as the base resin, various known compounds such as phenol, amine, acid anhydride, and imidazole can be used as the curing agent for the epoxy resin.

  As the metal contained in the conductive resin layer 28, Ag, Cu, or an alloy thereof can be used. Moreover, what coated Ag on the surface of metal powder can be used. When using the surface of the metal powder coated with Ag, it is preferable to use Cu or Ni as the metal powder. Moreover, what gave the antioxidant process to Cu can also be used. The reason for using the Ag-coated metal is that it is possible to make the metal of the base material inexpensive while maintaining the above Ag characteristics.

  The metal contained in the conductive resin layer 28 is preferably contained in an amount of 35 vol% or more and 75 vol% or less with respect to the volume of the entire conductive resin. The metal contained in the conductive resin layer 28 is contained as a conductive filler (metal powder). The shape of the conductive filler is not particularly limited. The conductive filler may be spherical, flat or the like, but it is preferable to use a mixture of spherical metal powder and flat metal powder. The average particle diameter of the conductive filler contained in the conductive resin layer 28 may be, for example, 0.3 μm or more and 10.0 μm, but is not particularly limited. The conductive filler contained in the conductive resin layer 28 is mainly responsible for the conductivity of the conductive resin layer 28. Specifically, a conductive path is formed inside the conductive resin layer 28 by contact between the conductive fillers. The tip of the conductive resin 28 is preferably formed to extend from the tip of the base electrode layer 26 to 50 μm or more and 800 μm or less. Thereby, a sufficient area of the resin electrode layer for reducing the stress during the thermal shock cycle can be taken, and a solder crack mitigating effect can be obtained.

The Cu plating layer 30 includes a first Cu plating layer 30a and a second Cu plating layer 30b.
The first Cu plating layer 30a is disposed so as to cover the first conductive resin layer 28a. Specifically, the first Cu plating layer 30a is disposed on the surface of the first conductive resin layer 28a located on the first end surface 12e, and the first main surface 12a and the second main surface 12b. In addition, it is preferably provided so as to reach the surface of the first conductive resin layer 28a located on the first side surface 12c and the second side surface 12d. The first Cu plating layer 30a may be disposed only on the surface of the first conductive resin layer 28a disposed on the first end surface 12e, or the first Cu plating layer 30a disposed on the first end surface 12e. A part of the surface of the conductive resin layer 28a, the first main surface 12a and the second main surface 12b, and the surface of the first conductive resin layer 28a disposed on the first side surface 12c and the second side surface 12d. It may be arranged so as to cover. In this case, the first Cu plating layer 30a may also be disposed on the surface of the portion of the first base electrode layer 26a that is not covered with the first conductive resin layer 28a.
Similarly, the second Cu plating layer 30b is disposed so as to cover the second conductive resin layer 28b. Specifically, the second Cu plating layer 30b is disposed on the surface of the second conductive resin layer 28b located on the second end surface 12f, and the first main surface 12a and the second main surface 12b. In addition, it is preferable to be provided so as to reach the surface of the second conductive resin layer 28b located on the first side surface 12c and the second side surface 12d. The second Cu plating layer 30b may be disposed only on the surface of the second conductive resin layer 28b disposed on the second end surface 12f, or the second Cu plating layer 30b disposed on the second end surface 12f. A part of the surface of the conductive resin layer 28b and the surface of the first main surface 12a and the second main surface 12b and the surface of the second conductive resin layer 28b disposed on the first side surface 12c and the second side surface 12d. It may be arranged so as to cover. In this case, the second Cu plating layer 30b may also be disposed on the surface of the second base electrode layer 26b in a portion not covered with the second conductive resin layer 28b.

  The Cu plating layer 30 is made of Cu. The Cu plating layer 30 may be formed of a plurality of layers, but is preferably formed of a single layer. The thickness of the Cu plating layer 30 is not less than 4.56 μm and not more than 37.31 μm.

The metal layer 32 includes a first metal layer 32a and a second metal layer 32b.
The first metal layer 32a is disposed so as to cover the first Cu plating layer 30a. Specifically, the first metal layer 32a is disposed on the surface of the first Cu plating layer 30a located on the first end surface 12e, and the first main surface 12a, the second main surface 12b, and the first It is preferable that the first Cu plating layer 30a is provided so as to reach the surface of the first side face 12c and the second side face 12d.
Similarly, the second metal layer 32b is disposed so as to cover the second Cu plating layer 30b. Specifically, the second metal layer 32b is disposed on the surface of the second Cu plating layer 30b located on the second end surface 12f, and the first main surface 12a, the second main surface 12b, and the second It is preferable to be provided so as to reach the surface of the second Cu plating layer 30b located on the first side surface 12c and the second side surface 12d.

  The metal layer 32 is preferably formed of a plurality of layers. Specifically, the first metal layer 32a is preferably a first Ni plating layer and a first Sn plating layer disposed on the surface of the first Ni plating layer. Similarly, the second metal layer 32b is preferably a second Ni plating layer and a second Sn plating layer disposed on the surface of the second Ni plating layer.

The multilayer ceramic capacitor 10 including the multilayer body 12, the first external electrode 24a, and the second external electrode 24b has a dimension L in the length direction z, and the multilayer body 12, the first external electrode 24a, and the second external electrode. The dimension in the stacking direction x of the multilayer ceramic capacitor 10 including the electrode 24b is T, and the dimension in the width direction y of the multilayer ceramic capacitor 10 including the multilayer body 12, the first external electrode 24a, and the second external electrode 24b is W. Dimension.
The dimensions of the multilayer ceramic capacitor 10 are such that the L dimension in the length direction z is 1.6 mm to 5.7 mm, the W dimension in the width direction y is 0.8 mm to 5.0 mm, and the T dimension in the stack direction x is 0.00. It is 8 mm or more and 3.0 mm or less.

In the multilayer ceramic capacitor 10 shown in FIG. 1, the thickness of the Cu plating layer 30 is 4.56 μm or more and 37.31 μm or less. As a result, a material having a linear expansion coefficient intermediate between the multilayer ceramic capacitor 10 and the glass epoxy substrate at the time of reflow mounting exists without being mechanically joined to the multilayer ceramic capacitor 10 on the surface of the resin electrode. Residual stress after mounting can be reduced by relieving stress due to the difference in expansion coefficient. Therefore, it is possible to suppress the occurrence of solder cracks caused by the sum of the linear expansion coefficient difference and the residual stress during the thermal shock cycle.
Also, a conductive resin layer is formed between the conductive resin layer 28 and the Ni plating layer that is the metal layer 32 by forming a Cu plating layer compatible with the metal powder and Ni plating in the base electrode layer 26. The contact resistance between 28 and the metal layer 32 can be reduced (that is, the conductivity of the entire external electrode 24 can be improved), and the ESR can be lowered.

  The multilayer ceramic capacitor 10 shown in FIG. 1 is provided with a plating layer made of Ni plating in the metal layer 32, so that when the multilayer ceramic capacitor is mounted, the ground electrode layer 26 and the conductive resin layer are formed by solder used for mounting. 28 can be prevented from being eroded. In addition, by providing a plating layer made of Sn plating on the surface of the plating layer made of Ni plating, when mounting a multilayer ceramic capacitor, the wettability of solder used for mounting is improved and mounting is easy. Can do.

2. 1. Manufacturing Method for Multilayer Ceramic Capacitor Next, an embodiment of a manufacturing method for a multilayer ceramic capacitor having the above-described configuration will be described using the manufacturing method for the multilayer ceramic capacitor 10 shown in FIG. 1 as an example.

  First, a ceramic green sheet, an internal electrode conductive paste for forming the internal electrode layer 16 and an external electrode conductive paste for forming the base electrode layer 26 of the external electrode 24 are prepared. The ceramic green sheet, the internal electrode conductive paste, and the external electrode conductive paste include an organic binder and a solvent, and a known organic binder or organic solvent can be used.

  Then, for example, the internal electrode conductive paste is printed in a predetermined pattern on the ceramic green sheet, and the internal electrode pattern is formed on the ceramic green sheet. Note that the conductive paste for the internal electrode can be printed by a known method such as a screen printing method or a gravure printing method.

  Next, a predetermined number of outer layer ceramic green sheets on which the internal electrode pattern is not printed are laminated, on which ceramic green sheets on which the internal electrode pattern is printed are sequentially laminated, and on the outer layer ceramic green sheets A predetermined number of sheets are laminated to produce a mother laminate. If necessary, this mother laminate may be pressure-bonded in the lamination direction x by means such as an isostatic press.

  Thereafter, the mother laminate is cut into a predetermined shape and a raw laminate chip is cut out. At this time, the corners and ridges of the laminate may be rounded by barrel polishing or the like. Subsequently, the cut raw laminate chip is fired to produce a laminate. The firing temperature of the raw laminate chip depends on the ceramic material and the material of the internal electrode conductive paste, but is preferably 900 ° C. or higher and 1300 ° C. or lower.

  Next, the base electrode layer 26 is formed. First, a conductive paste for external electrodes is applied to both end faces of the fired laminate, and baked to form a first base electrode layer 26a of the first external electrode 24a and a second base electrode of the second external electrode 24b. Layer 26b is formed. The baking temperature is preferably 700 ° C. or higher and 900 ° C. or lower.

Subsequently, the conductive resin layer 28 is formed. First, a conductive paste containing a metal component and a thermosetting resin is applied so as to cover the first base electrode layer 26a to form a first conductive resin layer 28a. Similarly, the second base electrode A conductive paste containing a metal component and a thermosetting resin is applied so as to cover the layer 26b, and the second conductive resin layer 28b is formed. The application of the conductive paste is performed by performing a heat treatment at a temperature of 250 ° C. or more and 550 ° C. or less to thermally cure the resin. The atmosphere during the heat treatment is preferably an N ₂ atmosphere. Further, in order to prevent the resin from scattering and to prevent oxidation of various metal components, the oxygen concentration is preferably suppressed to 100 ppm or less.

  Next, the Cu plating layer 30 is formed. First, the first Cu plating layer 30a is formed so as to cover the first conductive resin layer 28a, and similarly, the second Cu plating layer 30b is formed so as to cover the second conductive resin 28b. Is done. The Cu plating layer 30 can be formed by an electrolytic plating method or an electroless plating method. The thickness of the Cu plating layer 30 can be adjusted by controlling the current value and the plating time. Specifically, it is preferable to process by adjusting the plating current value x plating time with respect to the plating formation area.

  Subsequently, the metal layer 32 is formed. First, the first metal layer 32a is formed so as to cover the first Cu plating layer 30a, and similarly, the second metal layer 32b is formed so as to cover the second Cu plating layer 30b. The metal layer 32 is formed by two structures, for example, a Ni plating layer and a Sn plating layer.

  The multilayer ceramic capacitor 10 is manufactured as described above.

3. Experimental Example Next, for the multilayer ceramic capacitor 10 obtained by the above-described method, after preparing a sample in which the thickness of the Cu plating layer was changed, a thermal shock cycle test, a fixing force confirmation test, and a substrate bending resistance test were performed. went.

  According to the method for manufacturing a multilayer ceramic capacitor described above, samples of the multilayer ceramic capacitors of Sample 1 to Sample 9 having different specifications of the thickness of the Cu plating layer and having the specifications described below were prepared. In this experimental example, the Cu plating layer was formed by an electrolytic plating method.

Each example is a multilayer ceramic capacitor having the following specifications.
・ Size (design value) of multilayer ceramic capacitor: length x width x height = 3.2 mm x 2.5 mm x 2.5 mm
-Dielectric layer material: BaTiO ₃
・ Capacitance: 10μF
・ Rated voltage: 25V
・ Material of internal electrode: Ni
・ Structure of external electrode Base electrode layer Material of base electrode layer: Conductive metal (Cu)
The thickness of the base electrode layer: 65 μm (the thickest part at the center of the end face)
Conductive resin layer Conductive filler (metal powder): Ag
Resin: Epoxy thermosetting temperature: approx. 200 ° C
Conductive resin layer thickness: 50 μm (the thickest part at the center of the end face)
Cu plating layer: Refer to Table 1 for thickness Metal layer: Ni plating layer and two-layer structure in which Sn plating layer is arranged on the surface Thickness of Ni plating layer: 5.0 μm
Sn plating layer thickness: 5.0 μm

  For comparison, a multilayer ceramic capacitor of Sample 10 having no Cu plating layer was produced. The structure of the external electrode of the sample 10 includes a metal layer having a two-layer structure in which a conductive resin layer is formed on the base electrode layer, and a Ni plating layer and a Sn plating layer are disposed on the surface thereof. That is, the specifications of the multilayer ceramic capacitor of Sample 10 are the same as Samples 1 to 9 except for the structure of the external electrodes.

(1) Measuring method of thickness of Cu plating layer Using the X-ray film thickness meter, the thickness of the Cu plating layer of the end face center part thickness in the sample of each sample of a multilayer ceramic capacitor was measured. Each of the first end face side and the second end face side was measured and taken as the average of one sample. The number of samples for each sample was n = 10. And it measured with respect to the sample number n = 10 of each sample, respectively, and the average value of the measured value is shown in Table 1.

(2) Thermal shock cycle test A multilayer ceramic capacitor as a sample of each sample was mounted on a JIS substrate (glass epoxy substrate) using LF solder. And as a condition of the thermal shock cycle test by the air tank type thermal shock tester, the substrate used for the test is held for 30 minutes in a low temperature environment of −55 ° C., and then held for 30 minutes in an environment of 125 ° C. did. This was defined as one cycle, and 2000 cycles were alternately performed at a low temperature and a high temperature. Each sample was subjected to cross-sectional polishing from the side surface direction of the multilayer ceramic capacitor sample to ½ of the chip width in the substrate mounted state after the thermal shock cycle test. Thereafter, samples with a progress rate of 50% or more were counted when the completely broken state from the solder crack prediction path was taken as 100%. The cross section was confirmed on the first end face side and the second end face side of the sample, and the side with the long solder crack was used for measurement. The number of samples of each sample was set to n = 40, and samples having a progress rate of 50% or more and less than 10 samples were judged to be good samples.

(3) Adhesive strength confirmation test A multilayer ceramic capacitor as a sample of each sample was mounted on a JIS substrate (glass epoxy substrate) using LF solder. After mounting, the sample was pushed from the side into the center of the side of the sample using a push bull gauge, and the breaking strength when it broke was measured. After mounting, the thermal shock cycle test was not performed and after mounting, the thermal shock cycle test described above was performed at each n = 10, and each average value of n = 10 was calculated. Deterioration rate of adhesion force limit value = (Adhesion force of sample subjected to thermal shock cycle test after mounting) − (Adhesion force of sample not subjected to thermal shock cycle test after mounting) / (Performed thermal shock cycle test after mounting) The sticking force of the sample not to be calculated). -30% or more was judged to be a good sample.

(3) Substrate bending resistance test A sample of a multilayer ceramic capacitor was mounted on a JIS substrate (glass epoxy substrate) having a thickness of 1.6 mm using solder. The substrate was bent from the unmounted substrate surface with a pressing jig and subjected to mechanical stress. At this time, the holding time was 5 seconds, and the bending amount was 5 mm. After the substrate was bent, the multilayer ceramic capacitor sample was removed from the substrate, polished in a direction perpendicular to the substrate surface, cracks were observed, and the number of cracked samples in each sample was counted. The number of samples for each sample was n = 15.

  Table 1 shows the results of the measurement of the Cu plating layer thickness, the result of the thermal shock cycle test, the result of the adhesion strength confirmation test, and the result of the substrate bending resistance test for each sample of the multilayer ceramic capacitor.

As shown in Table 1, in Samples 3 to 8, the thickness of the Cu plating layer is 4.56 μm or more and 37.31 μm, and as a result of the thermal shock cycle test, the progress rate of solder cracks is 50% or more. All of the samples are good with less than 10 samples, the results of the adhesion confirmation test and the solder crack growth rate of all the samples are -30% or more, and the results of the substrate bending resistance test are Since no crack was generated in any of the samples, good results were obtained.
Thus, by having a specific Cu plating layer between the surface of the conductive resin layer and the metal layer, the residual resulting from the difference in linear expansion coefficient between the mounting substrate and the multilayer ceramic capacitor that occurs during reflow mounting The stress can be relaxed, and the occurrence of solder cracks when mounting the multilayer ceramic capacitor can be suppressed. Moreover, it was suggested that the fall of the adhering force is also suppressed.

  On the other hand, as shown in Table 1, in Sample 1 and Sample 2, the thickness of the Cu plating layer is less than 4.56 μm, and in Sample 10, since the Cu plating layer is not formed, as a result of the thermal shock cycle test, For any sample, the number of samples with a solder crack progress rate of 50% or more was 10 or more, and the results of the adhesion strength confirmation test were also less than -30% for all samples. . In sample 9, since the thickness of the Cu plating layer was 48.82 μm, cracks occurred in 6 out of 15 samples as a result of the substrate bending resistance test. This is because if the thickness of the Cu plating layer is thin, the difference in coefficient of linear expansion during mounting cannot be sufficiently relaxed. Therefore, a solder crack with a large progress rate occurs in many samples, and the thickness of the Cu plating layer is thick. If it is too much, the stress is concentrated at the tip of the Cu plating layer before the stress is relaxed in the conductive resin tank, and it is considered that a crack has occurred.

  In addition, this invention is not limited to the said embodiment, A various deformation | transformation is carried out within the range of the summary.

DESCRIPTION OF SYMBOLS 10 Multilayer ceramic capacitor 12 Laminated body 12a 1st main surface 12b 2nd main surface 12c 1st side surface 12d 2nd side surface 12e 1st end surface 12f 2nd end surface 14 Dielectric layer 14a Outer layer part 14b Inner layer part 16 Internal electrode layer 16a 1st internal electrode layer 16b 2nd internal electrode layer 18a 1st counter electrode part 18b 2nd counter electrode part 20a 1st extraction electrode part 20b 2nd extraction electrode part 22a Side part (W gap)
22b End (L gap)
24 external electrode 24a first external electrode 24b second external electrode 26 base electrode layer 26a first base electrode layer 26b second base electrode layer 28 conductive resin layer 28a first conductive resin layer 28b second Conductive resin layer 30 Cu plating layer 30a First Cu plating layer 30b Second Cu plating layer 32 Metal layer 32a First metal layer 32b Second metal layer x stacking direction y width direction z length direction

Claims (2)

A plurality of laminated dielectric layers and a laminated internal electrode layer; a first main surface and a second main surface opposite to the lamination direction; and a first opposite to the width direction perpendicular to the lamination direction. A laminate including a side surface and a second side surface, and a first end surface and a second end surface that face each other in a length direction orthogonal to the stacking direction and the width direction;
A pair of external electrodes disposed on the end surface and on the first and second main surfaces, and on the first and second side surfaces, connected to the internal electrode layer;
In a multilayer ceramic capacitor having
Each of the pair of external electrodes is
A base electrode layer containing a conductive metal and a glass component, a thermosetting resin and a conductive resin layer containing a metal component disposed on the surface of the base electrode layer, and a Cu disposed on the surface of the conductive resin layer A plating layer, and a metal layer disposed on the surface of the Cu plating layer,
A multilayer ceramic capacitor, wherein the Cu plating layer has a thickness of 4.56 μm to 37.31 μm.   The multilayer ceramic capacitor according to claim 1, wherein the metal layer is a Ni plating layer and a Sn plating layer disposed on a surface of the Ni plating layer.

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