JP2019040073A - Electro-optical device and electronic apparatus - Google Patents

Abstract

An electro-optical device and an electronic apparatus capable of suppressing light from being incident on a semiconductor layer of a pixel transistor from a substrate body side of an element substrate while suppressing an electrical influence from a scanning line to the pixel transistor. To provide. In an element substrate 10 of an electro-optical device, a light shielding shield wiring 2a to which a constant potential is applied is provided between a scanning line 3a and a semiconductor layer 1a of a pixel transistor 30, and the shield wiring 2a is provided. A constant potential is applied to. Therefore, even if the shield wiring 2a and the scanning line 3a are brought close to the semiconductor layer 1a, the pixel transistor 30 is hardly affected electrically, so that it enters the semiconductor layer 1a from the first substrate 19 side of the element substrate 10. It is possible to effectively block the light to be tried. The shield wiring 2a extends in a direction intersecting the scanning line 3a. [Selection] Figure 6

Description

The present invention relates to an electro-optical device provided with a light shielding layer for a pixel transistor on an element substrate, and an electronic apparatus.

In an electro-optical device (liquid crystal device) used as a light valve of a projection display device, strong light from a light source is irradiated. For this reason, when light from the light source enters from the element substrate side and enters the semiconductor layer of the pixel transistor, the pixel transistor may cause a malfunction due to the photocurrent. Also, even when light from the light source is incident from the counter substrate side,
When stray light or return light enters the semiconductor layer of the pixel transistor from the substrate body side of the element substrate,
There is a possibility that the pixel transistor may malfunction due to photocurrent. Therefore, a structure has been proposed in which a scanning line of a light shielding layer is provided between the substrate body of the element substrate and the semiconductor layer so as to overlap the semiconductor layer in a plan view, and the scanning line prevents light from entering the semiconductor layer. (See Patent Document 1).

JP 2014-119529 A

In order to increase the light shielding effect of the scanning line on the semiconductor layer of the pixel transistor, it is necessary to bring the scanning line close to the semiconductor layer. In this case, the scanning signal supplied through the scanning line has an electrical influence on the pixel transistor. There is a problem of affecting.

In view of the above problems, an object of the present invention is to suppress the incidence of light from the substrate body side of the element substrate to the semiconductor layer of the pixel transistor while suppressing the electrical influence from the scanning line to the pixel transistor. It is an object of the present invention to provide an electro-optical device and an electronic apparatus.

In order to solve the above-described problem, an aspect of the electro-optical device according to the present invention includes an element substrate having a pixel electrode provided on one side of a first substrate, and the element substrate of a second substrate facing the element substrate. A counter substrate provided with a common electrode on the side surface, and an electro-optic layer provided between the element substrate and the counter substrate, wherein the element substrate includes the first substrate and the pixel electrode. A pixel layer provided between the first substrate and the semiconductor layer, and a semiconductor transistor provided between the first substrate and the semiconductor layer, and a pixel transistor provided with a gate electrode provided on the pixel electrode side with respect to the semiconductor layer. One insulating layer, a second insulating layer provided between the first insulating layer and the semiconductor layer, and provided between the first substrate and the first insulating layer, the first insulating layer and The gate power is connected through a contact hole that penetrates the second insulating layer. A light shielding shield wiring to which a constant potential is applied and is provided so as to overlap the semiconductor layer in a plan view between the scanning line electrically connected to the semiconductor layer and the first insulating layer and the second insulating layer It is characterized by having.

In the present invention, since a light-shielding shield wiring to which a constant potential is applied is provided between the scanning line and the semiconductor layer of the pixel transistor, the semiconductor layer is formed from the first substrate (substrate body) side of the element substrate. The light that is about to enter the light can be blocked by the shield wiring. Further, if the shield wiring is applied with a constant potential, even if it is close to the semiconductor layer, the pixel transistor is hardly affected. Therefore, the light that attempts to enter the semiconductor layer from the first substrate side of the element substrate can be effectively blocked by the shield wiring while suppressing the electrical influence from the scanning line to the pixel transistor.

In the present invention, it is possible to adopt a mode in which the scanning line has a light shielding property and is provided so as to overlap the semiconductor layer in plan view. In the present invention, since the shield wiring is interposed between the scanning line and the semiconductor layer, the scanning line is brought close to the semiconductor layer, and the light to be incident on the semiconductor layer from the first substrate side of the element substrate is scanned. Even if it is blocked by, the electrical influence from the scanning line to the pixel transistor can be suppressed.

In the present invention, it is possible to adopt a mode in which the shield wiring extends in a direction crossing the scanning line. According to this aspect, the light that is about to enter the semiconductor layer obliquely from the extending direction of the shield wiring can be blocked by the shield wiring, and the light is about to enter the semiconductor layer obliquely from the extending direction of the scanning line. Light can be blocked by scanning lines.

In the present invention, the semiconductor layer has a channel length direction in a direction intersecting the scanning line, and the contact hole is provided at a position spaced from the semiconductor layer in the channel width direction. Can be adopted. According to this aspect, it is easy to extend the shield wiring in a region that does not overlap with the contact hole.

In the present invention, the constant potential is a ground potential, a common potential applied to the common electrode,
Alternatively, a mode in which the potential is low for a driving circuit can be employed. Since such a potential is more used in electro-optical devices, it is not necessary to separately prepare a constant potential to be supplied to the shield wiring.

The electro-optical device according to the invention is used in various electronic apparatuses. In the present invention, when an electro-optical device is used as a projection display device among electronic devices, the projection display device is modulated by a light source unit that emits light supplied to the electro-optical device and the electro-optical device. A projection optical system for projecting light.

1 is a plan view of an electro-optical device to which the present invention is applied. FIG. 2 is a cross-sectional view of the electro-optical device shown in FIG. 1. FIG. 2 is a plan view of a plurality of adjacent pixels in the electro-optical device shown in FIG. 1. FIG. 2 is a cross-sectional view of the electro-optical device shown in FIG. 1 taken along the line FF ′. FIG. 4 is a plan view showing a layout of a scanning line, a semiconductor layer, a gate electrode, a contact hole, and a shield wiring among the components shown in FIG. 3. FIG. 6 is an explanatory diagram showing a three-dimensional positional relationship among a scanning line, a semiconductor layer, a gate electrode, a contact hole, and a shield wiring shown in FIG. 5. 1 is a schematic configuration diagram of a projection display device (electronic device) using an electro-optical device to which the present invention is applied.

Embodiments of the present invention will be described with reference to the drawings. In the drawings to be referred to in the following description, the scales are different for each layer and each member so that each layer and each member have a size that can be recognized on the drawing. In the following description, when describing the layers formed on the element substrate, the upper layer side or the surface side is opposite to the side where the substrate is located (the side where the counter substrate is located).
The lower layer side means the side on which the substrate is located.

(Configuration of electro-optical device)
FIG. 1 is a plan view of an electro-optical device 100 to which the present invention is applied. FIG. 2 is a cross-sectional view of the electro-optical device 100 shown in FIG. As shown in FIGS. 1 and 2, in the electro-optical device 100, the element substrate 10 and the counter substrate 20 are bonded to each other with a sealant 107 through a predetermined gap, and the element substrate 10 and the counter substrate 20 face each other. doing. The sealing material 107 is provided in a frame shape along the outer edge of the counter substrate 20, and an electro-optical layer 80 such as a liquid crystal layer is provided in a region surrounded by the sealing material 107 between the element substrate 10 and the counter substrate 20. Has been placed. Accordingly, the electro-optical device 100 is configured as a liquid crystal device. The sealing material 107 is a photo-curing adhesive or a photo-curing and thermo-curing adhesive, such as glass fiber or glass beads for setting the distance between both substrates to a predetermined value. Gap material is blended. The element substrate 10 and the counter substrate 20 are both square, and a display area 10 a is provided as a square area in the approximate center of the electro-optical device 100. Corresponding to this shape, the sealing material 107 is also provided in a substantially square shape, and a rectangular frame-shaped peripheral region 10b is provided between the inner peripheral edge of the sealing material 107 and the outer peripheral edge of the display region 10a.

The element substrate 10 includes a light-transmitting first substrate 19 such as a quartz substrate or a glass substrate as a substrate body. On the one surface 19s side of the first substrate 19 on the counter substrate 20 side, the display region 10a
The data line driving circuit 101 and the plurality of terminals 10 are arranged along one side of the element substrate 10 on the outer side.
2 is formed, and the scanning line driving circuit 104 is formed along another side adjacent to the one side. A flexible wiring substrate (not shown) is connected to the terminal 102, and the element substrate 1
Various potentials and various signals are input to 0 through the flexible wiring board.

In addition, on one surface 19s of the first substrate 19, the display region 10a has an ITO (Indi
a plurality of translucent pixel electrodes 9a made of a um Tin Oxide) film and the like, and pixel transistors (not shown in FIG. 2) electrically connected to each of the plurality of pixel electrodes 9a are formed in a matrix. Yes. A first alignment film 16 is formed on the counter substrate 20 side with respect to the pixel electrode 9 a, and the pixel electrode 9 a is covered with the first alignment film 16.

The counter substrate 20 has a translucent second substrate 29 such as a quartz substrate or a glass substrate as a substrate body. On the one surface 29 s side of the second substrate 29 facing the element substrate 10, the ITO
A translucent common electrode 21 made of a film or the like is formed, and the element substrate 1 is formed with respect to the common electrode 21.
A second alignment film 26 is formed on the 0 side. The common electrode 21 is formed on substantially the entire surface of the second substrate 29 and is covered with the second alignment film 26. On the one surface 29 s side of the second substrate 29, a light-shielding light-shielding layer 27 made of resin, metal, or metal compound is formed on the opposite side of the common electrode 21 from the element substrate 10. A translucent protective layer 28 is formed between the electrodes 21. The light shielding layer 27 is formed, for example, as a frame-shaped parting line 27a extending along the outer peripheral edge of the display region 10a. The light shielding layer 27 is also formed as a light shielding layer 27b in a region overlapping a region sandwiched between adjacent pixel electrodes 9a in plan view. In the present embodiment, a dummy pixel electrode 9b that is formed simultaneously with the pixel electrode 9a is formed in the dummy pixel region 10c that overlaps the parting 27a in a plan view in the peripheral region 10b of the element substrate 10.

The first alignment film 16 and the second alignment film 26 are made of SiO _x (x <2), SiO ₂ , TiO ₂ ,
An inorganic alignment film (vertical alignment film) made of an obliquely deposited film of MgO, Al ₂ O ₃ or the like, and liquid crystal molecules having negative dielectric anisotropy used for the electro-optic layer 80 are inclined and aligned. . For this reason, the liquid crystal molecules form a predetermined angle with respect to the element substrate 10 and the counter substrate 20. In this manner, the electro-optical device 100 is configured as a VA (Vertical Alignment) mode liquid crystal device.

In the element substrate 10, an inter-substrate conduction electrode 1 for establishing electrical continuity between the element substrate 10 and the counter substrate 20 in a region overlapping the corner portion of the counter substrate 20 outside the sealing material 107.
09 is formed. The inter-substrate conducting electrode 109 includes an inter-substrate conducting material 1 containing conductive particles.
09a is disposed, and the common electrode 21 of the counter substrate 20 is electrically connected to the element substrate 10 side via the inter-substrate conducting material 109a and the inter-substrate conducting electrode 109. For this reason, a common potential is applied to the common electrode 21 from the element substrate 10 side.

In the present embodiment, the element substrate 10 has, for example, a common potential Vcom via a terminal 102a.
Is supplied, the ground potential GND is supplied via the terminal 102b, the high potential Vdd for the driving circuit is supplied via the terminal 102c, and the low potential Vs for the driving circuit is supplied via the terminal 102d.
s is supplied.

In the electro-optical device 100 of the present embodiment, the pixel electrode 9a and the common electrode 21 are formed of an ITO film (
The electro-optical device 100 is configured as a transmissive liquid crystal device. In the electro-optical device 100, light incident on the electro-optical layer 80 from one of the element substrate 10 and the counter substrate 20 is modulated while being transmitted through the other substrate and emitted to display an image. To do. In this embodiment, as indicated by an arrow L, the light incident from the counter substrate 20 is modulated for each pixel by the electro-optical layer 80 while being transmitted through the element substrate 10 and emitted to display an image.

(Specific pixel configuration)
FIG. 3 is a plan view of a plurality of adjacent pixels in the electro-optical device 100 shown in FIG.
FIG. 4 is a cross-sectional view of the electro-optical device 100 shown in FIG. In addition, in FIG. 3 and FIG. 5 mentioned later, each layer is represented by the following lines. Further, in FIG. 3, the positions of the end portions of the layers where the end portions overlap each other in plan view are shifted so that the shape of the layer can be easily understood.
Lower layer side light shielding layer 8a (scanning line 3a) and gate electrode 3b = thick solid line Semiconductor layer 1a = thin and short dotted line Shield wiring 2a = thick two-dot chain line Drain electrode 4a = thin solid line Data line 6a and relay electrode 6b = one thin point Chain line Capacitance line 5a = Thick one-dot chain line Upper layer side light-shielding layer 7a and relay electrode 7b = Thin two-dot chain line Pixel electrode 9a = Thick broken line

As shown in FIG. 3, a pixel electrode 9a is formed in each of a plurality of pixels on the surface of the element substrate 10 facing the counter substrate 20, and along the inter-pixel region sandwiched between adjacent pixel electrodes 9a. Thus, the data line 6a and the scanning line 3a are formed. The inter-pixel region extends vertically and horizontally, the scanning line 3a extends linearly along the first inter-pixel region extending in the X direction, and the data line 6a extends in the Y direction. Extends linearly along the second inter-pixel region. A pixel transistor 30 is formed corresponding to the intersection of the data line 6a and the scanning line 3a. In this embodiment, the pixel transistor 30 includes the data line 6a and the scanning line 3a.
It is formed using the intersection region with a and its vicinity. The element substrate 10 has a capacitance line 5a.
And a common potential Vcom is applied to the capacitor line 5a. Capacity line 5
a is formed in a lattice shape extending so as to overlap the scanning line 3a and the data line 6a.
An upper light shielding layer 7a is formed on the upper layer side of the pixel transistor 30, and the upper light shielding layer 7a extends so as to overlap the data line 6a and the scanning line 3a. A lower layer side light shielding layer 8a is formed on the lower layer side of the pixel transistor 30, and the lower layer side light shielding layer 8a is formed.
Are used as scanning lines 3a.

As shown in FIG. 4, in the element substrate 10, a translucent first insulating layer 11 made of a silicon oxide film or the like is formed on the one surface 19 s side of the first substrate 19, and an upper layer of the first insulating layer 11. On the side, a translucent second insulating layer 12 made of a silicon oxide film or the like is laminated. First substrate 19 and first
A lower side light shielding layer 8 a is formed between the insulating layer 11. The lower side light shielding layer 8a is made of a light shielding film such as tungsten silicide (WSi), tungsten, titanium nitride or the like. The lower-side light shielding layer 8a is configured as a scanning line 3a, and is electrically connected to the gate electrode 3b through a contact hole 12a described later. A shield wiring 2 a described later is formed between the first insulating layer 11 and the second insulating layer 12.

On the upper layer side of the second insulating layer 12, a pixel transistor 30 including the semiconductor layer 1a is formed. The pixel transistor 30 includes a semiconductor layer 1a having a long side direction in the extending direction of the data line 6a, and a direction perpendicular to the length direction of the semiconductor layer 1a on the upper side of the semiconductor layer 1a (scanning line 3
a gate electrode 3b extending in the extending direction of a) and overlapping the central portion in the length direction of the semiconductor layer 1a. The pixel transistor 30 includes a translucent gate insulating layer 32 between the semiconductor layer 1a and the gate electrode 3b. The semiconductor layer 1a includes a channel region 1g facing the gate electrode 3b via the gate insulating layer 32, and includes a source region 1b and a drain region 1c on both sides of the channel region 1g. The pixel transistor 30 has an LDD structure. Therefore, each of the source region 1b and the drain region 1c includes a low concentration region on both sides of the channel region 1g, and includes a high concentration region in a region adjacent to the low concentration region on the opposite side to the channel region 1g.

The semiconductor layer 1a is composed of a polysilicon film (polycrystalline silicon film) or the like. The gate insulating layer 32 includes a first gate insulating layer 32a made of a silicon oxide film obtained by thermally oxidizing the semiconductor layer 1a, and a second gate insulating layer 3 made of a silicon oxide film formed by a low pressure CVD method or the like.
It consists of a two-layer structure with 2b. The gate electrode 3b is made of a conductive film such as a conductive polysilicon film, a metal silicide film, a metal film, or a metal compound film, and penetrates the gate insulating layer 32, the second insulating layer 12, and the first insulating layer 11. It is electrically connected to the scanning line 3a through a contact hole 12a that reaches the scanning line 3a.

A translucent interlayer insulating film 41 made of a silicon oxide film or the like is formed on the upper layer side of the gate electrode 3b, and a drain electrode 4a is formed on the upper layer of the interlayer insulating film 41. Drain electrode 4
a is made of a conductive film such as a conductive polysilicon film, a metal silicide film, a metal film, or a metal compound film. The drain electrode 4a is formed so as to partially overlap the drain region 1c of the semiconductor layer 1a, and is electrically connected to the drain region 1c through a contact hole 41a penetrating the interlayer insulating film 41 and the gate insulating layer 32. .

A translucent etching stopper layer 49 made of a silicon oxide film or the like and a translucent dielectric layer 40 are formed on the upper layer side of the drain electrode 4a, and a capacitance is formed on the upper layer side of the dielectric layer 40. A line 5a is formed. As the dielectric layer 40, a silicon compound such as a silicon oxide film or a silicon nitride film can be used, and an aluminum oxide film, a titanium oxide film, a tantalum oxide film, a niobium oxide film, a hafnium oxide film, a lanthanum oxide film, zirconium A dielectric layer having a high dielectric constant such as an oxide film can be used. The capacitor line 5a is made of a conductive film such as a conductive polysilicon film, a metal silicide film, a metal film, or a metal compound film. Capacitance line 5a
Is overlapped with the drain electrode 4 a via the dielectric layer 40, and constitutes a storage capacitor 55.

A translucent interlayer insulating film 42 made of a silicon oxide film or the like is formed on the upper layer side of the capacitor line 5a. On the upper layer side of the interlayer insulating film 42, the data line 6a and the relay electrode 6b are the same. The conductive film is formed. The data line 6a and the relay electrode 6b are made of a conductive film such as a conductive polysilicon film, a metal silicide film, a metal film, or a metal compound film. Data line 6
a is electrically connected to the source region 1b through a contact hole 42a penetrating the interlayer insulating film 42, the etching stopper layer 49, the interlayer insulating film 41, and the gate insulating layer 32. The relay electrode 6 b is electrically connected to the drain electrode 4 a through a contact hole 42 b that penetrates the interlayer insulating film 42 and the etching stopper layer 49.

A light-transmitting interlayer insulating film 44 made of a silicon oxide film or the like is formed on the upper side of the data line 6a and the relay electrode 6b. On the upper layer side of the interlayer insulating film 44, the upper-layer light shielding layer 7a and the relay are formed. The electrode 7b is formed of the same conductive film. The surface of the interlayer insulating film 44 is planarized. The upper-side light shielding layer 7a and the relay electrode 7b are made of a conductive film such as a conductive polysilicon film, a metal silicide film, a metal film, or a metal compound film. The relay electrode 7 b is electrically connected to the relay electrode 6 b through a contact hole 44 a that penetrates the interlayer insulating film 44. The upper light shielding layer 7a extends so as to overlap the data line 6a and functions as a light shielding layer. The upper light shielding layer 7a may be electrically connected to the capacitor line 5a and used as a shield layer.

A translucent interlayer insulating film 45 made of a silicon oxide film or the like is formed on the upper layer side light shielding layer 7a and the relay electrode 7b, and an upper layer side of the interlayer insulating film 45 is made of an ITO film or the like. A pixel electrode 9a is formed. A contact hole 45a reaching the relay electrode 7b is formed in the interlayer insulating film 45, and the pixel electrode 9a is electrically connected to the relay electrode 7b through the contact hole 45a. As a result, the pixel electrode 9a is connected to the relay electrode 7b,
It is electrically connected to the drain region 1c through the relay electrode 6b and the drain electrode 4a. The surface of the interlayer insulating film 45 is planarized. A translucent first alignment film 16 made of polyimide or an inorganic alignment film is formed on the surface side of the pixel electrode 9a.

(Light shielding structure for the semiconductor layer 1a)
FIG. 5 is a plan view showing a layout of the scanning line 3a, the semiconductor layer 1a, the gate electrode 3b, the contact hole 12a, and the shield wiring 2a among the components shown in FIG. FIG.
Is a scanning line 3a, a semiconductor layer 1a, a gate electrode 3b, a contact hole 12a, shown in FIG.
It is explanatory drawing which shows the three-dimensional positional relationship of shield wiring 2a.

As described with reference to FIGS. 3 and 4, in the element substrate 10, the pixel transistor 30 is provided between the first substrate 19 and the pixel electrode 9a.
A semiconductor layer 1a and a gate electrode 3b provided on the pixel electrode 9a side with respect to the semiconductor layer 1a are provided. The element substrate 10 is provided with a first insulating layer 11 between the first substrate 19 and the semiconductor layer 1a, and a second insulating layer 12 is provided between the first insulating layer 11 and the semiconductor layer 1a. It has been. A scanning line 3a is provided between the first substrate 19 and the first insulating layer 11, and the scanning line 3a is formed so as to overlap the semiconductor layer 1a in plan view.

In this embodiment, as shown in FIG. 4, the shield wiring 2a is formed between the first insulating layer 11 and the second insulating layer 12 so as to overlap the semiconductor layer 1a in plan view. Therefore, the shield wiring 2a is interposed between the scanning line 3a and the semiconductor layer 1a. The shield wiring 2a is made of tungsten silicide, tungsten, titanium nitride or the like and has a light shielding property. The shield wiring 2a is connected to a ground potential G from a wiring (not shown) outside the display area 10a shown in FIG.
A constant potential such as ND, common potential Vcom, or low potential Vss for the drive circuit is applied.

Here, the scanning line 3a and the gate electrode 3b pass through the gate insulating layer 32, the second insulating layer 12, and the first insulating layer 11 through the contact hole 12a that reaches the scanning line 3a. Since it is electrically connected, the shield wiring 2a is connected to the first insulating layer 11 and the second
The insulating layer 12 extends in a direction not overlapping the contact hole 12a.

More specifically, as shown in FIG. 5 and FIG. 6, the semiconductor layer 1a has a channel length direction (a direction connecting the source region 1b and the drain region 1c) in a direction intersecting the scanning line 3a. The contact hole 12a is provided at a position separated from the semiconductor layer 1a in the channel width direction (direction intersecting the channel length direction). In this embodiment, the contact holes 12a are provided at two positions sandwiching the semiconductor layer 1a in the channel width direction, and the two contact holes 12a are separated in the extending direction of the scanning line 3a. Therefore, shield wiring 2
a extends between the two contact holes 12a in a direction intersecting the extending direction of the scanning line 3a.

(Main effects of this form)
As described above, in the electro-optical device 100 of this embodiment, the light-shielding shield wiring 2a to which a constant potential is applied is provided between the scanning line 3a and the semiconductor layer 1a of the pixel transistor 30. Light that is about to enter the semiconductor layer 1a from the first substrate 19 (substrate body) side of the element substrate 10 can be blocked by the shield wiring 2a. That is, when the light source light enters from the counter substrate 20 side, stray light and return light try to enter the semiconductor layer 1 a of the pixel transistor 30 from the first substrate 19 side of the element substrate 10. It can be blocked by the shield wiring 2a. Therefore, it is possible to prevent the pixel transistor 30 from malfunctioning due to the photocurrent.

Further, if the shield wiring 2a is applied with a constant potential, even if it is close to the semiconductor layer 1a,
It is difficult for the pixel transistor 30 to have an electrical influence. Therefore, it is possible to effectively block light that is about to enter the semiconductor layer 1a from the first substrate 19 side by the shield wiring 2a while suppressing an electrical influence from the scanning line 3a to the pixel transistor 30. .

In addition, since the scanning line 3a is provided so as to overlap the semiconductor layer 1a in plan view, the scanning line 3a also blocks light that is about to enter the semiconductor layer 1a from the first substrate 19 side of the element substrate 10. be able to. Here, since the shield wiring 2a is interposed between the scanning line 3a and the semiconductor layer 1a, the light to be incident on the semiconductor layer 1a from the first substrate 19 side with the scanning line 3a being close to the semiconductor layer 1a. Even when this is blocked by the scanning line 3a, the electrical influence from the scanning line 3a to the pixel transistor 30 can be suppressed.

The shield wiring 2a extends in a direction intersecting with the scanning line 3a. For this reason, the light that is about to enter the semiconductor layer 1a obliquely from the extending direction of the shield wiring 2a can be blocked by the shield wiring 2a, and the light is incident on the semiconductor layer 1a obliquely from the extending direction of the scanning line 3a. Can be blocked by the scanning line 3a. Therefore, the first substrate 1 of the element substrate 10
The light which is going to enter into the semiconductor layer 1a from the 9 side can be effectively blocked.

The semiconductor layer 1a has a channel length direction in a direction intersecting the scanning line 3a, and the contact hole 12a is separated from the semiconductor layer 1a in the channel width direction (extending direction of the scanning line 3a). It is provided in the position to do. For this reason, by extending the shield wiring 2a in a direction intersecting the scanning line 3a, it is easy to extend the shield wiring 2a in a region that does not overlap the contact hole 12a.

The constant potential applied to the shield wiring 2a is the ground potential GND or the common potential V.
com, or the low potential Vss for the drive circuit, and if it is such a potential, the electro-optical device 1
Even 00 is more used. Therefore, there is no need to separately prepare a constant potential to be supplied to the shield wiring 2a.

[Other Embodiments]
In the above embodiment, the shield wiring 2a extends in the direction intersecting with the scanning line 3a. However, the shield wiring 2a may extend along the scanning line 3a. For example, when the semiconductor layer 1a has the channel length direction in the extending direction of the scanning line 3a, the contact hole 12a is provided at a position spaced from the semiconductor layer 1a in the channel width direction (direction intersecting the scanning line 3a). It is done. Therefore, if the shield wiring 2a extends in the direction along the scanning line 3a, the shield wiring 2
It can be easily avoided that a overlaps with the contact hole 12a.

In the above-described embodiment, the case where the light source light is incident from the counter substrate 20 side has been described, but in particular, when the light source light is incident from the element substrate 10 side, the pixel transistor from the first substrate 19 side of the element substrate 10 is described. Thirty semiconductor layers 1a are likely to receive strong light. Even in this case, according to the present invention, the incidence of such light can be effectively blocked. The present invention also provides an element substrate 10.
The present invention may also be applied to a case where a lens that overlaps the pixel electrode 9a in a plan view is provided on at least one of the counter substrates 20.

[Example of mounting on electronic devices]
An electronic apparatus using the electro-optical device 100 according to the above-described embodiment will be described. FIG.
These are the schematic block diagrams of the projection type display apparatus (electronic device) using the electro-optical apparatus 100 to which this invention is applied. A projection display device 2100 illustrated in FIG. 7 is an example of an electronic apparatus using the electro-optical device 100. In the projection display device 2100, the electro-optical device 100 is used as a light valve, and high-definition and bright display is possible without increasing the size of the device. As shown in this figure, a lamp unit 2102 (light source unit) having a white light source such as a halogen lamp is provided inside the projection display device 2100. The projection light emitted from the lamp unit 2102 is converted into three primary colors of R (red), G (green), and B (blue) by three mirrors 2106 and two dichroic mirrors 2108 arranged inside. To be separated.
The separated projection lights are light valves 100R, 100G and 100B corresponding to the respective primary colors.
Each is guided and modulated. B light has a longer optical path than other R and G colors. Therefore, in order to prevent the loss, light of B color is guided through a relay lens system 2121 having an incident lens 2122, a relay lens 2123, and an output lens 2124. It is burned.

The lights modulated by the light valves 100R, 100G, and 100B are incident on the dichroic prism 2112 from three directions. The dichroic prism 21
12, R and B light is reflected at 90 degrees, and G light is transmitted. Accordingly, after the primary color images are combined, a color image is projected onto the screen 2120 by the projection lens group 2114 (projection optical system).

(Other projection display devices)
In addition, about a projection type display apparatus, you may comprise the LED light source etc. which radiate | emit the light of each color as a light source part, and supply each color light radiate | emitted from this LED light source to another liquid crystal device. .

(Other electronic devices)
The electronic apparatus including the electro-optical device 100 to which the present invention is applied is not limited to the projection display device 2100 of the above embodiment. For example, you may use for electronic devices, such as a projection type HUD (head-up display), a direct view type HMD (head mounted display), a personal computer, a digital still camera, and a liquid crystal television.

DESCRIPTION OF SYMBOLS 1a ... Semiconductor layer, 1b ... Source region, 1c ... Drain region, 1g ... Channel region, 2a ...
Shield wiring, 3a ... scanning line, 3b ... gate electrode, 5a ... capacitance line, 6a ... data line, 8a
... lower layer side light shielding layer, 9a ... pixel electrode, 10 ... element substrate, 10a ... display region, 11 ... first insulating layer, 12 ... second insulating layer, 12a ... contact hole, 19 ... first substrate, 20 ... counter substrate ,
21 ... Common electrode, 29 ... Second substrate, 30 ... Pixel transistor, 32 ... Gate insulating layer, 8
DESCRIPTION OF SYMBOLS 0 ... Electro-optical layer, 100 ... Electro-optical apparatus, 100B, 100G, 100R ... Light valve, 2100 ... Projection type display apparatus, 2102 ... Lamp unit, 2124 ... Outgoing lens.

Claims (6)

An element substrate provided with a pixel electrode on one side of the first substrate, and a second facing the element substrate
A counter substrate in which a common electrode is provided on a surface of the substrate on the element substrate side, and an electro-optical layer provided between the element substrate and the counter substrate,
The element substrate is
A pixel transistor comprising: a semiconductor layer provided between the first substrate and the pixel electrode; and a gate electrode provided on the pixel electrode side with respect to the semiconductor layer;
A first insulating layer provided between the first substrate and the semiconductor layer;
A second insulating layer provided between the first insulating layer and the semiconductor layer;
A scanning line provided between the first substrate and the first insulating layer and electrically connected to the gate electrode through a contact hole penetrating the first insulating layer and the second insulating layer;
A light-shielding shield wiring to which a constant potential is applied, provided to overlap the semiconductor layer in plan view between the first insulating layer and the second insulating layer;
An electro-optical device comprising: The electro-optical device according to claim 1.
The electro-optical device, wherein the scanning line has a light shielding property and is provided so as to overlap with the semiconductor layer in a plan view. The electro-optical device according to claim 2.
The electro-optical device, wherein the shield wiring extends in a direction intersecting the scanning line. The electro-optical device according to claim 3.
The semiconductor layer has a channel length direction in a direction intersecting the scanning line,
The electro-optical device, wherein the contact hole is provided at a position separated from the semiconductor layer in a channel width direction. The electro-optical device according to any one of claims 1 to 4,
The electro-optical device, wherein the constant potential is a ground potential, a common potential applied to the common electrode, or a low potential for a driving circuit. An electronic apparatus comprising the electro-optical device according to any one of claims 1 to 5.