JP2018512662A - Microcontroller device with multiple independent microcontrollers - Google Patents

Abstract

The microcontroller device includes a housing with a plurality of external pins, a first central processing unit (CPU), a first system bus coupled to the first CPU, and a first system bus coupled to the first system bus. And a first microcontroller with a first plurality of peripheral devices coupled to a first system bus, a second central processing unit (CPU), a second CPU coupled to the second CPU. A second microcontroller with a second system bus, a second memory coupled to the second system bus, and a second plurality of peripheral devices coupled to the second system bus; The first and second microcontrollers communicate only via a dedicated interface.

Description

(Cross-reference to related applications)
This application claims priority to commonly assigned US Provisional Patent Application No. 62 / 133,186, filed March 13, 2015. The above references are hereby incorporated by reference herein in their entirety.

(Technical field)
The present disclosure relates to microcontrollers, and more particularly to microcontroller devices with multiple independent processor cores.

(background)
Known microcontroller devices include a single central processing unit (microcontroller core), timer, analog / digital converter, digital / analog converter, pulse width modulation unit, memory, input / output (I / O) port, etc. A plurality of associated peripheral devices. Usually, the internal system bus and control logic link all the components so that the microcontroller core can individually access the peripherals. Externally, the microcontroller has multiple external pins, most of which are typically associated with I / O ports, and each port pin can also be shared with other peripheral devices. Can provide multiple functions. During configuration, the user selects which pins are assigned to perform which function. Such allocation can also be changed during the execution of the program.

  Some microcontrollers are known to include additional accelerators that may be capable of executing separate instructions from the main CPU. Other microcontrollers are known to include two separate CPUs and a plurality of shared peripherals. Thus, both cores share all peripherals, which requires a crossbar switch that adds latency, and the crossbar switch is prone to failure. Existing multi-core devices use a switch matrix to allow multiple processors to access shared system resources such as memory and peripherals. Multiple cores may require access to the same resource. Contention resolution circuitry adds latency, reduces performance, and increases cost. The switch matrix is a single point of failure for the system. Some manufacturers may implement multiple switch matrices. This requires more logic to handle fault resolution between switch matrices. Other manufacturers use multiple cores with different software architectures. These different cores may have some dedicated resources, but other resources are shared.

(wrap up)
However, there is a need for better implementation of dual or multi-core microcontroller devices.

  According to an embodiment, the microcontroller device includes a plurality of external pins, a first central processing unit (CPU), a first system bus coupled to the first CPU, a first system bus coupled to the first system bus. A first microcontroller comprising a first memory and a first plurality of peripheral devices coupled to a first system bus; a second central processing unit (CPU); and a second CPU. A second microcontroller comprising a second system bus, a second memory coupled to the second system bus, and a second plurality of peripheral devices coupled to the second system bus. Alternatively, the first and second microcontrollers communicate only via a dedicated interface.

  According to a further embodiment, the dedicated interface may comprise a bidirectional mailbox interface, a unidirectional master-slave interface, and a unidirectional slave-master interface. According to a further embodiment, each unidirectional interface may comprise a FIFO memory. According to a further embodiment, the first microcontroller can be a master and the second microcontroller can be a slave. According to a further embodiment, the program memory of the second microcontroller may comprise volatile memory writable by the first microcontroller. According to a further embodiment, the second microcontroller can be clocked faster than the first microcontroller. According to a further embodiment, the second microcontroller comprises a power mode control unit comprising a low power mode, and the first microcontroller is configured to control the power mode of the second microcontroller. it can. According to a further embodiment, the power control mode unit can be operable to disable the second microcontroller such that the second microcontroller does not consume any power. According to a further embodiment, each microcontroller may have a data bus width of 16 bits. According to further embodiments, each microcontroller may further comprise a pin selection unit programmable to select at least some of the plurality of external pins for the peripheral device associated with the microcontroller. According to further embodiments, each microcontroller may further comprise a pad ownership multiplexer unit that is controllable to assign control of the input / output pins to either the first microcontroller or the second microcontroller. . According to a further embodiment, each microcontroller can read any readable external pin, but only the pins assigned to the first or second microcontroller can be written by the respective microcontroller. According to a further embodiment, at least some of each of the peripherals of each microcontroller can be assigned to a predetermined external pin of the plurality of external pins.

  According to another embodiment, a plurality of external pins, a first central processing unit (CPU), a first system bus coupled to the first CPU, a first memory coupled to the first system bus, A first microcontroller comprising a first plurality of peripheral devices coupled to the first system bus, a second central processing unit (CPU), a second system coupled to the second CPU A microcontroller device comprising: a bus; a second memory coupled to the second system bus; and a second microcontroller comprising a second plurality of peripheral devices coupled to the second system bus. The method of operating may include communicating between the first and second microcontrollers only via a dedicated interface.

  According to a further embodiment of the method, the dedicated interface may comprise a bidirectional mailbox interface, a unidirectional master-slave interface, and a unidirectional slave-master interface. According to a further embodiment of the method, each unidirectional interface may comprise a FIFO memory. According to a further embodiment of the method, the first microcontroller can be a master and the second microcontroller can be a slave. According to a further embodiment of the method, the program memory of the second microcontroller may comprise volatile memory, the method comprising writing to the program memory of the second microcontroller by the first microcontroller. May be included. According to a further embodiment of the method, the method may further comprise clocking the second microcontroller faster than the first microcontroller. According to a further embodiment of the method, the second microcontroller may comprise a power mode control unit comprising a low power mode, the method further comprising a power of the second microcontroller by the first microcontroller. A step of controlling the mode may be included. According to a further embodiment of the method, the method may comprise the step of disabling the second microcontroller by the power control mode unit so that the second microcontroller does not consume any power. According to a further embodiment of the method, the method may further comprise the step of controlling pin ownership for each microcontroller, wherein the input / output pins are of the first microcontroller or the second microcontroller. Assigned to either. According to a further embodiment of the method, each microcontroller can read any readable external pin, but only the pins assigned to the first or second microcontroller are written by the respective microcontroller. Can do. According to a further embodiment of the method, the method further comprises reading one of the plurality of external pins by the first microcontroller and one of the plurality of external pins by the second microcontroller. And reading a value read from one of the plurality of external pins using a dedicated interface.

FIG. 1 shows a block diagram of a microcontroller, according to an embodiment. FIG. 2 shows a block diagram of a microcontroller according to another embodiment. FIG. 3 shows a top view of a housing for a microcontroller, according to various embodiments. FIG. 4 illustrates an embodiment of a pad ownership control mechanism. FIG. 5 illustrates power control of a microcontroller according to an embodiment.

(Detailed explanation)
A microcontroller is generally considered a system on a single chip because it does not require any external components. Such a device thus comprises a central processing unit, a memory and a plurality of I / O peripherals. In addition, I / O ports may be used for direct digital control. These I / O ports are typically shared with peripheral functions and can be programmed to have general purpose I / O port functions or specific peripheral functions.

  In a low pin count package, eg, a 28 pin package, the capability of a conventional single core microcontroller can be increased by providing two processor cores each having a data bus width of 16 bits. Further, according to various embodiments, the separation of hardware, software, and peripheral resources into multiple independent microcontrollers can facilitate customer software development for real-time control systems, providing safety. Increased monitoring (Class B) can be provided and error mitigation can be improved.

  According to some embodiments, the microcontroller device can comprise multiple instances of independent MCUs on a single die in a low pin count package (28-pin to 64-pin). Thus, an integrated circuit package includes, for example, two independent microcontrollers, each of which will involve its own memory and a plurality of associated peripheral devices. According to some embodiments, one microcontroller can be configured to be a master microcontroller and the other can be a slave microcontroller. Both microcontrollers may have the same or similar peripheral devices, but the peripheral devices can be different and in particular adapted to the specific task for which the respective microcontroller is intended. In addition, the size for data and program memory may be different and the master may generally comprise larger program and data memory.

  Thus, according to various embodiments, an assembly of two (or more) microcontrollers with its own dedicated processor, memory, and peripheral resources on a single silicon die is provided. Multiple microcontrollers share device pins, making it possible and practical to include the device in a low pin count package. External pins can therefore be assigned to either a master MCU or a slave MCU under program control (or configuration register control). According to the rules of the present disclosure for some embodiments, the number of external pins is less than the sum of the data bus widths of all integrated MCUs. For example, a two-core MCU may comprise two 16-bit MCUs each having a 16-bit data bus width. The sum of the data bus widths of all integrated MCUs will therefore be 32. When such a device is mounted in a 28-pin housing, such a device will follow the rules described above.

  According to various embodiments, in a multi-core MCU (multiprocessor) device, the number of external pins is the number of cores times the bit width of each processor. In particular, according to some embodiments, the number of external pins is less than the data bus width of the master processor. For example, a dual core microcontroller according to various embodiments can be fitted into a 28-pin housing, as will be described in more detail below. As described above, various embodiments consist of a microcontroller device with multiple microcontroller units (MCUs), each with its own processor, memory, and peripherals.

  Multiple MCUs are designed to share external device pins. All MCUs can be configured to be able to read (or observe) pins through their dedicated special function registers, however, writing (driving) to pins through dedicated registers is not Controlled through a non-volatile memory. Non-volatile memory is therefore used to define “ownership” of device pins, thereby preventing conflicts. Ownership may be defined during the configuration phase, for example, during device programming using configuration registers that cannot be modified once the device is in an operating mode. Alternatively, special function registers and procedures may be implemented to allow dynamic allocation through the use of special function registers. Such inadvertent overwriting of registers may be prevented through special write routines similar to those used in conventional EEPROM write routines. Assignment of one of the external pins to one of the cores prevents software and hardware failures. Controllable sharing of device pins allows multicore devices to be practical within a low pin count package.

  According to various embodiments, two (or more) microcontrollers, along with their own dedicated processor, memory, and peripheral resources, are assembled on a single silicon die, and a specific communication interface between the cores. Provided. The microcontrollers communicate with each other via a master-slave interface (MSI), which may be a set of registers (mailboxes) and associated status bits and interrupts (semaphores), according to one embodiment.

  The classical computer architecture approach is to have multiple processors communicate with device resources such as memory and peripherals via a switch matrix. In these conventional embodiments, two (or more) processors share all of the system resources. The switch matrix must assign a priority to each request from each processor for each resource, and contention must be resolved. This resource contention management significantly adds latency (time) to each request. The switch matrix is large and subject to a single point of failure. The classic solution to solve the switch matrix vulnerability is to duplicate the switch matrix. This requires more circuitry to detect faults and figure out which switch matrix is still feasible. Various embodiments instead avoid the complexity of attempting to share resources using a switch matrix by simply duplicating the resources.

  The second exemplary architecture is a processor + coprocessor concept that shares some peripherals but has access to its own limited set of resources such as memory and several peripherals. . The architecture typically has several peripherals that are expensive to replicate and are therefore shared between the processor and the coprocessor. Typically, processors and coprocessors have different software architectures and may therefore require different development tools for software generation.

  Instead of these conventional approaches, for example as shown in FIG. 1 according to various embodiments, the entire MCU (microcontroller unit), each with its own memory and peripherals, is replicated in a single chip. Is done. Separate MCUs share device pins via secure non-volatile registers and prevent contention when driving device pins, but all MCUs may be device-assigned at any time, even if they are not assigned to them The pin can be read. The embodiment in FIG. 1 results in a high pin count device.

  FIG. 1 shows a dual core microcontroller 100 with two microcontrollers in a single integrated circuit enclosure. The first microcontroller includes a CPU 110, a system bus 120, and a plurality of peripheral devices 130a. . n, and a data memory 140, eg, 16 kilobyte RAM, a program memory 150, eg, 128 kilobyte flash memory, and a DMA controller 160. The system bus can be divided into two buses, a peripheral bus and a memory bus, as shown in FIG. 1, or a single system bus connecting all devices may be implemented. Some peripherals such as DMA controller 160 may not have any external connections, and other peripherals such as PWMs, ADCs, comparators, and some serial interfaces may It may be assigned to a multi-function pin. Other peripheral devices such as other serial interfaces, touch sensors, timers, comparator outputs, etc. may be assigned to one of the plurality of external pins via the peripheral device pin selection unit 170. Some pins can be assigned to more than one peripheral on the first MCU and may generally share its function with the MCU's general purpose I / O port. Accordingly, this embodiment provides two pad ownership multiplexers 180 and 280. In the default assignment, each pin associated with a master or slave MCU may be assigned to a general purpose I / O port of the respective MCU, but under program control of the pad ownership multiplexer 180, one of the peripherals Can be assigned to. Some pins 190 may be assigned by default to a peripheral device such as a serial programming interface, ADC, or any other peripheral device, as shown in FIG. As described above, the peripheral device pin selection unit 180 may further allow some or all of the peripheral devices to be assigned to any of the respective sets of external pins.

  The external pins comprise a first set of pins that are used to provide power to the die. This can include, for example, digital and analog power supply pins and multiple instances of such pins, as shown in FIG. Further, the master clear pin may not have other functions and may be used to reset and / or program the device. The remaining second set of pins are generally input / output pins (I / O pins). However, there may be several other pins that are not controlled by one of the microcontrollers. An I / O pin according to the present disclosure is defined as any pin that can be programmed to be either an input pin or an output pin or a pin with a dedicated input or output function. The input pins can be used for digital or analog input, depending on the respective peripheral settings. Similarly, the output pins can be used for digital or analog output, depending on the respective peripheral settings. As mentioned above, this application generally refers to input / output pins, and some pins may only be used as input or output pins. All input / output pins are pins that are controlled by one of the microcontrollers when the output signal and the signal fed to these pins are signals received by one of the microcontrollers . The power supply pins are generally not considered to have this function. Some other pins may also not have such functionality, for example, the device may have a dedicated pin for the oscillator. However, such pins may also be multiplexed with microcontroller I / O functions, as shown in FIG. FIG. 3 shows that the pins that would not be considered I / O pins are pins 5-8, 19, 20, and pin 27. FIG.

  Special function registers may be used to control the pad ownership multiplexer. In this embodiment, each microcontroller core may have access only to its special function registers. However, according to yet another embodiment, only the master MCU may have access to special function registers that control the two pad ownership multiplexers 180,280. In addition, the master CPU 110 may also have access to the program RAM 250 of the slave MCU, either directly or through a specific interface. This feature allows programming / writing of the program RAM 250 of the slave MCU through the master MCU.

  In this embodiment, the second MCU includes a pin 290, a CPU 210, a system bus 220, and a plurality of peripheral devices 230a. . n, and a data memory 240, eg, 4 kilobyte RAM, a program memory 250, eg, 24 kilobyte RAM, and a DMA controller 260. As described above, the program memory 250 may be volatile and allow programming through the master MCU. However, other implementations are also possible according to other embodiments. All other units may be similar to the master MCU. A second peripheral device pin selection unit 270 is provided to allow flexible allocation of some of the external pins 290 to certain peripheral devices similar to the first MCU. However, in this embodiment, there is no pin sharing between the two MCUs.

  FIG. 1 further shows a communication interface between two MCUs via a bidirectional mailbox system 310 and two unidirectional FIFOs 320 and 330 that allow communication between the two cores in both directions. The mailbox can be used to transfer commands or short data to individual other microcontrollers. Multiple mailboxes 310 as shown in FIGS. 1 and 2 may be implemented. Once data or commands are written into the mailbox, a separate interrupt will be generated in the receiving microcontroller to indicate that a new message (command or data) is available. This allows for fast transfer of information without any additional delay.

  In addition, the two FIFOs 320 and 330 can be implemented to allow greater data transfer between the two microcontrollers. FIFOs 320 and 330 do not have the size limit of mailbox 310 and thus allow for greater data transfer. Given that the FIFO 320, 330 does not become empty (or does not encounter an error condition), the master and slave may access it in parallel. FIFOs 320, 330 may thus provide better throughput than mailbox 310 based data pipes that must be loaded by one processor before being read by the other. However, the FIFO 320, 330 content is loaded and unloaded sequentially and is not randomly accessible like the data in the mailbox data pipe. A FIFO is also unidirectional (by definition). This makes the FIFO more suitable for applications that require high-speed means to transfer blocks of data between processors.

  Multiple microcontrollers may share a common software architecture. Thus, according to one embodiment, the same microcontroller core is used for various integrated microcontrollers. The concept of providing a master and one or more slave microcontrollers further allows reducing power consumption. The slave microcontroller may be configured to be placed in a sleep mode that is disabled, thereby not requiring much energy. According to other implementations, the microcontroller in the device may be completely turned off to save energy.

  FIG. 5 shows an exemplary control structure for such a system. Each microcontroller 100a, 100b may have dedicated power control units 510 and 520, respectively. Each power control unit 510, 520 may be able to set a specific power consumption mode and associated processing power. For example, each microcontroller 100a, 100b may be set to sleep or low power mode. Various levels of power consumption may be provided. In addition, according to one embodiment, the master microcontroller 100a may be able to completely turn off the slave microcontroller 100b. In this mode, the microcontroller 100b will not consume any power.

  The core may further operate at different speeds. This feature can be implemented especially when using volatile memory as program memory for the second microcontroller. Volatile memory, such as RAM, is inherently faster, thus allowing faster access times and thus higher clock rates. The master core may be configured to handle system level functions using frequent interrupts. In addition, safety compliance features, communications, interrupt handling, software updates, user interfaces, etc. can be handled. Due to the feature that all microcontrollers can read any of the external pins, safety can be improved by multiple MCUs monitoring, for example, the same device pin. . For example, according to an embodiment, the two microcontrollers may comprise software for providing a safety enhancement feature, wherein one of the plurality of external pins is independent by the first and second microcontrollers. And read. The read value can then be compared using the communication interface. For example, in the case of a single pin, one of the mailboxes may be used to transfer readings to the other core. Alternatively, one of the FIFOs 320, 330 may be used to transfer one or more values. The system can output an alert if the values do not match, or a specific software routine, interrupt, or reset may be performed to correct the error.

  According to various embodiments, time constraint code can be partitioned to facilitate code development and support. Slave cores can be used for dedicated and more deterministic responses such as critical latency, motor control, control loops with digital power control, etc. Thus, as a slave microcontroller, it can be viewed as an additional programmable peripheral for the master microcontroller. The advantage of such an architecture is a step-wise performance increase. Two cores basically double the execution rate. As mentioned above, time critical functions and system functions can be separated and assigned to different cores. Control loop responsiveness can be optimized, interrupts can be minimized, and motor algorithm implementation can be simplified. The execution speed of the master core can be, for example, 100 MIPS, according to one embodiment, while the slave core target can process> 100 MIPS by providing faster program memory, eg, volatile random access memory. Can have power. Thus, the slave microcontroller can generally be faster than the master microcontroller.

  The number of required external pins may further be reduced according to some embodiments by sharing the pins used for the peripherals between the two MCUs, as shown in FIG. it can. FIG. 2 shows a block diagram of a multi-core device in a package with a reduced number of pins 420 as opposed to the embodiment shown in FIG. FIG. 2 specifically shows a 28-pin version of a dual core microcontroller with two separate MCUs. Here, only a single pad ownership multiplexer 410 may be provided that can only be controlled by the master MCU, for example through a special function register. However, according to some embodiments, both MCUs may have access, and in one embodiment, the master MCU may be prioritized over the slave MCUs.

  The reduced number of available I / O pins still provides the same or more pins to each MCU. In particular, low cost applications that require only certain peripheral devices that benefit from this solution, such as low pin count devices, among others, reduce costs for printed circuit boards. The pad ownership multiplexer 410 allows each MCU's universal port functionality to be shared with external pins and assigned to one of the peripherals of either the master MCU or the slave MCU.

  FIG. 2 further shows four digital power supply pins Vdd and Vss, a non-multiplexed master clear function pin used for resetting and programming, and two analog power supply pins AVdd and AVss. The remaining 21 pins are external I / O pins that can be assigned to either the master MCU or the slave MCU. Thus, in some configurations, all 21 I / O pins may be assigned to the master MCU, which reduces the functionality of the slave MCU to that of the coprocessor. Similarly, another configuration may assign all 21 I / O pins to the slave MCU. Any other assignment with any quantification between the master MCU and slave MCU assignments is also possible.

  FIG. 4 illustrates possible controls for the pad ownership multiplexer 180, 280 of FIG. 1 or the pad ownership multiplexer 410 of FIG. Control can be accomplished via configuration register 430. Such registers can be automatically programmed according to settings using an external programmer or emulator device. Thus, once programmed, the settings cannot be modified during operation of the device 100. Alternatively, special function registers may be used to control ownership pad multiplexers 180, 280/410. In such an embodiment, dynamic control is considered as a possibility. To avoid accidental overwriting, a writing mechanism similar to that used in EEPROM may be used, for example a sequence of special codes written in a time frame.

  FIG. 3 shows the actual pins from the device in a 28-pin package. Slave peripherals are indicated by the prefix “S1”. FIG. 3 specifically shows the multifunctional assignment of each pin. FIG. 3 does not necessarily show all the functions that can be assigned to external pins for better visibility, as will be described in more detail below. Here, typically, RAx refers to a general purpose I / O port A having 5 bits, and RBx refers to a 16-bit port RB. As mentioned above, FIG. 3 shows only a single set of I / O ports A and B for better visibility. However, two separate sets, controlled independently by the master and slave MCUs, may be implemented and assigned independently. According to one embodiment, each port pin can be assigned to either a master or slave using generic pin association, as shown in FIG. According to one embodiment, the assignment to the master MCU may take precedence over the assignment to the slave MCU. According to other embodiments, the ports for the master MCU and slave MCU may be assigned to different pins.

  ANx refers to the analog input for the master MCU, and S1ANx refers to the analog input for the slave MCU. Similar to port pins, other associations to external pins may be selected for master and slave MCUs. If capacitive divider peripherals are implemented, each analog pin may also be assigned to capacitive divider function and separate units for the master MCU and slave MCU may be provided. RPx refers to the 16 pins assigned by the peripheral device pin selection unit. Similar to the I / O port, the master and slave MCUs may each have, for example, 16 pins available, while FIG. 3 shows only a single set (again, for better visibility) ). According to other embodiments, a different number of peripheral pin selection pins may be used, for example, eight of these pins are assigned to the master and eight pins are assigned to the slave MCU. May be. Again, other numbers of pins and / or assignments of such peripheral device pin selection units may be selected. Other pin functions, such as pulse width modulator pins, use respective acronyms such as PWM, and the leading S1 of the acronym generally indicates that the unit belongs to a slave MCU.

  As described above, each pin may be assigned to a specific function by default. For example, pins 1-3 can be assigned as analog inputs of the master MCU by default. Pins 4 and 11 can be assigned as analog inputs of the slave MCU by default. Pins 9 and 10 can by default be oscillator input pins, but may also be assigned to other functions when an internal oscillator is used. Pins 12-13 can be assigned to the synchronous serial programming interface PGED2 by default, and PGEC2 only interacts with the master MCU. Pins 14-18 and 21-26 are assigned to PORTB bits 5-15 by default, and pin 28 is assigned to bit 0 of PORTA. The above assignments are merely examples, and other assignments are also possible.

Claims (24)

A microcontroller device,
Multiple external pins,
A first central processing unit (CPU), a first system bus coupled to the first CPU, a first memory coupled to the first system bus, and the first system bus; A first microcontroller comprising a coupled first plurality of peripheral devices;
A second central processing unit (CPU), a second system bus coupled to the second CPU, a second memory coupled to the second system bus, and the second system bus A second microcontroller comprising a coupled second plurality of peripheral devices;
A microcontroller device in which the first and second microcontrollers communicate only through a dedicated interface.   The microcontroller device of claim 1, wherein the dedicated interface comprises a bidirectional mailbox interface, a unidirectional master-slave interface, and a unidirectional slave-master interface.   The microcontroller device of claim 2, wherein each unidirectional interface comprises a FIFO memory.   The microcontroller device according to claim 1 or 2, wherein the first microcontroller is a master and the second microcontroller is a slave.   The microcontroller device according to claim 1, wherein the program memory of the second microcontroller comprises a volatile memory writable by the first microcontroller.   The microcontroller device according to claim 1, wherein the second microcontroller is clocked at a higher speed than the first microcontroller.   The second microcontroller comprises a power mode control unit with a low power mode, the first microcontroller configured to control a power mode of the second microcontroller. The microcontroller device according to one of -6.   8. The microcontroller device of claim 7, wherein the power control mode unit is operable to disable the second microcontroller so that the second microcontroller does not consume any power.   The microcontroller device according to claim 1, wherein each microcontroller has a data bus width of 16 bits.   Each microcontroller further comprises a pin selection unit programmable to select at least some of the plurality of external pins for the peripheral device associated with the microcontroller. A microcontroller device according to claim 1.   Each of the microcontrollers further comprises a pad ownership multiplexer unit that is controllable to assign control of input / output pins to either the first microcontroller or the second microcontroller. The microcontroller device according to one of them.   Each microcontroller can read any readable external pin, but only pins assigned to the first or second microcontroller can be written by the respective microcontroller. 12. The microcontroller device according to claim 1.   The microcontroller device according to claim 1, wherein at least some of each of the peripherals of each microcontroller is assigned to a predetermined external pin of the plurality of external pins. A plurality of external pins, a first central processing unit (CPU), a first system bus coupled to the first CPU, a first memory coupled to the first system bus, and the first A first microcontroller comprising a first plurality of peripheral devices coupled to a system bus; a second central processing unit (CPU); a second system bus coupled to the second CPU; Operating a microcontroller device comprising: a second memory coupled to a second system bus; and a second microcontroller comprising a second plurality of peripheral devices coupled to the second system bus. And the method comprises:
Communicating between the first and second microcontrollers only via a dedicated interface.   The method of claim 14, wherein the dedicated interface comprises a bidirectional mailbox interface, a unidirectional master-slave interface, and a unidirectional slave-master interface.   The method of claim 15, wherein each unidirectional interface comprises a FIFO memory.   17. A method according to one of claims 14-16, wherein the first microcontroller is a master and the second microcontroller is a slave.   18. The program memory of the second microcontroller comprises a volatile memory, and the method comprises writing to the program memory of the second microcontroller by the first microcontroller. 2. The method according to item 1.   19. The method of one of claims 14-18, further comprising clocking the second microcontroller faster than the first microcontroller.   The second microcontroller comprises a power mode control unit comprising a low power mode, and the method further comprises controlling a power mode of the second microcontroller by the first microcontroller. 20. The method according to one of 14-19.   21. A method according to any one of claims 14 to 20, comprising the step of disabling the second microcontroller so that the second microcontroller does not consume any power by means of a power control mode unit. .   The method of any of claims 14-21, further comprising controlling pin ownership for each microcontroller, wherein input / output pins are assigned to either the first microcontroller or the second microcontroller. 2. The method according to item 1.   Each microcontroller can read any readable external pin, but only pins assigned to the first or second microcontroller can be written by the respective microcontroller. 23. A method according to one of the twenty-two. Reading one of a plurality of external pins by the first microcontroller;
Reading one of a plurality of external pins by the second microcontroller;
24. The method of any one of claims 14-23, further comprising comparing a value read from one of the plurality of external pins using the dedicated interface.