JP2018200920A - Silicon carbide mosfet and method of manufacturing the same - Google Patents

Abstract

An SiC-MOSFET having a termination structure region capable of effectively suppressing expansion of stacking faults and increasing a breakdown voltage is provided.
An active portion, a termination structure region as a breakdown voltage region provided outside the active portion, and a drift layer 1 between the active portion and the termination structure region, the upper surface being a source P-type conduction induction regions 12a and 13a provided to be joined to the electrode 9 and having a junction area with the source electrode 9 set to be larger than a junction area with the source electrode 9 of the base contact regions 5a and 5b. .
[Selection] Figure 2

Description

  The present invention relates to a silicon carbide MOSFET and a manufacturing method thereof.

  Silicon carbide (SiC) semiconductors are attracting attention as next-generation power semiconductor materials. SiC has a band gap of 4H-SiC of 3.25 eV, which is about 3 times larger than 1.12 eV of silicon (Si) used in the past, and the electric field strength is 2 to 4 mV / cm, which is nearly an order of magnitude higher than Si. Yes, it has superior material properties compared to Si.

  Therefore, in the case of a semiconductor element composed of SiC, the resistance (on-resistance) of the element in a turn-on (hereinafter also simply referred to as “on”) state is several hundreds of times as compared with a semiconductor element composed of Si, for example. It can be reduced to one. The SiC semiconductor element can also be used in a high temperature environment of 200 ° C. or higher. Various devices such as a rectifying device such as a diode using SiC and a switching device such as a transistor and a thyristor have been prototyped so far.

  It is known that several types of dislocations exist in a SiC substrate. Non-Patent Document 1 discloses that when a device is fabricated on a SiC substrate and the fabricated device is operated, dislocations in the substrate grow into stacking faults due to recombination of electron-hole pairs. Yes. When a stacking fault occurs, the on-characteristics of the device are adversely affected, and the conduction loss of the power semiconductor module including the semiconductor element increases. Therefore, it is desirable that the stacking fault does not occur.

  As a technique for solving this problem, a method of manufacturing a SiC substrate (wafer) having no dislocations can be considered. For example, Patent Document 1 discloses that a basal plane dislocation (BPD) and a basal plane dislocation (BPD) are obtained by supplying a dopant gas by controlling the concentration ratio C / Si of carbon (C) and Si while controlling the substrate temperature within a certain range. A method for manufacturing a SiC epitaxial wafer having a low stacking fault density is disclosed.

  As another method for suppressing the extension of stacking faults, there is a technique related to the cell structure of a semiconductor device. For example, in Patent Document 2, the extension of stacking faults is provided by providing a stripe-shaped current limiting region in the active region. A method of preventing this is disclosed. In Patent Document 3, expansion of stacking faults is prevented by a method of forming a trench-like groove in the active region.

  Patent Document 4 and Patent Document 5 disclose an invention in which a Schottky contact region is provided in a region other than an active portion of a MOS (Metal-Oxide-Semiconductor) field effect transistor (MOSFET) of a semiconductor element. The Schottky contact region can reduce the current stress applied to the dislocation when the device is energized, and thus it is said that the expansion of stacking faults can be suppressed.

  However, in the case of the method of Patent Document 1, although it is possible to improve the quality of the SiC wafer to a certain extent, the dislocation has not yet been completely eliminated. In the case of a method in which a special structure is separately formed inside SiC as in the stripe-shaped current limiting region of Patent Document 2, or a trench-like groove is formed on the SiC surface side as in Patent Document 3. In addition, the process is accompanied by great difficulty and the process cost is greatly increased.

  In addition, it is necessary to provide an ohmic contact region on the surface of the SiC semiconductor device because of a requirement in specifications. Therefore, in the method of providing the Schottky contact region as in Patent Document 4 and Patent Document 5, both the ohmic contact region and the Schottky contact region are formed, and the process burden is significant.

  Further, as disclosed in Patent Document 6, in a SiC semiconductor device such as a MOSFET, a termination structure region may be selectively formed on the periphery of the active portion so as to surround the cell region that is the active portion. The termination structure region is a structure for relaxing the electric field concentration at the termination portion of the device and increasing the breakdown voltage, and thus is highly necessary in the SiC semiconductor device. Therefore, there is a strong demand for a technology that can effectively suppress the expansion of stacking faults in a SiC semiconductor device having a termination structure region.

JP, 2015-002207, A JP 2013-232574 A JP 2004-335720 A International Publication No. 2007/013367 JP, 2006-006854, A Japanese Patent No. 5751763

Journal of Applied Physics, Vol. 99, 01101 (2006)

  The present invention has been made paying attention to the above-described problems, and provides a silicon carbide MOSFET that can effectively suppress expansion of stacking faults in a silicon carbide MOSFET having a termination structure region. The purpose is to do.

  In order to solve the above-described problems, an aspect of the silicon carbide MOSFET according to the present invention according to the present invention includes a first conductivity type drift layer made of a silicon carbide semiconductor substrate, and a second conductivity type provided above the drift layer. A first conductivity type source region selectively provided above the base region, a gate insulating film provided on the drift layer, a gate electrode provided on the gate insulating film, and a drift layer A source electrode provided above, a base contact region of a second conductivity type provided in contact with the source electrode on the base region above the drift layer, and a drain of a first conductivity type provided below the drift layer An active portion having a drain electrode provided below the region and the drain region, a termination structure region as a breakdown voltage region provided outside the active portion, and a drain between the active portion and the termination structure region. A conduction-inducing region of a second conductivity type, the upper surface of which is provided on the upper surface of the base layer and bonded to the source electrode, and the bonding area with the source electrode is set larger than the bonding area with the source electrode of the base contact region; It is a summary to provide.

  According to another aspect of the method for manufacturing a silicon carbide MOSFET according to the present invention, a second conductivity type base region is formed on the first conductivity type drift layer made of a silicon carbide semiconductor substrate, and the first conductivity type is formed on the base region. A conductive source region is selectively formed, a gate insulating film is formed on the drift layer, a gate electrode is formed on the gate insulating film, a source electrode is formed on the drift layer, and A base contact region of the second conductivity type is formed on the base region and joined to the source electrode at the top, a drain region of the first conductivity type is formed under the drift layer, and a drain electrode is formed under the drain region A step of forming an active portion, a step of forming a termination structure region as a breakdown voltage region outside the active portion, and a top surface of the source electrode on the drift layer between the active portion and the termination structure region Together joined, and summarized in that comprises a step of forming a larger way conduction induction region of the second conductivity type than the junction area between the source electrode of the junction area is the base contact region between the source electrode.

  According to the silicon carbide MOSFET of the present invention, it is possible to effectively suppress the expansion of stacking faults in a state where the termination structure region is provided. Moreover, according to the method for manufacturing a silicon carbide MOSFET according to the present invention, a silicon carbide MOSFET having a termination structure region, which can suppress the burden of further additional steps in the manufacturing process and suppress the expansion of stacking faults, is manufactured. it can.

1 is a plan view schematically illustrating an outline of a configuration of a silicon carbide MOSFET (hereinafter also referred to as “SiC-MOSFET”) according to a first embodiment. It is sectional drawing which illustrates typically the outline of a structure of SiC-MOSFET which concerns on 1st Embodiment. It is sectional drawing of the drift layer for demonstrating the width | variety of a conduction induction area | region typically. In the SiC-MOSFET which concerns on 1st Embodiment, it is a top view which illustrates typically the outline of the state which the stacking fault expanded. It is a top view explaining typically the outline of the composition of SiC-MOSFET concerning the 1st comparative example. It is sectional drawing which illustrates typically the outline of a structure of SiC-MOSFET which concerns on a 1st comparative example. In SiC-MOSFET which concerns on a 1st comparative example, it is a top view explaining typically the outline of the state where the stacking fault expanded. It is a top view which illustrates typically the outline of the composition of SiC-MOSFET concerning the 2nd comparative example. It is a top view explaining typically the outline of the composition of SiC-MOSFET concerning the 3rd comparative example. It is process sectional drawing which illustrates typically the manufacturing method of SiC-MOSFET which concerns on 1st Embodiment (the 1). It is process sectional drawing which illustrates typically the manufacturing method of SiC-MOSFET which concerns on 1st Embodiment (the 2). It is process sectional drawing which illustrates typically the manufacturing method of SiC-MOSFET which concerns on 1st Embodiment (the 3). It is process sectional drawing which illustrates typically the manufacturing method of SiC-MOSFET which concerns on 1st Embodiment (the 4). It is process sectional drawing which illustrates typically the manufacturing method of SiC-MOSFET which concerns on 1st Embodiment (the 5). It is a top view explaining typically the outline of the composition of SiC-MOSFET concerning the 1st modification. It is a top view explaining typically the outline of the composition of SiC-MOSFET concerning the 2nd modification. It is sectional drawing which illustrates typically the outline of a structure of SiC-MOSFET which concerns on a 3rd modification. It is sectional drawing which illustrates typically the outline of a structure of SiC-MOSFET which concerns on a 4th modification. It is a top view which illustrates typically the outline of the composition of SiC-MOSFET concerning a 2nd embodiment. It is sectional drawing which illustrates typically the outline of a structure of SiC-MOSFET which concerns on 2nd Embodiment. It is a top view explaining typically the outline of the composition of SiC-MOSFET concerning the 5th modification. It is sectional drawing which illustrates typically the outline of a structure of the semiconductor module carrying the SiC-MOSFET which concerns on 1st or 2nd embodiment.

  The first and second embodiments of the present invention will be described below. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, the drawings are schematic, and it should be noted that the relationship between the thickness and the planar dimensions, the ratio of the thickness of each device and each member, and the like are different from the actual ones. Therefore, specific thicknesses and dimensions should be determined in consideration of the following description. Moreover, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings.

  Further, the directions of “left and right” and “up and down” in the following description are merely definitions for convenience of description, and do not limit the technical idea of the present invention. Thus, for example, if the paper is rotated 90 degrees, “left and right” and “up and down” are read interchangeably, and if the paper is rotated 180 degrees, “left” becomes “right” and “right” becomes “left”. Of course. In the following description, the case where the first conductivity type is n-type and the second conductivity type is p-type will be exemplarily described. However, the first conductivity type is p-type by selecting the conductivity type in the reverse relationship. The second conductivity type may be n-type. Further, + or − attached to n or p means a semiconductor region having a relatively higher or lower impurity element impurity density than a semiconductor region not including + and −.

-First embodiment-
<Semiconductor device>
As shown in FIG. 1, the SiC-MOSFET according to the first embodiment is a semiconductor chip having a planar pattern and a rectangular shape as a whole. A rectangular active portion 100 is provided at the center of the main surface of the semiconductor chip, and the active portion 100 has a transistor structure and a parasitic diode structure. For the sake of explanation, FIG. 1 schematically shows a state in which the layer above the gate insulating film is removed and the surface layer of SiC is exposed. However, as shown in FIG. Transistor structures are stacked.

The upper well contact regions 13a and 13b of the p-type conduction inducing region appear with the same width w at both ends of the active portion 100 in the <11-20> direction. Outside the active portion 100 and the conduction induction region, a termination structure region 14 as a high concentration p ⁺ -type withstand voltage region is provided in a frame shape in a planar pattern.

As shown in FIG. 2, the active part 100 includes an n ⁻ type drift layer 1, a plurality of high-concentration p ⁺ type base regions 2 a and 2 b provided on the drift layer 1, and a base region 2 a. , 2b and a plurality of p-type channel regions 3a-3c. In each of the channel regions 3a to 3c, n ⁺ type source regions 4a to 4c are selectively provided. On the base regions 2a and 2b, high-concentration p ⁺ -type base contact regions 5a and 5b are provided between the adjacent source regions 4a to 4c.

  On the upper surface of the drift layer 1, gate insulating films 6 a and 6 b are provided over the source regions 4 a to 4 c, the channel regions 3 a to 3 c and the upper surface of the drift layer 1. Gate electrodes 7a and 7b are provided on the gate insulating films 6a and 6b, and interlayer insulating films 8a and 8b are provided on the surfaces of the gate electrodes 7a and 7b. A source electrode 9 is provided on the interlayer insulating films 8a and 8b so as to be connected to the source regions 4a to 4c. A passivation film or the like is deposited as an outermost layer on the upper surface of the source electrode 9, and the main surface of the lower source electrode 9 is exposed in a window portion--opening portion formed in the passivation film or the like. .

Below the drift layer 1, an n ⁺ -type drain region 10 is provided in a layered form, and below the drain region 10, a drain electrode 11 connected to the drain region 10 is provided. In the active part 100, a main current flows between the source regions 4a to 4c and the drain region 10 by applying a gate voltage to the gate electrodes 7a and 7b.

The conduction induction regions (12a, 13a) are provided in the vicinity of the upper surface of the drift layer 1 with a high concentration p ⁺ -type lower conduction region 12a and the source electrode 9 on the lower conduction region 12a. A high concentration p ⁺ type upper well contact region 13a. The lower conductive region 12a is provided with substantially the same depth and the same thickness as the base regions 2a and 2b. The upper well contact region 13a has substantially the same depth and the same thickness as the base contact regions 5a and 5b.

Lower conductive region 12a is electrically connected to the source bonding pad by upper well contact region 13a. The doping concentration of the lower conduction region 12a and the upper well contact region 13a is set to be higher than the doping concentration of the base contact regions 5a and 5b. For example, when the doping concentration of the base contact regions 5a and 5b is about 1.0 × 10 ¹⁹ cm ⁻³ , the doping concentration of the conduction induction regions (12a and 13a) is 1.0 × 10 ¹⁹ cm ⁻³ or more as a whole. To be realized. When the conduction induction region (12a, 13a) is 1.0 × 10 ¹⁹ cm ⁻³ or more as a whole, the entire conduction induction region (12a, 13a) may be regarded as a p-type “well contact region”. it can.

  In the SiC-MOSFET according to the first embodiment, the sum of the areas where the conduction induction regions (12a, 13a) are joined to the source electrode 9 is larger than the sum of the areas of the base contact regions 5a, 5b of the active part 100. So that it is controlled. That is, the parasitic diode of the conduction induction region (12a, 13a) has a larger junction area with the source electrode 9 than the parasitic diode of the active part 100.

  In the SiC-MOSFET illustrated in FIG. 1, the total area of the two upper well contact regions 13a and 13b is realized to be larger than the total area of the three base contact regions 5a to 5c. In FIG. 1, for convenience of explanation, the upper well contact regions 13a and 13b and the upper surfaces of the base contact regions 5a to 5c are hatched.

Here, the area of the upper well contact region 13a of the left conduction induction region (12a, 13a) in FIG. 1 is S _13a , and the area of the upper well contact region 13b of the left conduction induction region is S _13b . Further, assuming that the area of the left base contact region 5a inside the active part 100 in FIG. 1 is S _5a , the area of the central base contact region 5b is S _5b , and the area of the right base contact region 5c is S _5c .
(S _13a + S _13b )> (S _5a + S _5b + S _5c ) (1)
Is established.

  The upper limit of the total area of the upper well contact regions 13a and 13b of the two conduction induction regions is about the total area including the active portion 100 and the conduction induction region because of the need to ensure the operation as a semiconductor device. It is set within the range of 70% to about 80%.

を満たすように設定される。 Further, the lower conduction region 12a and the upper well contact region 13a of the SiC-MOSFET according to the first embodiment extend in the vertical direction with the same length as the active portion 100, as shown in FIG. This vertical direction is a direction orthogonal to the <11-20> direction of the SiC single crystal, and is hereinafter also referred to as “longitudinal direction”. As shown in FIG. 3, the width w of the conduction induction regions (12a, 13a) is determined by using the thickness d of the drift layer 1 and the inclination angle θ with respect to the <11-20> direction of the SiC substrate.

It is set to satisfy.

For example, when the thickness d of the drift layer 1 is 10 μm and the inclination angle θ is about 4 °, the width w is w ≧ 10 / tan 4 ° [μm] = about 143 [μm] from the equation (2).
Therefore, the width w of the conduction induction regions (12a, 13a) needs to be about 143 μm or more.

  Here, in the MOS transistor structure, when a forward current is passed through a parasitic diode in the current path of the source electrode 9-base region 2a, 2b-drift layer 1-drain region 10-drain electrode 11, the bipolar operation is performed. Hole pair recombination occurs. Although dislocations in the SiC substrate expand to stacking faults due to recombination energy, the extension direction of stacking faults is limited to the vertical direction perpendicular to the <11-20> direction.

  In a normal MOSFET, a parasitic diode is present in the active part 100 having a MOS structure, so that a stacking fault 30 is generated immediately below the active part 100. And the on-resistance of the MOSFET increases, leading to an increase in power loss. Therefore, in the SiC-MOSFET according to the first embodiment, the conduction induction regions (12a, 13a) are provided, and the upper well contact region 13a for realizing ohmic contact is further provided in the conduction induction regions (12a, 13a). Provide.

  Then, as described using Expression (1), the total area of the upper well contact regions 13a and 13b is made larger than the areas of the base contact regions 5a to 5c existing in the active portion 100. Therefore, the current when the parasitic diode is energized easily flows to the upper well contact regions 13a and 13b. On the other hand, the dislocation has a current density threshold value at which expansion to stacking faults starts. Therefore, energization concentrates on the conduction induction regions (12a, 13a), and the current density of the parasitic diode in the active portion 100 relatively decreases, so that the expansion of the stacking fault 30 in the active portion 100 is suppressed.

Even if the SiC-MOSFET according to the first embodiment that satisfies the above expressions (1) and (2) at the same time is energized at 175 ° C. with a forward current of 400 [A / cm ² ] of the parasitic diode, it remains active. The stacking fault 30 did not occur in the portion 100, and the on-resistance did not increase. Further, when the fluctuation of the forward voltage drop of the parasitic diode was measured, the fluctuation was 0.5% or less, and the increase in resistance could be suppressed.

  When the forward current was further increased and current was applied, generation of stacking faults 30 was observed in the left conduction induction region (12a, 13a) as shown in FIG. However, no stacking fault occurred inside the active part 100, and the on-resistance did not increase. Further, when the fluctuation of the forward voltage drop of the parasitic diode was measured in the SiC-MOSFET in the state shown in FIG. 4, the influence on the voltage drop was still small, and the fluctuation was 0.5% or less at 175 ° C. .

(First comparative example)
Next, an SiC-MOSFET according to a comparative example in which no conduction induction region is provided at both ends of the active portion will be described with reference to FIGS. As shown in FIG. 5, the SiC-MOSFET according to the first comparative example is not provided with a conduction inducing region, and 10 channel regions 3 a to 3 j and 10 source regions are formed on the surface of the active portion 101. 4a to 4j and five base contact regions 5a to 5e appear.

The other structure of the SiC-MOSFET according to the first comparative example is the same as that of the SiC-MOSFET according to the first embodiment as shown in FIG. When 400 [A / cm ² ] forward current of the parasitic diode is applied to the SiC-MOSFET according to the first comparative example, the stacking fault 30a expanded in the vertical direction inside the active portion 101 as shown in FIG. Occurred and the on-resistance increased.

(Second comparative example)
As shown in FIG. 8, the SiC-MOSFET according to the second comparative example is provided with a p-type auxiliary contact region 5 f having a very narrow width around the active portion 101. And different. In the SiC-MOSFET according to the second comparative example, similarly to the case of the first comparative example, when a forward current of 400 [A / cm ² ] is applied to the parasitic diode, the stacking fault 30 expanded in the vertical direction is generated. On-resistance increased.

(Third comparative example)
As shown in FIG. 9, the SiC-MOSFET according to the third comparative example has the lengths of the channel regions 3g1, 3h1, the source regions 4g1, 4h1, and the base contact region 5d1 in the cell structure on the left side of the active portion 101. It is shorter than the case of one comparative example. The lengths of the channel regions 3i1, 3j1, the source regions 4i1, 4j1 and the base contact region 5e1 of the right cell structure are also shorter than in the first comparative example, and fan-shaped p-types are formed at the four corners of the rectangular active portion 101. Corner contact regions 5g1 to 5g4 are provided. In the SiC-MOSFET according to the third comparative example, as in the case of the first comparative example, when a forward current of 400 [A / cm ² ] is applied to the parasitic diode, a stacking fault expanded in the vertical direction occurs. On-resistance increased.

  In the SiC-MOSFET according to the first embodiment, conduction inducing regions (12a, 13a) that are diode regions are provided between the active part 100 and the termination structure region 14, and current during reverse conduction is induced by conduction. It is guided to the region (12a, 13a) side. Then, using equation (1), the sum of the areas of the upper well contact regions 13a joined to the source electrode 9 is made larger than the sum of the junction areas of the base contact regions 5a and 5b of the active part 100 to the source electrode 9. Is controlled.

  Therefore, during reverse conduction of the SiC-MOSFET, current is positively induced in the conduction induction region (12a, 13a), and energy for growing the stacking fault 30 is largely consumed in the conduction induction region (12a, 13a). The energy for growing the stacking faults 30 in the active part 100 is relatively reduced due to the energy consumption in the conduction induction regions (12a, 13a), so that the expansion of the stacking faults 30 can be largely suppressed.

  Considering this point, for example, a case where diode structures for simply inducing current other than the active portion 100 are connected in parallel, the conduction induction regions (12a, 13a) are provided and the total area of the upper well contact region 13a is determined. Compared to control, extra wiring is required. On the other hand, in the case of the SiC-MOSFET according to the first embodiment, a static characteristic equivalent to a diode structure connected in parallel can be realized, and the current flowing transiently to the active part 100 side is equivalent to the absence of wiring inductance. Can be reduced.

  In the SiC-MOSFET according to the first embodiment, a termination structure region 14 that is a breakdown voltage region is further provided outside the conduction induction region (12a, 13a) and on the periphery of the semiconductor chip. Therefore, it is possible to further increase the breakdown voltage as a semiconductor device while suppressing generation of the stacking fault 30 by the conduction induction regions (12a, 13a).

  In addition, since the conduction induction regions (12a, 13a) have the same length in the vertical direction as that of the active portion 100, the stacking fault 30 extending in the vertical direction in a band shape is reliably retained inside, and the ripple is transmitted to the active portion 100. Can be prevented.

  Further, when the width w of the conduction inducing region (12a, 13a) satisfies the formula (2), the extension of the stacking fault 30 extending along the terrace surface of the inclined epitaxial growth film is caused to extend inside the conduction inducing region (12a, 13a). To be held in. Therefore, the width w is greatly secured so as to include the maximum extension width of the stacking fault, so that the stacking fault 30 does not occur immediately below the active portion 100 adjacent in the <11-20> direction. Therefore, the influence on the on-characteristics of the MOSFET can be prevented.

  Further, in the SiC-MOSFET according to the first embodiment, the two conduction induction regions are disposed at both ends of the active portion 100 in a state where they are separated as much as possible. Therefore, the heat generated in each conduction induction region is efficiently dispersed in the semiconductor chip, and the quality of the SiC-MOSFET can be prevented from deteriorating.

<Method for Manufacturing Semiconductor Device>
Next, a method for manufacturing the SiC-MOSFET according to the first embodiment will be described with reference to FIGS. First, as the SiC substrate, for example, an n ⁺ -type 4H—SiC single crystal, which has a (0001) plane as a surface and a semiconductor substrate 10 _sub off by 4 ° with respect to the <11-20> direction is prepared. Then, as shown in FIG. 10, an n-type 4H—SiC drift layer 1 doped (doped) with, for example, nitrogen (N) is deposited on the semiconductor substrate 10 _sub by an epitaxial growth method with a thickness d of about 10 μm. Epitaxially grow.

  Next, as shown in FIG. 11, a mask 21a having an opening at a predetermined position is formed on the upper surface of the drift layer 1 using a photolithography technique and an etching technique, and aluminum, for example, is formed through the opening. Ions of p-type impurity elements such as (Al) and boron (B) are selectively implanted. By this ion implantation, planned regions that will later form the lower conductive region 12a and the base regions 2a and 2b are formed. In FIG. 11, the outer edges of the respective scheduled areas are schematically illustrated by broken lines. The ion implantation is performed so that the lower conductive region 12a and the base regions 2a and 2b have the same impurity density, the same depth, and the same thickness in the drift layer 1 when the predetermined region is activated. The acceleration voltage of the implanted ions is adjusted.

  Next, the mask 21 a is removed, and the acceleration voltage is suppressed so that ions of the p-type impurity element are accumulated in the vicinity of the upper surface of the drift layer 1 through a new mask formed on the upper surface of the drift layer 1. Inject selectively. By this ion implantation, planned regions that later partially form channel regions 3a to 3c are formed on the base regions 2a and 2b, respectively. Then, the mask for forming the channel regions 3a to 3c is removed.

  Next, ions of an n-type impurity element such as phosphorus (P), N, etc. are selectively introduced into the planned regions of the channel regions 3 a to 3 c through a new mask formed on the upper surface of the drift layer 1. Implantation is performed to form planned regions that will later form source regions 4a to 4c. Then, the mask for forming the source regions 4a to 4c is removed.

  Next, as shown in FIG. 12, through the new mask 21b formed on the upper surface of the drift layer 1, ions of the p-type impurity element are supplied into the source regions 4a to 4c in the planned regions of the channel regions 3a to 3c. Inject selectively during 4c. By this ion implantation, a planned region that later forms the upper well contact region 13a is formed on the lower conductive region 12a, and a planned region that later forms the base contact regions 5a and 5b is formed. In FIG. 12, the outer edge of each scheduled area is schematically illustrated by a broken line.

Then, the mask 21b is removed, and ions of a p-type impurity element are selectively implanted into the periphery of the semiconductor substrate 10 _sub by using a photolithography technique and an etching technique. Form. Then, the respective planned regions are activated by activation annealing or the like, and as shown in FIG. 13, base regions 2a and 2b, channel regions 3a to 3c, source regions 4a to 4c and base contact regions 5a and 5b are formed. To do. The lower conductive region 12a, the upper well contact region 13a, and the termination structure region 14 are also formed by the activation.

Next, for example, a silicon oxide (SiO ₂ ) film or the like is deposited on the surface of the drift layer 1 by thermal oxidation or the like, and the deposited film is patterned by a photolithography technique, an etching technique, or the like to form the gate insulating films 6a and 6b. Form. Next, a doped polysilicon film or the like to which an n-type impurity element such as P is added at a high impurity density is deposited on the entire surface by a low pressure CVD method or the like. Then, the doped polysilicon film is patterned by a process such as etching or chemical mechanical polishing (CMP) to form gate electrodes 7a and 7b.

Next, for example, a CVD method or the like is used to deposit an SiO ₂ film or the like on the entire surface, and this deposited film is patterned using a photolithography technique and an etching technique, and interlayer insulating films 8a and 8b are formed on the gate electrodes 7a and 7b. Is provided. Next, the lower surface of the semiconductor substrate 10 _sub is thinned and flattened by CMP or the like to form the drain region 10 as shown in FIG. Then, a metal film such as nickel (Ni) is formed under the drain region 10, and the formed metal film is patterned to form the drain electrode 11.

  Then, after performing predetermined annealing or the like as necessary, an alloy film containing Al as a main component is deposited, for example, and patterned into a predetermined shape by photolithography technology and etching technology to form the source electrode 9 To do. The source electrode 9 is provided over the drift layer 1, the base contact regions 5a and 5b, and the upper well contact region 13a. Thereafter, a sintering process or the like by annealing is performed. Through the above series of steps, the SiC-MOSFET according to the first embodiment can be obtained.

  In the method of manufacturing the SiC-MOSFET according to the first embodiment, ion implantation into the planned region forming the lower conductive region 12a and the base regions 2a and 2b is simultaneously performed by the same process. In addition, ion implantation into the planned region forming the upper well contact region 13a and the base contact regions 5a and 5b is simultaneously performed by the same process. Therefore, it is not necessary to provide a separate process with a large special burden in manufacturing the SiC-MOSFET provided with the conduction induction regions (12a, 13a). Therefore, it is possible to manufacture a SiC-MOSFET that can suppress the expansion of the stacking fault 30 while suppressing the burden of a further additional process.

<First Modification>
Next, a modification of the SiC-MOSFET according to the first embodiment will be described with reference to FIGS. As shown in FIG. 15, the SiC-MOSFET according to the first modified example has <-in addition to the structure of the SiC-MOSFET according to the first embodiment shown in FIG. And auxiliary base contact regions 5h1 and 5h2 extending in the 11-20> direction.

  The width L of the auxiliary base contact regions 5h1 and 5h2 is very narrow compared to the width w of the conduction induction region. For example, the width w of the conduction induction region is about 143 μm or more, but the width of the auxiliary base contact regions 5h1 and 5h2 is about 5 μm or less. Therefore, even if the areas of the auxiliary base contact regions 5h1 and 5h2 are included in the sum of the areas of the base contact regions 5a and 5b of the active part 100, the sum of the areas of the upper well contact regions 13a and 13b is more active. It is controlled to be larger than 100 side.

  Similarly to the SiC-MOSFET shown in FIG. 2, the concentration of the lower conduction region 12a is controlled to be high so that the conduction induction regions (12a, 13a) function as well contact regions as a whole. . The other structure of the SiC-MOSFET according to the first modification is equivalent to the member of the same name in the SiC-MOSFET shown in FIGS.

Even if the SiC-MOSFET according to the first modification is supplied with 400 [A / cm ² ] forward current of the parasitic diode at 175 ° C., the stacking fault 30 does not occur in the active part 100 and the on-resistance increases. I didn't. Moreover, the fluctuation of the forward voltage drop of the parasitic diode could be suppressed to 0.5% or less.

  Also in the SiC-MOSFET according to the first modification, current is positively induced in the conduction induction region during reverse conduction. Therefore, the energy for growing the stacking fault 30 is largely consumed in the conduction induction region, and the generation of the stacking fault 30 in the active part 100 can be suppressed.

  Further, according to the SiC-MOSFET according to the first modification, the structure of the base contact region of the active part 100 can be flexibly changed, so that the compatibility with a desired specification can be improved. Other effects of the SiC-MOSFET according to the first modification are the same as those of the SiC-MOSFET according to the first embodiment. The auxiliary base contact regions 5h1 and 5h2 may or may not be connected to the left and right conduction induction regions.

<Second Modification>
As in the SiC-MOSFET according to the second modification shown in FIG. 16, in addition to both ends of the semiconductor chip, a conduction induction region may be further provided in the center. In FIG. 16, the upper well contact provided at the center is divided so that the upper surface of the two upper well contact regions 13a and 13b at both ends and the distance between the two upper well contact regions 13a and 13b are divided into two equal parts. The upper surface of the region 13c appears.

  An active portion 100a is located between the left upper well contact region 13a and the central upper well contact region 13c, and an active portion 100b is located between the right upper well contact region 13b and the central upper well contact region 13c. Is located. The three conduction induction regions all have the same width w that satisfies the above formula (2). The other structure of the SiC-MOSFET according to the second modification is equivalent to the member of the same name in the SiC-MOSFET according to the first embodiment.

  Also in the SiC-MOSFET according to the second modification, the sum of the areas of the upper well contact regions 13a to 13c joined to the source electrode is equal to the junction area of the base contact regions 5a and 5c of the active portions 100a and 100b with the source electrode. It is controlled to be larger than the sum. Therefore, at the time of reverse conduction, current is positively induced in the conduction induction region, and generation of stacking faults in the active part 100 can be suppressed.

  Moreover, according to the SiC-MOSFET according to the second modification, it is possible to more reliably suppress the occurrence of stacking faults by increasing the conduction induction region. Other effects of the SiC-MOSFET according to the second modification are the same as those of the SiC-MOSFET according to the first embodiment. Note that the number of conduction induction regions may be three or more, or may be one.

<Third Modification>
Like the SiC-MOSFET according to the third modification shown in FIG. 17, the conduction induction regions (22a, 23a) may be deeper than the base regions 2a, 2b. In addition, the lower conduction region 22a and the upper well contact region 23a of the conduction induction regions (22a, 23a) are both high-concentration p ⁺⁺ type. The other structure of the SiC-MOSFET according to the third modification is equivalent to the member of the same name in the SiC-MOSFET according to the first embodiment.

  Also in the SiC-MOSFET according to the third modification, the sum of the areas of the upper well contact regions 23a joined to the source electrode 9 is greater than the sum of the junction areas of the base contact regions 5a and 5b of the active portion 100 to the source electrode 9. It is controlled to be large. Therefore, during reverse conduction, current is positively induced in the conduction induction regions (22a, 23a), and generation of stacking faults in the active part 100 can be suppressed.

  Further, according to the SiC-MOSFET according to the third modification, the conduction induction regions (22a, 23a) are formed deeper than the base regions 2a, 2b, so that current during reverse conduction is supplied to the conduction induction regions (22a, 23a). It becomes easier to guide to the side. Furthermore, since the impurity concentration of the conduction induction regions (22a, 23a) is further increased than that of the base contact regions 5a, 5b, the inductivity is further increased. Other effects of the SiC-MOSFET according to the third modification are the same as those of the SiC-MOSFET according to the first embodiment.

<Fourth Modification>
Like the SiC-MOSFET according to the fourth modification shown in FIG. 18, the conduction induction regions (22a, 23a) may be connected to the base regions 2a, 2b and the base contact regions 5a, 5b of the active part 100. . The conduction induction regions (22a, 23a) shown in FIG. 18 have a structure equivalent to the conduction induction regions (22a, 23a) of the SiC-MOSFET according to the third modification shown in FIG. The other structure of the SiC-MOSFET according to the fourth modification is equivalent to the member of the same name in the SiC-MOSFET according to the first embodiment.

  That is, if the inductivity of the current at the time of reverse conduction to the conduction induction region (22a, 23a) side is enhanced, the active portion 100 and the conduction induction region (22a, 22a, 22b) as in the SiC-MOSFET according to the fourth modification example. 23a) may be eliminated. Also in the SiC-MOSFET according to the fourth modification, the sum of the areas of the upper well contact regions 23a joined to the source electrode 9 is greater than the sum of the junction areas of the base contact regions 5a and 5b of the active part 100 to the source electrodes 9. It is controlled to be large. Therefore, during reverse conduction, current is positively induced in the conduction induction regions (22a, 23a), and generation of stacking faults in the active part 100 can be suppressed.

  In addition, according to the SiC-MOSFET according to the fourth modification, the isolation region between the active part 100 and the conduction induction regions (22a, 23a) is not necessary, so that the area of the active part 100 can be secured larger. Other effects of the SiC-MOSFET according to the fourth modification are the same as those of the SiC-MOSFET according to the first embodiment.

-Second Embodiment-
As shown in FIG. 19, the conduction inducing region of the SiC-MOSFET according to the second embodiment has a planar pattern, and a plurality of upper conductive base regions 16 and a plurality of cells provided inside the upper conductive base region 16. The upper well contact region 15 is different from the SiC-MOSFET according to the first embodiment. The cell-like upper well contact region 15 has a substantially hexagonal column shape, and is provided so as to extend between the lower conductive region 12a and the upper surface of the drift layer 1, as shown in FIG.

The doping concentration of the upper conductive base region 16 is, for example, about 1.0 × 10 ¹⁸ cm ⁻³ . Further, the doping concentration of the cell-like upper well contact region 15 may be equal to or higher than the doping concentration of the base contact regions 5a and 5b. For example, when the doping concentration of the base contact regions 5a and 5b is about 1.0 × 10 ¹⁹ cm ⁻³ , the doping concentration of the upper well contact region 15 is also set to about 1.0 × 10 ¹⁹ cm ⁻³ or more. Since the other structure of the SiC-MOSFET according to the second embodiment is equivalent to the member of the same name in the SiC-MOSFET according to the first embodiment, the duplicate description is omitted.

  The SiC-MOSFET according to the second embodiment also satisfies the same relationship as the above formula (1). That is, the sum of the areas of the upper surfaces of all the cell-like upper well contact regions 15 joined to the source electrode 9 is larger than the sum of the junction areas of the base contact regions 5a to 5c of the active part 100 to the source electrode 9. It is controlled. Further, the width w of the conduction induction region (12a, 15, 16) is set so that the relationship of the above expression (2) is satisfied.

  Also in the SiC-MOSFET according to the second embodiment, during reverse conduction, current is actively induced in the conduction induction region (12a, 15, 16), and the energy for growing stacking faults is the conduction induction region (12a). , 15, 16). Therefore, occurrence of stacking faults in the active part 100 can be suppressed. Other effects of the SiC-MOSFET according to the second embodiment are the same as those of the SiC-MOSFET according to the first embodiment. The cell shape of the upper well contact region 15 is not limited to a hexagonal shape, and can be appropriately changed to other polygonal shapes, circular shapes, elliptical shapes, or the like.

<Fifth Modification>
In the SiC-MOSFET according to the second embodiment, the vertical arrangement density of the cell-like upper well contact regions 15a to 15c is constant, as in the SiC-MOSFET according to the fifth modification shown in FIG. It does not have to be. However, it is preferable that the cell-like upper well contact regions 15a to 15c are arranged so that the density becomes higher as the distance from the active part 100 increases, and conversely, the density becomes lower as the distance from the active part 100 becomes closer. .

  For example, the number of cells included in the range X in FIG. 21 is five consecutive cells below the upper well contact region 15a on the left and four consecutive cells below the central upper well contact region 15b. There are two series of cells following the upper well contact region 15c on the right side. By increasing the cell density from the active part 100 side toward the termination structure region 14 side, it becomes possible to further suppress the injection of holes directly under the active part 100, so that the characteristic deterioration of the MOSFET can be prevented more reliably.

-Other embodiments-
Although the present invention has been described with reference to the above disclosed embodiments, it should not be understood that the descriptions and drawings constituting a part of this disclosure limit the present invention. From this disclosure, it should be understood that various alternative embodiments, examples, and operational techniques will become apparent to those skilled in the art.

  For example, as shown in FIG. 22, the semiconductor chip 44 of SiC-MOSFET according to the first and second embodiments is mounted on an insulating circuit substrate (41, 42, 43), and a power semiconductor module (41, 42, 43, 44) can also be realized. The insulating circuit board (41, 42, 43) includes an insulating substrate 41, a front surface metal foil 42 provided on the upper surface of the insulating substrate 41, and a back surface metal foil 43 provided on the lower surface of the insulating substrate 41. . Since the semiconductor chip 44 includes the conduction inducing region, the expansion of stacking faults in the active portion is suppressed, so that current deterioration of the power semiconductor module is suppressed and the conduction loss can be reduced.

  In the first and second embodiments, the transistor structure cell has been described as a stripe shape. However, the present invention is not limited to this, and for example, a polygonal shape or other shapes may be adopted. Also, the gate structure of the transistor has been described as a planar type, but may be a trench type. Further, although the n-type has been described as the first conductivity type and the p-type has been described as the second conductivity type, the present invention can also be realized by inverting the conductivity type.

  In the first and second embodiments, the tilt direction defining the tilt angle θ of the substrate has been described as the <11-20> direction from the (0001) plane or the (000-1) plane. Even if defined in a direction other than the <11-20> direction, the present invention holds. In addition, although the inclination angle θ is illustratively described as 4 °, the present invention is not limited to this. For example, the inclination angle θ can be set to about 8 °.

  Moreover, you may comprise the SiC-MOSFET which concerns on this invention combining the partial structure of each SiC-MOSFET shown in FIGS. As described above, the present invention includes various embodiments and the like not described above, and the technical scope of the present invention is defined only by the invention specifying matters according to the appropriate claims from the above description. Is.

1 Drift layer 2a, 2b Base region 3a-3j, 3g1-3j1 Channel region 4a-4j, 4g1-4j1 Source region 5a-5e, 5d1, 5e1 Base contact region 5f Auxiliary contact region 5g1-5g4 Corner contact region 5h1, 5h2 Auxiliary base contact regions 6a, 6b Gate insulating films 7a, 7b Gate electrodes 8a, 8b Interlayer insulating film 9 Source electrode 10 Drain region 10 _Sub semiconductor substrate 11 Drain electrode 12a Lower conduction regions 13a, 13b, 13c Upper well contact region 14 Termination structure Regions 15, 15a, 15b, 15c Upper well contact region 16 Upper conduction base regions 21a, 21b Mask 22a Lower conduction region 23a Upper well contact regions 30, 30a Stacking fault 41 Insulating substrate 42 Surface metal foil 43 Surface metal foil 44 semiconductor chips 100, 100a, the width θ angle of inclination of the thickness L auxiliary base contact region 100b active portion 101 active portion w-conductive guiding area width d drift layer

Claims (13)

A first conductivity type drift layer made of a silicon carbide semiconductor substrate, a second conductivity type base region provided above the drift layer, and a first conductivity type source region selectively provided above the base region A gate insulating film provided on the drift layer, a gate electrode provided on the gate insulating film, a source electrode provided on the drift layer, and on the base region above the drift layer A second conductivity type base contact region provided in contact with the source electrode, a first conductivity type drain region provided under the drift layer, and a drain electrode provided under the drain region. An active part,
A termination structure region as a withstand voltage region provided outside the active portion;
The upper surface of the drift layer between the active portion and the termination structure region is provided to be joined to the source electrode, and the junction area with the source electrode is joined to the source electrode in the base contact region. A second conductivity type conduction induction region set larger than the area;
A silicon carbide MOSFET comprising: The width w of the conduction induction region along the tilt direction of the silicon carbide semiconductor substrate is between the thickness d of the drift layer and the tilt angle θ of the silicon carbide semiconductor substrate.

The silicon carbide MOSFET according to claim 1, wherein: The conduction induction region has an upper well contact region having the upper surface joined to the source electrode,
3. The silicon carbide MOSFET according to claim 1, wherein an impurity concentration of the upper well contact region is equal to or higher than an impurity concentration of the base contact region.   The silicon carbide MOSFET according to any one of claims 1 to 3, wherein an auxiliary base contact region is further provided in the active portion.   5. The silicon carbide MOSFET according to claim 1, wherein three or more conduction induction regions are provided at equal intervals.   The silicon carbide MOSFET according to any one of claims 1 to 5, wherein the conduction induction region is provided deeper than the base contact region.   The silicon carbide MOSFET according to any one of claims 1 to 6, wherein the conduction induction region and the base contact region are connected to each other.   4. The silicon carbide MOSFET according to claim 3, wherein the upper well contact region has a plurality of cell shapes.   9. The silicon carbide MOSFET according to claim 8, wherein the plurality of cellular upper well contact regions are arranged so as to increase in density from the active portion toward the termination structure region.   A power semiconductor module comprising the silicon carbide MOSFET according to any one of claims 1 to 9. Forming a base region of the second conductivity type on the drift layer of the first conductivity type made of a silicon carbide semiconductor substrate, selectively forming a source region of the first conductivity type on the base region; A gate insulating film is formed on the gate insulating film, a gate electrode is formed on the gate insulating film, a source electrode is formed on the drift layer, and a second conductive layer is formed on the base region above the drift layer. A base contact region of a type is formed by bonding with the source electrode, a drain region of the first conductivity type is formed under the drift layer, and a drain electrode is formed under the drain region to form an active portion And a process of
Forming a termination structure region as a breakdown voltage region outside the active portion;
The upper surface of the drift layer between the active portion and the termination structure region is joined to the source electrode, and the junction area with the source electrode is larger than the junction area with the source electrode in the base contact region. Forming a second conductivity type conduction inducing region to be large;
A method for producing a silicon carbide MOSFET, comprising: The conduction induction region has a lower conduction region and an upper well contact region provided on the lower conduction region,
12. The method for manufacturing a silicon carbide MOSFET according to claim 11, wherein the formation of the lower conductive region and the formation of the base region are performed by the same ion implantation.   13. The method for manufacturing a silicon carbide MOSFET according to claim 12, wherein the upper well contact region and the base contact region are formed by the same ion implantation.

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