JP2018200919A - Semiconductor device and manufacturing method for the same - Google Patents

Abstract

To provide a trench-gate semiconductor device capable of selectively and easily increasing a thickness of a gate insulation film at a bottom surface side of a trench.SOLUTION: A trench-gate semiconductor device includes: an ntype drift layer 2; p type base areas 3a, 3b arranged at an upper surface side of the drift layer 2; ntype source regions 4a, 4b arranged on upper parts of the base areas 3a, 3b; gate insulation films (61, 63) provided at least on the surface where the base areas 3a, 3b at a trench 12 side going through the source regions 4a, 4b and the base areas 3a, 3b are exposed; a trench bottom-embedded insulating film 62 which is provided so as to be brought into contact with the gate insulation films (61, 63) in the way that a lower part of the trench 12 is embedded, and is composed of a non-calcinated insulating film smaller in dielectric constant smaller than those of the gate insulation films (61, 63); a gate embedding electrode 7 embedded in an upper part of the trench bottom-embedded insulating film 62 in the trench 12 via the gate insulation films (61, 63); and a drain region 1 arranged at a lower surface side of the drift layer 2.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a trench gate type semiconductor device and a manufacturing method thereof.

  The trench gate type semiconductor device can be expected to reduce the on-resistance by reducing the cell pitch compared to the planar type, but there is a concern that a high electric field is generated at the bottom of the trench and breakdown due to dielectric breakdown of the gate insulating film may occur. .

  Therefore, in order to ensure the breakdown voltage at the bottom of the trench, it has been studied to increase the thickness of the gate insulating film on the bottom of the trench. As a method of increasing the thickness of the gate insulating film on the bottom surface of the trench, there has been proposed a method in which an oxide film is formed on the bottom surface and side surfaces of the trench and then dielectric particles are filled in the lower portion of the trench (see Patent Document 2). . In addition, a method of depositing an oxide film only on the bottom surface of a trench by a high density plasma chemical vapor deposition (HDP-CVD) method has been proposed (see Patent Document 3).

  However, the method described in Patent Document 2 has a problem that gaps between dielectric fine particles filled in the trench are generated. Further, in the method described in Patent Document 3, it is actually difficult to form an oxide film only on the bottom surface of the trench by the HDP-CVD method.

Japanese Patent Laid-Open No. 2006-76553 Japanese Patent No. 4791723 Japanese Patent No. 5243671

  In view of the above problems, an object of the present invention is to provide a trench gate type semiconductor device and a method for manufacturing the same, in which the thickness of the gate insulating film on the bottom surface side of the trench can be selectively and easily increased.

  One embodiment of the present invention includes (a) a first conductivity type drift layer, (b) a second conductivity type base region disposed on an upper surface side of the drift layer, and (c) an upper portion of the base region. A first conductive type first main electrode region having a higher impurity density than the drift layer, and (d) a gate provided at least on a surface exposing a base region on a side surface of the trench penetrating the first main electrode region and the base region An insulating film, and (e) a trench bottom buried insulating film made of a fired insulating film having a relative dielectric constant smaller than that of the gate insulating film, provided in contact with the gate insulating film so as to bury the lower portion of the trench on the bottom side of the trench, (F) a gate embedded electrode embedded via a gate insulating film above the trench bottom embedded insulating film in the trench, and (g) a second main electrode region disposed on the lower surface side of the drift layer. A semiconductor characterized by And summarized in that a location.

  In another aspect of the present invention, (a) a step of forming a second conductivity type base region on the upper surface side of the first conductivity type drift layer, (b) a step of forming a trench penetrating the base region, (C) forming a gate insulating film on at least the side surface of the trench; (d) applying a photosensitive resin film so as to fill the trench; and (e) exposing the applied photosensitive resin film halfway. A step of leaving a non-photosensitive region under the trench; (f) a step of developing and selectively removing the exposed photosensitive resin film; and (g) a baking insulating film by baking the remaining photosensitive resin film. Forming a trench bottom buried insulating film comprising: (h) burying a gate buried electrode via a gate insulating film above the trench bottom buried insulating film in the trench; and (i) forming a base region Higher impurity density at the top than the drift layer And summarized in that a method of manufacturing a semiconductor device which comprises a step of forming a first main electrode region of the first conductivity type.

  In another aspect of the present invention, (a) a step of forming a second conductivity type base region on the upper surface side of the first conductivity type drift layer, (b) a step of forming a trench penetrating the base region, (C) a step of applying a photosensitive resin film so as to fill the trench, (d) a step of exposing the applied photosensitive resin film halfway to leave a non-photosensitive region below the trench, and (e) photosensitivity. (G) a step of developing and selectively removing the photosensitive resin film, and (f) baking the remaining photosensitive resin film to form a trench bottom embedded insulating film made of the fired insulating film; Forming a gate insulating film on at least a side surface of the trench; (h) embedding a buried gate electrode through the gate insulating film above the trench bottom buried insulating film in the trench; and (i) forming a base region Higher impurity density at the top than the drift layer The method of manufacturing a semiconductor device which comprises a step of forming a first main electrode region of the first conductivity type.

  According to the present invention, it is possible to provide a trench gate type semiconductor device and a method for manufacturing the same, in which the thickness of the gate insulating film on the bottom surface side of the trench can be selectively and easily increased.

It is principal part sectional drawing which shows an example of the semiconductor device which concerns on embodiment of this invention. It is process sectional drawing for demonstrating an example of the manufacturing method of the semiconductor device which concerns on embodiment of this invention. FIG. 3 is a process cross-sectional view subsequent to FIG. 2 for illustrating an example of the method for manufacturing the semiconductor device according to the embodiment of the present invention. FIG. 4 is a process cross-sectional view subsequent to FIG. 3 for describing an example of the method for manufacturing the semiconductor device according to the embodiment of the present invention. FIG. 5 is a process cross-sectional view subsequent to FIG. 4 for illustrating an example of the method for manufacturing the semiconductor device according to the embodiment of the present invention. FIG. 6 is a process cross-sectional view subsequent to FIG. 5 for illustrating an example of the method for manufacturing the semiconductor device according to the embodiment of the present invention. FIG. 7 is a process cross-sectional view subsequent to FIG. 6 for illustrating an example of the method for manufacturing the semiconductor device according to the embodiment of the present invention. FIG. 8 is a process cross-sectional view subsequent to FIG. 7 for illustrating the exemplary method for manufacturing the semiconductor device according to the embodiment of the present invention. FIG. 9 is a process cross-sectional view subsequent to FIG. 8 for describing an example of the method for manufacturing the semiconductor device according to the embodiment of the present invention. FIG. 10 is a process cross-sectional view subsequent to FIG. 9 for describing an example of the method for manufacturing the semiconductor device according to the embodiment of the present invention. FIG. 11 is a process cross-sectional view subsequent to FIG. 10 for illustrating an example of the method for manufacturing the semiconductor device according to the embodiment of the present invention. It is principal part sectional drawing which shows an example of the semiconductor device which concerns on the 1st modification of embodiment of this invention. It is principal part sectional drawing which shows an example of the semiconductor device which concerns on the 2nd modification of embodiment of this invention. It is principal part sectional drawing which shows an example of the semiconductor device which concerns on the 3rd modification of embodiment of this invention. It is principal part sectional drawing which shows an example of the semiconductor device which concerns on other embodiment of this invention. It is principal part sectional drawing which shows another example of the semiconductor device which concerns on other embodiment of this invention. It is principal part sectional drawing which shows another example of the semiconductor device which concerns on other embodiment of this invention.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the description of the drawings referred to in the following description, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thickness of each layer, and the like are different from the actual ones. Therefore, specific thicknesses and dimensions should be determined in consideration of the following description. Moreover, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings.

  In the present specification, the “first main electrode region” means a semiconductor region that is either a source region or a drain region in a field effect transistor (FET) or a static induction transistor (SIT). In an insulated gate bipolar transistor (IGBT), a semiconductor region that is either an emitter region or a collector region is used. In an electrostatic induction thyristor (SI thyristor) or a gate turn-off thyristor (GTO), either an anode region or a cathode region is used. It means a semiconductor region that becomes one side. The “second main electrode region” refers to a semiconductor region that is either a source region or a drain region that is not the first main electrode region in the FET or SIT, and the first main electrode region in the IGBT. The region that becomes either the emitter region or the collector region that does not become a region means the region that becomes either the anode region or the cathode region that does not become the first main electrode region in the SI thyristor or GTO. That is, if the “first main electrode region” is the source region, the “second main electrode region” means the drain region. If the “first main electrode region” is an emitter region, the “second main electrode region” means a collector region. If the “first main electrode region” is an anode region, the “second main electrode region” means a cathode region.

  In the following description of the embodiment, the case where the first conductivity type is n-type and the second conductivity type is p-type will be exemplarily described. However, the conductivity type is selected in the reverse relationship, and the first conductivity type is p. The type and the second conductivity type may be n-type. Further, in this specification and the accompanying drawings, + and − attached to superscripts of n and p are semiconductors whose impurity concentration is relatively higher or lower than that of a semiconductor region where + and − are not added. Means an area. Furthermore, in the following description, the members and regions to which the “first conductivity type” and the “second conductivity type” are added mean members and regions made of a semiconductor material without any particular limitation. Is obvious both technically and logically.

  Furthermore, in the following description, the definitions of “upper” and “lower” such as “upper surface” and “lower surface” are merely representational problems on the illustrated cross-sectional view. For example, the orientation of the semiconductor device is changed by 90 °. Observing, the names “upper” and “lower” become “left” and “right”, and if the observation is changed by 180 °, the relationship between the names “upper” and “lower” is of course reversed.

<Structure of semiconductor device>
An insulated gate FET (MISFET) having a trench gate will be described as a semiconductor device according to an embodiment of the present invention. As shown in FIG. 1, the semiconductor device according to the embodiment of the present invention includes a first conductivity type (n ⁻ type) drift layer 2 and a second conductivity type (p type) arranged on the upper surface side of the drift layer 2. ) Base regions 3a and 3b, and a first main electrode region (source region) 4a of the first conductivity type (n ⁺ type) having a higher impurity density than the drift layer 2 and disposed above the base regions 3a and 3b. 4b.

Above the base regions 3a and 3b, second contact type (p ⁺ -type) base contact regions 5a and 5b having a higher impurity density than the base regions 3a and 3b are provided so as to be in contact with the source regions 4a and 4b. Yes. A trench 12 is provided through the source regions 4a and 4b and the base regions 3a and 3b so as to reach the drift layer 2 from the upper surfaces of the source regions 4a and 4b. Gate insulating films (61, 63) are provided on the bottom and side surfaces of the trench 12, and the buried gate electrode 7 is embedded in the trench 12 via the gate insulating film (61, 63).

On the gate buried electrode 7, a first main electrode (source electrode) 9 is disposed separately from a gate surface electrode (not shown) located at the back of the paper surface via an interlayer insulating film 8. The source electrode 9 is in contact with the source regions 4a and 4b and the base contact regions 5a and 5b. On the lower surface side of the drift layer 2, a second main electrode region (drain region) 1 of the second conductivity type (n ⁺ type) is disposed so as to be in contact with the drift layer 2. The semiconductor device according to the embodiment of the present invention includes the structure shown in FIG. 1 as a unit cell structure, and a plurality of the unit cell structures are periodically arranged to form a multichannel structure.

  In the embodiment of the present invention, the drain region 1 is composed of a semiconductor substrate (SiC substrate) made of silicon carbide (SiC), and the drift layer 2 is made of an epitaxial layer (SiC layer) made of SiC. As the drain region 1 and the drift layer 2, in addition to SiC, a semiconductor material wider than the forbidden band width 1.1 eV of Si, such as silicon (Si), gallium nitride (GaN), diamond, or aluminum nitride (AlN), is used. Each can be used. The band gap at room temperature is 2.23 eV for 3C-SiC, 3.26 eV for 4H-SiC, 3.02 eV for 6H-SiC, 3.4 eV for GaN, 5.5 eV for diamond, and 6.2 eV for AlN. It has been reported. A wide bandgap semiconductor with a forbidden band width of 2.0 eV or more can be used as the drain region 1 and the drift layer 2, but a forbidden band width of 2.5 eV or more is defined as a “wide bandgap” in an LED or the like. There are many cases. In the present invention, the forbidden band width of the wide band gap semiconductor will be described with reference to the forbidden band width of 2.23 eV of 3C-SiC at room temperature.

  The bottom of the trench 12 that penetrates the source regions 4 a and 4 b and the base regions 3 a and 3 b in the depth direction reaches the drift layer 2. The width of the trench 12 is preferably about 0.5 μm to 1 μm, for example, and the depth of the trench 12 is preferably about 1 μm to 2 μm, for example. However, it will be understood from the following description that the width and depth of the trench 12 of the present invention are not limited to these values. Although FIG. 1 illustrates the case where the bottom surface of the trench 12 is a curved surface, the bottom surface of the trench 12 may be a flat surface. In order to alleviate electric field concentration at the bottom of the trench 12, a p-type well region (not shown) may be disposed at the bottom of the trench 12. In the embodiment of the present invention, the trenches 12 of each unit cell structure are arranged in a stripe pattern on the plane pattern, but the present invention is not limited to this. For example, the trench 12 may have a rectangular planar pattern or a polygonal planar pattern such as a hexagon.

  The thickness of the gate insulating film (61, 63) is, for example, about 20 nm to 150 nm. The gate insulating films (61, 63) have a laminated structure of the first gate insulating film 61 and the second gate insulating film 63 on the side surface side of the trench 12. In order to sufficiently suppress the electric field strength applied to the bottom of the trench 12, it is preferable that the thickness of the insulating film on the bottom surface side of the trench 12 is, for example, 5 times or more thicker than the side surface side of the trench 12. Therefore, at the bottom of the trench 12, the trench bottom buried insulating film 62 made of a fired insulating film is sandwiched between the first gate insulating film 61 and the second gate insulating film 63.

  That is, a trench inner dielectric film (61, 62, 63) having a three-layer structure including a first gate insulating film 61, a trench bottom buried insulating film 62, and a second gate insulating film 63 is formed at the bottom of the trench 12. Thus, the electric field strength applied to the bottom of the trench 12 is suppressed. For this reason, the thickness of the insulating film having a three-layer structure at the bottom of the trench 12 is, for example, about 100 nm to 750 nm, but may be about 750 nm or more when the trench 12 is deep.

  The first gate insulating film 61 is continuously provided on the bottom surface and side surfaces of the trench 12, and is in contact with the bottom surface of the trench 12 on the lower surface side of the trench bottom embedded insulating film 62. The first gate insulating film 61 is provided on the entire inner surface of the trench 12 including the position of the surface where the base regions 3 a and 3 b on the side surfaces of the trench 12 are exposed to the bottom surface of the trench 12. The trench bottom buried insulating film 62 is buried under the trench 12 in contact with the first gate insulating film 61 and the second gate insulating film 63. The second gate insulating film 63 is provided on the upper surface of the first gate insulating film 61 so as to extend from the position of the surface where the base regions 3a and 3b on the side surfaces of the trench 12 are exposed to the upper surface of the trench bottom buried insulating film 62. It has been. The second gate insulating film 63 covers the upper surface of the trench bottom buried insulating film 62 and is in contact with the gate buried electrode 7.

As the first gate insulating film 61 and the second gate insulating film 63, in addition to the silicon oxide film (SiO ₂ film), a strontium oxide (SrO) film having a relative dielectric constant larger than that of the SiO ₂ film, silicon nitride (Si ₃₎ N ₄ ) film, aluminum oxide (Al ₂ O ₃ ) film, magnesium oxide (MgO) film, yttrium oxide (Y ₂ O ₃ ) film, hafnium oxide (HfO ₂ ) film, zirconium oxide (ZrO ₂₎ ) Film, a tantalum oxide (Ta ₂ O ₅ ) film, a bismuth oxide (Bi ₂ O ₃ ) film, a single layer film, or a composite film in which a plurality of these layers are stacked can be employed. The first gate insulating film 61 and the second gate insulating film 63 may be made of the same material, or may be made of different materials.

  Each thickness of the first gate insulating film 61 and the second gate insulating film 63 is, for example, about 10 nm to 75 nm. The thickness of the first gate insulating film 61 may be the same as the thickness of the second gate insulating film 63, and the first gate insulating film 61 may be thicker or thinner than the second gate insulating film 63. May be. When the thickness of the first gate insulating film 61 is thicker than that of the second gate insulating film 63, the thickness of the first gate insulating film 61 may be about 15 nm to 100 nm, for example.

  The trench bottom buried insulating film 62 is a fired insulating film formed by firing a photosensitive resin film (photosensitive resin solution). As the photosensitive resin film, a material that can be applied by a spin coating method or the like, has positive photosensitivity, and becomes an insulating film when baked can be used. As the photosensitive resin film, for example, a photosensitive coated glass film called “spin-on-glass (SOG) film” can be used. The SOG liquid that is a component of the coated glass film is prepared from a siloxane component that is a coated glass film and an alcohol component as a solvent. When this solution is applied onto a substrate by spin coating or the like, the solvent is evaporated by heat treatment, and the film is cured, an SOG insulating film is formed. SOG is a general term for films formed with these solutions. SOG is classified into silica glass, alkylsiloxane polymer, alkylsilsesquioxane polymer (MSQ), hydrogenated silsesquioxane polymer (HSQ), hydrogenated alkylsilsesquioxane polymer (HOSP), etc., depending on the structure of siloxane. Is done.

  The positive photosensitive resin film according to the embodiment of the present invention includes, for example, at least two kinds of polysiloxanes, diazonaphthoquinone derivatives, photoacid generators, and solvents having different dissolution rates in an aqueous solution of tetramethylammonium hydroxide (TMAH). A positive-type photosensitive siloxane composition containing is preferred. As the polysiloxane having high heat resistance, silsesquioxane having a silanol group as a crosslinking point is preferable. The silanol group can impart high heat resistance by forming a siloxane bond by heating. Silsesquioxane is excellent in low-temperature curing and pattern stability. Silsesquioxanes called saddle type and ladder type have high crack resistance. Generally, saddle-type silsesquioxanes and ladder-type silsesquioxanes have low solubility in an alkaline developer because they have few free silanol groups. Therefore, as the positive photosensitive resin film according to the embodiment of the present invention, it is possible to use, for example, a combination of siloxane having low solubility in an alkali developer and siloxane having high solubility in an alkali developer.

The trench bottom buried insulating film 62 has a lower film density and lower mechanical strength than the first gate insulating film 61 and the second gate insulating film 63 formed by thermal oxidation or chemical vapor deposition. The relative dielectric constant of the thermal oxide film is about 3.5 to 4.2, but the relative dielectric constant of the SOG film can be about 2.1 to 3.0. The relative dielectric constant of the fired insulating film is lower than that of the first gate insulating film 61 and the second gate insulating film 63. When the trench bottom buried insulating film 62 is a fired insulating film of an SOG film, the trench bottom buried insulating film 62 can have an elastic modulus of about 6 GPa to 15 GPa and a hardness of about 0.7 GPa to 1.5 GPa. In addition, when the trench bottom buried insulating film 62 is a fired insulating film of an SOG film, microscopic vacancies of about 2 nm to 10 nm are almost uniformly dispersed from observation of a transmission electron microscope (TEM) image.

  The upper surface of the trench bottom buried insulating film 62 is flat because the transmission distance of the exposure light is constant before baking the SOG film, but becomes convex downward by baking the insulating film. On the other hand, since the cross-sectional shape of the bottom of the trench 12 is convex downward, the trench bottom embedded insulating film 62 has a crescent-shaped end surface shape having a curved surface whose upper and lower surfaces are convex downward. Have. The thickness of the trench bottom buried insulating film 62 is the thickest at the center in the width direction of the trench 12 and becomes thinner as the distance from the center is increased. The thickness of the trench bottom embedded insulating film 62 at the center in the width direction of the trench 12 is, for example, about 80 nm to 730 nm, and the exposure light transmission depth is appropriately set by adjusting the amount of light at the time of exposure. The thickness of the trench bottom embedded insulating film 62 made of an insulating film can be adjusted. However, if the trench 12 is deep, etc., it may be about 730 nm or more.

  The gate buried electrode 7 is provided above the trench bottom buried insulating film 62 in the trench 12 (on the upper surface side) via the first gate insulating film 61 and the second gate insulating film 63. As a material of the buried gate electrode 7, for example, a polysilicon layer (doped polysilicon layer) to which an n-type impurity is added can be used. As a material of the source electrode 9 and the gate surface electrode, for example, aluminum (Al), Al alloy such as Al-Si, Al-copper (Cu), Al-Cu-Si can be used. As the drain electrode 10, for example, a single layer film made of gold (Au) or a metal film laminated in the order of Al, nickel (Ni), Au can be used, and molybdenum (Mo), A metal plate such as tungsten (W) may be laminated.

  As an operation of the semiconductor device according to the embodiment of the present invention, when a positive voltage is applied to the drain electrode 10 and a positive voltage higher than the threshold is applied to the gate buried electrode 7, the gate buried electrode 7 in the base regions 3a and 3b is obtained. An inversion layer (channel) is formed on the side to be turned on. In the ON state, a current flows from the drain electrode 10 to the source electrode 9 through the drain region 1, the drift layer 2, the inversion layer of the base regions 3a and 3b, and the source regions 4a and 4b. On the other hand, when the voltage applied to the buried gate electrode 7 is less than the threshold value, the inversion layer is not formed in the base regions 3 a and 3 b, so that the inversion state occurs and no current flows from the drain electrode 10 to the source electrode 9.

  In the semiconductor device according to the embodiment of the present invention, the thickness of the trench bottom buried insulating film 62 buried in the lower portion of the trench 12 is adjusted, and the thickness of the dielectric film immediately below the gate buried electrode 7 is adjusted. It is easy to select arbitrarily. By increasing the thickness of the dielectric film immediately below the buried gate electrode 7, the electric field concentration at the bottom of the trench 12 can be relaxed, so that the breakdown voltage of the semiconductor device according to the embodiment of the present invention can be improved. Further, by providing the first gate insulating film 61 and the second gate insulating film 63 so as to sandwich the trench bottom buried insulating film 62, the dielectric film (dielectric film in the trench) around the gate buried electrode 7 is provided. Insulation and reliability can be improved.

<Method for Manufacturing Semiconductor Device>
Next, a method for manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to FIGS. Note that the method of manufacturing the trench gate type MISFET described below is an example, and can be realized by various other manufacturing methods including this modification as long as it is within the scope of the claims. Of course.

First, an n ⁺ type semiconductor substrate (SiC substrate) to which an n type impurity such as nitrogen (N) is added is prepared. Using this n ⁺ type SiC substrate as the drain region 1, an n ⁻ type drift layer 2 is epitaxially grown on the upper surface of the drain region 1. Subsequently, multi-stage ion implantation of p-type impurity ions such as Al is performed from the upper surface side of the drift layer 2. Thereafter, the implanted p-type ions are activated by heat treatment to form a p-type base region 3 as shown in FIG. Note that the base region 3 may be epitaxially grown on the upper surface of the drift layer 2.

  Next, a photoresist film 11 is applied on the drift layer 2, and the photoresist film 11 is patterned using a photolithographic technique. Using the patterned photoresist film 11 as a mask, by dry etching such as reactive ion etching (RIE) or the like, it penetrates through the base regions 3a and 3b and reaches the upper part of the drift layer 2 as shown in FIG. The trench 12 is selectively formed. Thereafter, the photoresist film 11 is removed by wet processing or the like. Alternatively, after forming an oxide film on the drift layer 2 and patterning the oxide film with a photoresist film, the trench 12 may be formed by dry etching using the oxide film as a mask.

Next, as shown in FIG. 4, a first gate insulating film 61 is formed on the bottom and side surfaces of the trench 12 and the top surfaces of the base regions 3a and 3b by thermal oxidation or the like. When forming a SiO ₂ film by thermally oxidizing SiC, for example, heat treatment may be performed at about 1000 ° C. in an oxygen atmosphere. Alternatively, a high temperature oxide film (HTO film) may be deposited as the first gate insulating film 61 by a low pressure CVD (LPCVD) method or the like.

  Next, as shown in FIG. 5, a photosensitive resin film (photosensitive resin solution) 62 x such as a photosensitive SOG solution is spin-coated on the upper surface of the first gate insulating film 61 to fill the trench 12. And the solvent etc. which were contained in the photosensitive resin film 62x are evaporated by heat processing (baking). Further, the photosensitive resin film 62x is patterned by a photolithography technique. That is, the photosensitive resin film 62x is exposed to exposure light having a predetermined wavelength to expose the entire surface of the photosensitive resin film 62x, the transmission distance of the exposure light is selected, and the photosensitive resin film 62x is partially exposed. Thus, a non-photosensitive region is left below the trench 12. If the photosensitive resin film 62x is sensitive to ultraviolet rays, for example, ultraviolet rays emitted from an excimer laser can be adopted as the exposure light. At this time, by adjusting the amount of exposure light and selecting the transmission distance of the exposure light, the depth at which the photosensitive resin film 62x is exposed is controlled to leave the photosensitive resin film 62x remaining in the lower portion of the trench 12. Control the thickness of the non-photosensitive area. As the amount of exposure light is increased, the transmission distance of exposure light is increased, so that the photosensitive resin film 62x is deeply exposed.

  Thereafter, when developed with an alkaline aqueous solution or the like, the photosensitive resin film 62x that has been exposed is selectively removed, and the photosensitive resin film 62x remains as a non-photosensitive region under the trench 12 after development. That is, the photosensitive resin film 62x which is the non-photosensitive region selectively remains in the depth direction of the trench 12, but the thickness of the photosensitive resin film 62x remaining as the non-photosensitive region decreases as the exposure amount is increased. To do.

  After development, the structure shown in FIG. 5 is subjected to acid cleaning and pure cleaning. Then, for example, by performing a heat treatment at about 700 ° C. to 900 ° C. for 30 minutes in an inert gas atmosphere such as argon (Ar) gas, the solvent in the photosensitive resin film 62x is volatilized, and the photosensitive resin film 62x is baked. To do. The upper surface of the photosensitive resin film 62x remaining as a non-photosensitive region is flat because the transmission distance of the exposure light is constant before baking, but is a cross-sectional shape that protrudes downward by baking the insulating film become. As a result, as shown in FIG. 6, a trench bottom embedded insulating film 62 made of a fired insulating film is formed below the trench 12. Since the bottom of the trench 12 has a shape that protrudes downward, the trench bottom embedded insulating film 62 has a crescent-shaped cross-sectional shape having a curved surface whose upper and lower surfaces protrude downward.

  Next, as shown in FIG. 7, a second gate insulating film 63 such as a high temperature oxide film (HTO film) is formed on the side surface of the trench 12 and the upper surface of the trench bottom buried insulating film 62 by LPCVD or the like by low pressure CVD or the like. Deposit to form. The second gate insulating film 63 extends from the position of the surface where the base regions 3 a and 3 b on the side surfaces of the trench 12 are exposed to the upper surface of the trench bottom buried insulating film 62 to cover the trench bottom buried insulating film 62. . The second gate insulating film 63 is also deposited on the upper surface of the first gate insulating film 61 located on the upper surfaces of the base regions 3a and 3b. As a result, an in-trench dielectric film (61, 62, 63) having a laminated structure including the first gate insulating film 61, the trench bottom buried insulating film 62, and the second gate insulating film 63 is formed.

  Next, as shown in FIG. 8, a polysilicon layer to which an n-type impurity such as N is added on the second gate insulating film 63 constituting the in-trench dielectric film (61, 62, 63) by CVD or the like. (Doped polysilicon layer) 7x is deposited. Thereafter, the polysilicon layer 7x is etched back to bury the polysilicon layer 7x in the trench 12 via the in-trench dielectric films (61, 62, 63). Further, the upper part of the polysilicon layer 7x is selectively removed by dry etching with high directivity to expose the second gate insulating film 63. Then, dry etching is performed so as to selectively remove the first gate insulating film 61 and the second gate insulating film 63 exposed on the upper surface side of the base regions 3a and 3b using the etching selection ratio between the oxide film and the polysilicon. Determine the endpoint. As a result, as shown in FIG. 9, the upper surfaces of the base regions 3a and 3b are exposed.

Next, a photoresist film (not shown) is applied on the base regions 3a and 3b, and the photoresist film is patterned using a photolithographic technique. Using the patterned photoresist film as a mask, n-type impurity ions such as N are ion-implanted. At the same time, ions are implanted into the polysilicon layer 7x. Thereafter, the photoresist film is removed by wet processing or the like. Further, a new photoresist film (not shown) is applied on the base regions 3a and 3b, and the photoresist film is patterned using a photolithographic technique. Using the patterned photoresist film as a mask, multistage ion implantation of p-type impurity ions such as Al is performed. At this time, the polysilicon layer 7x may be covered with a photoresist film so that p-type impurity ions are not implanted into the polysilicon layer 7x. Thereafter, the photoresist film is removed by wet processing or the like. Subsequently, the implanted n-type impurity and p-type impurity ions are activated by heat treatment, and as shown in FIG. 10, n ⁺ -type source regions 4a, 4b and p are formed above the base regions 3a and 3b. ⁺ Type base contact regions 5a and 5b are selectively formed. In this heat treatment step, n-type impurity ions and the like implanted into the polysilicon layer 7x are also activated.

The order of forming the source regions 4a and 4b and the p ⁺ type base contact regions 5a and 5b is not limited to this. For example, after the step of forming the p-type base region 3 shown in FIG. 2, before the step of forming the trench 12 shown in FIG. 3, n ⁺ -type source region 4a, n ⁺ -type region serving as 4b Also, p ⁺ -type base contact regions 5a and 5b may be formed. Then, the trench 12 may be formed so as to penetrate the n ⁺ -type region and the base region 3 to be the source regions 4a and 4b.

Next, an interlayer insulating film 8 made of a SiO ₂ film or the like is deposited on the buried gate electrode 7, the source regions 4a and 4b, and the p ⁺ type base contact regions 5a and 5b by CVD or the like. Then, a photoresist film 13 is applied on the interlayer insulating film 8, and the photoresist film 13 is patterned using a photolithographic technique. Using the patterned photoresist film 13 as a mask, as shown in FIG. 11, the interlayer insulating film 8 is selectively removed so as to remain on the gate buried electrode 7 by dry etching to open a source contact hole. Make a hole. Although not shown, the gate contact hole is also opened in the interlayer insulating film 8 so that a part of the gate wiring connected to the buried gate electrode 7 is exposed at a location different from the source contact hole. Thereafter, the photoresist film 13 is removed by wet processing or the like.

Next, as shown in FIG. 12, a metal layer made of Al or the like is deposited on the entire upper surface of the source regions 4a and 4b and the p ⁺ type base contact regions 5a and 5b by sputtering or vapor deposition. Then, a photoresist film is applied on the metal layer, and the photoresist film is patterned using a photolithographic technique. Using the patterned photoresist film as a mask, the metal layer is patterned by dry etching to form a pattern of the source electrode 9 and the gate surface electrode. Similarly, a drain electrode 10 made of Au or the like is formed on the lower surface of the drain region 1 by sputtering or vapor deposition as shown in FIG. In this way, the semiconductor device according to the embodiment of the present invention is completed.

  According to the method for manufacturing a semiconductor device according to the embodiment of the present invention, the thickness of the trench bottom buried insulating film 62 can be adjusted by adjusting the amount of light that exposes the photosensitive resin film 62x. Therefore, the thickness of each part of the in-trench dielectric film (61, 62, 63) composed of the first gate insulating film 61, the trench bottom buried insulating film 62, and the second gate insulating film 63 on the bottom surface side of the trench 12 is made independent. And can be easily adjusted.

(First modification)
In the semiconductor device according to the first modification of the embodiment of the present invention, as shown in FIG. 12, the in-trench dielectric films (61, 62) include the first gate insulating film 61 and the trench bottom embedded insulating film 62. 1 is different from the semiconductor device according to the embodiment of the present invention shown in FIG. 1 in that the second gate insulating film 63 shown in FIG. The first gate insulating film 61 is provided continuously on the bottom surface and side surfaces of the trench 12 and is in contact with the bottom surface of the trench 12. The first gate insulating film 61 is provided on the entire inner surface of the trench 12 including the position of the surface where the base regions 3 a and 3 b on the side surfaces of the trench 12 are exposed to the bottom surface of the trench 12. The trench bottom buried insulating film 62 is provided below the trench 12, the lower surface side of the trench bottom buried insulating film 62 is in contact with the first gate insulating film 61, and the upper surface side of the trench bottom buried insulating film 62 is the gate buried electrode. 7

  According to the semiconductor device according to the first modification of the embodiment of the present invention, the in-trench dielectric film (61, 62) is formed at the bottom of the trench at the lower portion of the trench 12, as in the semiconductor device according to the embodiment of the present invention. A buried insulating film 62 is provided. Thereby, it is easy to adjust the thickness of the trench bottom embedded insulating film 62 and independently increase the thickness of the in-trench dielectric film (61, 62) on the bottom surface side of the trench 12. It is possible to ensure the withstand pressure at the bottom of the.

  In the method of manufacturing a semiconductor device according to the first modification of the embodiment of the present invention, the step of forming the in-trench dielectric films (61, 62) is performed by a thermal oxidation method, a CVD method, or the like using the bottom surface and side surfaces of the trench 12 A first gate insulating film 61 is formed. Then, a photosensitive resin film (photosensitive resin solution) is applied so as to fill the trench 12, and the photosensitive resin film is exposed partway to leave a non-photosensitive region under the trench 12. Then, the exposed photosensitive resin film is developed and selectively removed to leave the photosensitive resin film below the trench 12. Subsequently, the remaining photosensitive resin film is baked, and a trench bottom embedded insulating film 62 made of a baked insulating film is embedded in the bottom of the trench 12. Since other processes are the same as those of the method for manufacturing a semiconductor device according to the embodiment of the present invention, description thereof is omitted.

(Second modification)
In the semiconductor device according to the second modification of the embodiment of the present invention, as shown in FIG. 13, the in-trench dielectric films (62, 63) include the trench bottom buried insulating film 62 and the second gate insulating film 63. 1 is different from the semiconductor device according to the embodiment of the present invention shown in FIG. 1 in that the first gate insulating film 61 shown in FIG. 1 is not provided. The trench bottom embedded insulating film 62 is provided below the trench 12 so as to be in contact with the bottom surface of the trench 12. The second gate insulating film 63 is continuously provided on the side surface of the trench 12 and the upper surface of the trench bottom buried insulating film 62 so as to cover the upper surface of the trench bottom buried insulating film 62. The second gate insulating film 63 is in contact with the trench bottom buried insulating film 62 and the gate buried electrode 7.

  According to the semiconductor device according to the second modification of the embodiment of the present invention, the in-trench dielectric film (62, 63) is formed at the bottom of the trench at the lower portion of the trench 12, as in the semiconductor device according to the embodiment of the present invention. A buried insulating film 62 is provided. Accordingly, the thickness of the trench bottom buried insulating film 62 can be adjusted, and the in-trench dielectric films (62, 63) on the bottom surface side of the trench 12 can be selectively and easily thickened. The withstand voltage can be secured.

  In the method of manufacturing a semiconductor device according to the second modification of the embodiment of the present invention, the step of forming the in-trench dielectric film (62, 63) includes applying a photosensitive resin film so as to fill the trench 12, The photosensitive resin film is exposed partway to leave a non-photosensitive region below the trench 12. The exposed photosensitive resin film is developed and selectively removed, leaving the photosensitive resin film below the trench 12. Thereafter, the remaining photosensitive resin film is baked, and a trench bottom embedded insulating film 62 made of a baked insulating film is embedded in the bottom of the trench 12. Further, a second gate insulating film 63 is deposited on the side surfaces of the trench 12 and the upper surface of the trench bottom buried insulating film 62 by CVD or the like. The second gate insulating film 63 is provided so as to extend from the surface position at which the base regions 3 a and 3 b on the side surfaces of the trench 12 are exposed to the upper surface of the trench bottom buried insulating film 62. Since other processes are the same as those of the method for manufacturing a semiconductor device according to the embodiment of the present invention, description thereof will be omitted.

(Third Modification)
In the semiconductor device according to the third modification of the embodiment of the present invention, as shown in FIG. 14, the second gate insulating film 63 of the in-trench dielectric film (62, 63) is selected only on the side surface of the trench 12. The semiconductor device according to the second modification of the embodiment of the present invention shown in FIG. 13 is different from the semiconductor device according to the second embodiment of the present invention shown in FIG. Under the trench 12, the trench bottom buried insulating film 62 is in contact with the gate buried electrode 7.

  According to the semiconductor device according to the third modification of the embodiment of the present invention, the in-trench dielectric film (62, 63) is formed at the bottom of the trench at the lower portion of the trench 12, similarly to the semiconductor device according to the embodiment of the present invention. Since the buried insulating film 62 is provided, the thickness of the trench buried insulating film 62 at the bottom of the trench can be adjusted so that the in-trench dielectric film (62, 63) on the bottom surface side of the trench 12 can be selectively thickened easily. In addition, the withstand voltage at the bottom of the trench 12 can be ensured.

  In the method of manufacturing a semiconductor device according to the third modification of the embodiment of the present invention, the step of forming the in-trench dielectric film (62, 63) applies a photosensitive resin film so as to fill the trench 12, The photosensitive resin film is exposed partway to leave a non-photosensitive region below the trench 12. The exposed photosensitive resin film is developed and selectively removed, leaving the photosensitive resin film below the trench 12. Thereafter, the remaining photosensitive resin film is baked, and a trench bottom embedded insulating film 62 made of a baked insulating film is embedded in the bottom of the trench 12. Further, the second gate insulating film 63 is selectively formed only on the side surface of the trench 12 by a thermal oxidation method or the like. Since other processes are the same as those of the method for manufacturing a semiconductor device according to the embodiment of the present invention, description thereof is omitted.

(Other embodiments)
As mentioned above, although this invention was described by embodiment, it should not be understood that the statement and drawing which form a part of this indication limit this invention. From this disclosure, various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art.

  In the embodiment of the present invention, the case where the trench bottom embedded insulating film 62 has a crescent-shaped cross-sectional shape as illustrated in FIG. 1 is illustrated, but the present invention is not limited to this. As described above, the upper surface of the trench bottom buried insulating film 62 is flat reflecting the fact that the light transmission distance is constant (uniform) before baking the photosensitive resin film such as the SOG film. Therefore, by adjusting the firing conditions, for example, as shown in FIG. 15, the upper surface of the trench bottom buried insulating film 62 is flattened and the entire cross-sectional shape including the lower surface is formed into a semicircular shape. Also good. Alternatively, as shown in FIG. 16, when the bottom surface of the trench 12 is flat, the trench bottom embedded insulating film 62 made of a fired insulating film has a rectangular cross-sectional shape corresponding to the shape of the bottom surface of the trench 12. You may do it. In particular, when the bottom surface of the trench 12 is flat, it is easy to flatten the top surface of the trench bottom buried insulating film 62 even after baking the photosensitive resin film.

  In the embodiment of the present invention, the trench gate type MISFET is exemplified. However, the present invention is not limited to this, and various trench structures such as an IGBT having a trench structure in which an electrode is disposed on a semiconductor layer via an insulating film. It is applicable to a semiconductor device having

For example, when the semiconductor device according to the embodiment of the present invention is an IGBT, the first conductivity type (n ⁻ -type) drift layer 31 and the upper surface side of the drift layer 31 are disposed as shown in FIG. Second conductivity type (p-type) base regions 32 a and 32 b, and a first main electrode of the first conductivity type (n ⁺ type) that is disposed above the base regions 32 a and 32 b and has a higher impurity density than the drift layer 31. Regions (emitter regions) 33a and 33b. A trench 42 penetrating the emitter regions 33a and 33b and the base regions 32a and 32b is provided so as to reach the drift layer 31 from the upper surfaces of the emitter regions 33a and 33b. Gate insulating films (51, 53) are provided on the bottom and side surfaces of the trench 42, and the gate electrode 36 is embedded in the trench 42 via the gate insulating films (51, 53).

Above the base regions 32a and 32b, a base contact region 34a of the second conductivity type (p ⁺ type) having a higher impurity density than the base regions 32a and 32b so as to be in contact with the emitter regions 33a and 33b and the base regions 32a and 32b. , 34b are provided. On the gate electrode 36, a first main electrode (emitter electrode) 38 is disposed in contact with the emitter regions 33a and 33b and the emitter regions 34a and 34b via an interlayer insulating film 37. On the lower surface side of the drift layer 31, a second main electrode region (collector region) 40 of the first conductivity type (p ⁺ type) is disposed. Between the drift layer 31 and the collector region 40, an n-type field stop (FS) layer 39 having a higher impurity density than the drift layer 31 is disposed. A second main electrode (collector electrode) 41 is disposed on the lower surface side of the collector region 40 so as to be in contact with the collector region 40.

  At the bottom of the trench 42, an in-trench dielectric film (61, 62, 63 including the three-layer structure of the first gate insulating film 61, the trench bottom buried insulating film 62, and the second gate insulating film 63 shown in FIG. ), A dielectric film (51, 52, 53) in a trench including a three-layer structure of a first gate insulating film 51, a trench bottom buried insulating film 52, and a second gate insulating film 53 is formed to form a trench. The electric field strength applied to the bottom of 42 is suppressed.

As a manufacturing method of the IGBT shown in FIG. 17, for example, a semiconductor substrate to be the n ⁻ type drift layer 31 is prepared, and a trench gate structure may be formed in the same manner as the MISFET. Further, n-type impurities such as N and p-type impurities such as Al are sequentially subjected to multi-stage ion implantation on the lower surface side of the drift layer 31 to perform heat treatment, thereby forming an n-type FS layer 39 and a p ⁺ -type collector region 40, respectively. do it.

  In the embodiment of the present invention, a semiconductor device using SiC is exemplified, but the present invention can also be applied to a semiconductor device using another wide band gap semiconductor such as gallium nitride (GaN) or diamond. Further, the present invention is not limited to a wide band gap semiconductor, and can be applied to a semiconductor device using silicon (Si).

1 ... Drain region (second main electrode region)
2, 31 ... drift layers 3, 3a, 3b, 32a, 32b ... base regions 4a, 4b ... source regions (first main electrode regions)
5a, 5b, 34a, 34b ... base contact regions 6, 6x, 6y, 6z, 35 ... gate insulating film 7 ... gate buried electrode 7x ... polysilicon layer 8, 37 ... interlayer insulating film 9 ... source electrode 10 ... drain electrode 11, 13 ... Photoresist films 12, 42 ... Trench 33a, 33b ... Emitter region (first main electrode region)
38 ... Emitter electrode 39 ... Field stop layer 40 ... Collector region (second main electrode region)
41 ... Collector electrodes 51, 61 ... First gate insulating films 52, 62 ... Trench bottom buried insulating films 53, 63 ... Second gate insulating film 62x ... Photosensitive resin film

Claims (12)

A first conductivity type drift layer;
A base region of a second conductivity type disposed on the upper surface side of the drift layer;
A first main electrode region of a first conductivity type disposed on the base region and having a higher impurity density than the drift layer;
A gate insulating film provided at least on the surface where the base region is exposed on the side surface of the trench penetrating the first main electrode region and the base region;
A trench bottom embedded insulating film made of a fired insulating film having a relative dielectric constant smaller than that of the gate insulating film, provided in contact with the gate insulating film so as to bury the lower portion of the trench on the bottom side of the trench;
A gate buried electrode buried via the gate insulating film above the trench bottom buried insulating film in the trench;
A second main electrode region disposed on the lower surface side of the drift layer;
A semiconductor device comprising:   2. The semiconductor device according to claim 1, wherein minute vacancies of 2 nm to 10 nm recognized from observation of a transmission electron microscope image are dispersed in the trench bottom buried insulating film.   3. The semiconductor according to claim 1, wherein the gate insulating film is provided on the entire inner surface of the trench including from the position of the surface of the side surface where the base region is exposed to the bottom surface. 4. apparatus.   The gate insulating film extends from the position of the surface of the side surface where the base region is exposed to the upper surface of the trench bottom buried insulating film, and covers the upper surface of the trench bottom buried insulating film. The semiconductor device according to claim 1 or 2. The gate insulating film is
A first gate insulating film provided on the bottom surface and the side surface and in contact with the bottom surface on a lower surface side of the trench bottom buried insulating film;
A second gate insulating layer provided on an upper surface of the first gate insulating film, extending from a surface position at which the base region of the side surface is exposed to an upper surface of the trench bottom embedded insulating film and being in contact with the gate embedded electrode; A membrane,
The semiconductor device according to claim 1, comprising:   4. The semiconductor device according to claim 1, wherein an upper surface of the trench bottom buried insulating film is in contact with the gate buried electrode.   5. The semiconductor device according to claim 1, wherein the trench bottom embedded insulating film is in contact with the bottom surface. 6.   The semiconductor device according to claim 1, wherein the drift layer is made of a semiconductor material having a wider forbidden band than silicon. Forming a second conductivity type base region on the upper surface side of the first conductivity type drift layer;
Forming a trench penetrating the base region;
Forming a gate insulating film on at least a side surface of the trench;
Applying a photosensitive resin film to fill the trench;
Exposing the coated photosensitive resin film halfway to leave a non-photosensitive region under the trench; and
Developing and selectively removing the exposed photosensitive resin film;
Firing the remaining photosensitive resin film to form a trench bottom buried insulating film made of a fired insulating film;
Burying a gate buried electrode through the gate insulating film above the trench bottom buried insulating film in the trench;
Forming a first main electrode region of a first conductivity type having a higher impurity density than the drift layer above the base region;
A method for manufacturing a semiconductor device, comprising: The gate insulating film as a first gate insulating film,
The second gate insulating film extends from the position of the surface where the base region on the side surface is exposed to the upper surface of the trench bottom buried insulating film and covers the upper surface of the trench bottom buried insulating film on the first gate insulating film. The method for manufacturing a semiconductor device according to claim 9, further comprising a step of forming a gate insulating film. Forming a second conductivity type base region on the upper surface side of the first conductivity type drift layer;
Forming a trench penetrating the base region;
Applying a photosensitive resin film to fill the trench;
Exposing the coated photosensitive resin film halfway to leave a non-photosensitive region under the trench; and
Developing and selectively removing the exposed photosensitive resin film;
Firing the remaining photosensitive resin film to form a trench bottom buried insulating film made of a fired insulating film;
Forming a gate insulating film on at least a side surface of the trench;
Burying a gate buried electrode through the gate insulating film above the trench bottom buried insulating film in the trench;
Forming a first main electrode region of a first conductivity type having a higher impurity density than the drift layer above the base region;
A method for manufacturing a semiconductor device, comprising: The method of manufacturing a semiconductor device according to claim 9, wherein the photosensitive resin film is a spin-on-glass film.

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