JP2018200666A - Detection system, sensor and microcomputer - Google Patents

Abstract

To correct the frequency of a clock signal of a sensor based on a clock signal input from a microcomputer. A detection system includes a sensor and a microcomputer. The sensor 1 is configured to be able to output sampling data SD generated by performing analog / digital conversion on an analog signal sampled based on the clock signal CLK1. The microcomputer 2 generates the clock signal CLK2 and outputs it to the sensor 1, and reads out the sampling data SD from the sensor 1. The sensor 1 corrects the frequency of the clock signal CLK1 based on the clock signal CLK2. [Selection diagram] Fig. 1

Description

  The present invention relates to a detection system, a sensor, and a microcomputer.

  In recent years, detection systems that acquire data from various sensors and process the acquired data have been used. As such an example, a sensor system that processes data acquired by a plurality of sensors has been proposed (Patent Document 1).

  In this system, data is exchanged between the control unit, the first sensor, and the second sensor. In this example, the first input terminal of the control unit and the input / output terminal of the first sensor are connected. The second input terminal of the control unit and the input / output terminal of the second sensor are connected. The input / output terminal of the first sensor and the input / output terminal of the second sensor are connected. The second sensor receives the first sensor signal, and in response to the input first sensor signal, the second sensor data based on the second synchronization signal and the second synchronization signal. The second sensor signal including is serially output. Thereby, in this system, the output data of at least two or more sensors becomes the output data of the sensor obtained in the same period, and this can be realized with a simple sensor system and sensor.

JP2015-228171A

  However, although the output timing of the data from the sensor can be synchronized with the above-described configuration, it cannot be guaranteed that the timing at which the data is sampled is the same. In this case, the sensor outputs data after converting the analog signal indicating the detection result into a digital signal. At this time, analog / digital conversion is performed in accordance with a clock signal which is a reference for sampling timing. Therefore, in order to synchronize the sampling timing of data in a plurality of sensors with high accuracy, it is necessary to maintain the frequency accuracy of the clock signal used in each sensor. However, it is not common to incorporate a highly accurate crystal oscillation circuit or the like in each sensor due to problems such as power consumption and cost. Therefore, a simple oscillation circuit such as a ring oscillator is used. However, such a simple oscillation circuit has a problem that the frequency is likely to fluctuate.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  According to one embodiment, a detection system includes a sensor configured to output sampling data generated by analog / digital conversion of an analog signal sampled based on a first clock signal, and a second clock signal And a microcomputer for reading out the sampling data from the sensor, the sensor based on the second clock signal, the frequency of the first clock signal Correct.

  According to an embodiment, the sensor is configured to output sampling data generated by analog / digital conversion of an analog signal sampled based on the first clock signal, and the second data generated by the microcomputer Based on the clock signal, the frequency of the first clock signal is corrected, and the sampling data is read out by the microcomputer.

  According to one embodiment, the microcomputer outputs a second clock signal to a sensor configured to output sampling data generated by analog / digital conversion of an analog signal sampled based on the first clock signal. And outputting the sampling data from the sensor, and the frequency of the first clock signal is corrected by the sensor based on the second clock signal.

  According to one embodiment, the frequency of the clock signal of the sensor can be corrected based on the clock signal input from the microcomputer.

1 is a diagram schematically illustrating a basic configuration of a detection system according to a first exemplary embodiment. 1 is a diagram schematically illustrating a configuration of a detection system according to a first exemplary embodiment. FIG. 3 is a diagram illustrating operation timings of the detection system according to the first exemplary embodiment. It is a figure which shows the structure of the sensor concerning Embodiment 1 in detail. It is a figure which shows the structure of a frequency voltage conversion part. It is a figure which shows the structure of a voltage hold part. It is a figure which shows the structure of an oscillator. It is a figure which shows return operation | movement when a sensor enters sleep mode unexpectedly. It is a figure which shows the return operation | movement when a microcomputer enters sleep mode unexpectedly. It is a figure which shows typically the structure of the detection system concerning Embodiment 2. FIG. It is a figure which shows typically the structure of the detection system concerning Embodiment 3. FIG. 10 is a diagram illustrating operation timings of the detection system according to the third exemplary embodiment. It is a figure which shows typically the structure of the detection system concerning Embodiment 4. FIG. It is a figure which shows typically the structure of the modification of the detection system concerning Embodiment 4. FIG. FIG. 10 is a diagram schematically illustrating a configuration of a detection system according to a fifth exemplary embodiment. FIG. 10 is a diagram schematically illustrating a configuration of a detection system according to a sixth embodiment. FIG. 10 is a diagram schematically illustrating a configuration of a modified example of the detection system according to the sixth exemplary embodiment.

  Embodiments of the present invention will be described below with reference to the drawings. In the drawings, the same elements are denoted by the same reference numerals, and redundant description is omitted as necessary.

Embodiment 1
Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram schematically illustrating a basic configuration of a detection system 100 according to the first embodiment. FIG. 2 is a diagram schematically illustrating a configuration of the detection system 100 according to the first embodiment.

  The detection system 100 includes a sensor 1 and a microcomputer 2. The sensor 1 and the microcomputer 2 can perform data communication with each other. Note that data communication between the sensor 1 and the microcomputer 2 may be performed by either wired communication or wireless communication. The sensor 1 is configured to detect a physical quantity such as pressure or acceleration and store the detection result in an internal memory. The microcomputer 2 is configured to be able to read data indicating the detection result from the sensor 1 and to control the operation of the sensor 1.

  First, the sensor 1 will be described. The sensor 1 includes a communication unit 11, a detection unit 12, an oscillator 13, an analog / digital (A / D) converter 14, a memory 15, and a frequency correction unit 16. The communication unit 11, the oscillator 13, the analog / digital (A / D) converter 14, the memory 15, and the frequency correction unit 16 are signals that are A / D conversion units that perform A / D conversion on analog signals from the detection unit 12. The processing unit 1A is configured.

  The communication unit 11 (also referred to as a first input / output unit) is an input / output device for performing data communication with the microcomputer 2.

  The detection unit 12 detects a predetermined physical quantity such as pressure or acceleration, and outputs the detection result as an analog signal AS.

  The oscillator 13 generates the clock signal CLK1 by the oscillation operation and outputs it to the A / D converter 14. In the present embodiment, the oscillator 13 has a relatively simple configuration, for example, a ring oscillator. In this case, the oscillator 13 has a characteristic that the oscillation frequency is likely to fluctuate due to a change with time or an environmental change. Therefore, in order to maintain the frequency of the clock signal CLK1 at a constant value, the oscillator 13 is configured to be able to adjust the frequency of the clock signal CLK1 in accordance with the control signal CON input from the frequency correction unit 16.

  The A / D converter 14 performs analog / digital conversion (A / D conversion) on the analog signal AS sampled based on the clock signal CLK1 received from the oscillator 13, and outputs the converted digital signal as sampling data SD.

  The memory 15 has a function of storing sampling data SD sequentially output from the A / D converter 14. The memory 15 outputs the stored sampling data SD to the microcomputer 2 via the communication unit 11 in response to a data read request REQ from the microcomputer 2. As the memory 15, for example, a FIFO (First In, First Out) or the like may be used.

  The frequency correction unit 16 receives the clock signal CLK2 input from the microcomputer 2 via the communication unit 11, and controls the control signal CON for correcting the frequency of the clock signal CLK1 output from the oscillator 13 based on the clock signal CLK2. Is output to the oscillator 13. The details of the operation of correcting the frequency of the clock signal CLK1 will be described later.

  Next, the microcomputer 2 will be described. As described above, the microcomputer 2 is configured to be able to read the sampling data SD from the sensor 1. The microcomputer 2 includes a communication unit 21, a clock signal generation unit 22, and a CPU and a memory (not shown).

  The communication unit 21 (also referred to as a second input / output unit) is an input / output device for performing data communication with the sensor 1.

  The clock signal generation unit 22 includes, for example, an oscillation circuit, and outputs a clock signal CLK2 used for processing of each unit provided in the microcomputer 2 based on the oscillation operation. The clock signal CLK2 is output to the sensor 1 together with the read request REQ, for example, via the communication unit 21. As described above, the clock signal CLK2 input to the sensor 1 is used for correction processing in the frequency correction unit 16.

  FIG. 3 shows an example of operation timing. The sensor 1 samples the output signal (analog signal AS) from the detection unit 12 at time T1, converts it into a digital signal (sampling data SD) by the A / D converter 14, and then holds it in the memory 15. Similarly, the sensor 1 samples the output signal (analog signal AS) from the detection unit 12 at time T2, converts it to a digital signal (sampling data SD) by the A / D converter 14, and then holds it in the memory 15. . Next, after the microcomputer 2 transits from sleep to active at time T <b> 3, the microcomputer 2 outputs the clock signal CLK <b> 2 and the read request REQ to the sensor 1. When the sensor 1 receives the read request REQ, the sensor 1 outputs the sampling data SD at the times T1 and T2 held in the memory 15 to the microcomputer via the communication unit 11. At time T4, the microcomputer 2 transitions to sleep. Similarly, when the microcomputer 2 transitions to the active state at time T8, the sampling data SD at times T5, T6, and T7 are output from the sensor 1.

  In the present embodiment, the clock signal generation unit 22 includes an oscillation circuit that can stabilize the frequency of the clock signal CLK2 with high accuracy, such as a crystal oscillation circuit or an on-chip oscillation circuit that is trimmed with high accuracy. , The oscillator 13 is configured to have higher frequency stability.

 The microcomputer 2 has a function of analyzing a plurality of sampling data SD sequentially read from the sensor 1 in a time series based on the clock signal CLK2.

  Next, the correction process of the clock signal CLK1 will be described. FIG. 4 is a diagram illustrating the configuration of the sensor 1 according to the first embodiment in more detail. As illustrated in FIG. 4, the frequency correction unit 16 includes a frequency divider 161, a frequency voltage conversion unit 162, a frequency voltage conversion unit 163, a comparator 164, a differential amplifier 165, a voltage hold unit 166, and a switch 167.

  The clock signal CLK <b> 2 is input from the microcomputer 2 through the communication unit 11 to the frequency divider 161. The frequency divider 161 divides the clock signal CLK2 by a predetermined ratio n. That is, the frequency divider 161 outputs a frequency-divided signal CLKD having a frequency of f / n, where f is the frequency of the clock signal CLK2.

  The frequency voltage converter 162 (also referred to as a first frequency voltage converter) converts the clock signal CLK1 output from the oscillator 13 into a voltage signal V1 (also referred to as a first signal). FIG. 5 shows an example of the configuration of the frequency / voltage converter 162. The clock signal CLKIN (corresponding to CLK1) is input to the timing control circuit 33. The timing control circuit 33 generates a charge signal CHR and a discharge signal DCHR based on the clock signal CLKIN. The switch 34 is inserted so that the constant current circuit 32 and the capacitor 36 can be conducted, and ON / OFF of the switch 34 is controlled by a charge signal CHR. The switch 35 is inserted so that the capacitor 36 and the ground potential can be connected, and ON / OFF of the switch 35 is controlled by a discharge signal DCHR. Therefore, the capacitor 36 is charged with the current output from the constant current circuit 32 in accordance with the clock signal CLKIN, and the charge held in the capacitor 36 is discharged, whereby the voltage VOUT corresponding to the frequency of the clock signal CLKIN. (Corresponding to the voltage signal V1) is output.

  A frequency voltage converter (also referred to as a second frequency voltage converter) 163 converts the frequency of the frequency-divided signal CLKD into a voltage signal V2 (also referred to as a second signal). The frequency voltage conversion unit 163 is configured in the same manner as the frequency voltage conversion unit 162 shown in FIG.

  The comparator 164 compares the voltage signal V2 with a predetermined voltage Vth, and outputs a signal Vc as a comparison result to the voltage hold unit 166 and the switch 167 as a switching signal.

  The voltage signal V1 is input to one input of the differential amplifier 165, and the voltage signal V2 is input to the other input. For example, in this embodiment, the voltage signal V2 is input to the inverting input of the differential amplifier 165, and the voltage signal V1 is input to the non-inverting input. Then, the differential amplifier 165 outputs an output voltage Vd indicating a voltage difference between the voltage signal V1 and the voltage signal V2.

  The voltage hold unit 166 holds the output voltage Vd of the differential amplifier 165 according to the signal Vc. FIG. 6 shows an example of the configuration of the voltage hold unit. The switch 42 is ON / OFF controlled by the signal Vc. The output voltage Vd is applied to the capacitor 43 when the switch 42 is ON, and the voltage value of the output voltage Vd is held in the capacitor 43 when the switch 42 is OFF. The held voltage value is output as a voltage Vh by a voltage follower circuit using the operational amplifier 41 or the like.

  The switch 167 connects the control terminal of the oscillator 13 to one of the output terminal of the differential amplifier 165 and the output terminal of the voltage hold unit 166 according to the signal Vc. FIG. 7 shows an example of the configuration of the oscillator 13. The oscillator 13 is configured by a ring oscillator in which n (n is a positive odd number) inversion circuits INV_1 to INV_n are connected in a ring shape. A power supply voltage is supplied from the voltage controller to each inverting circuit. By controlling the voltage value supplied from the voltage control circuit 31 by the control signal CON, the delay amount of each inverting circuit changes, whereby the frequency of the clock signal CLK1 output from the oscillator 13 is controlled.

  As described above, the clock signal generation unit 22 of the microcomputer 2 does not operate in synchronization with the sensor 1. Therefore, the frequency of the clock signal CLK1 varies regardless of the clock signal CLK2. In addition, as described above, the frequency of the clock signal CLK1 is relatively easy to fluctuate. Therefore, in order to ensure the accuracy of the time series processing of the data of the microcomputer 2, the frequency of the clock signal CLK1 is determined based on the clock signal CLK2. It is necessary to keep it at a constant value. If the sensor 1 cannot know in advance the oscillation frequency of the clock signal CLK1 received from the microcomputer 2, the microcomputer 2 can transmit frequency information of the clock used for communication to the sensor 1. The frequency information may be transmitted at a suitable timing.

Hereinafter, the operation of correcting the frequency of the clock signal CLK1 will be described.
[1. When clock signal CLK2 is input to sensor 1]
When the clock signal CLK2 is input to the sensor 1, the frequency voltage conversion unit 163 outputs a voltage signal V2 indicating the frequency of the divided signal CLKD.

  The predetermined voltage Vth input to the comparator 164 is set to a value such that the voltage signal V2 when the clock signal CLK2 is input is greater than the voltage Vth. Therefore, in this case, the comparator 164 outputs, for example, HIGH as the signal Vc.

  When the signal Vc is HIGH, the switch 167 connects the control terminal of the oscillator 13 to the output terminal of the differential amplifier 165. Further, in the differential amplifier 165, the voltage signal V1 indicating the frequency of the clock signal CLK1 and the voltage signal V2 indicating the frequency of the divided signal CLKD are compared, and the output voltage Vd which is a difference voltage between them is used as the control signal CON. Is output.

The oscillator 13 can make the frequency of the clock signal CLK1 coincide with the frequency of the divided signal CLKD by increasing or decreasing the frequency of the output clock signal CLK1 in accordance with the value of the control signal CON.
[2. When input of clock signal CLK2 to sensor 1 stops]
When the input of the clock signal CLK2 to the sensor 1 is stopped, the voltage signal V2 indicating the frequency of the divided signal CLKD becomes, for example, “0”.

  Therefore, since the voltage signal V2 becomes smaller than the voltage Vth, the comparator 164 outputs, for example, LOW as the signal Vc.

  When the signal Vc is LOW, the voltage hold unit 166 holds the control signal CON (that is, the output voltage Vd) output from the differential amplifier 165.

  The switch 167 connects the control terminal of the oscillator 13 to the output terminal of the voltage hold unit 166. Therefore, the control signal CON of the constant voltage Vh held by the voltage hold unit 166 is input to the oscillator 13. Thereby, the operation of correcting the frequency of the clock signal CLK1 in the oscillator 13 is stopped.

[3. When the clock signal CLK2 is input to the sensor 1 again]
In this case, as described above, the operation of correcting the frequency of the clock signal CLK1 in the oscillator 13 is resumed.

Next, an example of the correction operation of the clock signal CLK1 will be described.
Example 1 When Sensor 1 Enters Sleep Mode Unexpectedly
For example, the sensor 1 may enter a sleep mode in order to reduce power consumption. In this case, in order for the microcomputer 2 to read data from the sensor 1, the sensor 1 is activated and the clock signal CLK1 is corrected.

  FIG. 8 is a diagram illustrating a return operation when the sensor 1 unexpectedly enters the sleep mode.

Step S11
Sensor 1 enters sleep mode unexpectedly.

Step S12
The microcomputer 2 sends a read request REQ to the data stored in the memory 15 to the sensor 1.

Step S13
The microcomputer 2 determines whether there is a response to the read request from the sensor 1.

Step S14
When there is no response to the read command from the sensor 1, the microcomputer 2 sends an activation command to the sensor 1.

Step S15
After the start command is sent, the process returns to step S12 after a predetermined time has elapsed.

Step S16
When there is a response to the read command from the sensor 1, the microcomputer 2 outputs a clock signal CLK 2 to the sensor 1. The sensor 1 refers to the clock signal CLK2 and performs a correction operation on the clock signal CLK1. Thereby, the frequency of the clock signal CLK1 is corrected to a desired value.

Step S17
The microcomputer 2 reads predetermined sampling data SD from the sensor 1.

[Example 2 When the microcomputer 2 unexpectedly enters the sleep mode]
For example, the microcomputer 2 may enter a sleep mode in order to reduce power consumption. In this case, it is necessary to correct the clock signal CLK1 when the microcomputer 2 returns from the sleep mode.

  FIG. 9 is a diagram showing a return operation when the microcomputer 2 unexpectedly enters the sleep mode.

Step S21
The microcomputer (MCU) 2 unexpectedly enters the sleep mode.

Step S22
The microcomputer (MCU) 2 returns from the sleep mode.

Step S23
The microcomputer 2 sends a read request REQ to the sensor 1 and outputs a clock signal CLK2. The sensor 1 refers to the clock signal CLK2 and performs a correction operation on the clock signal CLK1. Thereby, the frequency of the clock signal CLK1 is corrected to a desired value.

Step S24
The microcomputer 2 reads predetermined sampling data SD from the sensor 1.

  As described above, according to this configuration, even if the frequency of the clock signal CLK1 output from the oscillator 13 of the sensor 1 fluctuates, the frequency of the clock signal CLK1 is set to an appropriate value based on the clock signal CLK2 supplied from the microcomputer 2. It can be corrected.

  Further, when the microcomputer 2 reads data from a plurality of sensors having the same configuration as the sensor 1, the frequency of the clock signal CLK1 of each sensor must be the same in order to synchronize the sampling of the data of each sensor. . On the other hand, in this configuration, since the microcomputer 2 outputs the clock signal CLK2 to each sensor and the clock signal CLK1 can be corrected by each sensor, the clock signal CLK1 of each sensor can be easily corrected. Is possible.

  Further, the microcomputer 2 may set the sampling frequency and the frequency of the clock signal CLK1 by outputting a necessary signal to the sensor 1, for example. For example, when the microcomputer 2 sets the sampling frequency or the frequency of the clock signal CLK1 for the sensor 1, the sensor 1 can set the frequency division ratio of the clock signal CLK2. Of course, the microcomputer 2 may set the frequency division ratio itself of the clock signal CLK2 in the sensor 1.

Embodiment 2
A detection system 100 according to the second embodiment will be described. FIG. 10 is a diagram schematically illustrating a configuration of the detection system 200 according to the second embodiment. The detection system 200 has a configuration in which the microcomputer 2 of the detection system 100 according to the first embodiment is replaced with a microcomputer 3. The detection system 200 is configured as a system in which the microcomputer 3 calculates the data sampling time based on the information received from the sensor 1 for calculating the time when the data was sampled. The operation timing of the detection system 200 is the same as that in FIG.

  The microcomputer 3 has a configuration in which a calculation unit 23 is added to the microcomputer 2. The arithmetic unit 23 can be configured with a logic circuit. Moreover, the calculating part 23 can also be implement | achieved by the program run with CPU which is not shown in figure.

  In the present embodiment, the memory 15 stores the sampling data SD output from the A / D converter 14, and sampling data to be output via the communication unit 11 in response to a request REQ of the microcomputer 3. SD and serial data SER, which is information indicating how many times the sampling data SD has been sampled since the reset, are output.

  In FIG. 10, as an example, the first sampling data after reset is SD1, the serial data is SER1, the second sampling data is SD2, the serial data is SER2,..., The i-th sampling data is SDi, and the serial data. Is SERi.

  Next, the sampling time calculation operation of the microcomputer 3 will be described. The microcomputer 3 can reset the serial data SER in the memory 15 of the sensor 1 when the detection system 200 is activated or at an arbitrary timing.

  Specifically, the microcomputer 3 outputs a reset signal RS. The reset signal RS is input to the memory 15 and the serial data SER is reset to “0”. Thereafter, each time the sampling data is received, the memory 15 increments the serial data SER and adds it to the sampling data SD.

  When the microcomputer 3 receives the sampling data SD and the serial data SER, the calculation unit 23 refers to the serial data SER and calculates the time when the corresponding sampling data SD is sampled. Hereinafter, the calculation method will be described.

As shown in the equation [1], the microcomputer 3 calculates the sampling time Ts by adding the value obtained by multiplying the reference time Tref by the value N of the serial data SER indicating the number of samplings to the sampling period Ps. Here, the reference time Tref is the time when the microcomputer 3 outputs the reset signal RS to the sensor 1. For example, the calculation unit 23 can refer to the reference time Tref as necessary by holding the time when the reset signal RS is output as the reference time Tref.

Ts = Tref + N · Ps [1]

It is also possible to calculate the sampling time with higher accuracy. For example, there is a delay time required for signal transmission and signal processing between the timing at which data is actually sampled and the timing at which the microcomputer 3 calculates the sampling time. Here, for example, the delay time due to the A / D conversion process in the A / D converter 14 is TD1. The delay time by the A / D conversion process here is the time required from the falling edge or falling edge of the clock signal CLK1 to the start of A / D conversion. Also, let TD2 be the delay time for time synchronization. The delay time TD2 required for time synchronization here is the time required from the microcomputer 3 outputting the reset signal RS until the reset of the serial data SER by the memory 15 is completed. In this case, the sampling time Ts is calculated by the following equation [2].

Ts = Tref + N · Ps + TD1 + TD2 [2]

  Although the delay time TD1 and the delay time TD2 are assumed here, it goes without saying that the delay times caused by other causes may be added as appropriate.

  Moreover, the information concerning the sampling period and delay time used for calculation may be stored in, for example, a memory (not shown) provided in the microcomputer 3. Further, the sampling period may be set in the sensor 1 by giving a signal indicating the sampling period from the memory of the microcomputer 3 to the sensor 1 as necessary.

  As described above, according to this configuration, not only the frequency of the clock signal CLK1 of the sensor 1 is corrected, but also the microcomputer 3 can calculate the sampling time of the sampling data SD based on the serial data SER. Thereby, it is possible to accurately grasp the time series of the sampling data SD.

  Further, according to this configuration, since the serial data SER is incremented every time sampling is performed by the sensor 1, if the sampling data received from the sensor 1 by the microcomputer 3 is lost, the value of the serial data SER is also lost. As a result, the presence of sampling data that has failed to be acquired can be easily detected. In this case, for example, the microcomputer 3 may request the sensor 1 to output again the sampling data that failed to be acquired.

  When the microcomputer 3 reads sampling data from a plurality of sensors having the same configuration as the sensor 1, in order to associate the sampling data of each sensor at the same time in the microcomputer 3, the microcomputer 3 uses the sampling data of each sensor. It is necessary to refer to the sampling time. On the other hand, in this configuration, as described above, the sampling time of the sampling data of each sensor can be calculated, so that sampling data sampled at the same time by a plurality of sensors can be easily associated.

  In this configuration, serial data SER is output from the sensor 1 to the microcomputer 3 in order to calculate the sampling time in the microcomputer 3. Therefore, for example, it is not necessary to provide a portion for outputting data indicating the time to the sensor 1, and time data indicating the sampling time itself may not be transmitted from the sensor 1 to the microcomputer 3. Thus, this configuration is advantageous in that the sensor can be downsized and the compression rate of data output from the sensor to the microcomputer can be improved.

Embodiment 3
A detection system 300 according to the third embodiment will be described. FIG. 11 is a diagram schematically illustrating a configuration of a detection system 300 according to the third embodiment. The detection system 300 has a plurality of sensors. The detection system 300 includes a microcomputer 2 and first and second sensors 4 and 5. In this example, the sensors 4 and 5 have the same configuration as the sensor 1 of the detection system 100. The microcomputer 2 is the same as the detection system 100.

  FIG. 12 shows an example of operation timing. The first sensor 4 holds the sampling data SD at times T9 and T10 in the memory. The second sensor 5 holds the sampling data at time T11 in the memory. Next, after the microcomputer 2 transits from sleep to active at time T <b> 12, the clock signal CLK <b> 2 and the read request REQ are output to the first sensor 4. When receiving the read request REQ, the first sensor 4 outputs the sampling data SD at times T9 and T10 to the microcomputer 2. Further, the clock signal CLK 2 and the read request REQ are output to the second sensor 5. Upon receiving the read request REQ, the second sensor 5 outputs the sampling data SD at time T11 to the microcomputer 2. Then, the microcomputer 2 shifts to sleep at time T13.

  The detection system 300 is a system that acquires and processes biological information, for example. For example, the sensor 4 is a pulse wave sensor, detects a pulse wave of a living body, and outputs a detection result as sampling data SD4. For example, the sensor 5 is an electrocardiographic sensor, detects the electrocardiogram of a living body, and outputs the detection result as sampling data SD5. The microcomputer 2 estimates the propagation speed of the pulse wave from the phase difference between the peak of the electrocardiogram and the peak of the pulse wave based on the sampling data SD4 and the sampling data SD5.

  Therefore, in order to ensure the estimation accuracy of the propagation speed of the pulse wave, the time accuracy of the data sampled by the sensor is important. On the other hand, in this configuration, the clock frequencies of the sensors 4 and 5 can be corrected in the same manner as in the detection system 100, so that the processing accuracy of the sampling data can be increased.

  In the present embodiment, the microcomputer 2 may be replaced with the microcomputer 3 according to the second embodiment. In this case, since the sampling time of the sampling data received from the plurality of sensors can be calculated, it becomes possible to compare the plurality of time series data more reliably and accurately.

Embodiment 4
A detection system 400 according to the fourth embodiment will be described. FIG. 13 is a diagram schematically illustrating a configuration of a detection system 400 according to the fourth embodiment. The detection system 400 includes a plurality of detection units 12_0 to 12_n (n is an integer of 1 or more), a signal processing unit 6A, and the microcomputer 2. Since the microcomputer 2 is the same as that of the first embodiment, the description thereof is omitted.

  The detection units 12_0 to 12_n may be the same type of detection unit, or may include different types of detection units. Analog signals AS0 to ASn that are output signals from the detection units 12_0 to 12_n are input to the signal processing unit 6A.

  The signal processing unit 6A includes a communication unit 11, an oscillator 13, an A / D converter 14, a memory 15, a frequency correction unit 16, and a multiplexer 17. In this example, the communication unit 11, the oscillator 13, the A / D converter 14, the memory 15, the frequency correction unit 16, and the multiplexer 17 convert analog signals AS0 to ASn, which are output signals from the detection units 12_0 to 12_n, into A / D. It is configured as an A / D conversion unit for conversion. The communication unit 11, the oscillator 13, the A / D converter 14, the memory 15, and the frequency correction unit 16 are the same as those in the first embodiment, and thus description thereof is omitted.

  The multiplexer 17 is configured to receive analog signals AS0 to ASn, which are output signals from the detection units 12_0 to 12_n, and output any one of the analog signals AS0 to ASn to the A / D converter 14. At this time, for example, the clock signal CLK1 may be input to the multiplexer 17, and a signal to be output based on the clock signal CLK1 may be switched among the analog signals AS0 to ASn.

  The multiplexer 17 may have a sample and hold function for the input signal. In this case, the multiplexer 17 can appropriately switch and output a signal obtained by sampling the analog signals AS0 to ASn. Further, a sample and hold circuit composed of, for example, an analog switch or a capacitor may be inserted between each of the detection units 12_0 to 12_n and the multiplexer 17. In this case, by simultaneously turning on / off the analog switches, it is possible to prevent a time difference for each detection unit from occurring in the sampling timing of the analog signals AS0 to ASn that are output signals from the detection units 12_0 to 12_n. It is. Note that the sampling timing of the analog signals AS0 to ASn may be determined based on the clock signal CLK1, for example.

  Since other operations of the detection system 400 are the same as those of the detection system 100 according to the first embodiment, the description thereof is omitted.

  In this example, the detection units 12_0 to 12_n and the signal processing unit 6A are physically separated from each other. However, the detection units 12_0 to 12_n and the signal processing unit 6A are integrated with each other according to the above-described embodiment. It can be understood as constituting the sensor 6 corresponding to the sensor. In other words, the detection unit may be provided as an external component of the signal processing unit. By physically separating the detection unit and the signal processing unit, the detection unit can be selected and exchanged according to the application, and the configuration flexibility of the detection system can be improved.

  In FIG. 13, the analog signals AS0 to ASn from the detection units 12_0 to 12_n have been described as being input to the multiplexer 17, but a plurality of A / D converters may be provided instead of the multiplexer 17. FIG. 14 is a diagram schematically illustrating a configuration of a detection system 401 that is a modification of the detection system 400 according to the fourth embodiment. As shown in FIG. 14, the detection system 401 has a configuration in which the signal processing unit 6A of the detection system 400 is replaced with a signal processing unit 7A. The signal processing unit 7A has a configuration in which the A / D converter 14 and the multiplexer 17 of the signal processing unit 6A are replaced with A / D converters 14_0 to 14_n.

  The A / D converters 14_0 to 14_n respectively sample the analog signals AS0 to ASn, convert them to digital signals (sampling data SD0 to SDn), and then output them to the memory 15. At this time, any one of the A / D converters 14_0 to 14_n alternatively outputs sampling data based on the clock signal CLK1 supplied from the oscillator 13. Then, the A / D converter that outputs the sampling data is switched according to the clock signal CLK1, so that the memory 15 selectively selects any of the sampling data SD0 to SDn output from the A / D converters 14_0 to 14_n. The received sampling data can be sequentially held.

  Since other operations of the detection system 401 are the same as those of the detection system 100 according to the first embodiment, the description thereof is omitted.

  Also in this example, the detection units 12_0 to 12_n and the signal processing unit 7A are physically separated from each other, but the detection units 12_0 to 12_n and the signal processing unit 7A are integrally applied to the above-described embodiment. It can be understood as constituting the sensor 7 corresponding to the sensor. In other words, the detection unit may be provided as an external component of the signal processing unit. By physically separating the detection unit and the signal processing unit, the detection unit can be selected and exchanged according to the application, and the configuration flexibility of the detection system can be improved.

  As described above, according to the present configuration, even when a plurality of detection units are provided, sampling data can be output from the signal processing unit to the microcomputer in response to a request from the microcomputer, as in the first embodiment. it can.

  In addition, although the detection system 400 was demonstrated as what is a modification of the detection system 100 concerning Embodiment 1, this is only an illustration. It goes without saying that the sensor of the detection system 200 according to the second exemplary embodiment may similarly include a plurality of detection units and multiplexers. In the second embodiment, the calculation unit 23 of the microcomputer 3 calculates the sampling time Ts in consideration of the delay times TD1 and TD2 using the equation [2]. However, in this configuration, the multiplexer The sampling time Ts may be calculated by further adding the time required for switching the signal output from the signal or the delay of the signal generated by the multiplexer itself as a delay time.

  Needless to say, the sensor of the detection system 200 according to the second embodiment may similarly include a plurality of detection units and a plurality of A / D converters.

  Furthermore, it goes without saying that the sensor of the detection system 300 according to the third embodiment may be appropriately replaced with a plurality of detection units and signal processing units described in the present embodiment.

Embodiment 5
A detection system 500 according to the fifth embodiment will be described. FIG. 15 is a diagram schematically illustrating a configuration of a detection system 500 according to the fifth embodiment. The detection system 500 is a modification of the detection system 400 according to the fourth embodiment, and a reference clock CLKR referred to by the oscillator 13 is given to the oscillator 13 by an oscillator 50 outside the signal processing unit 6A. Since the other configuration of the detection system 500 is the same as that of the detection system 400, description thereof is omitted.

  According to this configuration, the oscillator 13 can output the clock signal CLK1 whose frequency is adjusted so as to be frequency-synchronized with the clock signal CLK2 in the microcomputer by the control signal CON with the reference clock CLKR as a reference. It becomes.

  In this example, the detection units 12_0 to 12_n and the signal processing unit 6A are physically separated from each other. However, like the detection system 400, the detection units 12_0 to 12_n and the signal processing unit 6A are integrated. It can be understood as constituting the sensor 6 corresponding to the sensor according to the above-described embodiment. In other words, the detection unit may be provided as an external component of the signal processing unit. By physically separating the detection unit and the signal processing unit, the detection unit can be selected and exchanged according to the application, and the configuration flexibility of the detection system can be improved.

  In addition, although the detection system 500 was demonstrated as what is a modification of the detection system 400 concerning Embodiment 4, this is only an illustration. That is, the resonator 50 may be provided similarly in the detection system according to the fourth embodiment other than the detection system 400.

Embodiment 6
A detection system 600 according to the sixth embodiment will be described. FIG. 16 is a diagram schematically illustrating a configuration of a detection system 600 according to the sixth embodiment. The detection system 600 has a configuration in which the signal processing unit 6A of the detection system 400 according to the fourth embodiment is replaced with a microcontroller unit (MCU: Micro Control Unit) 8A that is one form of the signal processing unit. Since the other configuration of the detection system 600 is the same as that of the detection system 400, description thereof is omitted.

  The detection system 600 realizes a frequency correction function by the frequency correction unit 16 of the detection system 400 by calculation with a CPU. Therefore, as shown in FIG. 16, in the MCU 8A of the detection system 600, the communication unit 11 and the frequency correction unit 16 of the detection system 400 signal processing unit 6A are removed, and a bus 61 and a CPU 62 are provided instead. Since the oscillator 13, the A / D converter 14, the memory 15, and the multiplexer 17 are the same as those in the detection system 400, description thereof is omitted.

  The bus 61 is configured to exchange address information and data among the oscillator 13, the A / D converter 14, the memory 15, and the CPU 62.

  Based on the clock signal CLK1 output from the oscillator 13 and the clock signal CLK2 output from the microcomputer 2 via the bus 61, the CPU 62 generates an oscillator so that the clock signal CLK1 is frequency-synchronized with the clock signal CLK2. The control signal CON for controlling 13 is output to the oscillator 13.

  In this example, the CPU 62 can receive the clock signal CLK1 output from the oscillator 13 and the clock signal CLK2 output from the microcomputer 2. Then, the CPU 62 compares the clock signal CLK1 and the clock signal CLK2, detects a frequency shift between them, and outputs a control signal CON based on the detection result. The oscillator 13 appropriately adjusts the frequency of the clock signal CLK1 in accordance with the received control signal CON.

  In this example, the detection units 12_0 to 12_n and the signal processing unit 8A are physically separated from each other. However, the detection units 12_0 to 12_n and the signal processing unit 8A are integrally formed according to the above-described embodiment. It can be understood as constituting the sensor 8 corresponding to the sensor. In other words, the detection unit may be provided as an external component of the signal processing unit. By physically separating the detection unit and the signal processing unit, the detection unit can be selected and exchanged according to the application, and the configuration flexibility of the detection system can be improved.

  Next, a modified example of the detection system 600 will be described. FIG. 17 is a diagram schematically illustrating a configuration of a detection system 601 that is a modification of the detection system 600 according to the sixth embodiment. The detection system 601 has a configuration in which the MCU 8A of the detection system 600 is replaced with an MCU 9A that is a form of a signal processing unit.

  The MCU 9A has a configuration in which a communication unit 71, a DMAC (Direct Memory Access Controller) 72, a ROM (Read Only Memory) 73, and a timer 74 are added to the MCU 8A.

  The communication unit 71 is connected to the bus 61 and has the same function as the communication unit 11 described above.

  The DMAC 72 can perform data transfer performed via the CPU. For example, the DMAC 72 can execute data transfer from the memory 15 to the communication unit 71 instead of the CPU 62. As a result, the data transfer load of the CPU 62 can be reduced. Note that data transfer performed by the DMAC is not limited to this example.

  The ROM 73 stores, for example, a program that defines the processing in the CPU 62 and parameters used for the processing, and the CPU 62 can read out the program and parameters from the ROM 62 as necessary.

  The timer 74 receives the clock signal CLK1 output from the oscillator 13 via the bus 61. The timer 74 receives the clock signal CLK2 output from the microcomputer 2 via the communication unit 71 and the bus 61. The timer 74 can detect the pulse width and frequency of the clock signals CLK1 and CLK2 by a timer function. Accordingly, the timer 74 detects a frequency shift of the clock signal CLK1 with respect to the clock signal CLK2. The CPU 62 receives the data DET indicating the frequency shift of the clock signal CLK1 detected by the timer 74 via the bus 61, and outputs the control signal CON to the oscillator 13 according to the data DET, so that the clock signal CLK1 The frequency can be synchronized with the frequency of the clock signal CLK2.

  Since other configurations and operations of the detection system 601 are the same as those of the detection system 400, description thereof is omitted.

  In this example, the detection units 12_0 to 12_n and the signal processing unit 9A are physically separated from each other, but the detection units 12_0 to 12_n and the signal processing unit 9A are integrally applied to the above-described embodiment. It can be understood as constituting the sensor 9 corresponding to the sensor. In other words, the detection unit may be provided as an external component of the signal processing unit. By physically separating the detection unit and the signal processing unit, the detection unit can be selected and exchanged according to the application, and the configuration flexibility of the detection system can be improved.

  According to this configuration, the frequency of the clock signal CLK1 is changed to the clock signal as in the first to fifth embodiments by applying arithmetic processing by a CPU or a microcomputer instead of the frequency correction unit 16 configured by an electric circuit. It can be synchronized with the frequency of CLK2.

  Also in this configuration, as in the fourth embodiment, the sampling time Ts is calculated by adding the time required for switching the signal output from the multiplexer and the delay of the signal generated in the multiplexer itself as a delay time. Needless to say. Similarly to the fifth embodiment, the reference clock CLKR referred to by the oscillator 13 may be supplied to the oscillator 13 by an oscillator outside the signal processing unit.

  Similarly to the detection system 401, the MCUs 8 </ b> A and 9 </ b> A may include A / D converters 14 </ b> _ <b> 0 to 14 </ b> _n corresponding to the detection units 12 </ b> _ <b> 0 to 12 </ b> _n instead of the A / D converter 14 and the multiplexer 17. Needless to say good things.

Other Embodiments The present invention is not limited to the above-described embodiments, and can be appropriately changed without departing from the spirit of the present invention. For example, in the first to third embodiments, the sensor is described as including a detection unit and a signal processing unit, but the configuration of the detection system is not limited to this. Needless to say, the detection unit and the signal processing unit may be physically separated as in the fourth to sixth embodiments. In other words, the detection unit may be provided as an external component of the signal processing unit. By physically separating the detection unit and the signal processing unit, the detection unit can be selected and exchanged according to the application, and the configuration flexibility of the detection system can be improved.

  In the above embodiment, information such as data, a clock signal, and a request is exchanged between the sensor or signal processing unit and the microcomputer, but this exchange of information may be performed by wired communication. The wireless communication may be performed.

  Although the serial data SER has been described in the second embodiment, not only the serial data SER is added to all the sampling data SD output from the sensor, but also the serial data SER is added to the sampling data SD at every fixed number of outputs. May be. For example, every time the sampling data SD is output ten times, the serial data SER incremented by “10” from the previous data output may be added. The microcomputer 3 can calculate the sampling time of the output data to which the serial data SER is not added by adding an integer multiple of the sampling period to the calculated sampling time.

  In the above description, the second embodiment has been described on the assumption that the data sampling time is calculated based on the serial data SER as well as the frequency correction of the clock signal CLK1 according to the first embodiment. However, the configuration for calculating the sampling time based on the serial data SER described in the second embodiment is not based on the existence of the configuration for correcting the frequency of the clock signal CLK1 according to the first embodiment. In other words, it does not hinder the realization of the detection system having the configuration for calculating the sampling time according to the second embodiment without the configuration for correcting the frequency of the clock signal CLK1 according to the first embodiment.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the embodiments already described, and various modifications can be made without departing from the scope of the invention. It goes without saying that it is possible.

  In the first embodiment, the configuration of the frequency correction unit has been described with reference to FIG. 4, but this is merely an example. As long as the same control signal can be output to the oscillator, other configurations can be applied as appropriate.

  As described above, the detection system, the sensor, the microcomputer, and the correction method of the detection system can be described as follows.

  (Supplementary note 1) A sensor configured to output sampling data which is a digital signal generated by analog / digital conversion of an analog signal indicating a detection result sampled based on the first clock signal, and a second clock signal And a microcomputer that reads out the sampling data from the sensor, and the sensor determines the frequency of the first clock signal based on the second clock signal. Correction system to correct.

(Appendix 2) The sensor corrects the frequency based on a first input / output unit that performs data communication with the microcomputer, a detection unit that outputs a detection result as the analog signal, and a given control signal An oscillator that outputs the first clock signal; a frequency correction unit that outputs the control signal based on the second clock signal received from the microcomputer via the first input / output unit; An analog signal is sampled based on the first clock signal, converted from analog to digital, and an analog / digital converter that outputs the sampling data; a memory that stores the sampling data;
The detection according to claim 1, further comprising: a clock signal generation unit that generates the second clock signal; and a second input / output unit that performs data communication with the sensor. system.

  (Supplementary note 3) The detection system according to supplementary note 2, wherein the microcomputer outputs the second clock signal when reading the sampling data from the memory.

  (Supplementary Note 4) The frequency correction unit includes a frequency divider that divides the second clock signal, a first frequency voltage conversion unit that outputs a first signal indicating the frequency of the first clock signal, and A second frequency voltage converter for outputting a second signal indicating the frequency of the signal divided by the frequency divider, and a signal indicating a difference voltage between the first signal and the second signal. A differential amplifier for outputting, a comparator for comparing the second signal with a signal of a predetermined value, and outputting a switching signal indicating a comparison result, and the differential amplifier outputting the switching signal in response to the switching signal A voltage hold unit that holds a voltage of a signal; and a switch that connects the oscillator to either the output of the differential amplifier or the output of the voltage hold unit in response to the switching signal; The oscillator is the differential amplifier By being connected to the output, the voltage of the signal output from the differential amplifier is input to the oscillator as the control signal, and the oscillator is connected to the output of the voltage hold unit, so that the voltage The detection system according to appendix 2, wherein the voltage held by the hold unit is input to the oscillator as the control signal.

  (Supplementary Note 5) The switch connects the oscillator and the output of the differential amplifier when the second clock signal is input from the microcomputer, and the second clock is output from the microcomputer. The detection system according to appendix 4, wherein when no signal is input, the oscillator and the output of the voltage hold unit are connected.

  (Additional remark 6) The said microcomputer can output a reset signal to the said sensor, The said memory is a serial which shows the sampling frequency of the data after receiving the said reset signal according to the read-out request from the said microcomputer The data is output to the microcomputer together with the corresponding sampling data, and the microcomputer receives the reset signal based on the reference time, the sampling period of the sensor, and the received serial data. The detection system according to appendix 2, further comprising a calculation unit that calculates a sampling time of the sampling data.

  (Supplementary note 7) The detection system according to supplementary note 6, wherein the calculation unit calculates the sampling time by adding a value obtained by multiplying the sampling period by the value of the received serial data to the reference time.

  (Additional remark 8) The said calculating part further adds the delay time after the said calculating part outputs the said reset signal until the said serial data is reset, and calculates the said sampling time, Additional remark 7 Detection system.

  (Additional remark 9) The said calculating part further adds the delay time required to convert the said analog signal into the said sampling data based on the said 1st clock signal, and calculates the said sampling time, Additional remark 7 Detection system.

  (Supplementary note 10) The detection system according to supplementary note 6, wherein the serial data is output to the microcomputer together with corresponding sampling data every time reading is requested from the microcomputer.

  (Supplementary note 11) The detection system according to supplementary note 6, wherein the serial data is output to the microcomputer together with corresponding sampling data every time a predetermined number of readings are requested from the microcomputer.

  (Supplementary note 12) The detection system according to supplementary note 6, wherein a plurality of the sensors are provided, and sampling data sampled at the same time by the plurality of sensors are correlated with each other based on the calculated sampling time.

  (Additional remark 13) It is comprised so that the sampling data which is a digital signal produced | generated by carrying out analog / digital conversion of the analog signal which shows the detection result sampled based on the 1st clock signal can be output, and the 2nd produced | generated by the microcomputer A sensor that corrects the frequency of the first clock signal based on the clock signal and reads the sampling data by the microcomputer.

(Supplementary Note 14) A first input / output unit that performs data communication with the microcomputer, a detection unit that outputs a detection result as the analog signal, and a frequency that is corrected based on a given control signal An oscillator that outputs the clock signal, a frequency correction unit that outputs the control signal based on the second clock signal received from the microcomputer via the first input / output unit, and the analog signal, An analog / digital converter for sampling and analog / digital conversion based on the first clock signal and outputting the sampling data; and a memory for storing the sampling data;
The sensor according to appendix 13, comprising:

  (Supplementary note 15) The microcomputer includes a clock signal generation unit that generates the second clock signal and a second input / output unit that performs data communication with the sensor. Sensor.

  (Supplementary note 16) The sensor according to supplementary note 14, wherein the microcomputer outputs the second clock signal when reading the sampling data from the memory.

  (Supplementary Note 17) The frequency correction unit includes a frequency divider that divides the second clock signal, a first frequency voltage conversion unit that outputs a first signal indicating the frequency of the first clock signal, and A second frequency voltage converter for outputting a second signal indicating the frequency of the signal divided by the frequency divider, and a signal indicating a difference voltage between the first signal and the second signal. A differential amplifier for outputting, a comparator for comparing the second signal with a signal of a predetermined value, and outputting a switching signal indicating a comparison result, and the differential amplifier outputting the switching signal in response to the switching signal A voltage hold unit that holds a voltage of a signal; and a switch that connects the oscillator to either the output of the differential amplifier or the output of the voltage hold unit in response to the switching signal; The oscillator is the differential amplification The voltage of the signal output from the differential amplifier is input to the oscillator as the control signal, and the oscillator is connected to the output of the voltage hold unit. 15. The sensor according to appendix 14, wherein the voltage held by the voltage hold unit is input to the oscillator as the control signal.

  (Supplementary note 18) When the second clock signal is input from the microcomputer, the switch connects the oscillator and the output of the differential amplifier, and the switch supplies the second clock from the microcomputer. 18. The sensor according to appendix 17, wherein the sensor is connected to the output of the voltage hold unit when no signal is input.

  (Supplementary note 19) The microcomputer is capable of outputting a reset signal to the sensor, and the memory is a serial indicating the number of times data is sampled after receiving the reset signal in response to a read request from the microcomputer. The data is output to the microcomputer together with the corresponding sampling data, and the microcomputer receives the reset signal based on the reference time, the sampling period of the sensor, and the received serial data. The sensor according to appendix 14, further comprising a calculation unit that calculates a sampling time of the sampling data.

  (Supplementary note 20) The sensor according to supplementary note 19, wherein the calculation unit calculates the sampling time by adding a value obtained by multiplying the sampling period by the value of the received serial data to the reference time.

  (Supplementary note 21) The calculation unit according to supplementary note 20, wherein the calculation unit further calculates a sampling time by further adding a delay time from when the calculation unit outputs the reset signal to when the serial data is reset. Sensor.

  (Additional remark 22) The said calculating part further adds the delay time required to convert the said analog signal into the said sampling data based on the said 1st clock signal, and calculates the said sampling time, Additional remark 20 Sensor.

  (Supplementary note 23) The sensor according to supplementary note 19, wherein the serial data is output to the microcomputer together with corresponding sampling data every time reading is requested from the microcomputer.

  (Supplementary note 24) The sensor according to supplementary note 19, wherein the serial data is output to the microcomputer together with corresponding sampling data every time the microcomputer requests reading a predetermined number of times.

  (Supplementary note 25) The sensor according to supplementary note 19, wherein the sampling data sampled at the same time by the plurality of sensors are correlated with each other based on the calculated sampling time.

  (Supplementary Note 26) A second clock signal is output to a sensor configured to output sampling data which is a digital signal generated by analog / digital conversion of an analog signal indicating a detection result sampled based on the first clock signal. And the sampling data can be read from the sensor, and the frequency of the first clock signal is corrected by the sensor based on the second clock signal. Computer.

(Supplementary Note 27) A clock signal generation unit that generates the second clock signal and a second input / output unit that performs data communication with the sensor.
27. The microcomputer according to claim 26.

(Supplementary Note 28) The sensor corrects the frequency based on a first input / output unit that performs data communication with the microcomputer, a detection unit that outputs a detection result as the analog signal, and a given control signal An oscillator that outputs the first clock signal; a frequency correction unit that outputs the control signal based on the second clock signal received from the microcomputer via the first input / output unit; An analog signal is sampled based on the first clock signal, converted from analog to digital, and an analog / digital converter that outputs the sampling data; a memory that stores the sampling data;
27. The microcomputer according to appendix 26.

  (Supplementary note 29) The microcomputer according to supplementary note 28, wherein the second clock signal is output when the sampling data is read from the memory.

  (Supplementary Note 30) The frequency correction unit includes a frequency divider that divides the second clock signal, a first frequency voltage conversion unit that outputs a first signal indicating the frequency of the first clock signal, and A second frequency voltage converter for outputting a second signal indicating the frequency of the signal divided by the frequency divider, and a signal indicating a difference voltage between the first signal and the second signal. A differential amplifier for outputting, a comparator for comparing the second signal with a signal of a predetermined value, and outputting a switching signal indicating a comparison result, and the differential amplifier outputting the switching signal in response to the switching signal A voltage hold unit that holds a voltage of a signal; and a switch that connects the oscillator to either the output of the differential amplifier or the output of the voltage hold unit in response to the switching signal; The oscillator is the differential amplification The voltage of the signal output from the differential amplifier is input to the oscillator as the control signal, and the oscillator is connected to the output of the voltage hold unit. 29. The microcomputer according to appendix 28, wherein the voltage held by the voltage hold unit is input to the oscillator as the control signal.

  (Supplementary Note 31) When the second clock signal is input from the microcomputer, the switch connects the oscillator and the output of the differential amplifier, and the switch supplies the second clock from the microcomputer. 31. The microcomputer according to appendix 30, wherein the microcomputer and the output of the voltage hold unit are connected when no signal is input.

  (Supplementary Note 32) A reset signal can be output to the sensor, and the memory corresponds to serial data indicating the number of times of sampling of the data after receiving the reset signal in response to a read request from the microcomputer. The microcomputer outputs the sampling data together with the sampling data, and the microcomputer samples the received sampling data based on the reference time when the reset signal is output, the sampling period of the sensor, and the received serial data. 29. The microcomputer according to appendix 28, further comprising a calculation unit that calculates time.

  (Supplementary note 33) The microcomputer according to supplementary note 32, wherein the calculation unit calculates the sampling time by adding a value obtained by multiplying the sampling period by the value of the received serial data to the reference time.

  (Supplementary note 34) The calculation unit according to supplementary note 33, wherein the calculation unit further adds a delay time from when the calculation unit outputs the reset signal to when the serial data is reset to calculate the sampling time. Microcomputer.

  (Additional remark 35) The said calculating part further adds the delay time required to convert the said analog signal into the said sampling data based on the said 1st clock signal, and calculates the said sampling time, Additional remark 33 Microcomputer.

  (Supplementary note 36) The microcomputer according to supplementary note 32, wherein the serial data is output to the microcomputer together with corresponding sampling data every time reading is requested from the microcomputer.

  (Supplementary note 37) The microcomputer according to supplementary note 32, wherein the serial data is output to the microcomputer together with corresponding sampling data every time the microcomputer requests reading a predetermined number of times.

  (Supplementary note 38) The microcomputer according to supplementary note 32, comprising a plurality of the sensors, wherein the sampling data sampled at the same time by the plurality of sensors are correlated with each other based on the calculated sampling times.

  (Supplementary note 39) The microcomputer according to supplementary note 28, wherein the second clock signal is output when the sampling data is read from the sensor.

  (Supplementary Note 40) A reset signal can be output to the sensor, and the sensor corresponds to serial data indicating the number of times of sampling of the data after receiving the reset signal in response to a read request from the microcomputer. The microcomputer outputs the sampling data together with the sampling data, and the microcomputer samples the received sampling data based on the reference time when the reset signal is output, the sampling period of the sensor, and the received serial data. 29. The microcomputer according to appendix 28, further comprising a calculation unit that calculates time.

  (Supplementary Note 41) The second clock signal is generated, and sampling data which is a digital signal generated by analog / digital conversion of an analog signal indicating a detection result sampled based on the first clock signal can be output. The sensor outputs the second clock signal from a microcomputer that reads the sampling data from the sensor, and causes the sensor to correct the frequency of the first clock signal based on the second clock signal. , Detection system correction method.

  (Supplementary Note 42) The sensor corrects the frequency based on a first input / output unit that performs data communication with the microcomputer, a detection unit that outputs a detection result as the analog signal, and a control signal that is provided. An oscillator that outputs the first clock signal; a frequency correction unit that outputs the control signal based on the second clock signal received from the microcomputer via the first input / output unit; The microcomputer comprising: an analog / digital converter that samples and analog / digital converts an analog signal based on the first clock signal and outputs the sampling data; and a memory that stores the sampling data Between the clock signal generator that generates the second clock signal and the sensor. Comprising a second output unit for performing Data Communications, a method of correcting the detection system according to note 41.

  (Supplementary note 43) The correction method of the detection system according to supplementary note 42, wherein the microcomputer outputs the second clock signal when reading the sampling data from the memory.

  (Supplementary Note 44) The frequency correction unit includes a frequency divider that divides the second clock signal, and a first frequency-voltage conversion unit that outputs a first signal indicating the frequency of the first clock signal. A second frequency voltage converter for outputting a second signal indicating the frequency of the signal divided by the frequency divider, and a signal indicating a difference voltage between the first signal and the second signal. A differential amplifier for outputting, a comparator for comparing the second signal with a signal of a predetermined value, and outputting a switching signal indicating a comparison result, and the differential amplifier outputting the switching signal in response to the switching signal A voltage hold unit that holds a voltage of a signal; and a switch that connects the oscillator to either the output of the differential amplifier or the output of the voltage hold unit in response to the switching signal; The oscillator is the differential amplification The voltage of the signal output from the differential amplifier is input to the oscillator as the control signal, and the oscillator is connected to the output of the voltage hold unit. 43. The correction method of the detection system according to appendix 42, wherein the voltage held by the voltage hold unit is input to the oscillator as the control signal.

  (Supplementary Note 45) When the second clock signal is input from the microcomputer to the switch, the oscillator and the output of the differential amplifier are connected to the switch. 45. The correction method of the detection system according to appendix 44, wherein when the clock signal is not input, the oscillator and the output of the voltage hold unit are connected.

  (Supplementary Note 46) The microcomputer is capable of outputting a reset signal to the sensor, and a serial number indicating the number of times data is sampled after the reset signal is received in the memory in response to a read request from the microcomputer The data is output to the microcomputer together with the corresponding sampling data, and the microcomputer receives the reset time based on the reference time, the sampling period of the sensor, and the received serial data. 45. The correction method of the detection system according to appendix 44, wherein a sampling time of the sampling data is calculated.

  (Supplementary note 47) The correction method of the detection system according to supplementary note 46, wherein the sampling time is calculated by adding a value obtained by multiplying the sampling period by the value of the received serial data to the reference time.

  (Supplementary note 48) The detection system correction method according to supplementary note 47, wherein a delay time from when the reset signal is output to when the serial data is reset is further added to calculate the sampling time.

  (Supplementary note 49) The correction of the detection system according to supplementary note 47, wherein the sampling time is calculated by further adding a delay time required to convert the analog signal into the sampling data based on the first clock signal. Method.

  (Supplementary note 50) The detection system correction method according to supplementary note 46, wherein the serial data is output to the microcomputer together with corresponding sampling data every time reading is requested from the microcomputer.

  (Supplementary note 51) The detection system correction method according to supplementary note 46, wherein the serial data is output to the microcomputer together with corresponding sampling data each time a read request is made from the microcomputer a predetermined number of times.

  (Supplementary note 52) The detection system correction method according to supplementary note 46, wherein a plurality of the sensors are provided, and sampling data sampled at the same time by the plurality of sensors are correlated with each other based on the calculated sampling time.

1, 4-9 Sensor 1A, 6A, 7A Signal processor 2, 3 Microcomputer 8A, 9A MCU
DESCRIPTION OF SYMBOLS 11, 71 Communication part 12, 12_0-12_n Detection part 13 Oscillator 14, 14_0-14_n A / D converter 15 Memory 16 Frequency correction part 17 Multiplexer 21 Communication part 22 Clock signal generation part 23 Calculation part 31 Voltage control circuit 32 Constant current Circuit 33 Timing control circuit 34, 35, 42 Switch 36, 43 Capacitance 41 Operational amplifier 50 Oscillator 61 Bus 62 CPU
72 DMAC
73 ROM
74 Timer 161 Divider 162, 163 Frequency Voltage Converter 164 Comparator 165 Differential Amplifier 166 Voltage Hold Unit 167 Switch CHR Charge Signal CLK1, CLK2 Clock Signal CLKD Divided Signal CLKIN Clock Signal CLKR Reference Clock DCHR Discharge Signal CON Control Signal INV_1 to INV_n Inversion circuit SD sampling data REQ request RS reset signal AS analog signal SD sampling data SER serial data 100, 200, 300, 400, 401, 500, 600, 601 detection system

Claims (20)

A sensor configured to output sampling data which is a digital signal generated by analog / digital conversion of an analog signal indicating a detection result sampled based on a first clock signal;
A microcomputer that generates and outputs a second clock signal to the sensor and reads the sampling data from the sensor;
The sensor corrects the frequency of the first clock signal based on the second clock signal;
Detection system. The sensor is
A first input / output unit for performing data communication with the microcomputer;
A detection unit for outputting a detection result as the analog signal;
An oscillator for outputting the first clock signal whose frequency is corrected based on a given control signal;
A frequency correction unit that outputs the control signal based on the second clock signal received from the microcomputer via the first input / output unit;
An analog / digital converter that samples the analog signal based on the first clock signal, performs analog / digital conversion, and outputs the sampling data;
A memory for storing the sampling data;
With
The microcomputer is
A clock signal generator for generating the second clock signal;
A second input / output unit that performs data communication with the sensor,
The detection system according to claim 1. The microcomputer outputs the second clock signal when reading the sampling data from the memory.
The detection system according to claim 2. The frequency correction unit is
A frequency divider for dividing the second clock signal;
A first frequency-voltage converter that outputs a first signal indicating the frequency of the first clock signal;
A second frequency voltage converter that outputs a second signal indicating the frequency of the signal divided by the frequency divider;
A differential amplifier that outputs a signal indicating a voltage difference between the first signal and the second signal;
A comparator that compares the second signal with a signal of a predetermined value and outputs a switching signal indicating a comparison result;
In response to the switching signal, a voltage hold unit that holds the voltage of the signal output from the differential amplifier;
In response to the switching signal, the oscillator includes a switch that connects either the output of the differential amplifier or the output of the voltage hold unit, and the oscillator,
By connecting the oscillator to the output of the differential amplifier, the voltage of the signal output from the differential amplifier is input to the oscillator as the control signal,
By connecting the oscillator to the output of the voltage hold unit, the voltage held by the voltage hold unit is input to the oscillator as the control signal.
The detection system according to claim 2. The switch is
When the second clock signal is input from the microcomputer, the oscillator and the output of the differential amplifier are connected,
When the second clock signal is not input from the microcomputer, the oscillator and the output of the voltage hold unit are connected.
The detection system according to claim 4. The microcomputer can output a reset signal to the sensor,
In response to a read request from the microcomputer, the memory outputs serial data indicating the number of times of sampling of the data after receiving the reset signal, together with corresponding sampling data, to the microcomputer.
The microcomputer further includes a calculation unit that calculates a sampling time of the received sampling data based on a reference time at which the reset signal is output, a sampling period in the sensor, and the received serial data.
The detection system according to claim 2. The calculation unit calculates the sampling time by adding a value obtained by multiplying the value of the received serial data by the sampling period to the reference time.
The detection system according to claim 6. The calculation unit further adds a delay time from when the calculation unit outputs the reset signal until the serial data is reset, to calculate the sampling time,
The detection system according to claim 7. The arithmetic unit further adds a delay time required to convert the analog signal to the sampling data based on the first clock signal to calculate the sampling time.
The detection system according to claim 7. The serial data is output to the microcomputer together with corresponding sampling data each time reading is requested from the microcomputer.
The detection system according to claim 6. The serial data is output to the microcomputer together with corresponding sampling data every time reading from the microcomputer is requested a predetermined number of times.
The detection system according to claim 6. A plurality of the sensors;
Based on the calculated sampling time, correlate sampling data sampled at the same time by a plurality of the sensors,
The detection system according to claim 6. It is configured to be able to output sampling data which is a digital signal generated by analog / digital conversion of an analog signal indicating a detection result sampled based on the first clock signal,
Based on the second clock signal generated by the microcomputer, the frequency of the first clock signal is corrected,
The sampling data is read by the microcomputer.
Sensor. A first input / output unit for performing data communication with the microcomputer;
A detection unit for outputting a detection result as the analog signal;
An oscillator for outputting the first clock signal whose frequency is corrected based on a given control signal;
A frequency correction unit that outputs the control signal based on the second clock signal received from the microcomputer via the first input / output unit;
An analog / digital converter that samples the analog signal based on the first clock signal, performs analog / digital conversion, and outputs the sampling data;
A memory for storing the sampling data;
Comprising
The sensor according to claim 13. The frequency correction unit is
A frequency divider for dividing the second clock signal;
A first frequency-voltage converter that outputs a first signal indicating the frequency of the first clock signal;
A second frequency voltage converter that outputs a second signal indicating the frequency of the signal divided by the frequency divider;
A differential amplifier that outputs a signal indicating a voltage difference between the first signal and the second signal;
A comparator that compares the second signal with a signal of a predetermined value and outputs a switching signal indicating a comparison result;
In response to the switching signal, a voltage hold unit that holds the voltage of the signal output from the differential amplifier;
In response to the switching signal, the oscillator includes a switch that connects either the output of the differential amplifier or the output of the voltage hold unit, and the oscillator,
By connecting the oscillator to the output of the differential amplifier, the voltage of the signal output from the differential amplifier is input to the oscillator as the control signal,
By connecting the oscillator to the output of the voltage hold unit, the voltage held by the voltage hold unit is input to the oscillator as the control signal.
The sensor according to claim 14. The switch is
When the second clock signal is input from the microcomputer, the oscillator and the output of the differential amplifier are connected,
When the second clock signal is not input from the microcomputer, the oscillator and the output of the voltage hold unit are connected.
The sensor according to claim 15. A second clock signal is generated in a sensor configured to output sampling data that is a digital signal generated by analog / digital conversion of an analog signal indicating a detection result sampled based on the first clock signal. Output, and configured to be able to read the sampling data from the sensor,
The frequency of the first clock signal is corrected by the sensor based on the second clock signal.
Microcomputer. A clock signal generator for generating the second clock signal;
A second input / output unit that performs data communication with the sensor,
The microcomputer according to claim 17. The microcomputer outputs the second clock signal when reading the sampling data from the sensor.
The microcomputer according to claim 18. A reset signal can be output to the sensor;
In response to a read request from the microcomputer, the sensor outputs serial data indicating the number of times of sampling of the data after receiving the reset signal, together with corresponding sampling data, to the microcomputer.
The microcomputer further includes a calculation unit that calculates a sampling time of the received sampling data based on a reference time at which the reset signal is output, a sampling period in the sensor, and the received serial data.
The microcomputer according to claim 18.

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