JP2018137423A - Thin-film transistor, thin-film device, and method for manufacturing thin-film transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a thin film transistor, a thin film device and a method for manufacturing a thin film transistor, in which the length of the TFT having an etch stop structure can be shortened as compared with the channel of the prior art and the on-current can be increased. SOLUTION: A gate electrode 12, a gate insulating film 13, an oxide semiconductor film 14, an etch stop layer 15 for protecting the oxide semiconductor film 14, and a source / drain electrode portion (16, 17) are provided on a substrate 1. The etch stop layer 15 is laminated in this order, and the first etch stop layer 1 (15A) having a SiNx content of a predetermined reference value or more and a SiNx content of less than a predetermined reference value. It is composed of a second etch stop layer 2 (15B). [Selection diagram] Fig. 1

Description

The present invention, for example, a thin film transistor used for driving an organic EL element or LCD,
The present invention relates to a thin film device and a method for manufacturing a thin film transistor.

  An oxide semiconductor has higher carrier mobility than general-purpose amorphous silicon. Oxide semiconductors have a large optical band gap and can be deposited at low temperatures, so they are expected to be applied to next-generation displays that require large size, high resolution, and high-speed driving, and resin substrates with low heat resistance. .

When the oxide semiconductor is used as a semiconductor layer of a TFT, it is required that the TFT has excellent switching characteristics. Specifically, (1) the on-current, that is, the maximum drain current when a positive voltage is applied to the gate electrode and the drain electrode is large, and (2) the off-current, that is, the negative voltage is applied to the gate electrode. When the positive voltage is applied, the drain current is small, (3) S value (Subthreshold Swing), that is, the gate voltage required to increase the drain current by one digit is small, and (4) the threshold voltage, It is required that the voltage at which the drain current starts flowing when a positive voltage is applied to the drain electrode and a positive or negative voltage is applied to the gate voltage does not change with time and is stable.
Here, in order to increase the on-state current, it is required that the field effect mobility (hereinafter, simply referred to as mobility) is high, the channel length is short, and the like.

Examples of the oxide semiconductor include an In—Ga—Zn-based oxide semiconductor composed of indium, gallium, zinc, and oxygen, and In—Ga— composed of indium, gallium, and tin, as shown in Patent Documents 1 and 2 below. Sn-based oxide semiconductors are well known.
As shown in FIG. 9, the TFT structure includes a gate electrode 112, a gate insulating film 113, an oxide semiconductor film 114, an etch stop layer 115 for protecting the oxide semiconductor film 114, and source / drain electrode portions on a substrate 111. An etch stop structure for forming (116, 117) in this order is used (see Patent Documents 1 and 2).

Japanese Patent No. 5357342 JP 2011-174134 A

As described above, in order to increase the on-current, it is useful to set the channel length short.
However, in the case of the etch stop structure, the channel length is the shortest distance from the position where the source electrode 116 and the oxide semiconductor 114 are in contact to the position where the drain electrode 117 and the oxide semiconductor 114 are in contact (see FIG. 9). Lsd), the length Ls of the channel 114A1 in the channel length direction of the region of the source electrode 116 in the etch stop layer 115, the length Ld of the channel 114A2 in the channel length direction of the drain electrode region in the etch stop layer 115, and the source This is indicated by the sum of the distance Lg between the electrode 116 and the drain electrode 117.

Therefore, when a TFT is manufactured by processing each layer constituting the TFT using photolithography into a fine pattern, the above Ls and Ld are both set to the alignment margin of photolithography (margin that needs to be provided for misalignment) Da. However, since Lg is limited by the minimum processing dimension Dm of photolithography, it is difficult to adjust the channel length to be shorter than 2 Da + Dm. As a result, it has been difficult to shorten the channel length and increase the on-current.
The present invention has been made in view of the above circumstances, and in a TFT having an etch stop structure, the channel length can be shortened compared to the prior art, and the on-current can be increased. An object of the present invention is to provide a manufacturing method.

In order to solve the above problems, the thin film transistor according to the present invention provides:
A gate electrode, a gate insulating film, an oxide semiconductor film, an etch stop layer for protecting the oxide semiconductor film, and a source / drain electrode portion having a source electrode and a drain electrode on a substrate,
A thin film transistor laminated in this order,
The etch stop layer includes SiNx as a constituent material,
The oxide semiconductor film has electrode part adjacent regions in contact with the source electrode and the drain electrode,
The oxide semiconductor film has a first channel region in contact with the electrode portion adjacent region on the source electrode side, and a second channel region in contact with the electrode portion adjacent region on the drain electrode side,
The oxide semiconductor film further includes a low resistance region that is disposed between the first channel region and the second channel region and has an electrical resistivity lower than an electrical resistivity of each of the two channel regions. It is characterized by having.

The etch stop layer includes a first etch stop layer having a SiNx content equal to or higher than a predetermined reference value and a second etch stop layer having a SiNx content less than the predetermined reference value. It is preferable that the second etch stop layer and the first etch stop layer are sequentially stacked on the oxide semiconductor film.
Here, “content” means the contained weight.
The first etch stop layer preferably has a hydrogen content greater than or equal to a specific reference value, and the second etch stop layer preferably has a hydrogen content less than the specific reference value.

Here, the “first etch stop layer and the second etch stop layer” do not have to be clearly separated as two layers. For example, the content of SiNx gradually increases from the oxide semiconductor film side. In such a case, the portion where the SiNx content is equal to or higher than the predetermined reference value with the predetermined reference value as a boundary is referred to as a first etch stop layer, and the SiNx content is predetermined. A portion less than the reference value is referred to as a second etch stop layer.
In addition, the “first etch stop layer and the second etch stop layer” do not have to be clearly separated as two layers as in the above case. For example, the hydrogen content is on the oxide semiconductor film side. In this case, the portion where the hydrogen content is equal to or higher than the predetermined reference value is referred to as the first etch stop layer, and the hydrogen content is increased. A portion whose content is less than a predetermined reference value is referred to as a second etch stop layer.

Further, the length between the source electrode and the drain electrode, which is parallel to the surface of the substrate, is set larger in the second etch stop layer than in the first etch stop layer. Preferably it is.
Further, the source / drain electrode portion may be configured such that one of the source electrode and the drain electrode and the etch stop layer do not overlap in the vertical direction, or the source / drain electrode portion Each of the source electrode and the drain electrode and the etch stop layer may be configured to overlap in the vertical direction.
The oxide semiconductor film preferably contains at least In, Ga, Sn, and O.

In addition, the ratio of the number of atoms of each metal element to the total number of atoms of In, Ga, and Sn included in the oxide semiconductor film is preferably a structure that satisfies all of the following formulas (1) to (3). .
0.30 ≦ In / (In + Ga + Sn) ≦ 0.50 (1)
0.20 ≦ Ga / (In + Ga + Sn) ≦ 0.30 (2)
0.25 ≦ Sn / (In + Ga + Sn) ≦ 0.45 (3)
The resistivity of the low resistance region is preferably less than 1.8 Ω · cm.
The resistivity of the low resistance region is preferably 1/100 or less of the resistivity of each of the first channel region and the second channel region.
The thin film device of the present invention is a thin film device including any of the thin film transistors described above,
The gate electrode is divided so as to respectively correspond to the two regions on the source electrode side and the drain electrode side constituting the source / drain electrode portion,
A first thin film transistor including one of the divided gate electrodes, the source electrode, and the region of the oxide semiconductor film that does not overlap the source electrode in the vertical direction but overlaps the etch stop layer And the other of the divided gate electrodes, the drain electrode, and a region of the oxide semiconductor film that does not overlap the drain electrode in the vertical direction but overlaps the etch stop layer. The thin film transistor is provided.
In this case, it is preferable that the oxide semiconductor film is divided so as to correspond to two regions on the source electrode side and the drain electrode side that constitute the source / drain electrode portion.

Furthermore, the manufacturing method of the thin film transistor of the present invention includes:
A method of manufacturing any of the above-described thin film transistors, comprising a step of performing a heat treatment at a temperature of 200 ° C. or higher after forming the source / drain electrode portion.

  According to the thin film transistor, the thin film device, and the thin film transistor manufacturing method of the present invention, it is possible to obtain a shorter channel length and higher on-current in the etch stop structure TFT than in the prior art.

That is, as a conceptual action of the present invention, an etch stop layer containing SiNx is formed on a region of an oxide semiconductor film, and hydrogen accompanying the inclusion of SiNx is diffused from the etch stop layer. It is possible to proceed to the semiconductor film. When hydrogen penetrates into the oxide semiconductor film, the region of the oxide semiconductor film in which hydrogen penetrates can have a significantly increased carrier density and can serve as a conductor.
On the other hand, the region in the oxide semiconductor film in which hydrogen is not sufficiently diffused and hydrogen does not enter the inside functions as a channel layer.

  In the above description using FIG. 9 showing the prior art, the channel length is the length Ls of the source electrode region on the etch stop layer 115 in the channel length direction and the channel length direction of the drain electrode region on the etch stop layer 115. , And the distance Lg between the source electrode 116 and the drain electrode 117. If the resistance between the source electrode 116 and the drain electrode 117 is reduced, the channel length is the sum of Ls and Lg. Can be shortened. If this length is expressed using the alignment margin Da of photolithography, it becomes 2 Da.

1 shows a cross-sectional structure of a thin film transistor according to an embodiment of the present invention. 3 is a graph showing drain current (Id) -gate voltage (Vg) characteristics of a TFT prepared according to Example 1 of the present invention. 4 is a graph showing drain current (Id) -gate voltage (Vg) characteristics of a TFT fabricated according to Example 3 of the present invention. 4 is a graph showing a change in on-current with respect to Lsd in a TFT manufactured according to Example 3 of the present invention. 4 is a graph showing drain current (Id) -gate voltage (Vg) characteristics of a TFT fabricated according to Example 4 of the present invention. 1 shows a cross-sectional structure of a thin film transistor according to a modification 1 of the embodiment of the present invention. The cross-section of the thin-film transistor (thin film device) which concerns on the modification 2 of embodiment of this invention is shown. The cross-section of the thin-film transistor (thin film device) which concerns on the modification 3 of embodiment of this invention is shown. 1 shows a cross-sectional structure of a thin film transistor according to a conventional technique.

  Hereinafter, a thin film transistor, a thin film device, and a method of manufacturing a thin film transistor according to an embodiment of the present invention will be described with reference to the drawings.

<Embodiment>
Hereinafter, the thin film transistor according to Embodiment 1 will be described in detail with reference to FIG.
As shown in FIG. 1A, the thin film transistor according to the first embodiment includes a gate electrode 12, a gate insulating film 13, an oxide semiconductor film 14, an etch stop layer 2 (15B) that contains less SiNx on a substrate 11, An etch stop layer 1 (15A) containing more SiNx, a source / drain electrode portion (including the source electrode 16 and the drain electrode 17), and a protective film (not shown) are stacked in this order. Note that, in the oxide semiconductor film 14, the source electrode is formed between the electrode portion adjacent regions 14 </ b> C <b> 1 and 14 </ b> C <b> 2 that constitute the source / drain electrode portion and are adjacent to the source electrode 16 and the drain electrode 17 in the lower part of the drawing. The first channel region 14A1 in contact with the electrode portion adjacent region 14C1 on the 16th side, the second channel region 14A2 in contact with the electrode portion adjacent region 14C2 on the drain electrode 17 side, the first channel region 14A1 and the second channel region A low resistance region 14B having a resistivity lower than the resistivity of each of these two channel regions 14A1 and 14A2 is formed between 14A2.

Hereinafter, each layer (film | membrane, electrode) 11-17 of the thin-film transistor which concerns on embodiment is demonstrated in detail using FIG. At the same time, a method for manufacturing a thin film transistor will be described.
First, the gate electrode 12 and the gate insulating film 13 are formed in this order on the substrate 11. These forming methods can employ various known methods.
Various known materials can be used as the constituent material of the gate electrode 12 and the gate insulating film 13. As the gate electrode 12, for example, Al or Cu metal having a low electrical resistivity, refractory metal such as Mo, Cr, or Ti having high heat resistance, or an alloy of these metals can be used. The gate insulating film 13 is typically exemplified by a silicon oxide film, a silicon nitride film, a silicon oxynitride film, and the like.
In addition, oxides such as Al ₂ O ₃ and Y ₂ O ₃ or a laminate of these can also be used.

Next, the oxide semiconductor film 14 is formed over the gate insulating film 13.
The oxide semiconductor film 14 is made of an oxide composed of In, Ga, Sn, and O as metal elements, and the ratio of the number of atoms of each metal element to the total number of atoms of In, Ga, and Sn is expressed by the following formula. It is preferable that all of (1) to (3) are satisfied. In the following formulas (1) to (3), In, Ga, and Sn represent the number of atoms of In, Ga, and Sn, respectively.
0.30 ≦ In / (In + Ga + Sn) ≦ 0.50 (1)
0.20 ≦ Ga / (In + Ga + Sn) ≦ 0.30 (2)
0.25 ≦ Sn / (In + Ga + Sn) ≦ 0.45 (3)

  Hereinafter, the number of atoms contained in In (atomic%) with respect to the total number of In, Ga and Sn atoms excluding oxygen O represented by the above formula (1) may be referred to as an In atom number ratio. Similarly, the number of Ga atoms contained (atomic%) relative to the total number of In, Ga and Sn atoms excluding oxygen O represented by the above formula (2) may be referred to as a Ga atom number ratio. Similarly, when the number of atoms contained in Sn (atomic%) relative to the total number of atoms of In, Ga and Sn, which are all metal elements excluding oxygen O, represented by the above formula (3) is referred to as the Sn atomic ratio There is.

<In atomic ratio>
In is an element that contributes to the improvement of electrical conductivity. As the In atom number ratio represented by the above formula (1) increases, that is, as the ratio of the number of In atoms to the total number of In, Ga, and Sn metal elements increases, the conductivity of the oxide semiconductor film 14 increases. The field effect mobility increases because it increases.

  In order to make the above-mentioned operation and effect better, the In atom number ratio needs to be 0.30 or more. The In atom number ratio is preferably 0.31 or more, more preferably 0.35 or more, and further preferably 0.40 or more. However, if the In atom number ratio is too large, there is a problem that the carrier density increases excessively and the threshold voltage is lowered. Further, the In atom number ratio is preferably 0.48 or less, more preferably 0.45 or less.

<About the number ratio of Ga atoms>
Ga is an element that can contribute to reduction of oxygen vacancies and control of carrier density. As the Ga atom number ratio shown in the above formula (2) is larger, the electrical stability of the oxide semiconductor film 14 is improved, and the effect of suppressing the excessive generation of carriers is improved. In order to achieve the above effect, the Ga atom number ratio needs to be 0.20 or more. The Ga atom number ratio is preferably 0.22 or more, more preferably 0.25 or more. However, if the Ga atom number ratio is too large, the conductivity of the oxide semiconductor film 14 is lowered and the field-effect mobility is easily lowered. Therefore, the Ga atom number ratio is set to 0.30 or less. More preferably, it is 0.28 or less.

<Sn atom number ratio>
Sn is an element that can contribute to improvement of acid etching resistance. The resistance to the inorganic acid etching solution in the oxide semiconductor film 14 is improved as the Sn atomic ratio represented by the above formula (3) is larger. In order to improve the above-described effects, the Sn atom number ratio needs to be 0.25 or more. The Sn atom number ratio is preferably 0.30 or more, more preferably 0.31 or more, and further preferably 0.35 or more. On the other hand, if the Sn atom number ratio becomes too large, the field effect mobility of the oxide semiconductor film 14 decreases and the resistance to the acid etching solution increases more than necessary, making it difficult to process the oxide semiconductor film 14 itself. . Therefore, the Sn atom number ratio is set to 0.45 or less. The Sn atom number ratio is preferably 0.40 or less, more preferably 0.38 or less.

The upper limit of the thickness of the oxide semiconductor film 14 is preferably 10 nm or more, more preferably 20 nm or more, and the lower limit is preferably 200 nm or less, more preferably 100 nm or less.
The oxide semiconductor film 14 is preferably formed using a sputtering target by a sputtering method, for example, by a DC sputtering method or an RF sputtering method.

Hereinafter, the sputtering target may be simply referred to as “target”. According to the sputtering method, a thin film having excellent in-plane uniformity of components and film thickness can be easily formed. Alternatively, the oxide may be formed by a chemical film formation method such as a coating method.
As a target used for the sputtering method, it is preferable to use a target having the same composition as the desired oxide, including the elements of In, Ga, Sn, and O described above. A thin film can be formed.
As a composition ratio, it is recommended to use a target in which the number of atoms of each metal element with respect to the total number of atoms of In, Ga, and Sn satisfies the above formulas (1) to (3).

Or you may form into a film using the combinatorial sputtering method which discharges simultaneously two targets from which a composition differs. For example, an oxide target of each element of In, Ga, and Sn, such as In ₂ O ₃ , Ga ₂ O ₃ , SnO ₂ , or a mixture of two or more of the above elements can be used. A method of forming a film while using one or a plurality of pure metal targets or alloy targets containing the above metal elements and supplying oxygen as an atmospheric gas is also possible.

The target can be manufactured by, for example, a powder sintering method.
In the case where a film is formed by sputtering using the above target, in addition to the gas pressure at the time of film formation described above, the partial pressure of oxygen, the input power to the target, the temperature of the substrate 11, and the distance between the target and the substrate 11. It is preferable to appropriately control the distance between TS and the like.
Specifically, for example, it is preferable to form a film under the following sputtering conditions.
The amount of oxygen added is preferably such that the carrier density of the oxide semiconductor film 14 is in the range of 1 × 10 ¹⁵ to 10 ¹⁷ / cm ³ so as to operate as a semiconductor.
The optimum oxygen addition amount is appropriately controlled according to the sputtering apparatus, target composition, thin film transistor manufacturing process, and the like.

The higher the power density during film formation, the better. It is recommended to set the power density to approximately 2.0 W / cm ² or more in DC or RF. However, if the power density at the time of film formation is too high, the oxide target may be broken or chipped and damaged, so the upper limit is about 50 W / cm ² .
The oxide semiconductor film 14 is not limited to an oxide composed of In, Ga, Sn, and O, and an oxide semiconductor film 14 in which another element is added to the above oxide or another metal is used is used. May be.

It is recommended that the temperature of the substrate 11 during film formation be controlled within the range of room temperature to 200 ° C. Furthermore, since the amount of defects in the oxide semiconductor film 14 is also affected by heat treatment conditions after film formation, it is preferably controlled appropriately.
The heat treatment conditions after film formation are preferably performed, for example, at 250 to 400 ° C. for 10 minutes to 3 hours in an air atmosphere. As the heat treatment, for example, a pre-annealing process (a heat treatment performed immediately after patterning after the oxide semiconductor film 14 is wet-etched) can be given.

After the oxide semiconductor film 14 is formed, patterning is performed by wet etching. Immediately after the patterning, heat treatment (pre-annealing) is preferably performed to improve the film quality of the oxide semiconductor film 14, whereby the on-state current and field-effect mobility of transistor characteristics are increased, and the transistor performance is improved. For example, the pre-annealing is preferably performed at 350 to 400 ° C. for 30 to 60 minutes in a water vapor atmosphere or an air atmosphere.

Thereafter, etch stop layers 1 and 2 (15A1 and 15A2) are formed over the oxide semiconductor film 14.
The formation method of the etch stop layers 1 and 2 (15A1 and 15A2) is not particularly limited, and a conventionally known method can be used.
In the TFT according to this embodiment, it is particularly important that the etch stop layer 1 (15A1) contains SiNx as a constituent material. By using the etch stop layer 1 (15A1) containing SiNx, the low resistance region can be efficiently formed by hydrogen diffusion in the oxide semiconductor film 14. As the etch stop layer 1 (15A1), any film other than the SiNx film may be stacked as long as it has a SiNx film. For example, only a SiNx film may be used as a single layer, or a plurality of SiNx films may be stacked. Further, at least one film of SiNx film and SiOxNy film, SiOx film, Al ₂ O ₃ film, Ta ₂ O ₅ or the like may be laminated. For example, as shown in FIG. A laminated film in which the etch stop layer 1 (15A1) is a SiNx film and the lower etch stop layer 2 (15A2) is a SiOx film may be used.

  The film thickness of the SiNx film in the etch stop layer 1 (15A1) is preferably 50 to 250 nm, and more preferably 100 to 200 nm. In the case of an etch stop layer in which a plurality of SiNx films are stacked, the film thickness of the SiNx film means the sum of the film thicknesses of all the SiNx films.

Next, the etch stop layer 1 (15A) and the etch stop layer 2 (15B) are processed into desired shapes. For example, it can be processed by patterning and dry etching by photolithography.
Thereafter, source / drain electrode portions (source electrode 16 and drain electrode 17) are formed.
The constituent material of the source / drain electrode part is not particularly limited, and conventionally known materials can be used. For example, similarly to the gate electrode 12, a metal or alloy such as Al, Mo, or Cu may be used.

The constituent material of the source / drain electrode portion (source electrode 16 and drain electrode 17) is not particularly limited, and conventionally known materials can be used. For example, similarly to the gate electrode 12, a metal or alloy such as Al, Mo, or Cu may be used.
As a method for forming the source / drain electrode portion, for example, a metal thin film is formed by a magnetron sputtering method, then patterned by photolithography, and wet etching is performed to form an electrode. Further, before the formation of a protective film (not shown) (usually formed on the source / drain electrode portion for protecting the laminated film), heat treatment (200 ° C. to 300 ° C.) or N ₂ O plasma treatment.

After forming the source / drain electrode portion, post-annealing is performed at a temperature of 200 ° C. or higher. By performing post-annealing, hydrogen contained in the SiNx of the etch stop layer 1 (15A) is diffused into the region of the oxide semiconductor film 14 below the etch stop layer 1 (15A) to form a shallow impurity level. As a result, the resistivity decreases.
Since hydrogen diffusion from the etch stop layer 1 (15A) is performed not only in the direction directly below the oxide semiconductor film 14, but also in a radial manner, the etch stop starts from the region of the oxide semiconductor film 14 below the center of the etch stop layer 1 (15A). The amount of hydrogen diffusion gradually decreases toward the region of the oxide semiconductor film 14 below both ends of the layer 1 (15A). As a result, there are regions (channel regions 1 and 2 (14A1 and 14A2)) where the amount of hydrogen diffusion is small and the resistance is not lowered below the end of the etch stop layer 1 (15A).

  Further, as shown in FIG. 1, when the etch stop layer 1 (15A) has an upwardly convex trapezoidal shape, the oxide semiconductor immediately below the thin region at both ends of the etch stop layer 1 (15A) In the region of the film 14, the amount of hydrogen diffusion decreases. Further, when SiOx is present in the etch stop layer 2 (15B) as in this embodiment, the end portion of the etch stop layer 2 (15B) includes SiNx from the etch stop layer 1 (15A) at the top. In other words, there are regions of the oxide semiconductor film 14 (channel regions 1 and 2 (14A1 and 14A2)) in which the amount of hydrogen diffusion is reduced.

Therefore, as shown in FIG. 1, the resistance is not reduced between the electrode portion adjacent region 14C1 adjacent to the source electrode 16 and the electrode portion adjacent region 14C2 adjacent to the drain electrode 17 of the oxide semiconductor film 14. There are a channel region 1 (14A1) (in contact with the electrode portion adjacent region 14C1) and a channel region 2 (14A2) (in contact with the electrode portion adjacent region 14C2). By including SiNx in the etch stop layer 1 (15A), a channel region 1 (14A1) in contact with the electrode adjacent region 14C1 between both regions in contact with the electrode adjacent regions 14C1 and 14C2 of the oxide semiconductor film 14; Efficiently forming channel region 2 (14A2) in contact with electrode portion adjacent region 14C2 and low resistance region 14B having a resistivity lower than the resistivity of channel region 1 (14A1) and channel region 2 (14A2) Can do. The length of the channel region 1 (14A1) and the channel region 2 (14A2) in the channel length direction depends on the film forming conditions and film thickness of SiNx of the etch stop layer 1 and SiOx of the etch stop layer 2, and the etch stop layers 1 and 2 It varies depending on the shape of (15A, 15B), the film forming conditions and the film thickness of the source / drain electrode portion. By controlling these, the length of the channel region 1 (14A1) and the channel region 2 (14A2) in the channel length direction can be controlled.

The lower limit of the heat treatment temperature for post-annealing is preferably 200 ° C, more preferably 230 ° C. However, if the heat treatment temperature is too high, the resistance of the channel region 1 (14A1) and the channel region 2 (14A2) is also reduced and the off-current is increased. Therefore, the upper limit is preferably 300 ° C. and is preferably 280 ° C. More preferably.
The optimum post-annealing temperature depends on the thickness of the oxide semiconductor film 14, the etch stop layers 1 and 2 (15A, 15B), the protective film, and the film formation conditions, and is appropriately set in consideration of these values. It is important. Furthermore, in the said post-annealing, it is preferable to control processing time within the range of 30 to 90 minutes, for example. The atmosphere is not particularly limited, and examples thereof include a nitrogen atmosphere and an air atmosphere.

As shown in FIG. 1, the TFT of this embodiment includes a low resistance region 14B, a channel region 1 (14A1), and a channel region 2 between the electrode portion adjacent region 14C1 and the electrode portion adjacent region 14C2 of the oxide semiconductor film 14. It can be divided into three areas (14A2). The drain current is inversely proportional to the total resistance value when the three regions are connected in series. Here, when the resistance value of the low resistance region 14B is negligibly small as compared with the resistance value in the case where the three regions are connected in series, the drain current is connected in series between the channel region 1 (14A1) and the channel region 2 (14A2). It is inversely proportional to the resistance value when connected.
The channel length of the TFT of this embodiment is effectively represented by the sum of the lengths of the channel region 1 (14A1) and the channel region 2 (14A2), which is significantly larger than the channel length Lsd of the conventional etch stop structure. And a high on-current can be obtained.

In order to make the effect of increasing the on-current good, the resistivity of the low resistance region 14B is less than 1.8 Ω · cm, more preferably 0.1 Ω · cm or less.
However, an appropriate resistivity of the low resistance region 14B is applied to drive each of the lengths of Ls, Lg, and Ld, the thickness of the oxide semiconductor film 14, the thickness and capacity of the gate insulating film 13, and the TFT. Since it varies depending on conditions such as the drain voltage and the gate voltage, it is important to set them appropriately in consideration of these values.

  The TFT of this embodiment obtained in this way can have a shorter channel length and a higher on-current than a TFT having no low resistance region 14B.

Hereinafter, the thin film transistor of the present invention will be verified by the following examples.
(Overview)
Examples 1 to 5 were produced by using the TFT shown in FIG. The reference numerals shown in FIG. 1 are used as reference numerals of the respective members.

First, on a glass substrate (Corning Eagle 2000, diameter 100 mm × thickness 0.7 mm) 11, a Mo thin film is formed as the gate electrodes 12A and B, 100 nm, and a gate insulating film 13 is formed as SiO ₂ (film thickness 200 nm). Films were sequentially formed. The gate electrodes 12A and B were formed by a DC sputtering method using a pure Mo sputtering target. The sputtering conditions are: film formation temperature: room temperature, film formation power density: 3.8 W / cm ² , carrier gas: Ar
The gas pressure during film formation was 2 mTorr (0.267 Pa), and the Ar gas flow rate was 20 sccm. The gate insulating film 13 uses a plasma CVD method, carrier gas: a mixed gas of SiH ₄ and N ₂ O, film formation power density: 0.96 W / cm ² , film formation temperature: 320 ° C., gas during film formation Pressure: 1
The film was formed under the condition of 33 Pa.

Next, an oxide semiconductor film (In—Ga—Sn—O film, film thickness: 40 nm) 14 having the following composition was formed by a sputtering method under the following conditions.
Sputtering equipment: “CS-200” manufactured by ULVAC, Inc.
Substrate temperature: Room temperature Gas pressure: 1 mTorr (0.133 Pa)
Carrier gas: Ar
Oxygen partial pressure: 100 × O ₂ / (Ar + O ₂ ) = 4% by volume
Deposition power density: 1.27, 2.55, 3.83 W / cm ²
Sputtering target used: In: Ga: Sn = 42.7: 26.7: 30.6 atomic%

After forming the oxide semiconductor film 14 as described above, patterning was performed by photolithography and wet etching. As a wet etchant, “ITO-07N” manufactured by Kanto Chemical Co., Inc. was used. In this example, for all the oxide semiconductor films 14 that were tested, residues due to wet etching were not detected, and it was confirmed that etching was appropriately performed.
As described above, after the oxide semiconductor film 14 was patterned, pre-annealing was performed to improve the film quality. Pre-annealing was performed at 400 ° C. for 1 hour in an air atmosphere.

After the pre-annealing, SiOx films (thickness 200 nm) and SiNx films (thickness 150 nm) were formed in this order on the oxide semiconductor film 14 as the etch stop layers 1 and 2 (15A, 15B). The SiOx film was formed by a plasma CVD method using a mixed gas of N ₂ O and SiH ₄ . The film formation conditions were film formation power density: 0.32 W / cm ² , film formation temperature: 230 ° C., and gas pressure during film formation: 133 Pa. After the formation of the SiOx film, the etch stop layers 1 and 2 (15A and 15B) were patterned by photolithography and dry etching.
Next, in order to form source / drain electrode portions (source electrode 16 and drain electrode 17), a pure Mo film having a thickness of 200 nm was formed on the oxide semiconductor film 14 by a sputtering method. The pure Mo film was formed under the following conditions: input power: DC 300 W (deposition power density: 3.8 W / cm ² ), carrier gas: Ar, gas pressure: 2 mTorr (0.267 Pa), and substrate temperature: room temperature.

Subsequently, the source / drain electrode part was patterned by photolithography and wet etching. Specifically, a mixed acid etchant comprising a mixed solution of phosphoric acid: nitric acid: acetic acid = 70: 2: 10 (mass ratio) and having a liquid temperature of 40 ° C. was used.
Then, as post-annealing, a heat treatment was performed for 30 minutes at 200 ° C. to produce the TFT of Example 1.

FIG. 2 shows the drain current (Id) -gate voltage (Vg) characteristics of Example 1. Here, in order to clarify the effect of SiNx in the etch stop layer 1 (15A), SiOx (film thickness: 100 nm) is used instead of the etch stop layer 1 (15A) and the etch stop layer 2 (15B) in Example 1. A TFT sample according to a comparative example in which a layer is provided (other structures and film forming conditions are all the same as those of the TFT of this example) and the results of measuring Id-Vg characteristics are shown simultaneously.
Channel width (W) = 100 μm and Lsd = 50 μm. The measurement was performed at Vg = −10 to 20V and the drain voltage (Vd) = 10V. Here, the on-current is the drain current when Vg = 20V and Vd = 10V.
The on-state currents of Example 1 and Comparative Example were 434 μA and 46 μA, respectively, and the on-current increased about 9.4 times by adding SiNx to the etch stop layers 1 and 2 (15A and 15B).

  As described above, it has been clarified that the on-current is increased by including SiNx in the etch stop layers 1 and 2 (15A and 15B). Hydrogen contained in the SiNx of the stop layers 1 and 2 (15A and 15B), in particular, the etch stop layer 1 (15A) is diffused into the oxide semiconductor film 14 region, and partially has low resistance as shown in FIG. The region 14B is formed, and the channel length is substantially shortened. The effective channel length of the TFT according to Example 1 including SiNx in the etch stop layers 1 and 2 (15A and 15B) estimated from the increase in on-current (about 9.4 times) was 5.4 μm.

  The etch stop layers 1 and 2 (15A and 15B) do not contain SiNx, and the resistance of the channel region (the region of the oxide semiconductor film 14 not reduced in resistance) based on the on-current value of the TFT according to the comparative example. When the rate was estimated, it was 1.8 Ω · cm. This resistivity value is the resistivity of the channel region 1 (14A1) and the channel region 2 (14A2) where the diffusion amount of hydrogen is small and the resistance is not lowered in the TFT including SiNx in the etch stop layers 1 and 2 (15A, 15B). Is estimated to be equivalent. If the resistivity of the low resistance region 14B is not smaller than this resistivity, the effect of increasing the on-current does not appear. Therefore, the resistivity of the low resistance region 14B is preferably less than 1.8 Ω · cm. . However, the appropriate resistivity value of the low resistance region 14B includes the length of the low resistivity region 14B, the length of the channel region 1 (14A1), the length of the channel region 2 (14A2), and the oxide semiconductor thin film. Since it varies depending on the conditions such as the thickness, gate insulating film thickness and dielectric constant, and the drain voltage and gate voltage applied to drive the TFT, it is important to set them appropriately in consideration of these conditions. is there.

<Example 2>
A TFT sample was produced in the same manner as in Example 1 above.
For the TFT according to Example 2, the resistivity of the oxide semiconductor film 14 was measured by a Hall effect measuring device, and the resistivity of the low resistance region 14B was estimated. The film thickness and film formation conditions of each layer in this example were the same as those for the TFT of Example 1 above. After the oxide semiconductor film 14 was formed, pre-annealing was performed under the same conditions as described above. After each layer was formed, post-annealing was performed under the same conditions as in Example 1.
The measurement result is 0.012 Ω · cm, which is 1 in comparison with the value 1.5 Ω · cm estimated as the resistivity of the channel region 1 (14A1) and the channel region 2 (14A2) by the TFT manufacturing process of this example. It became clear that it can be sufficiently reduced to / 100 or less. It is apparent that the on-current can be increased by setting the resistivity of the low resistance region 14B to 1/100 or less of the resistivity of the channel region 1 (14A1) and the channel region 2 (14A2).

<Example 3>
Next, in order to more clearly demonstrate that the low resistance region 14B is formed in the TFT of the present invention, TFT samples having different Lsd were prepared, and Id-Vg characteristics were measured.
That is, four types of TFT samples having different values of Lsd of 50 μm, 30 μm, 20 μm, and 10 μm were prepared, and Id-Vg characteristics were measured for each. The manufacturing process of the TFT sample was the same as in Example 1, and the post-annealing temperature was 200 ° C.
In all TFT samples, W (channel width) = 100 μm. The measurement was performed at Vg = −10 to 20V and Vd = 10V. Here, the on-current is the drain current when Vg = 20V and Vd = 10V.
As a result, the Id-Vg characteristic of the TFT of this example was as shown in FIG. 3, and the change in on-current with respect to Lsd was as shown in FIG.

As shown in FIG. 3, it is clear that the Id-Vg characteristic hardly changes even when Lsd is changed, and the on-current becomes substantially constant. Further, as shown in FIG. 4, since Lsd is not inversely proportional to the on-current, it is clear that Lsd does not coincide with the channel length. It can be concluded that the TFT shown in this example has a channel region that does not depend on Lsd.
From the results described above, the TFT of this embodiment has a channel region 1 (14A1) and a channel region 2 (14A2) which are regions independent of Lsd, and the sum of the lengths of these two channel regions is an effective channel. It will be long.

<Example 4>
Next, in order to investigate the film thickness dependency of the etch stop layers 1 and 2 (15A and 15B), the SiOx film (thickness 50 nm) is used as the etch stop layer 2 (15B) and the etch stop layer 1 (15A) is used. A TFT sample in which a SiNx film (thickness: 150 nm) is formed in this order on the oxide semiconductor film 14 (other structure and film formation conditions are the same as those of the TFT manufacturing method shown in Example 1) is manufactured, and Id − Vg characteristics were measured.

FIG. 5 shows the Id-Vg characteristics of the TFT of this example manufactured based on this measured value. Here, instead of the etch stop layer 1 (15A) and the etch stop layer 2 (15B) in Example 4, a TFT sample according to a comparative example in which a SiOx (film thickness of 100 nm) layer was provided (other structure, film formation conditions) Are the same as those of the TFT of this example), and the results of measuring the Id-Vg characteristics are shown simultaneously.
The channel width W = 100 μm and Lsd = 10 μm. The measurement was performed at Vg = −10 to 20V and the drain voltage Vd = 1V. Here, the on-current is the drain current when Vg = 20V and Vd = 1V.

  The on-currents of Example 4 and Comparative Example were 214 μA and 25 μA, respectively, and the on-current was increased about 8.6 times by including SiNx in the etch stop layers 1 and 2 (15A and 15B).

As described above, it has been clarified that the on-current is increased by including SiNx in the etch stop layers 1 and 2 (15A and 15B). Hydrogen contained in the SiNx of the stop layers 1 and 2 (15A and 15B), in particular, the etch stop layer 1 (15A) is diffused into the oxide semiconductor film 14 region and partially has low resistance as shown in FIG. The region 14B is formed, and the channel length is substantially shortened. The effective channel length of the TFT according to Example 4 in which SiNx is included in the etch stop layers 1 and 2 (15A and 15B) estimated from the increase in on-current (approximately 8.6 times) was 1.2 μm.

<Example 5>
A TFT sample in which the SiOx film thickness of the etch stop layer 2 (15B) in Example 4 is reduced from 100 nm to 50 nm (the other structure and film formation conditions are the same as those of the TFT manufacturing method shown in Example 1) is prepared. When the channel length was estimated in the same manner as in Example 4, the substantial channel length was reduced from 5.4 μm to 1.2 μm. The reason is that the distance between the SiNx of the etch stop layer 1 (15A) for supplying hydrogen and the oxide semiconductor film 14 is shortened due to the thin film thickness of the SiOx of the etch stop layer 2 (15B), and the etch stop. As a result, hydrogen diffusion is efficiently performed in the oxide semiconductor film 14 region below the layer edge, and as a result, the length of the channel region 1 (14A1) and the channel region 2 (14A2) is substantially shortened. It is done. Thus, the channel length direction length of the channel region 1 (14A1) and the channel region 2 (14A2) is changed by changing the distance between the SiNx and the oxide semiconductor film 14 included in the etch stop layer 1 (15A). It is possible to control.

The thin film transistor, the thin film device, and the method for manufacturing the thin film transistor of the present invention are not limited to those described in the above embodiment, and various other modifications can be made.
For example, other layers may be sandwiched between the layers in the above embodiment.

As described above, in the present embodiment, the upper etch stop layer 1 (15A) is made of SiNx and the lower etch stop layer 2 (15B) is made of SiOx. The SiNx content of the upper etch stop layer 1 (15A) may be larger than the SiNx content of the lower etch stop layer 2 (15B).
In addition, the lower etch stop layer 2 (15B) is diffused by hydrogen from the upper etch stop layer 1 (15A) in a radial manner, and is mostly in the center of the oxide semiconductor film 14 region. It is considered that it is provided in order to increase the distance between the etch stop layer 1 (15A) and the oxide semiconductor film 14 region to some extent so that the distribution is reduced at both ends. Therefore, also from such a viewpoint, the thickness of the oxide semiconductor film 14 region is preferably adjusted.

  Further, as a modification mode 1 of the thin film transistor described in the above embodiment, as illustrated in FIG. 6, the source electrode 216 is arranged in the vertical direction (stacking direction) with one of the etch stop layer 1 (215 A) and the etch stop layer 2 (215 B). It is also possible to make it not overlap. In addition, the code | symbol which added 200 to the code | symbol attached | subjected to each corresponding member shown in FIG.

For example, when the source electrode 216 (which may be the drain electrode 217) does not overlap the etch stop layer 1 (215A) and the etch stop layer 2 (215B), the source electrode 216 and the etch stop layer 1 are illustrated as illustrated. 2 (215A, 215B) is vacant. Then, since the region of the oxide semiconductor film 214 located immediately below this portion cannot receive the supply of hydrogen from the etch stop layers 1 and 2 (215A and 215B), the resistance of the region can be reduced. Thus, the length of the oxide semiconductor film 214 in which the resistance is not reduced (channel region) cannot be shortened. However, a protective film 218 is laminated on the uppermost layer, and this protective film 218 fills the space between the source electrode 216 and the etch stop layer 1 (215A) and the etch stop layer 2 (215B), and is located immediately below this portion. If hydrogen is supplied from the protective film 218 to the region of the oxide semiconductor film 214, the length of the region where the resistance is not reduced (channel region) can be shortened.

For this reason, in the modification 1, the protective film 218 is formed on the source / drain electrode portions 216 and 217 after the source / drain electrode portions 216 and 217 are formed. As a constituent material of the protective film 218, a constituent material containing SiNx (silicon nitride film) is preferably used. Specifically, a silicon nitride film, a silicon oxynitride film, or the like is preferably used, and these may be used alone, in combination, or may be used by stacking them. Alternatively, a laminated film having an upper layer of SiNx and a lower layer of SiOx (silicon oxide film) may be used.
When the source electrode 216 overlaps the etch stop layer 1 (215A) and the etch stop layer 2 (215B) in the vertical direction (stacking direction), a protective film as shown in FIG. 6 may be provided. However, it is not necessarily provided.

  According to the first modification, the oxide semiconductor film (region) 214 between the source electrode 216 and the drain electrode 217 is provided with two regions having different resistance values, a low resistance region 214B and a channel region 214A. Yes. The drain current is inversely proportional to the series resistance value of the resistors in the two regions 214A and 214B. Here, when the resistance value of the low resistance region 214B is negligibly small as compared to the series resistance value of the resistors in the two regions, the drain current is inversely proportional to the resistance value of the channel region. The channel length of the present modification 1 is effectively represented by the length of the channel region 214A (the length of the arrow shown), which is significantly larger than the channel length of the conventional etch stop structure shown in FIG. It can be shortened and a high on-current can be obtained.

  Further, as a modification mode 2 of the thin film transistor described in the above embodiment, as shown in FIG. 7A, the gate electrode 1 (312A) and the gate electrode 2 (312B) arranged with a space therebetween are arranged on the substrate 311. You may do it. In addition, the code | symbol which added 300 to the code | symbol attached | subjected to each corresponding member shown in FIG. That is, on the top of the substrate 311, the gate electrode 1 (312A) corresponding to the source electrode 316 side, the gate electrode 2 (312B) corresponding to the drain electrode 317 side, and the insulating layer 312C (the gate insulating film 313 and The present embodiment is different from the above embodiment in that the same material is used and the gate insulating film 313 may be formed at the same time.

  As shown in FIGS. 7 (a) and 7 (b) ((b) is an equivalent circuit), the gate electrode portion is divided into two, gate electrode 1 (312A) and gate electrode 2 (312B). A series connection structure of two short channel TFTs (see FIG. 7B, which is an equivalent circuit diagram) can be formed in the space of one TFT shown.

  In other words, the thin film device having the serial connection structure of the two short channel TFTs according to the modified embodiment 2 obtained in this way has a lower per TFT than the TFT shown in FIG. The channel length of the TFT is shortened to obtain a high on-current, and the necessary space per TFT is half that of the TFT having no low resistance region.

Further, as a modification mode 3 of the thin film transistor described in the above embodiment, as illustrated in FIG. 8A, the oxide semiconductor film 1 (electrode region adjacent region: 414C1) arranged with a gap in the oxide semiconductor film portion is provided. The oxide semiconductor film 2 (electrode part adjacent region: 414C2) may be provided over the gate insulating film 413. In addition, the code | symbol which added 400 to the code | symbol attached | subjected to each corresponding member shown in FIG.

  That is, as shown in FIGS. 8A, 8B, and 8B (equivalent circuit), the oxide semiconductor portion is divided into the oxide semiconductor film 1 (electrode portion adjacent region: 414C1) and the oxide semiconductor film 2 (electrode). The channel length can be shortened by dividing it into two adjacent regions: 414C2), and two short channel TFTs (L1, L2) are formed independently in the space of one TFT shown in FIG. (See FIG. 9B which is an equivalent circuit diagram). At this time, the low resistance region 1 (414B1) is used as a drain electrode, and the low resistance region 2 (414B2) is used as a source electrode.

  That is, the thin film device according to the present modification 3 obtained in this way can drive two single-channel TFTs independently, and in the case of the modification 2 in which two TFTs are arranged in series. In comparison, the range of circuit applications can be expanded.

11, 111, 211, 311, 411 Substrate 12, 112, 212, 312A, B, 412A, B Gate electrode 13, 113, 213, 313, 413, 412C Gate insulating film 312C, 412C Insulating regions 14, 114, 214, 314, 414 Oxide semiconductor films 14A1, 14A2, 114A1, 114A2, 214A, 314A1, 314A2, 414A1, 414A2 Channel regions 14B, 114B, 214B, 314B, 414B Low resistance regions 14C1, 14C2, 214C1, 214C2, 314C1, 314C2, 414C1, 414C2 Electrode portion adjacent regions 15A, 15B, 115, 215A, 215B, 315A, 315B, 415A, 415B Etch stop layers 16, 116, 216, 316, 416 Source electrodes 17, 117 217, 317, 417 Drain electrode

Claims (13)

A gate electrode, a gate insulating film, an oxide semiconductor film, an etch stop layer for protecting the oxide semiconductor film, and a source / drain electrode portion having a source electrode and a drain electrode on a substrate,
A thin film transistor laminated in this order,
The etch stop layer includes SiNx as a constituent material,
The oxide semiconductor film has electrode part adjacent regions in contact with the source electrode and the drain electrode,
The oxide semiconductor film has a first channel region in contact with the electrode portion adjacent region on the source electrode side, and a second channel region in contact with the electrode portion adjacent region on the drain electrode side,
The oxide semiconductor film further includes a low resistance region that is disposed between the first channel region and the second channel region and has an electrical resistivity lower than an electrical resistivity of each of the two channel regions. A thin film transistor comprising:   The etch stop layer includes a first etch stop layer having a SiNx content greater than or equal to a predetermined reference value, and a second etch stop layer having a SiNx content less than the predetermined reference value. 2. The thin film transistor according to claim 1, wherein the second etch stop layer and the first etch stop layer are stacked in this order on the oxide semiconductor film.   The first etch stop layer has a hydrogen content greater than or equal to a specific reference value, and the second etch stop layer has a hydrogen content less than the specific reference value. Item 3. The thin film transistor according to Item 2.   The length of the second etch stop layer that is parallel to the surface of the substrate and sandwiched between the source electrode and the drain electrode is set to be larger than that of the first etch stop layer. The thin film transistor according to claim 2 or 3. 5. The source / drain electrode portion, wherein either the source electrode or the drain electrode and the etch stop layer are configured not to overlap in the vertical direction. The thin film transistor according to any one of the above. 5. The structure according to claim 1, wherein each of the source electrode and the drain electrode constituting the source / drain electrode portion and the etch stop layer overlap each other in the vertical direction. A thin film transistor according to 1.   The thin film transistor according to claim 1, wherein the oxide semiconductor film contains at least In, Ga, Sn, and O. The ratio of the number of atoms of each metal element to the total number of atoms of In, Ga, and Sn contained in the oxide semiconductor film satisfies the following formulas (1) to (3). The thin film transistor according to claim 7.
0.30 ≦ In / (In + Ga + Sn) ≦ 0.50 (1)
0.20 ≦ Ga / (In + Ga + Sn) ≦ 0.30 (2)
0.25 ≦ Sn / (In + Ga + Sn) ≦ 0.45 (3)   The thin film transistor according to claim 1, wherein a resistivity of the low resistance region is less than 1.8 Ω · cm. The resistivity of the low resistance region is 1/100 or less of the resistivity of each of the first channel region and the second channel region. Thin film transistor. A thin film device comprising the thin film transistor according to claim 1,
The gate electrode is divided so as to respectively correspond to the two regions on the source electrode side and the drain electrode side constituting the source / drain electrode portion,
A first thin film transistor including one of the divided gate electrodes, the source electrode, and the region of the oxide semiconductor film that does not overlap the source electrode in the vertical direction but overlaps the etch stop layer And the other of the divided gate electrodes, the drain electrode, and a region of the oxide semiconductor film that does not overlap the drain electrode in the vertical direction but overlaps the etch stop layer. A thin film device comprising: a thin film transistor. 12. The thin film according to claim 11, wherein the oxide semiconductor film is divided so as to respectively correspond to two regions on the source electrode side and the drain electrode side constituting the source / drain electrode portion. device. A method for producing the thin film transistor according to claim 1,
A method of manufacturing a thin film transistor, comprising a step of performing a heat treatment at a temperature of 200 ° C. or higher after forming the source / drain electrode portion.

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