JP2018133016A - Neural network system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a neural network system which can flexibly switch the circuit configuration in response to input data.SOLUTION: A first integrated circuit has a first programmable logic device, a first arithmetic unit, and a first memory unit. A second integrated circuit has a second programmable logic device, a second arithmetic unit, and a second memory unit. Each of the first arithmetic unit, the second arithmetic unit, the first memory unit and the second memory unit has a first transistor. The first transistor has an oxide semiconductor in its channel forming region. The first programmable logic device is electrically connected to the second programmable logic device. The first programmable logic device and the second programmable logic device execute deduction in a neural network by switching the configuration.SELECTED DRAWING: Figure 1

Description

  One embodiment of the present invention relates to a neural network system.

  One embodiment of the present invention relates to a semiconductor device. Note that one embodiment of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, a manufacture, or a composition (composition of matter).

  Note that in this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. A display device, a light-emitting device, a memory device, an electro-optical device, a power storage device, a semiconductor circuit, and an electronic device may include a semiconductor device.

  In recent years, research on artificial neural networks (Artificial Neural Network; hereinafter also referred to as ANN or simply neural network) has been active.

  For example, Patent Document 1 discloses a neural network system in which a neural network engine and a Neumann type microprocessor are combined. In the neural network system disclosed in Patent Document 1, the network configuration information and weight information for the network structure are set or updated in the neural network engine. With this configuration, it is possible to reconfigure the network structure suitable for various applications as well as reducing circuit resources.

International Publication No. 2010/106587

  In the ANN, when large-scale data processing is performed with hardware circuit resources, the circuit resources need to be enlarged.

  However, an increase in circuit resources may increase power consumption. In addition, when data processing is small, circuit resources are wasted.

  An object of one embodiment of the present invention is to provide a neural network system that can effectively use circuit resources without increasing power consumption. Another object of one embodiment of the present invention is to provide a novel neural network system.

  Note that the description of these problems does not disturb the existence of other problems. Note that one embodiment of the present invention does not have to solve all of these problems. Issues other than these will be apparent from the description of the specification, drawings, claims, etc., and other issues can be extracted from the descriptions of the specification, drawings, claims, etc. It is.

  One embodiment of the present invention is a neural network system that processes input data using a first integrated circuit and a second integrated circuit, the first integrated circuit including: a first programmable logic device; The second integrated circuit includes a second programmable logic device, a second arithmetic unit, and a second memory unit, and a second memory unit. The first arithmetic unit, the second arithmetic unit, the first memory unit, and the second memory unit each include a first transistor, and the first transistor includes an oxide semiconductor in a channel formation region. And the first programmable logic device is electrically connected to the second programmable logic device, and the first programmable logic device and the second programmable logic are configured Deployment By switching a neural network system having a function of executing the inference in the neural network.

  In one embodiment of the present invention, the first calculation unit or the second calculation unit is preferably a neural network system having a function of executing learning in a neural network.

  In one embodiment of the present invention, the first memory unit or the second memory unit is preferably a neural network system having a function of holding a weighting coefficient obtained by learning.

  In one embodiment of the present invention, the first programmable logic device or the second programmable logic device updates configuration data including information on weighting factors held in the first memory unit or the second memory unit. A neural network system is preferred.

  In one embodiment of the present invention, the first calculation unit, the second calculation unit, the first memory unit, and the second memory unit include a second transistor, and the second transistor is a channel. A layer including silicon in the formation region and provided with the first transistor is preferably a neural network system arranged to overlap the layer provided with the second transistor.

  Note that other aspects of the present invention are described in the description and drawings in the following embodiments.

  One embodiment of the present invention can provide a neural network system that can effectively use circuit resources without increasing power consumption. One embodiment of the present invention can provide a novel neural network system.

  Note that the description of these effects does not disturb the existence of other effects. Note that one embodiment of the present invention need not have all of these effects. It should be noted that the effects other than these are naturally obvious from the description of the specification, drawings, claims, etc., and it is possible to extract the other effects from the descriptions of the specification, drawings, claims, etc. It is.

The block diagram explaining the operation example of a neural network system. The block diagram explaining the operation example of a neural network system. The block diagram explaining the operation example of a neural network system. The block diagram explaining the operation example of a neural network system. The flowchart explaining the operation example of a neural network system. The block diagram explaining the operation example of a neural network system. The block diagram explaining the operation example of a neural network system. The perspective schematic diagram which shows the structural example of IC incorporating a neural network system. A: A functional block diagram showing a configuration example of DOSRAM. B: A diagram showing a configuration example of a memory cell array. C: A circuit diagram showing a configuration example of a memory cell. The functional block diagram which shows the structural example of NOSRAM. AE: A circuit diagram showing a configuration example of a memory cell. The block diagram explaining the structural example of OS-FPGA. The block diagram explaining the structural example of OS-FPGA. FIG. 6 is a circuit diagram and a timing chart illustrating a configuration example of an OS-FPGA. FIG. 10 is a circuit diagram illustrating a configuration example of an OS-FPGA. FIG. 6 is a circuit diagram and a timing chart illustrating a configuration example of an OS-FPGA. The figure for demonstrating the structure of the product-sum operation circuit which a neural network system has. The figure for demonstrating the structure of the product-sum operation circuit which a neural network system has. The figure for demonstrating the structure of the product-sum operation circuit which a neural network system has. The figure for demonstrating the structure of the product-sum operation circuit which a neural network system has. The figure which shows an example of a hierarchical neural network. The figure which shows an example of a hierarchical neural network. The figure which shows an example of a hierarchical neural network. 10A and 10B each illustrate a configuration example of a circuit.

  Hereinafter, embodiments will be described with reference to the drawings. However, the embodiments can be implemented in many different modes, and it is easily understood by those skilled in the art that the modes and details can be variously changed without departing from the spirit and scope thereof. . Therefore, the present invention should not be construed as being limited to the description of the following embodiments.

  In the present specification and the like, the ordinal numbers “first”, “second”, and “third” are given to avoid confusion between components. Therefore, the number of components is not limited. Further, the order of the components is not limited. Further, for example, a component referred to as “first” in one embodiment of the present specification or the like is a component referred to as “second” in another embodiment or in the claims. It is also possible. In addition, for example, the constituent elements referred to as “first” in one embodiment of the present specification and the like may be omitted in other embodiments or in the claims.

  Note that in the drawings, the same element, an element having a similar function, an element of the same material, an element formed at the same time, or the like may be denoted by the same reference numeral, and repeated description thereof may be omitted.

  In this specification, the term “neural network” refers to all models that imitate the neural network of a living organism, determine the connection strength between neurons by learning, and have problem solving ability. The neural network has an input layer, an intermediate layer (also referred to as a hidden layer), and an output layer. A neural network having two or more intermediate layers is called deep learning (or deep neural network).

  In this specification, when describing a neural network, determining the connection strength (also referred to as a weighting factor) between neurons from existing information may be referred to as “learning”.

  Further, in this specification, the construction of a neural network using the connection strength obtained by learning and deriving a new conclusion therefrom may be referred to as “inference”.

(Embodiment 1)
In the present embodiment, a configuration of a neural network system, which is a system for performing arithmetic processing of data input based on the function of an artificial neural network (ANN), will be described.

  FIG. 1A is a block diagram for explaining a neural network system. The neural network system 10 includes a plurality of integrated circuits 11. The integrated circuits 11 are electrically connected to each other via wiring or a network.

  FIG. 1A illustrates an integrated circuit 11 [1] and an integrated circuit 11 [2] as an example of the plurality of integrated circuits 11. The integrated circuit 11 [1] includes a programmable logic device 20 [1], a memory unit 30 [1], and an arithmetic unit 40 [1]. The integrated circuit 11 [2] includes a programmable logic device 20 [2], a memory unit 30 [2], and an arithmetic unit 40 [2].

  The programmable logic devices 20 [1] and 20 [2] are FPGAs having OS transistors. Note that in this specification, an FPGA having an OS transistor is referred to as an OS-FPGA.

  The OS-FPGA can reduce the area of the memory compared to the FPGA configured with the SRAM. Therefore, even if a context switching function is added, the area increase is small. The OS-FPGA can transmit data and parameters at high speed by boosting. Details of the OS-FPGA will be described in a fourth embodiment described later.

  The programmable logic device 20 [1] has a function of switching connection with a programmable logic device (for example, the programmable logic device 20 [2]) included in another integrated circuit (for example, the integrated circuit 11 [2]) via the input / output unit. Have. The programmable logic device 20 [1] has a function of performing different data processing according to the setting of the circuit configuration. Specifically, the inference is executed by switching the weighting coefficient (parameter) used for inference in the artificial neural network and the number of input / output data.

  The programmable logic device 20 [2] has a function of switching connection with a programmable logic device (for example, the programmable logic device 20 [1]) included in another integrated circuit (for example, the integrated circuit 11 [1]) via the input / output unit. Have. The programmable logic device 20 [2] has a function of performing different data processing according to the circuit configuration setting. Specifically, the inference is executed by switching the weighting coefficient (parameter) used for inference in the artificial neural network and the number of input / output data.

  As an artificial neural network, depending on the problem to be solved, a deep neural network (DNN), a convolutional neural network (CNN), a recursive neural network (RNN), a self-encoder, a deep Boltzmann machine (DBM), a deep belief Operations such as a network (DBN) can be executed.

  The programmable logic devices 20 [1] and 20 [2] have a function of switching input / output unit settings in accordance with switching of data processing. Specifically, when the number of input / output data is larger than the number of programmable IOs in the input / output unit, the setting of the input / output unit is performed so that data processing is performed in parallel with the programmable logic device 20 included in another integrated circuit 11. Has a function of switching between.

  The memory unit 30 [1] has a function of holding configuration data including information about weighting coefficients used by the program executed by the arithmetic unit 40 [1] and the programmable logic device 20 [1]. As an example, the memory unit 30 [1] includes a NOSRAM 31 [1] and a DOSRAM 32 [1]. NOSRAM 31 [1] and DOSRAM 32 [1] are formed using OS transistors.

  The memory unit 30 [2] has a function of holding configuration data including information about weighting coefficients used in the program executed by the arithmetic unit 40 [2] and the programmable logic device 20 [2]. As an example, the memory unit 30 [2] includes a NOSRAM 31 [2] and a DOSRAM 32 [2]. NOSRAM 31 [2] and DOSRAM 32 [2] are formed using OS transistors.

  Configuration data including information on weighting factors used for calculation of the neural network can be temporarily held in the memory units 30 [1] and 30 [2]. The configuration data may be held in a memory provided outside the integrated circuits 11 [1] and 11 [2] via the arithmetic units 40 [1] and 40 [2]. The memory units 30 [1] and 30 [2] thus configured can access (read and write) the parameters at higher speed and with lower power consumption.

  Note that DOSRAM (registered trademark) is an abbreviation for “Dynamic Oxide Semiconductor RAM” and refers to a RAM having 1T (transistor) 1C (capacitance) type memory cells. DOSRAM is a memory that utilizes the low off-state current of an OS transistor.

  The DOSRAMs 32 [1] and 32 [2] are DRAMs formed using OS transistors. The DOSRAMs 32 [1] and 32 [2] each include a memory cell including an OS transistor and a reading circuit portion including a Si transistor. Since the memory cell and the reading circuit portion can be provided in different stacked layers, the entire circuit area of the DOSRAMs 32 [1] and 32 [2] can be reduced. The details of DOSRAM will be described in Embodiment 3 to be described later.

  In large-scale parallel computation using a neural network, input data may exceed 1000. When storing the input data in the SRAM, the SRAM has a limited bus width and circuit area, and has a small storage capacity. Therefore, the input data must be stored in small portions. Since the DOSRAMs 32 [1] and 32 [2] can be stacked even with a limited circuit area, memory cells can be arranged highly integrated.

  NOSRAM (registered trademark) is an abbreviation of “Nonvolatile Oxide Semiconductor RAM” and refers to a RAM having gain cell type (2T type, 3T type) memory cells. NOSRAM is a memory that utilizes the low off-state current of the OS transistor.

  NOSRAM 31 [1] and 31 [2] are memories using OS transistors. The NOSRAM 31 consumes less power when writing data than other non-volatile memories such as flash memory, ReRAM (Resistive Random Access Memory), and MRAM (Magnetic Resistive Random Access Memory). Further, unlike the flash memory and the ReRAM, the element is not deteriorated when data is written, and the number of times data can be written is not limited. Further, unlike the flash memory and the ReRAM, there is no problem of cell-to-cell variation due to deterioration of the element. Further, unlike a two-terminal memory such as a flash memory or a ReRAM, a circuit for writing and reading is not complicated. Details of NOSRAM will be described in Embodiment 3 described later.

  Further, the NOSRAMs 31 [1] and 31 [2] can hold multi-value data of 2 bits or more in addition to 1-bit binary data. The NOSRAMs 31 [1] and 31 [2] hold multi-value data, so that the memory cell area per bit can be reduced.

  The NOSRAMs 31 [1] and 31 [2] can hold analog data in addition to digital data. Since NOSRAM 31 [1] and 31 [2] can hold analog data as they are, a D / A conversion circuit and an A / D conversion circuit are unnecessary. Therefore, NOSRAM 31 [1], 31 [2] can reduce the area of the peripheral circuit.

  The arithmetic unit 40 [1] has a function of executing data processing based on a program held in the memory unit 30 [1]. Specifically, configuration data including weight coefficient information obtained by learning with an artificial neural network is estimated based on input data, and stored in the memory unit 30 [1]. As an example, the arithmetic unit 40 [1] includes a processor 41 [1] and an analog arithmetic circuit 42 [1]. As the processor 41 [1], there is a GPU (Graphics Processing Unit) in addition to a CPU (Central Processing Unit).

  The arithmetic unit 40 [2] has a function of executing data processing based on a program held in the memory unit 30 [2]. Specifically, the configuration data including information on the weighting coefficient obtained by learning with the artificial neural network is estimated based on the input data, and stored in the memory unit 30 [2]. As an example, the arithmetic unit 40 [2] includes a processor 41 [2] and an analog arithmetic circuit 42 [2]. The processor 41 [1] includes a GPU in addition to the CPU.

  The analog arithmetic circuits 42 [1] and 42 [2] are formed using OS transistors. The analog operation circuits 42 [1] and 42 [2] using OS transistors have analog memories, and can perform product-sum operations necessary for estimation and learning with low power consumption. Note that details of the product-sum operation circuit using the OS transistor will be described in Embodiment 5 described later.

  The neural network system having the integrated circuit 11 described above can combine software processing and hardware processing in order to make many functions function more effectively. Specifically, software processing can be executed by the arithmetic unit, and hardware processing can be executed by the programmable logic device.

  Therefore, the integrated circuit 11 can execute complicated processing that is difficult to implement by hardware processing such as conditional branching by software processing, and can execute parallel processing that is difficult by software processing by hardware. Therefore, large-scale data processing can be executed efficiently. In the neural network system having the integrated circuit 11, the processing performance of the neural network system can be further improved by using the circuit at the right place for the right material.

  Since the circuits constituting the integrated circuit 11 are mixedly mounted in the same chip, they can be transmitted at high speed. In addition, by performing data processing in conjunction with another integrated circuit, the neural network system can be easily expanded or reduced. That is, it is possible to perform parallel data processing by utilizing circuit resources of another integrated circuit 11. Therefore, by connecting a plurality of integrated circuits 11 in parallel, large-scale data can be processed simultaneously, and large-scale data can be processed in a short time.

  When the integrated circuit 11 [1] and the integrated circuit 11 [2] are not distinguished, they are referred to as an integrated circuit 11. The same applies to other elements (programmable logic device 20, memory unit 30, arithmetic unit 40, etc.).

  FIG. 1B illustrates each block of the programmable logic device 20, the memory unit 30, and the arithmetic unit 40 included in the integrated circuit 11 described in FIG. 1A. In FIG. 1B, as details of the programmable logic device 20, an input / output block 22 and a core 23 in the programmable area 21 are illustrated.

  The programmable area 21 has a plurality of input / output blocks 22 and a core 23. The programmable area 21 is also called a circuit block. The programmable logic device 20 can also be configured to have a plurality of circuit blocks that are programmable areas. In this case, configuration data for realizing different functions for each of the plurality of circuit blocks can be held, and a connection state between programmable logic devices and a function of processing data can be provided.

  The connection state between the programmable logic devices 20 and the function of processing data are set by a plurality of sets of configuration data. Configuration data is stored in a plurality of sets of configuration memories. The configuration memory sets the input / output block 22 and the core 23 according to the context. By switching this setting, it is possible to realize a so-called multi-context system in which the function for processing data described above is set and the function for processing data is switched instantaneously by context switching. The core 23 has a programmable logic element (PLE) and a programmable switch (PRS), and the input / output block 22 has a programmable IO (PIO).

  In the integrated circuit 11, the programmable logic device 20, the memory unit 30, and the arithmetic unit 40 can be provided on one die (chip). Therefore, the neural network system 10 can execute a neural network calculation at high speed and with low power consumption. Moreover, the programmable logic device 20, the memory part 30, and the calculating part 40 can be produced with the same manufacturing process. Therefore, the neural network system 10 can be manufactured at low cost.

  FIG. 2A illustrates the controller 50 in addition to the blocks constituting the neural network system 10. The programmable logic device 20 included in the integrated circuit 11 of the neural network system 10 can be controlled by a calculation unit in an individual integrated circuit, but can also be controlled by the controller 50 in an integrated manner.

  The controller 50 can perform configuration, context switching (CONTEXT), or power gating (PG) to the unused integrated circuit 11 in accordance with input data (DATA). The integrated circuit 11 may have a gating switch. The controller 50 may be configured to perform clock gating or the like of the integrated circuit 11. By adopting a configuration in which the neural network system 10 is controlled by the controller 50 in an integrated manner, the power consumption of the entire system can be reduced.

  The controller 50 operates each integrated circuit 11 in conjunction with each other as shown in FIG. FIG. 2B is a block diagram schematically showing the state of the integrated circuit of the neural network system 10 when the four circuit configurations of context 0 to context 3 are switched.

  In FIG. 2B, an integrated circuit 11_A represents an integrated circuit that performs data processing by utilizing circuit resources such as the programmable logic device 20, the memory unit 30, and the arithmetic unit 40. The integrated circuit 11_B represents an integrated circuit that does not use circuit resources such as the programmable logic device 20, the memory unit 30, and the arithmetic unit 40. That is, the integrated circuit 11_B is an integrated circuit that can reduce power consumption by actively performing power gating or clock gating. In FIG. 2B, 16 integrated circuits constituting the neural network system 10 are illustrated.

  In the context 0 in FIG. 2B, 6 are the integrated circuits 11_A and 10 are the integrated circuits 11_B. In the context 1 in FIG. 2B, eight are the integrated circuits 11_A and eight are the integrated circuits 11_B. In context 2 in FIG. 2B, four are the integrated circuits 11_A and twelve are the integrated circuits 11_B. In the context 3 of FIG. 2B, 16 are the integrated circuits 11_A and there is no integrated circuit 11_B. Each state in FIG. 2B can be switched to each other by switching contexts or dynamically reconfiguring configuration data.

  As shown in FIG. 2B, by selecting the number of integrated circuits 11_A by context switching or dynamic reconfiguration of configuration data, a programmable logic device having a limited number of input / output units is provided. In the integrated circuit, the number of input / output terminals can be increased or decreased in accordance with the change in the parallel number of input data.

  For example, FIG. 3A illustrates the programmable area 21 included in the six integrated circuits 11_A corresponding to the context 0 state in FIG. In FIG. 3A, the number of pins of the input / output block 22 in the programmable area 21 is 100. That is, in the neural network system 10, the data d0 to d599 can be collectively processed in parallel as the input / output block 22 having 600 pins.

  FIG. 3B illustrates the programmable area 21 included in the ten integrated circuits 11_A corresponding to the state of the context 1 in FIG. In FIG. 3B, the number of pins of the input / output block 22 in the programmable area 21 is set to 100, as in FIG. That is, in the neural network system 10, the data d0 to d999 can be collectively processed in parallel as the input / output block 22 having 1000 pins.

  As illustrated in FIGS. 3A and 3B, in the neural network system which is one embodiment of the present invention, the number of integrated circuits 11_A can be selected by context switching. Therefore, in an integrated circuit having a programmable logic device having an input / output unit with a limited number of pins, the number of input / output units can be increased or decreased according to a change in the parallel number of input data.

  Although not illustrated in FIGS. 3A and 3B, the integrated circuit 11_B illustrated in FIG. 2B is a circuit resource that does not perform data processing. The integrated circuit 11_B can achieve low power consumption by applying power gating or the like.

  In the neural network system according to one aspect of the present invention, the circuit resources can be increased by increasing the number of programmable areas per programmable logic device while continuing the circuit operation by utilizing context switching and dynamic reconfiguration. Can be planned. That is, the number of pins of the input / output block 22 can be increased, and the parallel number of input data can be increased.

  For example, as shown in FIG. 4A, the programmable logic device 20 has four programmable areas 21A to 21D. By adopting a configuration having a plurality of programmable areas 21A to 21D, it is possible to increase the number of pins of the input / output block 22 for context switching.

  Note that in the neural network system which is one embodiment of the present invention, a larger system can be obtained by further combining a plurality of neural network systems.

  For example, as illustrated in FIG. 4B, the neural network system 10 can be incorporated into a huge neural network system 70 including a plurality of neural network systems 10. With this configuration, the number of programmable logic devices 20 having an interface of the neural network system increases, so that the number of pins of the input / output block 22 can be increased.

  In the huge neural network system 70, the neural network systems 10 may be connected to each other via a network. Note that each network may have a configuration in which a communication module is provided for wireless or wired communication. The communication module can communicate via an antenna. For example, the Internet, Intranet, Extranet, PAN (Personal Area Network), LAN (Local Area Network), MAN (MetropoliAW, MAN) Each electronic device can be connected to a computer network such as a network (network) or GAN (global area network) to perform communication. When performing wireless communication, as communication protocols or communication technologies, LTE (Long Term Evolution), GSM (Global System for Mobile Communications: registered trademark), EDGE (Enhanced Data Rates for GSM Evolution), CDMA2000 (Amplification) , Communication standards such as W-CDMA (registered trademark), or specifications standardized by IEEE such as Wi-Fi (registered trademark), Bluetooth (registered trademark), ZigBee (registered trademark) can be used.

  4A and 4B, analog signals obtained by an external sensor or the like can be processed by separate neural network systems. For example, like biological information, information such as brain waves, pulse, blood pressure, body temperature is acquired by various sensors such as brain wave sensors, pulse wave sensors, blood pressure sensors, temperature sensors, and analog signals are processed by separate neural network systems. Can do. The amount of information processing per one neural network system can be reduced by performing signal processing or learning in each of the different neural network systems. Therefore, signal processing or learning can be performed with a smaller amount of calculation. As a result, recognition accuracy can be increased. From the information obtained by each neural network system, it can be expected that changes in biological information that change in a complex manner can be instantly and comprehensively grasped.

  FIG. 5 is a flowchart for explaining the operation of the neural network system 10.

  The operation of the neural network system 10 includes, for example, a configuration operation (including initialization and reconfiguration), a learning operation, and an estimation operation.

In the following description of the operation, a dynamic reconfiguration for updating configuration data when switching the circuit configuration of the programmable logic device 20 will be described as an example. When the programmable logic device 20 has a plurality of programmable areas, it is possible to switch the circuit configuration in combination with context switching by a multi-context method in addition to dynamic reconfiguration.

  First, an initialization operation (step S101) is performed. In the initialization operation, each integrated circuit performs an operation of writing configuration data and initial values of weighting factors used for machine learning to the memory unit 30 from the controller 60 or the like outside the system. The initial value of the weighting coefficient is given by a value obtained by machine learning, a random number, or the like.

  Next, a configuration operation (step S102) is performed. Each integrated circuit reads configuration data from the memory unit 30 under the control of the arithmetic unit 40 and executes a configuration operation of the programmable logic device 20. After completing the configuration, the programmable logic device has a circuit configuration based on the configuration data. By this configuration operation, a circuit network is formed by interconnection between the integrated circuits via the programmable logic device 20.

  Next, the learning operation or the estimation operation is determined according to the presence or absence of learning data (step S103). The flag signal that shifts to the learning operation can be supplied as an input signal to the neural network system 10 from the outside, an output signal of the programmable logic device 20 that can be configured, an output signal when the learning unit 40 starts the learning program, and the like.

  If there is learning data, a reconfiguration operation (step S104) for performing the learning operation is performed. The configuration data is read from the memory unit 30 under the control of the arithmetic unit 40, and the reconfiguration operation of the programmable logic device 20 is executed. After completing the reconfiguration, the programmable logic device has a circuit configuration based on the configuration data. By this configuration operation, a circuit network in which learning data is input to the arithmetic unit 40 is constructed.

  Next, a learning operation (step S105) is performed. The learning operation is performed by software processing in the calculation unit 40. Each integrated circuit reads a program necessary for a learning operation and an initial value of a weighting coefficient from the memory unit 30 under the control of the calculation unit 40, and calculates a weighting coefficient corresponding to the learning data.

  Next, learning ends (step S106). The learning ends when the learning data is stopped.

  Next, learning data is stored (step S107). The calculation unit 40 stores the weighting coefficient obtained by the calculation unit 40 by learning in the memory unit 30.

  Next, it is determined whether or not to continue the learning operation according to the presence or absence of other learning data (step S108). The flag signal that shifts to the learning operation can be supplied as an input signal to the neural network system 10 from the outside, an output signal of the programmable logic device 20 that can be configured, an output signal when the learning unit 40 starts the learning program, and the like.

  If there is another learning data, a reconfiguration operation (step S109) for performing the learning operation is performed. The configuration data is read from the memory unit 30 under the control of the arithmetic unit 40, and the reconfiguration operation of the programmable logic device 20 is executed. After completing the reconfiguration, the programmable logic device has a circuit configuration based on the configuration data. By this configuration operation, a circuit network in which learning data is input to the arithmetic unit 40 is constructed.

  Next, a learning operation (step S110) is performed. The learning operation is performed by software processing in the calculation unit 40. Each integrated circuit reads a program necessary for a learning operation and an initial value of a weighting coefficient from the memory unit 30 under the control of the calculation unit 40, and calculates a weighting coefficient corresponding to the learning data.

  Next, the learning ends (step S111). The learning ends when the learning data is stopped.

  Next, learning data storage (step S112) is performed. The calculation unit 40 causes the memory unit 30 to hold the weighting coefficient obtained by the calculation unit 40 through learning.

  Thereafter, by repeating Steps S103 to S112, it is possible to acquire a plurality of weighting factors according to the learning data.

  Next, the estimation operation will be described. A reconfiguration operation (step S113) for performing the estimation operation is performed. Each integrated circuit reads the program necessary for the learning operation and the weighting factor estimated by the learning from the memory unit 30 under the control of the arithmetic unit 40 and executes the reconfiguration operation of the programmable logic device 20. After completing the reconfiguration, the programmable logic device has a circuit configuration based on the configuration data. By this reconfiguration operation, a circuit network in which the estimation data is input to the programmable logic device 20 is constructed.

  Next, an estimation operation (step S114) is performed. The estimation operation is performed by hardware processing in the programmable logic device 20. Each integrated circuit outputs output data expected from the estimated data in accordance with the configuration data including information on the weighting factor set in the programmable logic device 20.

  Next, the continuation of the estimation operation is determined according to the presence / absence of other estimation data (step S115). The flag signal that shifts to the estimation operation can be supplied as an input signal to the neural network system 10 from the outside, an output signal of the programmable logic device 20 that can be configured, and the like. If there is no other estimated data, the process ends.

  If there is another estimation data, a reconfiguration operation (step S116) for performing another estimation operation is performed. Each integrated circuit reads the program necessary for the learning operation and the weighting factor estimated by the learning from the memory unit 30 under the control of the arithmetic unit 40 and executes the reconfiguration operation of the programmable logic device 20. After completing the reconfiguration, the programmable logic device has a circuit configuration based on the configuration data. By this reconfiguration operation, a circuit network in which the estimation data is input to the programmable logic device 20 is constructed.

  Next, an estimation operation (step S117) is performed. The estimation operation is performed by hardware processing in the programmable logic device 20. Each integrated circuit outputs output data expected from the estimated data in accordance with the configuration data including information on the weighting factor set in the programmable logic device 20.

  Next, the continuation of the estimation operation is determined according to the presence / absence of other estimation data (step S118). The flag signal that shifts to the estimation operation can be supplied as an input signal to the neural network system 10 from the outside, an output signal of the programmable logic device 20 that can be configured, and the like. If there is no other estimated data, the process ends.

  Thereafter, it is possible to obtain output data expected from the estimated data by repeating Steps S113 to S118.

  The operation of acquiring a plurality of weighting factors according to the learning data performed in steps S103 to S112 described in FIG. 5 and the operation of acquiring output data expected from the estimation data performed in steps S113 to S118 are illustrated in FIG. This can be schematically described with reference to the block diagram shown in FIG.

  6A and 6B, the integrated circuit 11 is illustrated. Each structure of the integrated circuit 11 is the same as that in FIG.

  In FIG. 6A, operations for acquiring a plurality of weighting factors according to the learning data performed in steps S103 to S112 are indicated by thick dashed arrows 71 to 72.

  In FIG. 6A, an arrow 71 corresponds to a configuration operation (reconfiguration operation). That is, the operation corresponds to steps S104 and S108 described in FIG. By the configuration operation, a circuit network by the programmable logic device 20 is constructed so that data is input to the arithmetic unit 40 in the predetermined integrated circuit 11.

  In FIG. 6A, an arrow 72 corresponds to a learning operation. That is, the operations correspond to steps S105 to S107 and S110 to S112 described in FIG. By the learning operation, the arithmetic unit 40 in the predetermined integrated circuit 11 performs arithmetic processing by software processing, and obtains a weighting factor for performing the estimation operation by the programmable logic device 20. The weighting coefficient obtained by the calculation unit 40 is held in the memory unit 30.

  In FIG. 6B, the operation of outputting the output data corresponding to the estimated data performed in steps S113 to S118 is indicated by thick dashed arrows 74 to 75.

  In FIG. 6B, an arrow 74 corresponds to a configuration operation (reconfiguration operation). That is, the operation corresponds to steps S113 and S116 described in FIG. By the configuration operation, a circuit network is constructed so that the programmable logic device 20 in the predetermined integrated circuit 11 is set according to the configuration data including information on the weighting coefficient held in the memory unit 30.

  In FIG. 6B, an arrow 75 corresponds to the estimation operation. That is, the operation corresponds to steps S114 and S117 described in FIG. By the estimation operation, the programmable logic device 20 in the predetermined integrated circuit 11 performs arithmetic processing by hardware processing. The obtained output signal is output to the outside.

  7A and 7B show the integrated circuits 11 [1] and 11 [2] as a plurality of integrated circuits, with the operations schematically described in FIGS. 6A and 6B. . Each structure of the integrated circuits 11 [1] and 11 [2] is similar to that illustrated in FIG.

  In FIG. 7A, arrows 71 [1] and 71 [2] correspond to a configuration operation (reconfiguration operation). Programmable logic devices 20 [1], 20 [2] so that data is input to the arithmetic units 40 [1], 40 [2] in the plurality of integrated circuits 11 [1], 11 [2] by the configuration operation. A circuit network is constructed.

  In FIG. 7A, arrows 72 [1] and 72 [2] correspond to learning operations. By the learning operation, the arithmetic units 40 [1] and 40 [2] of the plurality of integrated circuits 11 [1] and 11 [2] perform arithmetic processing by software processing, and the programmable logic devices 20 [1] and 20 [2]. The weighting coefficient for performing the estimation operation by is acquired. The weighting coefficients obtained by the arithmetic units 40 [1] and 40 [2] are held in the memory units 30 [1] and 30 [2].

  In FIG. 7B, arrows 74 [1] and 74 [2] correspond to a configuration operation (reconfiguration operation). Weighting coefficients held by the programmable logic devices 20 [1], 20 [2] in the predetermined integrated circuits 11 [1], 11 [2] in the memory units 30 [1], 30 [2] by the configuration operation The circuit network is constructed so as to be set according to the configuration data including the information.

  In FIG. 7B, arrows 75 [1] and 75 [2] correspond to the estimation operation. By the estimation operation, arithmetic processing by hardware processing is performed in the programmable logic devices 20 [1] and 20 [2] in the predetermined integrated circuits 11 [1] and 11 [2]. The obtained output signal is output to the outside.

  As described above, a neural network system having a plurality of integrated circuits 11 can combine software processing and hardware processing in order to make many functions function more effectively. Specifically, software processing can be executed by the arithmetic unit, and hardware processing can be executed by the programmable logic device.

  Therefore, the integrated circuit 11 can execute complicated processing that is difficult to implement by hardware processing such as conditional branching by software processing, and can execute parallel processing that is difficult by software processing by hardware. Therefore, large-scale data processing can be executed. In the neural network system having the integrated circuit 11, the processing performance of the neural network system can be further improved by using the circuit at the right place for the right material.

  Since the circuits constituting the integrated circuit 11 are mixedly mounted in the same chip, they can be transmitted at high speed. In addition, by performing data processing in conjunction with another integrated circuit, the neural network system can be easily expanded or reduced. That is, it is possible to perform parallel data processing by utilizing circuit resources of another integrated circuit 11. Therefore, by connecting a plurality of integrated circuits 11 in parallel, large-scale data can be processed simultaneously, and large-scale data can be processed in a short time.

  The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

(Embodiment 2)
This embodiment shows an example of an IC in which the neural network system described in the above embodiment is incorporated.

  The neural network system described in the above embodiment includes an arithmetic unit including a processor such as a CPU such as a CPU and an analog arithmetic circuit using an OS transistor, a memory unit including an OS-FPGA, DOSRAM, and NOSRAM. Can be integrated on the die.

  FIG. 8 shows an example of an IC incorporating a neural network system. A neural network system IC 7000 shown in FIG. 8 includes a lead 7001 and a circuit unit 7003. In the circuit portion 7003, various circuits described in this embodiment are provided in one die. The circuit portion 7003 has a stacked structure, and is roughly divided into a Si transistor layer 7031, a wiring layer 7032, and an OS transistor layer 7033. Since the OS transistor layer 7033 can be stacked on the Si transistor layer 7031, the neural network system IC7000 can be easily downsized.

  In FIG. 8, QFP (Quad Flat Package) is applied to the package of the neural network system IC 7000, but the form of the package is not limited to this.

  An arithmetic unit including a processor such as a CPU such as a CPU and an analog arithmetic circuit using an OS transistor, and a memory unit including an OS-FPGA, DOSRAM, and NOSRAM are all included in an Si transistor layer 7031, a wiring layer 7032, and an OS. The transistor layer 7033 can be formed. That is, the elements constituting the neural network system can be formed by the same manufacturing process. Therefore, the IC shown in this embodiment mode does not require an increase in the manufacturing process even if the number of constituent elements increases, and the neural network system can be incorporated at a low cost.

(Embodiment 3)
In this embodiment, an OS memory that can be installed in the neural network system described in the above embodiment will be described. In the present embodiment, DOSRAM and NOSRAM will be described as examples of the OS memory.

<< DOSRAM 1400 >>
With reference to FIGS. 9A to 9C, the DOSRAM will be described.

  A DOSRAM 1400 illustrated in FIG. 9A includes a controller 1405, a row circuit 1410, a column circuit 1415, and an MC-SA array 1420. The row circuit 1410 includes a decoder 1411, a word line driver 1412, a column selector 1413, and a sense amplifier driver 1414. The column circuit 1415 includes a global sense amplifier array 1416 and an input / output circuit 1417. The global sense amplifier array 1416 has a plurality of global sense amplifiers 1447. The MC-SA array 1420 includes a memory cell array 1422, a sense amplifier array 1423, and global bit lines GBLL and GBLR.

(MC-SA array 1420)
The MC-SA array 1420 has a stacked structure in which the memory cell array 1422 is stacked on the sense amplifier array 1423. Global bit lines GBLL and GBLR are stacked on the memory cell array 1422. In the DOSRAM 1400, a hierarchical bit line structure in which a local bit line and a global bit line are hierarchized is adopted as the bit line structure.

  The memory cell array 1422 includes N (N is an integer of 2 or more) local memory cell arrays 1425 <0> -425 <N-1>. As shown in FIG. 9B, the local memory cell array 1425 includes a plurality of memory cells 1445, a plurality of word lines WL, and a plurality of bit lines BLL and BLR. In the example of FIG. 9B, the structure of the local memory cell array 1425 is an open bit line type, but may be a folded bit line type.

  A memory cell 1445 illustrated in FIG. 9A includes an OS transistor MO45 and a capacitor C45. The OS transistor MO45 has a function of controlling charging / discharging of the capacitor C45. The gate of the OS transistor MO45 is electrically connected to the word line, the back gate is electrically connected to the wiring BGL, the first terminal is electrically connected to the bit line BLL or BLR, and the second terminal is the capacitor C45. Is electrically connected to the first terminal. A second terminal of the capacitor C45 is electrically connected to the wiring PCL. The wirings CSL and BGL are power supply lines for supplying a voltage.

  The threshold voltage of the OS transistor MO45 can be changed by the voltage of the wiring BGL. For example, the voltage at the terminal B2 may be a fixed voltage (for example, a negative constant voltage), or the voltage at the terminal B2 may be changed according to the operation of the DOSRAM 1400.

  The back gate of the OS transistor MO45 may be electrically connected to the gate, source, or drain of the OS transistor MO45. Alternatively, the OS transistor MO45 may not have a back gate.

  The sense amplifier array 1423 includes N local sense amplifier arrays 1426 <0> -426 <N-1>. The local sense amplifier array 1426 includes one switch array 1444 and a plurality of sense amplifiers 1446. A bit line pair is electrically connected to the sense amplifier 1446. The sense amplifier 1446 has a function of precharging the bit line pair, a function of amplifying the voltage difference between the bit line pair, and a function of holding this voltage difference. The switch array 1444 has a function of selecting a bit line pair and bringing the selected bit line pair and the global bit line pair into a conductive state.

  Here, the bit line pair refers to two bit lines that are simultaneously compared by the sense amplifier. A global bit line pair refers to two global bit lines that are simultaneously compared by a global sense amplifier. A bit line pair can be called a pair of bit lines, and a global bit line pair can be called a pair of global bit lines. Here, the bit line BLL and the bit line BLR form one bit line pair. Global bit line GBLL and global bit line GBLR form a pair of global bit lines. Hereinafter, the bit line pair (BLL, BLR) and the global bit line pair (BLL, BLR) are also represented.

(Controller 1405)
The controller 1405 has a function of controlling the overall operation of the DOSRAM 1400. The controller 1405 performs a logical operation on an externally input command signal to determine an operation mode, and a function to generate control signals for the row circuit 1410 and the column circuit 1415 so that the determined operation mode is executed. , A function of holding an address signal input from the outside, and a function of generating an internal address signal.

(Row circuit 1410)
The row circuit 1410 has a function of driving the MC-SA array 1420. The decoder 1411 has a function of decoding an address signal. The word line driver 1412 generates a selection signal for selecting the word line WL of the access target row.

  The column selector 1413 and the sense amplifier driver 1414 are circuits for driving the sense amplifier array 1423. The column selector 1413 has a function of generating a selection signal for selecting the bit line of the access target column. The switch array 1444 of each local sense amplifier array 1426 is controlled by a selection signal from the column selector 1413. The plurality of local sense amplifier arrays 1426 are independently driven by the control signal of the sense amplifier driver 1414.

(Column circuit 1415)
The column circuit 1415 has a function of controlling input of the data signal WDA [31: 0] and a function of controlling output of the data signal RDA [31: 0]. The data signal WDA [31: 0] is a write data signal, and the data signal RDA [31: 0] is a read data signal.

  The global sense amplifier 1447 is electrically connected to a global bit line pair (GBLL, GBLR). The global sense amplifier 1447 has a function of amplifying a voltage difference between the global bit line pair (GBLL, GBLR) and a function of holding this voltage difference. Data input / output to / from the global bit line pair (GBLL, GBLR) is performed by an input / output circuit 1417.

  An outline of the writing operation of the DOSRAM 1400 will be described. Data is written to the global bit line pair by the input / output circuit 1417. Data of the global bit line pair is held by the global sense amplifier array 1416. The data of the global bit line pair is written to the bit line pair of the target column by the switch array 1444 of the local sense amplifier array 1426 specified by the address. The local sense amplifier array 1426 amplifies and holds the written data. In the specified local memory cell array 1425, the row circuit 1410 selects the word line WL of the target row, and the data held in the local sense amplifier array 1426 is written into the memory cell 1445 of the selected row.

  An outline of the reading operation of the DOSRAM 1400 will be described. One row of the local memory cell array 1425 is designated by the address signal. In the designated local memory cell array 1425, the word line WL in the target row is selected, and the data in the memory cell 1445 is written to the bit line. The local sense amplifier array 1426 detects and holds the voltage difference between the bit line pairs in each column as data. The switch array 1444 writes the data in the column specified by the address among the data held in the local sense amplifier array 1426 to the global bit line pair. The global sense amplifier array 1416 detects and holds data of the global bit line pair. Data held in the global sense amplifier array 1416 is output to the input / output circuit 1417. This completes the read operation.

  Since data is rewritten by charging / discharging the capacitive element C45, the DOSRAM 1400 has no restriction on the number of times of rewriting in principle, and can write and read data with low energy. Further, since the circuit configuration of the memory cell 1445 is simple, the capacity can be easily increased. Therefore, the DOSRAM 1400 is suitable for a memory device that rewrites a large amount of data at a high frequency, for example, a frame memory used for image processing.

  The OS transistor MO45 is an OS transistor. Since the OS transistor has an extremely small off-state current, it is possible to suppress charge leakage from the capacitor C45. Therefore, since the DOSRAM 1400 has a much longer retention time than the DRAM, the refresh rate frequency can be reduced. Therefore, the DOSRAM 1400 can reduce the power required for the fresh operation.

  Since the MC-SA array 1420 has a stacked structure, the bit line can be shortened to the same length as the local sense amplifier array 1426. By shortening the bit line, the bit line capacitance can be reduced and the storage capacity of the memory cell 1445 can be reduced. Further, by providing the switch array 1444 in the local sense amplifier array 1426, the number of long bit lines can be reduced. For the above reasons, the load that is driven when the DOSRAM 1400 is accessed is reduced.

  From the above, the power consumption of the neural network system can be reduced by using the DOSRAM 1400 for the DOSRAM 32 described in the above embodiment.

<< NOSRAM >>
The NOSRAM will be described with reference to FIGS. Here, a multi-level NOSRAM that stores multi-level data in one memory cell will be described.

  A NOSRAM 1600 illustrated in FIG. 10 includes a memory cell array 1610, a controller 1640, a row driver 1650, a column driver 1660, and an output driver 1670.

  The memory cell array 1610 includes a plurality of memory cells 1611, a plurality of word lines WWL and RWL, a bit line BL, and a source line SL. The word line WWL is a write word line, and the word line RWL is a read word line. In the NOSRAM 1600, one memory cell 1611 stores 3-bit (eight values) data.

  The controller 1640 comprehensively controls the entire NOSRAM 1600 and writes data WDA [31: 0] and reads data RDA [31: 0]. The controller 1640 processes command signals from the outside (for example, a chip enable signal, a write enable signal, etc.), and generates control signals for the row driver 1650, the column driver 1660, and the output driver 1670.

  The row driver 1650 has a function of selecting a row to be accessed. The row driver 1650 includes a row decoder 1651 and a word line driver 1652.

  The column driver 1660 drives the source line SL and the bit line BL. The column driver 1660 includes a column decoder 1661, a write driver 1662, and a DAC (digital-analog conversion circuit) 1663.

  The DAC 1663 converts 3-bit digital data into an analog voltage. The DAC 1663 converts 32-bit data WDA [31: 0] into an analog voltage every 3 bits.

  The write driver 1662 has a function of precharging the source line SL, a function of electrically floating the source line SL, a function of selecting the source line SL, and a write voltage generated by the DAC 1663 to the selected source line SL. A function of precharging the bit line BL, a function of electrically floating the bit line BL, and the like.

  The output driver 1670 includes a selector 1671, an ADC (analog-digital conversion circuit) 1672, and an output buffer 1673. The selector 1671 selects the source line SL to be accessed and transmits the voltage of the selected source line SL to the ADC 1672. The ADC 1672 has a function of converting an analog voltage into 3-bit digital data. The voltage of the source line SL is converted into 3-bit data in the ADC 1672, and the output buffer 1673 holds data output from the ADC 1672.

<Memory cell>
FIG. 11A is a circuit diagram illustrating a structural example of the memory cell 1611. The memory cell 1611 is a 2T type gain cell, and the memory cell 161 is electrically connected to the word lines WWL and RWL, the bit line BL, the source line SL, and the wiring BGL. The memory cell 1611 includes a node SN, an OS transistor MO61, a transistor MP61, and a capacitor C61. The OS transistor MO61 is a write transistor. The transistor MP61 is a read transistor, and is composed of, for example, a p-channel Si transistor. The capacitive element C61 is a holding capacitor for holding the voltage of the node SN. The node SN is a data holding node and corresponds to the gate of the transistor MP61 here.

  Since the write transistor of the memory cell 1611 includes the OS transistor MO61, the NOSRAM 1600 can hold data for a long time.

  In the example of FIG. 11A, the bit line is a common bit line for writing and reading. However, as shown in FIG. 11B, a writing bit line WBL and a reading bit line RBL may be provided. Good.

  FIG. 11C to FIG. 11E show other configuration examples of the memory cell. FIGS. 11C to 11E show an example in which a write bit line and a read bit line are provided. However, as shown in FIG. May be provided.

  A memory cell 1612 shown in FIG. 11C is a modified example of the memory cell 1611 and is obtained by changing a reading transistor to an n-channel transistor (MN61). The transistor MN61 may be an OS transistor or a Si transistor.

  In the memory cells 1611 and 1612, the OS transistor MO61 may be an OS transistor without a back gate.

  A memory cell 1613 illustrated in FIG. 11D is a 3T type gain cell, and is electrically connected to the word lines WWL and RWL, the bit lines WBL and RBL, the source line SL, and the wirings BGL and PCL. The memory cell 1613 includes a node SN, an OS transistor MO62, a transistor MP62, a transistor MP63, and a capacitor C62. The OS transistor MO62 is a write transistor. The transistor MP62 is a read transistor, and the transistor MP63 is a selection transistor.

  A memory cell 1614 shown in FIG. 11E is a modification example of the memory cell 1613, in which a read transistor and a selection transistor are changed to n-channel transistors (MN62 and MN63). The transistors MN62 and MN63 may be OS transistors or Si transistors.

  The OS transistor provided in the memory cells 1611 to 1614 may be a transistor without a back gate or a transistor with a back gate.

  Since data is rewritten by charging / discharging the capacitive element C61, the NOSRAM 1600 has no restriction on the number of times of rewriting in principle, and can write and read data with low energy. Further, since the data can be held for a long time, the refresh frequency can be reduced. Therefore, the DOSRAM 1400 is suitable for a memory device that rewrites a large amount of data at a high frequency, for example, a frame memory used for image processing.

  By using the NOSRAM 1600 for the NOSRAM 31 described in the above embodiment, the power consumption of the neural network system can be reduced.

(Embodiment 4)
In this embodiment, an OS-FPGA that can be installed in the neural network system described in the above embodiment will be described with reference to FIGS.

<Configuration example of OS-FPGA>
FIG. 12 is a block diagram of the OS-FPGA. The OS-FPGA 100 includes a controller 110 and circuit blocks 101A to 101D. FIG. 12 illustrates four circuit blocks. The circuit blocks 101A to 101D each function as an OS-FPGA that can realize a multi-context method.

  The circuit blocks 101A to 101D each have a programmable area 111, a word driver 112, and a data driver 113. The programmable area 111 includes an input / output block (hereinafter referred to as IOB 117) and a core 118. The programmable area 111 has a function of storing configuration data for realizing different functions for each of the circuit blocks 101A to 101D and processing the data.

  The function of processing data is set by a plurality of sets of configuration data. Configuration data is stored in a plurality of sets of configuration memories. The configuration memory sets a programmable logic element (PLE), a programmable switch (PRS), and a programmable IO (PIO) according to the context. By switching this setting, it is possible to realize a so-called multi-context system in which the function for processing data described above is set and the function for processing data is switched instantaneously by context switching. The circuit blocks 101A to 101D can be dynamically reconfigured. The context switching is controlled by the controller 110.

  In the OS-FPGA 100, in the circuit blocks 101A to 101D functioning as an FPGA capable of realizing data processing of a plurality of functions, settings for performing data processing by a plurality of functions, context switching, and configuration data dynamically It is possible to adopt a configuration in which switching is performed one after another by so-called dynamic reconfiguration to be rewritten. With this configuration, different data processing can be realized with one data processing device by repeatedly setting and switching data. Therefore, when configuring the artificial neural network functions such as deep learning and deep learning, the circuit implementation scale can be reduced.

  FIG. 13A is a diagram for describing a configuration example of the programmable area 111. The programmable area 111 has an IOB 117 and a core 118. The IOB 117 has a programmable input / output circuit (PIO). The core 118 includes a plurality of logic array blocks (hereinafter referred to as LAB 120) and a plurality of switch array blocks (hereinafter referred to as SAB 130).

  FIG. 13B is a diagram for describing a configuration example of the LAB 120. As an example, the LAB 120 illustrated in FIG. 13B includes five programmable logic elements (hereinafter, PLE 121).

  FIG. 13C is a diagram for describing a configuration example of the SAB 130. The SAB 130 shown in FIG. 13C includes a plurality of switch blocks (hereinafter referred to as SB 131) arranged in an array.

  Next, with reference to FIGS. 14A to 14C, the SB 131 will be described. The SB 131 receives the signal data, the signal context [1: 0], and the signal word [1: 0]. The signal data is configuration data. The signal context [1: 0] is a context selection signal. Signal word [1: 0] is a word line selection signal.

  The SB 131 includes a programmable routing switch (hereinafter referred to as PRS 133 [0], 133 [1]). The PRS 133 [0] and 133 [1] have a configuration memory (CM) that can store configuration data. The configuration data is information for setting the conduction state of the PRS 133 [0] and 133 [1]. For example, PRS133 [0] and 133 [1] are set to a conductive state when the level is high (hereinafter, “H”), and PRS133 [0] and 133 [1] are not set when the level is low (hereinafter, “L”). Set to the conductive state.

  FIG. 14B is a circuit diagram of the PRS 133 [0]. PRS133 [0] and PRS133 [1] have the same circuit configuration. The PRS133 [0] and the PRS133 [1] are different in input context selection signal and word line selection signal. The signals context [0] and word [0] are input to the PRS 133 [0], and the signals context [1] and word [1] are input to the PRS 133 [1]. For example, in the SB 131, when the signal context [0] becomes “H”, the PRS 133 [0] becomes active.

  The PRS 133 [0] includes a CM 135 and a transistor M1. The transistor M1 is described as an n-channel type, but may be a p-channel type.

  The transistor M1 is a pass transistor whose conduction state is controlled by the CM 135. The transistor M1 is a Si transistor. This configuration is preferable because a high-speed switching operation can be performed.

  The CM 135 includes a nonvolatile memory (hereinafter referred to as NVM 137) and a transistor M2. The transistor M2 is described as an n-channel type, but may be a p-channel type.

  The NVM 137 includes a capacitor C1, a transistor MO1, and a transistor MO2. The transistors MO1 and MO2 are described as n-channel type, but may be p-channel type. The transistors MO1 and MO2 are OS transistors. With such a structure, a transistor with low off-state current and favorable transistor characteristics even when the gate insulating layer is thick can be obtained.

  The gate of the transistor MO2 is the node N1. The gate of the transistor M1 is the node N2. The transistor MO1 controls the conduction state between the node N1 and the signal line for signal data. The node N1 is a charge holding node of the CM 135. The transistor MO1 can be held at the node N1 according to the set information by being controlled to be in a non-conductive state. The transistor MO2 controls a conduction state between the node N2 and the signal line for the signal context [0].

  Note that the gate insulating layers of the OS transistors such as the transistors MO1 and MO2 are preferably thicker than the gate insulating layers of the Si transistors such as the transistors M1 and M2. As described above, since the transistor is an OS transistor, the transistor characteristics are excellent even when the gate insulating layer is thickened. Since the gate insulating layer of the transistor MO2 can be thick, charge retention characteristics at the node N1, which is a charge retention node, can be improved.

  The logic of the signal context [0] is given to the node N1 when the transistor MO2 is in a conductive state. That is, when the signal context [0] becomes “H”, the PRS 133 [0] becomes active. That is, a voltage corresponding to the voltage of the node N1, which is the logic of the signal data, is applied to the node N2.

  Specifically, since the voltage of the node N1 is “H”, the transistor MO2 is turned on, and the signal context [0] is “H”, so that the node N2 is “H”. Further, when the voltage at the node N1 is “L”, the transistor MO2 is turned off, and the node N2 becomes “L”. Depending on whether the node N2 is “H” or “L”, that is, the conduction state between the input terminal input and the output terminal output is controlled.

  FIG. 14B illustrates a structure in which a transistor M2 connected to the ground potential is provided and the transistor M2 is diode-connected as an example. The node N2 is likely to be in an electrically floating state because the transistor MO2 is an OS transistor with a low off-state current. Therefore, it is effective to use a Si transistor having a relatively high off-state current compared to the OS transistor as the transistor M2 and to be directly connected to the node N2. The transistor M2 is a diode-connected transistor. With this structure, the off-state current of the transistor M2 can be prevented from being brought into an electrically floating state at the node N2. In addition, the operation is not affected during the period in which the node N2 is “H”, and the node N2 can be “L” more reliably.

  In addition, when not distinguishing PRS133 [0] and PRS133 [1], it calls PRS133. The same applies to other elements.

  Note that the PRS 133 can improve the switching characteristics by boosting using the fact that the gate of the transistor M1 is in a floating state. On the other hand, when the Si transistor adopts the 65 nm Si process, the gate leakage of the Si transistor cannot be ignored. Therefore, without adopting the configuration of holding the charge at the gate of the Si transistor, the charge holding node is changed to the gate of the transistor MO2, which is an OS transistor in which the short channel effect hardly occurs even when the gate insulating film is thick, A non-volatile OS memory can be realized.

  With reference to FIGS. 14C and 14D, the switching operation of the PRS 133 [0] will be described.

  FIG. 14C illustrates a switching operation in a state where configuration data has already been written to the PRS 133 [0] so that the node N1 of the PRS 133 [0] is “H”.

  During the period when the signal context [0] is “H”, the PRS 133 [0] is active. Since the transistor MO2 becomes conductive when the node N1 is “H”, “H” corresponding to the configuration data stored in the CM 135 changes to “H”, and the transistor M1 becomes conductive. Become. When the input terminal input changes to “H” in this state, the potential of the gate of the transistor M1 rises due to boosting. When the input terminal input changes to “H”, the transistor MO2 of the NVM 137 is a source follower, and thus the gate voltage of the transistor M1 rises due to boosting. As a result, the transistor MO2 of the NVM 137 loses drive capability, and the gate of the transistor M1 is in a floating state. As a result, the potential of the output terminal output can be increased by further increasing the gate voltage of the transistor M1. Therefore, improvement in switch characteristics can be realized.

  During the period when the signal context [0] is “L”, the PRS 133 [0] is inactive. When the node N1 is “H”, the transistor MO2 is turned on. Since the signal context [0] is “L”, the gate of the transistor M1 is changed to “L”, and the transistor M1 is turned off. As a result, even if the input terminal input changes to “H”, the potential of the output terminal output does not change.

  FIG. 14D illustrates a switching operation in a state where configuration data has already been written in the PRS 133 [0] so that the node N1 of the PRS 133 [0] is “L”.

  During the period when the signal context [0] is “H”, the PRS 133 [0] is active. When the node N1 is “L”, the transistor MO2 is turned off. The potential of the gate of the transistor M1, that is, the node N2, becomes “L” due to the leakage current of the transistor M2. That is, the node N2 is prevented from being electrically floating. Transistor M1 is turned off. As a result, even if the input terminal input changes to “H”, the potential of the output terminal output does not change.

  During the period when the signal context [0] is “L”, the PRS 133 [0] is inactive. When the node N1 is “L”, the transistor MO2 is turned on. The potential of the gate of the transistor M1, that is, the node N2, becomes “L” due to the leakage current of the transistor M2. Transistor M1 is turned off. As a result, even if the input terminal input changes to “H”, the potential of the output terminal output does not change.

  In the PRS 133 having a multi-context function, the CM 135 also has a multiplexer function. The PRS 133 is preferable because it has a smaller number of transistors than a CM using an SRAM (Static RAM) and has an effect of increasing the driving capability of the transistor M1 by boosting.

  FIG. 15 is a block diagram of the PLE 121. The PLE 121 includes an LUT block 123, a register block 124, a selector 125, and a CM 126. The LUT block 123 has a lookup table function and, as an example, is configured to select an output of an internal 16-bit CM pair according to inputs inA-inD. The selector 125 is configured to select the output of the LUT block 123 or the output of the register block 124 according to the configuration data stored in the CM 126.

  The PLE 121 is connected to the high potential power supply line VDD via the power switch 127. On / off of the power switch 127 is set by configuration data stored in the CM 128. By providing the power switch 127 in each PLE 121, a fine-grain power gating (FG-PG) function is enabled. With the FG-PG function, the PLE 121 that is not used after context switching can be power-gated, so that standby power can be reduced.

  In order to realize normally-off (NOFF) computing, the register block 124 includes a nonvolatile register (NV-Reg). NV-Reg in the PLE 121 is a flip-flop (OS-FF) including a nonvolatile OS memory.

  The register block 124 includes an OS-FF 140 [1] and an OS-FF 140 [2]. The signal user_res, the signal load, and the signal store are input to the OS-FF 140 [1] and the OS-FF 140 [2]. The clock signal CLK1 is input to the OS-FF 140 [1], and the clock signal CLK2 is input to the OS-FF 140 [2].

  FIG. 16A illustrates a circuit diagram of the OS-FF 140 as an example.

  The OS-FF 140 includes an FF 141 and a shadow register 142. The FF 141 includes a node CK, a node R, a node D, a node Q, and a node QB. The clock signal CLK1 (or the clock signal CLK2) is input to the node CK. A signal user_res is input to the node R. The signal user_res is a reset signal. Node D is a data input node, and node Q is a data output node. Nodes Q and QB have a complementary logic relationship.

  The shadow register 142 functions as a backup circuit for the FF 141. The shadow register 142 backs up the data of the nodes Q and QB according to the signal store, and writes back up the backed up data to the nodes Q and QB according to the signal load.

  The shadow register 142 includes an inverter circuit 88, an inverter circuit 89, a transistor M7, a transistor MB7, an NVM 143, and an NVM 143B. The NVM 143 and the NVM 143B have the same circuit configuration as the NVM 137 of the PRS 133. The NVM 143 includes a capacitor C6, a transistor MO5, and a transistor MO6. The NVM 143B includes a capacitor CB6, a transistor MOB5, and a transistor MOB6. Node N6 is the gate of transistor MO6, and node NB6 is the gate of transistor MOB6. Each node is a charge holding node. Node N7 is the gate of transistor M7. Node NB7 is the gate of transistor MB7.

  With reference to FIG. 16B, an operation method of the OS-FF 140 will be described.

  A data backup operation will be described. When the “H” signal store is input to the OS-FF 140, the shadow register 142 backs up the data in the FF 141. The node N6 becomes “L” when the data of the node Q is written, and the node NB6 becomes “H” when the data of the node QB is written. Thereafter, power gating is executed, and the power switch 127 is turned off. Although the data of the nodes Q and QB of the FF 141 are lost, the shadow register 142 holds the backed up data even when the power is turned off.

  The data recovery operation will be described. The power switch 127 is turned on to supply power to the PLE 121. Thereafter, when the “H” signal load is input to the OS-FF 140, the shadow register 142 writes backed-up data back to the FF 141. Since the node N6 is “L”, the node N7 is maintained at “L” and the node NB6 is “H”, so that the node NB7 is “H”. Therefore, the node Q becomes “H” and the node QB becomes “L”. That is, the OS-FF 140 returns to the state during the backup operation.

  With the above configuration, the OS-FPGA described above can be realized.

(Embodiment 5)
In the present embodiment, a product-sum operation circuit applied to the analog operation circuit 42 will be described. FIG. 17 shows a configuration example of the product-sum operation circuit.

  The product-sum operation circuit 200 illustrated in FIG. 17 includes an analog memory 201, a reference analog memory 202, drivers 206 and 207, a read circuit 208, and a current source circuit 205.

  The analog memory 201 includes a plurality of memory cells MC and a plurality of wirings RW, WW, WD, VR, and BL. In the example of FIG. 17, the analog memory 201 is provided with memory cells MC arranged in y rows and x columns (y and x are integers of 1 or more). Each memory cell MC is electrically connected to wirings RW and WW in the corresponding row, and is electrically connected to wirings WD, VR, and BL in the corresponding column.

  The reference analog memory 202 has memory cells MCR and wirings WDREF, WDREF, and VRREF arranged in y rows and 1 column. The analog memory 201 and the reference analog memory 202 share the wirings RW and WW. Each memory cell MC is electrically connected to wirings RW, WW and wirings WDREF, VRREF, BLREF in the corresponding row.

  In this specification, when a specific memory cell MC is represented among the plurality of memory cells MC, it is expressed as a memory cell MC [i, j] or the like. The expression “memory cell MC” refers to an arbitrary memory cell MC. The same applies to other elements.

  The driver 206 drives the wirings RW and WW. The driver 207 drives the wiring WD. The reading circuit 208 reads data written in the wiring BL. The current source circuit 205 generates a reference current and supplies it to the wirings BL and BLREF.

  A specific example of each circuit of the product-sum operation circuit 200 is shown and described.

  The product-sum operation circuit 200 illustrated in FIG. 18 includes an analog memory 201, a reference analog memory 202, a current source circuit 203, a current sink circuit 204, and a current source circuit 205.

  The analog memory 201 includes a memory cell MC exemplified by a memory cell MC [i, j] and a memory cell MC [i + 1, j]. Each memory cell MC includes an element having a function of converting an input potential into a current. As an element having the above function, for example, an active element such as a transistor can be used. FIG. 18 illustrates a case where each memory cell MC includes a transistor Tr1.

  A first analog potential is input to the memory cell MC from the wiring WD exemplified by the wiring WD [j]. The memory cell MC has a function of generating a first analog current corresponding to the first analog potential. Specifically, the drain current of the transistor Tr1 obtained when the first analog potential is supplied to the gate of the transistor Tr1 can be used as the first analog current. Hereinafter, the current flowing through the memory cell MC [i, j] is I [i, j], and the current flowing through the memory cell MC [i + 1, j] is I [i + 1, j].

  Note that when the transistor Tr1 operates in the saturation region, the drain current does not depend on the voltage between the source and the drain, but is controlled by the difference between the gate voltage and the threshold voltage. Therefore, it is desirable to operate the transistor Tr1 in the saturation region. In order to operate the transistor Tr1 in the saturation region, it is assumed that the gate voltage and the voltage between the source and the drain are appropriately set to a voltage within a range in which the transistor Tr1 operates in the saturation region.

  Specifically, in the product-sum operation circuit 200 illustrated in FIG. 18, the first analog potential Vx [i, j] or the first analog potential Vx [i] from the wiring WD [j] to the memory cell MC [i, j]. , J] is input. The memory cell MC [i, j] has a function of generating a first analog current corresponding to the first analog potential Vx [i, j]. That is, in this case, the current I [i, j] of the memory cell MC [i, j] corresponds to the first analog current.

  Specifically, in the product-sum operation circuit 200 illustrated in FIG. 18, the first analog potential Vx [i + 1, j] or the first analog potential Vx is connected to the memory cell MC [i + 1, j] from the wiring WD [j]. A potential corresponding to [i + 1, j] is input. The memory cell MC [i + 1, j] has a function of generating a first analog current corresponding to the first analog potential Vx [i + 1, j]. That is, in this case, the current I [i + 1, j] of the memory cell MC [i + 1, j] corresponds to the first analog current.

  The memory cell MC has a function of holding the first analog potential. That is, it can be said that the memory cell MC has a function of holding the first analog current corresponding to the first analog potential by holding the first analog potential.

  In addition, the second analog potential is input to the memory cell MC from the wiring RW exemplified by the wiring RW [i] and the wiring RW [i + 1]. The memory cell MC has a function of adding the second analog potential or a potential corresponding to the second analog potential to the already held first analog potential, and a third analog potential obtained by the addition. Holding function. The memory cell MC has a function of generating a second analog current corresponding to the third analog potential. That is, it can be said that the memory cell MC has a function of holding the second analog current corresponding to the third analog potential by holding the third analog potential.

  Specifically, in the product-sum operation circuit 200 illustrated in FIG. 18, the second analog potential Vw [i, j] is input to the memory cell MC [i, j] from the wiring RW [i]. The memory cell MC [i, j] has a function of holding a third analog potential corresponding to the first analog potential Vx [i, j] and the second analog potential Vw [i, j]. The memory cell MC [i, j] has a function of generating a second analog current corresponding to the third analog potential. That is, in this case, the current I [i, j] of the memory cell MC [i, j] corresponds to the second analog current.

  In the product-sum operation circuit 200 illustrated in FIG. 18, the second analog potential Vw [i + 1, j] is input to the memory cell MC [i + 1, j] from the wiring RW [i + 1]. The memory cell MC [i + 1, j] has a function of holding a third analog potential corresponding to the first analog potential Vx [i + 1, j] and the second analog potential Vw [i + 1, j]. The memory cell MC [i + 1, j] has a function of generating a second analog current corresponding to the third analog potential. That is, in this case, the current I [i + 1, j] of the memory cell MC [i + 1, j] corresponds to the second analog current.

  The current I [i, j] flows between the wiring BL [j] and the wiring VR [j] through the memory cell MC [i, j]. The current I [i + 1, j] flows between the wiring BL [j] and the wiring VR [j] through the memory cell MC [i + 1, j]. Therefore, a current I [j] corresponding to the sum of the current I [i, j] and the current I [i + 1, j] is passed through the memory cell MC [i, j] and the memory cell MC [i + 1, j]. It flows between the wiring BL [j] and the wiring VR [j].

  The reference analog memory 202 includes a memory cell MCR exemplified by a memory cell MCR [i] and a memory cell MCR [i + 1]. A first reference potential VPR is input to the memory cell MCR from the wiring WDREF. The memory cell MCR has a function of generating a first reference current corresponding to the first reference potential VPR. Hereinafter, the current flowing through the memory cell MCR [i] is referred to as IREF [i], and the current flowing through the memory cell MCR [i + 1] is referred to as IREF [i + 1].

  Specifically, in the product-sum operation circuit 200 illustrated in FIG. 18, the first reference potential VPR is input to the memory cell MCR [i] from the wiring WDREF [i]. The memory cell MCR [i] has a function of generating a first reference current corresponding to the first reference potential VPR. That is, in this case, the current IREF [i] of the memory cell MCR [i] corresponds to the first reference current.

  In the product-sum operation circuit 200 illustrated in FIG. 10, the first reference potential VPR is input to the memory cell MCR [i + 1] from the wiring WDREF. The memory cell MCR [i + 1] has a function of generating a first reference current corresponding to the first reference potential VPR. That is, in this case, the current IREF [i + 1] of the memory cell MCR [i + 1] corresponds to the first reference current.

  The memory cell MCR has a function of holding the first reference potential VPR. That is, it can be said that the memory cell MCR has a function of holding the first reference current corresponding to the first reference potential VPR by holding the first reference potential VPR.

  In addition, the second analog potential is input to the memory cell MCR from the wiring RW exemplified by the wiring RW [i] and the wiring RW [i + 1]. The memory cell MCR adds the second analog potential or a potential corresponding to the second analog potential to the already held first reference potential VPR, and holds the second reference potential obtained by the addition. It has the function to do. The memory cell MCR has a function of generating a second reference current corresponding to the second reference potential. That is, it can be said that the memory cell MCR has a function of holding the second reference potential corresponding to the second reference potential by holding the second reference potential.

  Specifically, in the product-sum operation circuit 200 illustrated in FIG. 18, the second analog potential Vw [i, j] is input to the memory cell MCR [i] from the wiring RW [i]. The memory cell MCR [i] has a function of holding a second reference potential corresponding to the first reference potential VPR and the second analog potential Vw [i, j]. The memory cell MCR [i] has a function of generating a second reference current corresponding to the second reference potential. That is, in this case, the current IREF [i] of the memory cell MCR [i] corresponds to the second reference current.

  In the product-sum operation circuit 200 illustrated in FIG. 18, the second analog potential Vw [i + 1, j] is input to the memory cell MCR [i + 1] from the wiring RW [i + 1]. The memory cell MCR [i + 1] has a function of holding a second reference potential corresponding to the first reference potential VPR and the second analog potential Vw [i + 1, j]. The memory cell MCR [i + 1] has a function of generating a second reference current corresponding to the second reference potential. That is, in this case, the current IREF [i + 1] of the memory cell MCR [i + 1] corresponds to the second reference current.

  Then, the current IREF [i] flows between the wiring BLREF and the wiring VRREF through the memory cell MCR [i]. The current IREF [i + 1] flows between the wiring BLREF and the wiring VRREF through the memory cell MCR [i + 1]. Therefore, the current IREF corresponding to the sum of the current IREF [i] and the current IREF [i + 1] flows between the wiring BLREF and the wiring VRREF via the memory cell MCR [i] and the memory cell MCR [i + 1]. Become.

  The current source circuit 205 has a function of supplying a current having the same value as the current IREF flowing through the wiring BLREF or a current corresponding to the current IREF to the wiring BL. When setting an offset current, which will be described later, a current flowing between the wiring BL [j] and the wiring VR [j] through the memory cell MC [i, j] and the memory cell MC [i + 1, j]. When I [j] is different from the current IREF flowing between the wiring BLREF and the wiring VRREF via the memory cell MCR [i] and the memory cell MCR [i + 1], the difference current is the current source circuit 203 or the current sink circuit 204. Flowing into.

  Specifically, when the current I [j] is larger than the current IREF, the current source circuit 203 has a function of generating a current ΔI [j] corresponding to the difference between the current I [j] and the current IREF. The current source circuit 203 has a function of supplying the generated current ΔI [j] to the wiring BL [j]. That is, it can be said that the current source circuit 203 has a function of holding the current ΔI [j].

  When the current I [j] is smaller than the current IREF, the current sink circuit 204 has a function of generating a current ΔI [j] corresponding to the difference between the current I [j] and the current IREF. Further, the current sink circuit 204 has a function of drawing the generated current ΔI [j] from the wiring BL [j]. That is, it can be said that the current sink circuit 204 has a function of holding the current ΔI [j].

  Next, an example of the operation of the product-sum operation circuit 200 illustrated in FIG. 18 will be described.

  First, a potential corresponding to the first analog potential is stored in the memory cell MC [i, j]. Specifically, a potential VPR−Vx [i, j] obtained by subtracting the first analog potential Vx [i, j] from the first reference potential VPR is set to the memory cell MC [i] via the wiring WD [j]. , J]. In the memory cell MC [i, j], the potential VPR−Vx [i, j] is held. In the memory cell MC [i, j], a current I [i, j] corresponding to the potential VPR−Vx [i, j] is generated. For example, the first reference potential VPR is a high level potential higher than the ground potential. Specifically, it is desirable that the potential is higher than the ground potential and is approximately equal to or lower than the high-level potential VDD supplied to the current source circuit 205.

  Further, the first reference potential VPR is stored in the memory cell MCR [i]. Specifically, the potential VPR is input to the memory cell MCR [i] through the wiring WDREF. In the memory cell MCR [i], the potential VPR is held. In the memory cell MCR [i], a current IREF [i] corresponding to the potential VPR is generated.

  In addition, a potential corresponding to the first analog potential is stored in the memory cell MC [i + 1, j]. Specifically, the potential VPR−Vx [i + 1, j] obtained by subtracting the first analog potential Vx [i + 1, j] from the first reference potential VPR is connected to the memory cell MC [i + 1] via the wiring WD [j]. , J]. In the memory cell MC [i + 1, j], the potential VPR−Vx [i + 1, j] is held. Further, in the memory cell MC [i + 1, j], a current I [i + 1, j] corresponding to the potential VPR−Vx [i + 1, j] is generated.

  In addition, the first reference potential VPR is stored in the memory cell MCR [i + 1]. Specifically, the potential VPR is input to the memory cell MCR [i + 1] through the wiring WDREF. In the Mori cell MCR [i + 1], the potential VPR is held. In the memory cell MCR [i + 1], a current IREF [i + 1] corresponding to the potential VPR is generated.

  In the above operation, the wiring RW [i] and the wiring RW [i + 1] are set to the reference potential. For example, a ground potential, a low-level potential VSS lower than the reference potential, or the like can be used as the reference potential. Alternatively, when a potential between the potential VSS and the potential VDD is used as the reference potential, the potential of the wiring RW can be higher than the ground potential even if the second analog potential Vw is positive or negative, so that signal generation is facilitated. This is preferable because product operation for positive and negative potentials can be performed.

  Through the above operation, currents that are combined with currents generated in the memory cells MC connected to the wiring BL [j] flow through the wiring BL [j]. Specifically, in FIG. 18, the current I [i, j] generated in the memory cell MC [i, j] is combined with the current I [i + 1, j] generated in the memory cell MC [i + 1, j]. Current I [j] flows. Further, by the above operation, currents that are combined with currents generated in the memory cells MCR connected to the wiring BLREF flow through the wiring BLREF. Specifically, in FIG. 18, a current IREF that is a combination of the current IREF [i] generated in the memory cell MCR [i] and the current IREF [i + 1] generated in the memory cell MCR [i + 1] flows.

  Next, from the difference between the current I [j] obtained by the first analog potential and the current IREF obtained by the first reference potential, with the potentials of the wiring RW [i] and the wiring RW [i + 1] being the reference potential. The obtained offset current Ioffset [j] is held in the current source circuit 203 or the current sink circuit 204.

  Specifically, when the current I [j] is larger than the current IREF, the current source circuit 203 supplies the current Ioffset [j] to the wiring BL [j]. That is, the current ICM [j] flowing through the current source circuit 203 corresponds to the current Ioffset [j]. Then, the value of the current ICM [j] is held in the current source circuit 203. On the other hand, when the current I [j] is smaller than the current IREF, the current sink circuit 204 draws the current Ioffset [j] from the wiring BL [j]. That is, the current ICP [j] flowing through the current sink circuit 204 corresponds to the current Ioffset [j]. The value of the current ICP [j] is held in the current sink circuit 204.

  Then, according to the second analog potential or the second analog potential so as to be added to the first analog potential already held in the memory cell MC [i, j] or the potential according to the first analog potential. The stored potential is stored in the memory cell MC [i, j]. Specifically, by setting the potential of the wiring RW [i] to a potential higher by Vw [i] than the reference potential, the second analog potential Vw [i] is stored in the memory via the wiring RW [i]. Input to cell MC [i, j]. In the memory cell MC [i, j], the potential VPR−Vx [i, j] + Vw [i] is held. In the memory cell MC [i, j], a current I [i, j] corresponding to the potential VPR−Vx [i, j] + Vw [i] is generated.

  Further, according to the second analog potential or the second analog potential so as to be added to the first analog potential already held in the memory cell MC [i + 1, j] or the potential according to the first analog potential. The stored potential is stored in the memory cell MC [i + 1, j]. Specifically, by setting the potential of the wiring RW [i + 1] higher by Vw [i + 1] than the reference potential, the second analog potential Vw [i + 1] is stored in the memory through the wiring RW [i + 1]. It is input to the cell MC [i + 1, j]. In the memory cell MC [i + 1, j], the potential VPR−Vx [i + 1, j] + Vw [i + 1] is held. In the memory cell MC [i + 1, j], a current I [i + 1, j] corresponding to the potential VPR−Vx [i + 1, j] + Vw [i + 1] is generated.

  Note that in the case where the transistor Tr1 that operates in the saturation region is used as an element that converts potential into current, the potential of the wiring RW [i] is Vw [i], and the potential of the wiring RW [i + 1] is Vw [i + 1]. Assuming that the drain current of the transistor Tr1 included in the memory cell MC [i, j] corresponds to the current I [i, j], the second analog current is expressed by the following Expression 1. Note that k is a coefficient and Vth is a threshold voltage of the transistor Tr1.

I [i, j] = k (Vw [i] −Vth + VPR−Vx [i, j]) ² (1)

  Further, since the drain current of the transistor Tr1 included in the memory cell MCR [i] corresponds to the current IREF [i], the second reference current is expressed by the following Expression 2.

IREF [i] = k (Vw [i] −Vth + VPR) ² (2)

  The current I [j] corresponding to the sum of the current I [i, j] flowing through the memory cell MC [i, j] and the current I [i + 1, j] flowing through the memory cell MC [i + 1, j] is: I [j] = ΣiI [i, j], and the current IREF corresponding to the sum of the current IREF [i] flowing through the memory cell MCR [i] and the current IREF [i + 1] flowing through the memory cell MCR [i + 1] is , IREF = ΣiIREF [i], and the current ΔI [j] corresponding to the difference is expressed by the following Equation 3.

  ΔI [j] = IREF−I [j] = ΣiIREF [i] −ΣiI [i, j] (3)

  From Equation 1, Equation 2, and Equation 3, current ΔI [j] is derived as in Equation 4 below.

ΔI [j]
= Σi {k (Vw [i] −Vth + VPR) ² −k (Vw [i] −Vth + VPR−Vx [i, j]) ² }
= 2kΣi (Vw [i] · Vx [i, j]) − 2kΣi (Vth−VPR) · Vx [i, j] −kΣiVx [i, j] ² (4)

  In Equation 4, the term represented by 2kΣi (Vw [i] · Vx [i, j]) is the product of the first analog potential Vx [i, j] and the second analog potential Vw [i], This corresponds to the sum of the product of one analog potential Vx [i + 1, j] and the second analog potential Vw [i + 1].

  Further, Ioffset [j] is when the potential of the wiring RW [i] is all set as the reference potential, that is, when the second analog potential Vw [i] is 0 and the second analog potential Vw [i + 1] is 0. If the current ΔI [j] is, then the following equation 5 is derived from the equation 4.

Ioffset [j] = − 2kΣi (Vth−VPR) · Vx [i, j] −kΣiVx [i, j] ² (5)

  Therefore, from Expressions 3 to 5, 2kΣi (Vw [i] · Vx [i, j]) corresponding to the product sum of the first analog current and the second analog current is expressed by Expression 6 below. I understand that

  2kΣi (Vw [i] · Vx [i, j]) = IREF−I [j] −Ioffset [j] (6)

  When the sum of currents flowing through the memory cell MC is current I [j], the sum of currents flowing through the memory cell MCR is current IREF, and the current flowing through the current source circuit 203 or the current sink circuit 204 is current Ioffset [j]. When the potential of the wiring RW [i] is Vw [i] and the potential of the wiring RW [i + 1] is Vw [i + 1], the current Iout [j] that flows out of the wiring BL [j] is IREF−I [j] −. Ioffset [j]. From Expression 6, the current Iout [j] is 2kΣi (Vw [i] · Vx [i, j]), and the first analog potential Vx [i, j] and the second analog potential Vw [i] are It can be seen that this corresponds to the sum of the product and the product of the second analog potential Vx [i + 1, j] and the second analog potential Vw [i + 1].

  Note that the transistor Tr1 is desirably operated in a saturation region, but even if the operation region of the transistor Tr1 is different from an ideal saturation region, the first analog potential Vx [i, j] and the second analog potential are A current corresponding to the sum of the product of Vw [i] and the product of the second analog potential Vx [i + 1, j] and the second analog potential Vw [i + 1] is obtained without any problem with accuracy within a desired range. If it can, the transistor Tr1 can be regarded as operating in the saturation region.

  With the configuration of the product-sum operation circuit illustrated in FIG. 18, operation processing can be performed without conversion to digital data, so that the circuit scale of the semiconductor device can be reduced. Alternatively, with the configuration of the product-sum operation circuit illustrated in FIG. 18, the operation process can be executed without being converted into digital data, so that the time required for the operation process can be reduced. Alternatively, the configuration of the product-sum operation circuit illustrated in FIG. 18 can reduce the power consumption of the semiconductor device while suppressing the time required for the operation processing.

  Next, examples of specific structures of the analog memory 201, the reference analog memory 202, the current source circuit 203, the current sink circuit 204, and the current source circuit 205 will be described with reference to FIG.

  In FIG. 19, as an example, a specific circuit configuration and connection relationship between an arbitrary memory cell MC of 2 rows and 2 columns and an arbitrary memory cell MCR of 2 rows and 1 column are shown. Specifically, in FIG. 19, the memory cell MC [i, j] in the i-th row and j-th column, the memory cell MC [i + 1, j] in the i + 1-th row and j-th column, and the memory cell MC [i in the i-th row j + 1-th column. , J + 1] and the memory cell MC [i + 1, j + 1] in the (i + 1) th row and j + 1th column. Specifically, FIG. 19 illustrates the memory cell MCR [i] in the i-th row and the memory cell MCR [i + 1] in the i + 1-th row.

  The memory cell MC [i, j] in the i-th row, the memory cell MC [i, j + 1], and the memory cell MCR [i] are connected to the wiring RW [i] and the wiring WW [i]. The memory cell MC [i + 1, j] in the i + 1th row, the memory cell MC [i + 1, j + 1], and the memory cell MCR [i + 1] are connected to the wiring RW [i + 1] and the wiring WW [i + 1]. Yes.

  The memory cell MC [i, j] in the j-th column and the memory cell MC [i + 1, j] are connected to the wiring WD [j], the wiring VR [j], and the wiring BL [j]. The memory cell MC [i, j + 1] in the j + 1 column and the memory cell MC [i + 1, j + 1] are connected to the wiring WD [j + 1], the wiring VR [j + 1], and the wiring BL [j + 1]. . The memory cell MCR [i] and the memory cell MCR [i + 1] in the (i + 1) th row are connected to the wiring WDREF, the wiring VRREF, and the wiring BLREF.

  Each memory cell MC and each memory cell MCR includes a transistor Tr1, a transistor Tr2, and a capacitor C1. The transistor Tr2 has a function of controlling input of the first analog potential to the memory cell MC or the memory cell MCR. The transistor Tr1 has a function of generating an analog current in accordance with the potential input to the gate. The capacitor C1 has a second analog potential or a potential corresponding to the second analog potential to the first analog potential or the potential corresponding to the first analog potential held in the memory cell MC or the memory cell MCR. Has the function of adding.

  Specifically, in the memory cell MC illustrated in FIG. 19, the transistor Tr1 has a gate connected to the wiring WW, one of the source and the drain connected to the wiring WD, and the other of the source and the drain connected to the gate of the transistor Tr2. ing. In the transistor Tr2, one of a source and a drain is connected to the wiring VR, and the other of the source and the drain is connected to the wiring BL. In the capacitor C1, the first electrode is connected to the wiring RW, and the second electrode is connected to the gate of the transistor Tr2.

  In the memory cell MCR shown in FIG. 19, the transistor Tr1 has a gate connected to the wiring WW, one of the source and the drain connected to the wiring WDREF, and the other of the source and the drain connected to the gate of the transistor Tr2. . In the transistor Tr2, one of a source and a drain is connected to the wiring VRREF, and the other of the source and the drain is connected to the wiring BLREF. In the capacitor C1, the first electrode is connected to the wiring RW, and the second electrode is connected to the gate of the transistor Tr2.

  In the memory cell MC, when the gate of the transistor Tr1 is a node N, in the memory cell MC, the first analog potential is input to the node N through the transistor Tr2. Then, when the transistor Tr2 is turned off, the node N is in a floating state. The node N holds the first analog potential or the potential corresponding to the first analog potential. In the memory cell MC, when the node N is in a floating state, the second analog potential input to the first electrode of the capacitor C1 is applied to the node N. With the above operation, the node N has a potential obtained by adding the second analog potential or the potential corresponding to the second analog potential to the potential corresponding to the first analog potential or the first analog potential. Become.

  Note that since the potential of the first electrode of the capacitor C1 is applied to the node N via the capacitor C1, in practice, the amount of change in the potential of the first electrode is directly reflected in the amount of change in the potential of the node N. It is not done. Specifically, by multiplying the amount of change in potential of the first electrode by a coupling coefficient that is uniquely determined from the capacitance value of the capacitive element C1, the capacitance value of the gate capacitance of the transistor Tr1, and the capacitance value of the parasitic capacitance. The amount of change in the potential of the node N can be accurately calculated. Hereinafter, in order to make the description easy to understand, it is assumed that the change amount of the potential of the first electrode is reflected in the change amount of the potential of the node N.

  The drain current of the transistor Tr1 is determined according to the potential of the node N. Therefore, when the potential of the node N is held by turning off the transistor Tr2, the value of the drain current of the transistor Tr1 is also held. The drain current reflects the first analog potential and the second analog potential.

  Further, when the gate of the transistor Tr1 in the memory cell MCR is the node NREF, in the memory cell MCR, a first reference potential or a potential corresponding to the first reference potential is input to the node NREF through the transistor Tr2, and then the transistor When Tr2 is turned off, the node NREF enters a floating state, and the first reference potential or a potential corresponding to the first reference potential is held at the node NREF. In the memory cell MCR, when the node NREF is in a floating state, the second analog potential input to the first electrode of the capacitor C1 is applied to the node NREF. Through the above operation, the node NREF has the potential obtained by adding the second analog potential or the potential corresponding to the second analog potential to the potential corresponding to the first reference potential or the first reference potential. Become.

  The drain current of the transistor Tr1 is determined according to the potential of the node NREF. Therefore, when the potential of the node NREF is held by turning off the transistor Tr2, the value of the drain current of the transistor Tr1 is also held. The drain current reflects the first reference potential and the second analog potential.

  If the drain current flowing through the transistor Tr2 of the memory cell MC [i, j] is current I [i, j], and the drain current flowing through the transistor Tr2 of the memory cell MC [i + 1, j] is current I [i + 1, j]. The sum of the currents supplied from the wiring BL [j] to the memory cell MC [i, j] and the memory cell MC [i + 1, j] is the current I [j]. The drain current flowing through the transistor Tr2 of the memory cell MC [i, j + 1] is defined as a current I [i, j + 1], and the drain current flowing through the transistor Tr2 of the memory cell MC [i + 1, j + 1] is defined as a current I [i + 1, j + 1]. Then, a sum of currents supplied from the wiring BL [j + 1] to the memory cell MC [i, j + 1] and the memory cell MC [i + 1, j + 1] is a current I [j + 1]. Further, when the drain current flowing through the transistor Tr2 of the memory cell MCR [i] is current IREF [i] and the drain current flowing through the transistor Tr2 of the memory cell MCR [i + 1] is current IREF [i + 1], the memory cell is connected to the wiring BLREF. The sum of the currents supplied to MCR [i] and memory cell MCR [i + 1] is current IREF.

  The current source circuit 203 illustrated in FIG. 19 includes a current source circuit 203 [j] corresponding to the memory cell MC in the jth column and a current source circuit 203 [j + 1] corresponding to the memory cell MC in the j + 1th column. . Further, the current sink circuit 204 shown in FIG. 19 includes a current sink circuit 204 [j] corresponding to the memory cell MC in the jth column and a current sink circuit 204 [j + 1] corresponding to the memory cell MC in the j + 1th column. Have.

  The current source circuit 203 [j] and the current sink circuit 204 [j] are connected to the wiring BL [j]. In addition, the current source circuit 203 [j + 1] and the current sink circuit 204 [j + 1] are connected to the wiring BL [j + 1].

  The current source circuit 205 is connected to the wiring BL [j], the wiring BL [j + 1], and the wiring BLREF. The current source circuit 205 has a function of supplying the current IREF to the wiring BLREF and a function of supplying the same current as the current IREF or a current corresponding to the current IREF to each of the wiring BL [j] and the wiring BL [j + 1]. Have

  Specifically, the current source circuit 203 [j] and the current source circuit 203 [j + 1] each include transistors Tr7 to Tr9 and a capacitor C3. When setting the offset current, in the current source circuit 203 [j], the transistor Tr7 has a current corresponding to the difference between the current I [j] and the current IREF when the current I [j] is larger than the current IREF. It has a function of generating ICM [j]. In the current source circuit 203 [j + 1], the transistor Tr7 generates a current ICM [j + 1] corresponding to the difference between the current I [j + 1] and the current IREF when the current I [j + 1] is larger than the current IREF. It has a function. The current ICM [j] and the current ICM [j + 1] are supplied from the current source circuit 203 [j] and the current source circuit 203 [j + 1] to the wiring BL [j] and the wiring BL [j + 1].

  In the current source circuit 203 [j] and the current source circuit 203 [j + 1], in the transistor Tr7, one of the source and the drain is connected to the corresponding wiring BL, and the other of the source and the drain is supplied with a predetermined potential. Connected to wiring. In the transistor Tr8, one of the source and the drain is connected to the wiring BL, and the other of the source and the drain is connected to the gate of the transistor Tr7. In the transistor Tr9, one of the source and the drain is connected to the gate of the transistor Tr7, and the other of the source and the drain is connected to a wiring to which a predetermined potential is supplied. In the capacitor C3, the first electrode is connected to the gate of the transistor Tr7, and the second electrode is connected to a wiring to which a predetermined potential is supplied.

  The gate of the transistor Tr8 is connected to the wiring OSM, and the gate of the transistor Tr9 is connected to the wiring ORM.

  Note that FIG. 19 illustrates a case where the transistor Tr7 is a p-channel type and the transistors Tr8 and Tr9 are n-channel types.

  The current sink circuit 204 [j] and the current sink circuit 204 [j + 1] include transistors Tr4 to Tr6 and a capacitor C4, respectively. When setting the offset current, in the current sink circuit 204 [j], the transistor Tr4 has a current corresponding to the difference between the current I [j] and the current IREF when the current I [j] is smaller than the current IREF. It has a function of generating ICP [j]. In the current sink circuit 204 [j + 1], the transistor Tr4 generates a current ICP [j + 1] corresponding to the difference between the current I [j + 1] and the current IREF when the current I [j + 1] is smaller than the current IREF. It has a function. The current ICP [j] and the current ICP [j + 1] are drawn from the wiring BL [j] and the wiring BL [j + 1] to the current sink circuit 204 [j] and the current sink circuit 204 [j + 1].

  Note that the current ICM [j] and the current ICP [j] correspond to Ioffset [j]. Note that the current ICM [j + 1] and the current ICP [j + 1] correspond to Ioffset [j + 1].

  In the current sink circuit 204 [j] and the current sink circuit 204 [j + 1], the transistor Tr4 has one of the source and the drain connected to the corresponding wiring BL, and the other of the source and the drain is supplied with a predetermined potential. Connected to the wiring. In the transistor Tr5, one of the source and the drain is connected to the wiring BL, and the other of the source and the drain is connected to the gate of the transistor Tr4. In the transistor Tr6, one of the source and the drain is connected to the gate of the transistor Tr4, and the other of the source and the drain is connected to a wiring to which a predetermined potential is supplied. In the capacitor C4, the first electrode is connected to the gate of the transistor Tr4, and the second electrode is connected to a wiring to which a predetermined potential is supplied.

  The gate of the transistor Tr5 is connected to the wiring OSP, and the gate of the transistor Tr6 is connected to the wiring ORP.

  Note that FIG. 19 illustrates the case where the transistors Tr4 to Tr6 are n-channel type.

  The current source circuit 205 includes a transistor Tr10 corresponding to the wiring BL and a transistor Tr11 corresponding to the wiring BLREF. Specifically, the current source circuit 205 illustrated in FIG. 19 includes a transistor Tr10 [j] corresponding to the wiring BL [j] and a transistor Tr10 [j + 1] corresponding to the wiring BL [j + 1] as the transistor Tr10. Is illustrated.

  The gate of the transistor Tr10 is connected to the gate of the transistor Tr11. In the transistor Tr10, one of the source and the drain is connected to the corresponding wiring BL, and the other of the source and the drain is connected to a wiring to which a predetermined potential is supplied. In the transistor Tr11, one of a source and a drain is connected to the wiring BLREF, and the other of the source and the drain is connected to a wiring to which a predetermined potential is supplied.

  The transistor Tr10 and the transistor Tr11 have the same polarity. FIG. 19 illustrates a case where both the transistor Tr10 and the transistor Tr11 have a p-channel type.

  The drain current of the transistor Tr11 corresponds to the current IREF. Since the transistor Tr10 and the transistor Tr11 have a function as a current mirror circuit, the drain current of the transistor Tr10 has almost the same value as the drain current of the transistor Tr11 or a value corresponding to the drain current of the transistor Tr11.

  Next, an example of a specific operation of the product-sum operation circuit 200 will be described with reference to FIG.

  20 corresponds to an example of a timing chart illustrating operations of the memory cell MC, the memory cell MCR, the current source circuit 203, the current sink circuit 204, and the current source circuit 205 illustrated in FIG. In FIG. 20, the operation of storing the first analog current in the memory cell MC and the memory cell MCR is performed from time T01 to time T04. From time T05 to time T10, an operation of setting an offset current Ioffset in the current source circuit 203 and the current sink circuit 204 is performed. From time T11 to time T16, an operation of acquiring data corresponding to the product-sum value of the first analog current and the second analog current is performed.

  Note that a low-level potential is supplied to the power supply line VR [j] and the power supply line VR [j + 1]. In addition, all the wirings having a predetermined potential connected to the current source circuit 203 are supplied with the high-level potential VDD. Further, all the wirings having a predetermined potential connected to the current sink circuit 204 are supplied with the low-level potential VSS. In addition, all the wirings having a predetermined potential connected to the current source circuit 205 are supplied with the high-level potential VDD.

  The transistors Tr1, Tr4, Tr7, Tr10 [j], Tr10 [j + 1], and Tr11 are assumed to operate in the saturation region.

  First, from time T01 to time T02, a high-level potential is applied to the wiring WW [i], and a low-level potential is applied to the wiring WW [i + 1]. Through the above operation, the transistor Tr2 is turned on in the memory cell MC [i, j], the memory cell MC [i, j + 1], and the memory cell MCR [i] illustrated in FIG. In addition, the transistor Tr2 is kept off in the memory cell MC [i + 1, j], the memory cell MC [i + 1, j + 1], and the memory cell MCR [i + 1].

  From time T01 to time T02, a potential obtained by subtracting the first analog potential from the first reference potential VPR is supplied to the wiring WD [j] and the wiring WD [j + 1] illustrated in FIG. Specifically, the potential VPR-Vx [i, j] is applied to the wiring WD [j], and the potential VPR-Vx [i, j + 1] is applied to the wiring WD [j + 1]. The wiring WDREF is supplied with the first reference potential VPR, and the wiring RW [i] and the wiring RW [i + 1] have a potential between the potential VSS and the potential VDD as a reference potential, for example, a potential (VDD + VSS) / 2. Given.

  Accordingly, the node N [i, j] of the memory cell MC [i, j] illustrated in FIG. 19 is supplied with the potential VPR−Vx [i, j] through the transistor Tr2, and the memory cell MC [i, j + 1]. Node N [i, j + 1] is supplied with the potential VPR-Vx [i, j + 1] through the transistor Tr2, and the node NREF [i] of the memory cell MCR [i] is supplied with the potential VPR through the transistor Tr2. Given.

  When the time T02 ends, the potential applied to the wiring WW [i] illustrated in FIG. 19 changes from a high level to a low level, and the memory cell MC [i, j], the memory cell MC [i, j + 1], and the memory cell MCR In [i], the transistor Tr2 is turned off. Through the above operation, the node N [i, j] holds the potential VPR−Vx [i, j], the node N [i, j + 1] holds the potential VPR−Vx [i, j + 1], and the node NREF [I] holds the potential VPR.

  Next, from time T03 to time T04, the potential of the wiring WW [i] illustrated in FIG. 19 is maintained at a low level, and a high-level potential is applied to the wiring WW [i + 1]. Through the above operation, the transistor Tr2 is turned on in the memory cell MC [i + 1, j], the memory cell MC [i + 1, j + 1], and the memory cell MCR [i + 1] illustrated in FIG. Further, the transistor Tr2 is kept off in the memory cell MC [i, j], the memory cell MC [i, j + 1], and the memory cell MCR [i].

  From time T03 to time T04, a potential obtained by subtracting the first analog potential from the first reference potential VPR is supplied to the wiring WD [j] and the wiring WD [j + 1] illustrated in FIG. Specifically, the potential VPR−Vx [i + 1, j] is applied to the wiring WD [j], and the potential VPR−Vx [i + 1, j + 1] is applied to the wiring WD [j + 1]. The wiring WDREF is supplied with the first reference potential VPR, and the wiring RW [i] and the wiring RW [i + 1] have a potential between the potential VSS and the potential VDD as a reference potential, for example, a potential (VDD + VSS) / 2. Given.

  Accordingly, the node N [i + 1, j] of the memory cell MC [i + 1, j] illustrated in FIG. 19 is supplied with the potential VPR−Vx [i + 1, j] through the transistor Tr2, and the memory cell MC [i + 1, j + 1]. Node N [i + 1, j + 1] is supplied with the potential VPR-Vx [i + 1, j + 1] via the transistor Tr2, and the node NREF [i + 1] of the memory cell MCR [i + 1] is supplied with the potential VPR via the transistor Tr2. Given.

  When the time T04 ends, the potential applied to the wiring WW [i + 1] illustrated in FIG. 19 changes from a high level to a low level, and the memory cell MC [i + 1, j], the memory cell MC [i + 1, j + 1], and the memory cell MCR. In [i + 1], the transistor Tr2 is turned off. Through the above operation, the node N [i + 1, j] holds the potential VPR−Vx [i + 1, j], the node N [i + 1, j + 1] holds the potential VPR−Vx [i + 1, j + 1], and the node NREF [I + 1] holds the potential VPR.

  Next, at time T05 to time T06, a high-level potential is applied to the wiring ORP and the wiring ORM illustrated in FIG. In the current source circuit 203 [j] and the current source circuit 203 [j + 1] illustrated in FIG. 19, the transistor Tr9 is turned on when a high-level potential is applied to the wiring ORM, and the potential VDD is applied to the gate of the transistor Tr7. To reset. In the current sink circuit 204 [j] and the current sink circuit 204 [j + 1] illustrated in FIG. 19, when a high-level potential is applied to the wiring ORP, the transistor Tr6 is turned on, and the gate of the transistor Tr4 has a potential VSS. Is reset when given.

  When the time T06 ends, the potentials applied to the wiring ORP and the wiring ORM illustrated in FIG. 19 change from a high level to a low level, and the transistor Tr9 is turned off in the current source circuit 203 [j] and the current source circuit 203 [j + 1]. Thus, the transistor Tr6 is turned off in the current sink circuit 204 [j] and the current sink circuit 204 [j + 1]. With the above operation, the potential VDD is held at the gate of the transistor Tr7 in the current source circuit 203 [j] and the current source circuit 203 [j + 1], and the transistor Tr4 in the current sink circuit 204 [j] and the current sink circuit 204 [j + 1]. The potential VSS is held at the gate.

  Next, at time T07 to time T08, a high-level potential is applied to the wiring OSP illustrated in FIG. In addition, a potential between the potential VSS and the potential VDD, for example, a potential (VDD + VSS) / 2 is supplied as a reference potential to the wiring RW [i] and the wiring RW [i + 1] illustrated in FIG. When the high-level potential is applied to the wiring OSP, the transistor Tr5 is turned on in the current sink circuit 204 [j] and the current sink circuit 204 [j + 1].

  When I [j] flowing through the wiring BL [j] is smaller than the current IREF flowing through the wiring BLREF, that is, when ΔI [j] is positive, the transistor Tr1 of the memory cell MC [i, j] illustrated in FIG. This means that the sum of the current that can be drawn and the current that can be drawn by the transistor Tr1 of the memory cell MC [i + 1, j] is smaller than the drain current of the transistor Tr10 [j]. Therefore, when the current ΔI [j] is positive and the transistor Tr5 is turned on in the current sink circuit 204 [j], part of the drain current of the transistor Tr10 [j] flows into the gate of the transistor Tr4, and the potential of the gate Begins to rise. When the drain current of the transistor Tr4 becomes substantially equal to the current ΔI [j], the potential of the gate of the transistor Tr4 converges to a predetermined value. At this time, the gate potential of the transistor Tr4 corresponds to a potential at which the drain current of the transistor Tr4 becomes the current ΔI [j], that is, Ioffset [j] (= ICP [j]). That is, it can be said that the transistor Tr4 of the current sink circuit 204 [j] is set to a current source that can flow the current ICP [j].

  Similarly, when I [j + 1] flowing through the wiring BL [j + 1] is smaller than the current IREF flowing through the wiring BLREF, that is, when the current ΔI [j + 1] is positive, the transistor Tr5 is turned on in the current sink circuit 204 [j + 1]. Then, part of the drain current of the transistor Tr10 [j + 1] flows into the gate of the transistor Tr4, and the potential of the gate starts to rise. When the drain current of the transistor Tr4 becomes substantially equal to the current ΔI [j + 1], the gate potential of the transistor Tr4 converges to a predetermined value. The potential of the gate of the transistor Tr4 at this time corresponds to a potential at which the drain current of the transistor Tr4 becomes the current ΔI [j + 1], that is, Ioffset [j + 1] (= ICP [j + 1]). That is, it can be said that the transistor Tr4 of the current sink circuit 204 [j + 1] is set to a current source that can flow the current ICP [j + 1].

  When the time T08 ends, the potential applied to the wiring OSP illustrated in FIG. 19 changes from a high level to a low level, and the transistor Tr5 is turned off in the current sink circuit 204 [j] and the current sink circuit 204 [j + 1]. With the above operation, the potential of the gate of the transistor Tr4 is maintained. Therefore, the current sink circuit 204 [j] maintains the state set as a current source capable of flowing the current ICP [j], and the current sink circuit 204 [j + 1] is set as the current source capable of flowing the current ICP [j + 1]. Maintain the state.

  Next, at time T09 to time T10, a high-level potential is applied to the wiring OSM illustrated in FIG. In addition, a potential between the potential VSS and the potential VDD, for example, a potential (VDD + VSS) / 2 is supplied as a reference potential to the wiring RW [i] and the wiring RW [i + 1] illustrated in FIG. When the high-level potential is applied to the wiring OSM, the transistor Tr8 is turned on in the current source circuit 203 [j] and the current source circuit 203 [j + 1].

  When I [j] flowing through the wiring BL [j] is larger than the current IREF flowing through the wiring BLREF, that is, when ΔI [j] is negative, the transistor Tr1 of the memory cell MC [i, j] illustrated in FIG. This means that the sum of the current that can be drawn and the current that can be drawn by the transistor Tr1 of the memory cell MC [i + 1, j] is larger than the drain current of the transistor Tr10 [j]. Therefore, when the current ΔI [j] is negative and the transistor Tr8 is turned on in the current source circuit 203 [j], current flows from the gate of the transistor Tr7 to the wiring BL [j], and the potential of the gate starts to decrease. . When the drain current of the transistor Tr7 becomes substantially equal to the current ΔI [j], the potential of the gate of the transistor Tr7 converges to a predetermined value. At this time, the gate potential of the transistor Tr7 corresponds to a potential at which the drain current of the transistor Tr7 becomes a current ΔI [j], that is, Ioffset [j] (= ICM [j]). That is, it can be said that the transistor Tr7 of the current source circuit 203 [j] is set to a current source that can flow the current ICM [j].

  Similarly, when I [j + 1] flowing through the wiring BL [j + 1] is larger than the current IREF flowing through the wiring BLREF, that is, when the current ΔI [j + 1] is negative, the transistor Tr8 is turned on in the current source circuit 203 [j + 1]. Then, current flows from the gate of the transistor Tr7 to the wiring BL [j + 1], and the potential of the gate starts to drop. When the drain current of the transistor Tr7 becomes substantially equal to the absolute value of the current ΔI [j + 1], the potential of the gate of the transistor Tr7 converges to a predetermined value. The potential of the gate of the transistor Tr7 at this time corresponds to a potential at which the drain current of the transistor Tr7 is equal to the current ΔI [j + 1], that is, the absolute value of Ioffset [j + 1] (= ICM [j + 1]). That is, it can be said that the transistor Tr7 of the current source circuit 203 [j + 1] is set to a current source that can flow the current ICM [j + 1].

  When the time T08 ends, the potential applied to the wiring OSM illustrated in FIG. 19 changes from a high level to a low level, and the transistor Tr8 is turned off in the current source circuit 203 [j] and the current source circuit 203 [j + 1]. With the above operation, the potential of the gate of the transistor Tr7 is maintained. Therefore, the current source circuit 203 [j] maintains the state set as a current source that can flow the current ICM [j], and the current source circuit 203 [j + 1] is set as a current source that can flow the current ICM [j + 1]. Maintain the state.

  Note that in the current sink circuit 204 [j] and the current sink circuit 204 [j + 1], the transistor Tr4 has a function of drawing current. Therefore, when the current I [j] flowing through the wiring BL [j] is larger than the current IREF flowing through the wiring BLREF from time T07 to time T08 and ΔI [j] is negative, or the current I flowing through the wiring BL [j + 1] When [j + 1] is larger than the current IREF flowing through the wiring BLREF and ΔI [j + 1] is negative, the current BL [j] or the wiring BL [] is not excessively shorted from the current sink circuit 204 [j] or the current sink circuit 204 [j + 1]. It may be difficult to supply current to j + 1]. In this case, in order to balance the current flowing through the wiring BL [j] or the wiring BL [j + 1] with the current flowing through the wiring BLREF, the transistor Tr1 of the memory cell MC and the current sink circuit 204 [j] or the current sink It may be difficult for the transistor Tr4 of the circuit 204 [j + 1] and the transistor Tr10 [j] or Tr10 [j + 1] to operate in the saturation region.

  Even in the case where ΔI [j] is negative from time T07 to time T08, in order to ensure the operation in the saturation region of the transistor Tr1, Tr4, Tr10 [j], or Tr10 [j + 1], the transistor from time T05 to time T06 Instead of resetting the gate of Tr7 to the potential VDD, the gate potential of the transistor Tr7 may be set to such a level that a predetermined drain current can be obtained. With the above structure, since current is supplied from the transistor Tr7 in addition to the drain current of the transistor Tr10 [j] or Tr10 [j + 1], a current that cannot be drawn in the transistor Tr1 can be drawn to some extent in the transistor Tr4. The operation in the saturation region of the transistors Tr1, Tr4, Tr10 [j] or Tr10 [j + 1] can be ensured.

  Note that at time T09 to time T10, when I [j] flowing through the wiring BL [j] is smaller than the current IREF flowing through the wiring BLREF, that is, when ΔI [j] is positive, current sinking is performed from time T07 to time T08. Since the circuit 204 [j] is already set as a current source capable of flowing the current ICP [j], the potential of the gate of the transistor Tr7 remains substantially at the potential VDD in the current source circuit 203 [j]. Similarly, when I [j + 1] flowing through the wiring BL [j + 1] is smaller than the current IREF flowing through the wiring BLREF, that is, when ΔI [j + 1] is positive, the current sink circuit 204 [j + 1] is switched from time T07 to time T08. Since the current source is already set to a current source through which the current ICP [j + 1] can flow, the potential of the gate of the transistor Tr7 remains substantially the potential VDD in the current source circuit 203 [j + 1].

  Next, at time T11 to time T12, the second analog potential Vw [i] is applied to the wiring RW [i] illustrated in FIG. The wiring RW [i + 1] is still supplied with a potential between the potential VSS and the potential VDD, for example, the potential (VDD + VSS) / 2 as the reference potential. Specifically, the potential of the wiring RW [i] is higher by a potential difference Vw [i] than the potential between the potential VSS and the potential VDD, for example, the potential (VDD + VSS) / 2. For easy understanding, it is assumed that the potential of the wiring RW [i] is the potential Vw [i].

  When it is assumed that when the wiring RW [i] becomes the potential Vw [i], the amount of change in the potential of the first electrode of the capacitor C1 is substantially reflected in the amount of change in the potential of the node N, the memory illustrated in FIG. The potential of the node N in the cell MC [i, j] is VPR−Vx [i, j] + Vw [i], and the potential of the node N in the memory cell MC [i, j + 1] is VPR−Vx [i, j + 1] + Vw. [I]. From the above equation 6, the product sum of the first analog current and the second analog current corresponding to the memory cell MC [i, j] is the current obtained by subtracting Ioffset [j] from the current ΔI [j]. In other words, it is reflected in the current Iout [j] flowing out from the wiring BL [j]. The product sum of the first analog current and the second analog current corresponding to the memory cell MC [i, j + 1] is a current obtained by subtracting Ioffset [j + 1] from the current ΔI [j + 1], that is, the wiring BL [ It can be seen that the current Iout [j + 1] flowing out from j + 1] is reflected.

  When the time T12 ends, the wiring RW [i] is again supplied with a potential between the potential VSS and the potential VDD which is the reference potential, for example, the potential (VDD + VSS) / 2.

  Next, at time T13 to time T14, the second analog potential Vw [i + 1] is supplied to the wiring RW [i + 1] illustrated in FIG. The wiring RW [i] is still supplied with a potential between the potential VSS and the potential VDD, for example, the potential (VDD + VSS) / 2 as the reference potential. Specifically, the potential of the wiring RW [i + 1] is higher by a potential difference Vw [i + 1] than the potential between the reference potential VSS and the potential VDD, for example, the potential (VDD + VSS) / 2. For ease of explanation, it is assumed that the potential of the wiring RW [i + 1] is the potential Vw [i + 1].

  When it is assumed that when the wiring RW [i + 1] becomes the potential Vw [i + 1], the amount of change in the potential of the first electrode of the capacitor C1 is almost reflected in the amount of change in the potential of the node N. The potential of the node N in the cell MC [i + 1, j] is VPR−Vx [i + 1, j] + Vw [i + 1], and the potential of the node N in the memory cell MC [i + 1, j + 1] is VPR−Vx [i + 1, j + 1] + Vw. [I + 1]. From Equation 6 above, the first and second product-sum values corresponding to the memory cell MC [i + 1, j] are the current obtained by subtracting Ioffset [j] from the current ΔI [j], that is, Iout [j ] Is reflected in the The product sum of the first analog current and the second analog current corresponding to the memory cell MC [i + 1, j + 1] is a current obtained by subtracting Ioffset [j + 1] from the current ΔI [j + 1], that is, Iout [j + 1]. ] Is reflected in the

  When the time T12 ends, the wiring RW [i + 1] is again supplied with a potential between the potential VSS which is the reference potential and the potential VDD, for example, the potential (VDD + VSS) / 2.

  Next, at time T15 to time T16, the second analog potential Vw [i] is supplied to the wiring RW [i] illustrated in FIG. 19, and the second analog potential Vw [i + 1] is supplied to the wiring RW [i + 1]. . Specifically, the potential of the wiring RW [i] is higher by a potential difference Vw [i] than a potential between the reference potential VSS and the potential VDD, for example, the potential (VDD + VSS) / 2, and the wiring RW [i] The potential of (i + 1) is higher than the potential between the potential VSS and the potential VDD, for example, the potential (VDD + VSS) / 2 by a potential difference Vw [i + 1]. Further, it is assumed that the potential of the wiring RW [i] is the potential Vw [i] and the potential of the wiring RW [i + 1] is the potential Vw [i + 1].

  When it is assumed that when the wiring RW [i] becomes the potential Vw [i], the amount of change in the potential of the first electrode of the capacitor C1 is substantially reflected in the amount of change in the potential of the node N, the memory illustrated in FIG. The potential of the node N in the cell MC [i, j] is VPR−Vx [i, j] + Vw [i], and the potential of the node N in the memory cell MC [i, j + 1] is VPR−Vx [i, j + 1] + Vw. [I]. Further, when it is assumed that when the wiring RW [i + 1] becomes the potential Vw [i + 1], the amount of change in the potential of the first electrode of the capacitor C1 is substantially reflected in the amount of change in the potential of the node N in FIG. The potential of the node N in the memory cell MC [i + 1, j] shown is VPR−Vx [i + 1, j] + Vw [i + 1], and the potential of the node N in the memory cell MC [i + 1, j + 1] is VPR−Vx [i + 1, j + 1. ] + Vw [i + 1].

  From Equation 6 above, the first and second product sum values corresponding to the memory cell MC [i, j] and the memory cell MC [i + 1, j] are obtained from the current ΔI [j] to Ioffset [j]. It can be seen that the current is subtracted from the current Iout [j]. The first and second product sum values corresponding to the memory cell MC [i, j + 1] and the memory cell MC [i + 1, j + 1] are currents obtained by subtracting Ioffset [j + 1] from the current ΔI [j + 1], that is, It can be seen that the current Iout [j + 1] is reflected.

  When the time T16 ends, the wiring RW [i] and the wiring RW [i + 1] are again supplied with a potential between the potential VSS and the potential VDD, for example, the potential (VDD + VSS) / 2.

  With the above configuration, the product-sum operation can be performed with a small circuit scale. In addition, with the above configuration, the product-sum operation can be performed at high speed. In addition, with the above configuration, the product-sum operation can be performed with low power consumption.

  Note that the circuit configuration of the product-sum operation circuit described with reference to FIGS. 18 to 20 is merely an example, and any configuration can be employed as long as one embodiment of the present invention can be realized.

  Note that as the transistor Tr2, Tr5, Tr6, Tr8, or Tr9, a transistor with extremely low off-state current is preferably used. By using a transistor with extremely low off-state current as the transistor Tr2, the potential of the node N can be held for a long time. Further, by using transistors with extremely low off-state current for the transistors Tr5 and Tr6, the potential of the gate of the transistor Tr4 can be held for a long time. Further, by using transistors with extremely low off-state current for the transistors Tr8 and Tr9, the potential of the gate of the transistor Tr7 can be held for a long time.

In order to reduce the off-state current of the transistor, for example, the channel formation region may be formed using a semiconductor with a wide energy gap. The energy gap of the semiconductor is preferably 2.5 eV or more, 2.7 eV or more, or 3 eV or more. As such a semiconductor material, an oxide semiconductor can be given. A transistor including an oxide semiconductor in a channel formation region may be used as the transistors Tr2, Tr5, Tr6, Tr8, or Tr9. The leakage current of the OS transistor normalized by the channel width can be 10 × 10 ⁻²¹ A / μm (10 zept A / μm) or less when the source drain voltage is 10 V and room temperature (about 25 ° C.). is there. The leakage current of the OS transistor applied to the switches SW2 and SW3 is 1 × 10 ⁻¹⁸ A or less, 1 × 10 ⁻²¹ A or less, or 1 × 10 ⁻²⁴ A or less at room temperature (about 25 ° C.). preferable. Alternatively, the leakage current is preferably 1 × 10 ⁻¹⁵ A or less, or 1 × 10 ⁻¹⁸ A or less, or 1 × 10 ⁻²¹ A or less at 85 ° C.

  An oxide semiconductor is a semiconductor with a large energy gap, difficulty in excitation of electrons, and a large effective mass of holes. For this reason, a transistor including an oxide semiconductor in a channel formation region may hardly undergo avalanche collapse or the like as compared with a general transistor using silicon or the like. By suppressing hot carrier deterioration caused by avalanche collapse, a transistor including an oxide semiconductor in a channel formation region has a high drain breakdown voltage, and can be driven with a high drain voltage.

  The oxide semiconductor included in the channel formation region of the transistor is preferably an oxide semiconductor including at least one of indium (In) and zinc (Zn). As such an oxide semiconductor, an In oxide, a Zn oxide, an In—Zn oxide, an In—M—Zn oxide (the element M includes Ga, Al, Ti, Y, Zr, La, Ce, and Nd). Or Hf) is typical. These oxide semiconductors reduce an impurity such as hydrogen that serves as an electron donor (donor) and reduce oxygen vacancies to make the oxide semiconductor an i-type semiconductor (intrinsic semiconductor), or to an i-type semiconductor. It can be as close as possible. Such an oxide semiconductor can be referred to as a highly purified oxide semiconductor.

The channel formation region is preferably formed using an oxide semiconductor with low carrier density. For example, the carrier density of the oxide semiconductor is preferably less than 8 × 10 ¹¹ / cm ^{3 and} 1 × 10 ⁻⁹ / cm ³ or more. The carrier density is preferably less than 1 × 10 ¹¹ / cm ^{3, and} more preferably less than 1 × 10 ¹⁰ / cm ³ .

<Configuration example of artificial neural network>
The product-sum operation circuit described above can be used as a feature extraction filter for convolution operation or a fully-coupled operation circuit to extract feature amounts using a CNN (Convolutional Neural Network). Specifically, by using the product-sum operation circuit described above for a hierarchical neural network, parameters used for image data correction can be determined by machine learning.

  FIG. 21 is a diagram illustrating an example of a hierarchical neural network. The (k−1) -th layer (k is an integer of 2 or more) has P neurons (P is an integer of 1 or more), and the k-th layer has Q neurons (Q is The (k + 1) th layer has R neurons (R is an integer of 1 or more).

The product of the output signal z _p ^(k−1) and the weight coefficient w _qp ^(k) of the p-th neuron of the (k−1) -th layer (p is an integer of 1 or more and P or less) is the k-th layer. The q-th neuron (q is an integer between 1 and Q), and the output signal z _q ^(k) of the ^k- th neuron in the k-th layer and the weight coefficient w _rq ^{(k + 1)} Assume that the product is input to the r-th neuron in the (k + 1) -th layer (r is an integer of 1 to R), and the output signal of the r-th neuron in the (k + 1) -th layer is expressed as z _r ^{(k + 1)} To do.

  At this time, the total sum of signals input to the k-th neuron in the k-th layer is expressed by the following equation (D1).

The output signal z _q ^(k) from the q-th neuron in the k-th layer is defined by the following equation (D2).

The function f (u _q ^(k) ) is a neuron output function, and a step function, a linear ramp function, a sigmoid function, or the like can be used. The product-sum operation of equation (D1) can be realized by the product-sum operation circuit described above. Note that the calculation of Expression (D2) can be realized by a circuit 411 illustrated in FIG.

  Note that the output function of the neurons may be the same or different in all the neurons. In addition, the output function of the neuron may be the same or different for each layer.

  Here, a hierarchical neural network including all L layers shown in FIG. 22 is considered (that is, k here is an integer of 2 or more and (L−1) or less). The first layer is an input layer of the hierarchical neural network, the Lth layer is an output layer of the hierarchical neural network, and the second to (L-1) th layers are hidden layers.

  The first layer (input layer) has P neurons, and the kth layer (hidden layer) has Q [k] neurons (Q [k] is an integer equal to or greater than 1). The L layer (output layer) has R neurons.

The output signal of the s [1] neuron in the first layer (s [1] is an integer between 1 and P) is z _{s [1]} ^(1), and the s [k] neuron in the kth layer. The output signal (s [k] is an integer between 1 and Q [k]) is z _{s [k]} ^(k), and the s [L] neuron (s [L] is 1 in the Lth layer. The output signal is an integer less than or equal to R.) z _{s [L]} ^(L) .

The output signal z _{s [k−1} ] of the s [k−1] th neuron (s [k−1] is an integer of 1 to Q [k−1]) in the (k−1) th layer. _] Product _{k s [k]} ^{(k )} and weight coefficient w _{s [k] s [k−1]} ^(k) are input to the s [k] neuron in the k-th layer. It is assumed that the output signal z _{s [L−} ] of the s [L−1] neuron (s [L−1] is an integer of 1 to Q [L−1]) in the (L−1) th layer. _1] ^(L−1) and the weight coefficient w _{s [L] s [L−1]} ^(L) and the product u _{s [L]} ^(L) are input to the s [L] neuron in the Lth layer. Shall be.

  Next, supervised learning will be described. Supervised learning means that when the output result differs from the desired result (sometimes referred to as teacher data or teacher signal) in the function of the above-described hierarchical neural network, An operation for updating the weighting coefficient based on the output result and the desired result.

  As a specific example of supervised learning, a learning method using a back propagation error method will be described. FIG. 23 is a diagram for explaining a learning method using the back propagation error method. The back propagation error method is a method of changing the weighting coefficient so that the error between the output of the hierarchical neural network and the teacher data becomes small.

For example, assume that input data is input to the s [1] neuron in the first layer, and output data z _{s [L]} ^(L) is output from the s [L] neuron in the Lth layer. Here, when the teacher signal for the output data z _{s [L]} ^(L) is t _{s [L]} , the error energy E is determined by the output data z _{s [L]} ^(L) and the teacher signal t _{s [L]} . Can be represented.

For the error energy E, the update amount of the weight coefficient w _{s [k] s [k−1]} ^(k) of the s [k] neuron in the k-th layer is expressed as ∂E / ∂w _{s [k] s [k −1] By} setting ^(k) , the weighting factor can be newly changed. Here, if the error δ _{s [k]} ^(k) of the output value z _{s [k]} ^(k) of the s [k] neuron in the k-th layer is defined as ∂E / ∂u _{s [k]} ^(k) , Δ _{s [k]} ^(k) and ∂E / ∂w _{s [k] s [k−1]} ^(k) can be expressed by the following equations (D3) and (D4), respectively.

f ′ (u _{s [k]} ^(k) ) is a derivative of the output function of the neuron circuit. Note that the calculation of Expression (D3) can be realized by a circuit 413 illustrated in FIG. Moreover, the calculation of Formula (D4) is realizable by the circuit 414 shown in FIG.24 (C), for example. The derivative of the output function can be realized, for example, by connecting an arithmetic circuit corresponding to a desired derivative to the output terminal of the operational amplifier.

Further, for example, the calculation of the part of Σw _{s [k + 1] · s [k]} ^{(k + 1)} · δ _{s [k + 1]} ^{(k + 1) in} the equation (D3) can be realized by the product-sum operation circuit described above.

Here, when the (k + 1) th layer is the output layer, that is, when the (k + 1) th layer is the Lth layer, δ _{s [L]} ^(L) and ∂E / ∂w _{s [L] s [L -1]} ^(L) can be represented by the following formulas (D5) and (D6), respectively.

  The calculation of Expression (D5) can be realized by a circuit 415 illustrated in FIG. Further, the calculation of the equation (D6) can be realized by a circuit 414 illustrated in FIG.

That is, the errors δ _{s [k]} ^(k) and δ _{s [L]} ^(L) of all the neuron circuits can be obtained from the equations (D1) to (D6). The update of the weighting coefficient is set based on the errors δ _{s [k]} ^(k) , δ _{s [L]} ^(L), desired parameters, and the like.

  As described above, the hierarchical neural network to which supervised learning is applied can be calculated by using the circuit shown in FIG. 24 and the product-sum operation circuit described above.

Specifically, in the circuits shown in FIGS. 18 and 19, the first analog data is used as a weighting factor, and a plurality of second analog data is associated with the neuron output, so that the weighted sum operation of each neuron output is performed in parallel. The data corresponding to the result of the weighting calculation, that is, the synaptic input can be acquired as the output signal. Specifically, the weight coefficients w _{s [k] · 1} ^{(k) to} w _s of the s [k] neuron in the k-th layer are assigned to the memory cells AM [1, j] to AM [m, j]. _{[K] · Q [k−1]} ^(k) is stored as the first analog data, and the output signal z ₁ of each neuron of the (k−1) th layer is respectively connected to the wiring RW [1] to the wiring RW [m]. _By supplying _{s [k]} ^{(k-1) to} zQ _{[k-1] .s [k]} ^(k-1) as the second analog data, the s [k] neuron in the kth layer is supplied. The sum total u _{s [k]} ^(k) of the input signals can be calculated. That is, the product-sum operation shown in Expression (D1) can be realized by the product-sum operation circuit.

Further, when updating the weighting coefficient by supervised learning, the memory cell AM [1, j] to memory cell AM [m, j] are transferred from the kth layer s [k] neuron to the (k + 1) th layer. The weighting factors w _{1 · s [k]} ^{(k + 1) to} w _{Q [k + 1] s [k]} ^{(k + 1)} applied when signals are sent to the respective neurons are stored as first analog data, and wirings RW [1] to RW [1] to When the errors δ ₁ ^{(k + 1) to} δ _{Q [k + 1]} ^{(k + 1)} of each neuron of the ^{(k + 1)} -th layer are supplied as the second analog data to the wiring RW [m], Σw _{s [k + 1] · The value of s [k]} ^{(k + 1)} · δ _{s [k + 1]} ^{(k + 1)} can be obtained from the differential current ΔI _B [j] flowing in the wiring B [j]. That is, a part of the calculation shown in Expression (D3) can be realized by the product-sum calculation circuit.

(Additional notes regarding the description of this specification etc.)
The above embodiment and description of each component in the embodiment will be added below.

  The structure described in each embodiment can be combined with the structure described in any of the other embodiments as appropriate, for one embodiment of the present invention. In addition, in the case where a plurality of structure examples are given in one embodiment, any of the structure examples can be combined as appropriate.

  Note that the content described in one embodiment (may be a part of content) is different from the content described in the embodiment (may be a part of content) and / or one or more Application, combination, replacement, or the like can be performed on the content described in another embodiment (or part of the content).

  Note that the contents described in the embodiments are the contents described using various drawings or the contents described in the specification in each embodiment.

  Note that a drawing (or a part thereof) described in one embodiment may be another part of the drawing, another drawing (may be a part) described in the embodiment, and / or one or more. More diagrams can be formed by combining the diagrams (may be a part) described in another embodiment.

  Further, in the present specification and the like, in the block diagram, the constituent elements are classified by function and shown as independent blocks. However, in an actual circuit or the like, it is difficult to separate the components for each function, and there may be a case where a plurality of functions are involved in one circuit or a case where one function is involved over a plurality of circuits. Therefore, the blocks in the block diagram are not limited to the components described in the specification, and can be appropriately rephrased depending on the situation.

  In the drawings, the size, the layer thickness, or the region is shown in an arbitrary size for convenience of explanation. Therefore, it is not necessarily limited to the scale. Note that the drawings are schematically shown for the sake of clarity, and are not limited to the shapes or values shown in the drawings. For example, variation in signal, voltage, or current due to noise, variation in signal, voltage, or current due to timing shift can be included.

  In this specification and the like, when describing a connection relation of a transistor, one of a source and a drain is referred to as “one of a source and a drain” (or a first electrode or a first terminal), and the source and the drain The other is referred to as “the other of the source and the drain” (or the second electrode or the second terminal). This is because the source and drain of a transistor vary depending on the structure or operating conditions of the transistor. Note that the names of the source and the drain of the transistor can be appropriately rephrased depending on the situation, such as a source (drain) terminal or a source (drain) electrode.

  Further, in this specification and the like, the terms “electrode” and “wiring” do not functionally limit these components. For example, an “electrode” may be used as part of a “wiring” and vice versa. Furthermore, the terms “electrode” and “wiring” include a case where a plurality of “electrodes” and “wirings” are integrally formed.

  In this specification and the like, voltage and potential can be described as appropriate. The voltage is a potential difference from a reference potential. For example, when the reference potential is a ground voltage (ground voltage), the voltage can be rephrased as a potential. The ground potential does not necessarily mean 0V. Note that the potential is relative, and the potential applied to the wiring or the like may be changed depending on the reference potential.

  Note that in this specification and the like, terms such as “film” and “layer” can be interchanged with each other depending on the case or circumstances. For example, the term “conductive layer” may be changed to the term “conductive film”. Alternatively, for example, the term “insulating film” may be changed to the term “insulating layer” in some cases.

  In this specification and the like, a switch refers to a switch that is in a conductive state (on state) or a non-conductive state (off state) and has a function of controlling whether or not to pass current. Alternatively, the switch refers to a switch having a function of selecting and switching a current flow path.

  As an example, an electrical switch or a mechanical switch can be used. That is, the switch is not limited to a specific one as long as it can control the current.

  Examples of electrical switches include transistors (for example, bipolar transistors, MOS transistors, etc.), diodes (for example, PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes. , Diode-connected transistors, etc.), or a logic circuit combining these.

  Note that in the case where a transistor is used as the switch, the “conducting state” of the transistor means a state where the source and the drain of the transistor can be regarded as being electrically short-circuited. In addition, the “non-conducting state” of a transistor refers to a state where the source and drain of the transistor can be regarded as being electrically cut off. Note that when a transistor is operated as a simple switch, the polarity (conductivity type) of the transistor is not particularly limited.

  An example of a mechanical switch is a switch using MEMS (micro electro mechanical system) technology, such as a digital micromirror device (DMD). The switch has an electrode that can be moved mechanically, and operates by controlling conduction and non-conduction by moving the electrode.

  In this specification and the like, the channel length means, for example, in a top view of a transistor, a region where a semiconductor (or a portion where a current flows in the semiconductor when the transistor is on) and a gate overlap, or a channel is formed. This is the distance between the source and drain in the region.

  In this specification and the like, the channel width refers to, for example, a source in a region where a semiconductor (or a portion where a current flows in the semiconductor when the transistor is on) and a gate electrode overlap, or a region where a channel is formed And the length of the part where the drain faces.

  In this specification and the like, “A and B are connected” includes not only those in which A and B are directly connected but also those that are electrically connected. Here, A and B are electrically connected. When there is an object having some electrical action between A and B, it is possible to send and receive electrical signals between A and B. It says that.

B2 terminal C1 capacitor element C3 capacitor element C4 capacitor element C6 capacitor element C45 capacitor element C61 capacitor element C62 capacitor element CB6 capacitor element CLK1 clock signal CLK2 clock signal M1 transistor M2 transistor M7 transistor MB7 transistor MN61 transistor MN62 transistor MO1 transistor MO2 transistor MO5 transistor MO6 transistor MO45 OS transistor MO61 OS transistor MO62 OS transistor MOB5 transistor MOB6 transistor MP61 transistor MP62 transistor MP63 transistor N1 node N2 node N6 node N7 node NB6 node NB7 node SW2 switch T01 time T02 time T03 time T04 time T05 time T06 time T07 Time T08 Time T09 Time T10 Time T11 Time T12 Time T13 Time T14 Time T15 Time T16 Time Tr1 Transistor Tr2 Transistor Tr4 Transistor Tr5 Transistor Tr6 Transistor Tr7 Transistor Tr8 Transistor Tr9 Transistor Tr10 Transistor Tr11 Transistor 10 Neural Network System 11 Integrated Circuit 11_A 11_B integrated circuit 12 DOSRAM
13 NOSRAM
20 Programmable Logic Device 21 Programmable Area 21A Programmable Area 21D Programmable Area 22 Input / Output Block 23 Core 30 Memory Unit 31 NOSRAM
32 DOSRAM
40 arithmetic unit 41 processor 42 analog arithmetic circuit 50 controller 60 controller 70 giant neural network system 61 MN
62 MN
63 MN
71 Arrow 72 Arrow 74 Arrow 75 Arrow 88 Inverter circuit 89 Inverter circuit 100 OS-FPGA
101A circuit block 101D circuit block 110 controller 111 programmable area 112 word driver 113 data driver 117 IOB
118 Core 120 LAB
121 PLE
123 LUT block 124 Register block 125 Selector 126 CM
127 Power switch 128 CM
130 SAB
131 SB
133 PRS
135 CM
137 NVM
140 OS-FF
141 FF
142 shadow register 143 NVM
143B NVM
161 memory cell 200 sum-of-products operation circuit 201 analog memory 202 reference analog memory 203 current source circuit 204 current sink circuit 205 current source circuit 206 driver 207 driver 208 circuit 411 circuit 413 circuit 414 circuit 415 circuit 1400 DOSRAM
1405 Controller 1410 Row circuit 1411 Decoder 1412 Word line driver 1413 Column selector 1414 Sense amplifier driver 1415 Column circuit 1416 Global sense amplifier array 1417 Input / output circuit 1420 MC-SA array 1422 Memory cell array 1423 Sense amplifier array 1425 Local memory cell array 1426 Local sense amplifier Array 1444 Switch array 1445 Memory cell 1446 Sense amplifier 1447 Global sense amplifier 1600 NOSRAM
1610 memory cell array 1611 memory cell 1611-1614 memory cell 1612 memory cell 1613 memory cell 1614 memory cell 1640 controller 1650 row driver 1651 row decoder 1652 word line driver 1660 column driver 1661 column decoder 1662 driver 1663 DAC
1670 output driver 1671 selector 1672 ADC
1673 Output buffer 2000 CDMA
7000 Neural Network System IC
7001 Lead 7003 Circuit part 7031 Si transistor layer 7032 Wiring layer 7033 OS transistor layer

Claims (5)

A neural network system for processing input data using a first integrated circuit and a second integrated circuit,
The first integrated circuit includes a first programmable logic device, a first arithmetic unit, and a first memory unit,
The second integrated circuit includes a second programmable logic device, a second arithmetic unit, and a second memory unit,
The first arithmetic unit, the second arithmetic unit, the first memory unit, and the second memory unit each include a first transistor,
The first transistor has an oxide semiconductor in a channel formation region,
The first programmable logic device is electrically connected to the second programmable logic device;
The neural network system, wherein the first programmable logic device and the second programmable logic have a function of executing inference in a neural network by switching configurations. In claim 1,
The first arithmetic unit or the second arithmetic unit has a function of executing learning in a neural network. In claim 2,
The neural network system, wherein the first memory unit or the second memory unit has a function of holding a weighting coefficient obtained by the learning. In claim 3,
The first programmable logic device or the second programmable logic device updates configuration data including information on the weighting coefficient held in the first memory unit or the second memory unit. Characteristic neural network system. In any one of Claims 1 thru | or 4,
The first arithmetic unit, the second arithmetic unit, the first memory unit, and the second memory unit include a second transistor,
The second transistor includes silicon in a channel formation region,
The neural network system, wherein the layer provided with the first transistor is disposed so as to overlap the layer provided with the second transistor.

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