JP2018132981A - Information processing apparatus having accelerator and information processing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate the need to determine an offload function in consideration of the scale of a hardware accelerator, and to efficiently determine an offload function. An information processing apparatus 1 has a source program conversion means 4 that converts an application source program into a program for a processor and generates a program for a hardware accelerator from an instructed offloadable program in the source program. , The application based on the execution status monitoring means 5 for monitoring the execution status of the program, the accelerator determination means 6 for determining the margin capacity of the hardware accelerator, and the monitoring result of the execution status monitoring means and the determination result of the accelerator determination means. The program is provided with an offload determining means 7 for determining a program to be offloaded to the hardware accelerator during execution of the program. [Selection diagram] FIG. 7

Description

  The present invention relates to an information processing apparatus and an information processing method using a hardware accelerator.

  In areas where high performance computing (HPC) is required, such as data centers, a processor (hereinafter referred to as a CPU: Central Processing Unit) and a hardware accelerator are combined to achieve high performance and low power consumption of computers. Technology is adopted. In the fields of big data analysis and image processing, high-speed data processing is realized by combining a CPU and a GPU (Graphics Processing Unit).

  An FPGA (Field Programmable Gate Array) is a device that can implement an arbitrary logical function. The functions of the FPGA can be updated even after shipment of a product in which the FPGA is mounted. Taking advantage of such features, an FPGA may be used as a hardware accelerator (see, for example, Patent Document 1).

  In a system including a CPU and an FPGA as a hardware accelerator, the FPGA performs, for example, a specific process that increases the load on the CPU instead of the CPU. The shoulder of processing is called off-road. When a process that increases the load can be assumed in advance, for example, as described in Patent Document 1, an FPGA function for executing a specific process is selected in consideration of the scale (capacity) of the FPGA. Is done.

  As an example, an application program is executed as a test outside a system including a CPU and an FPGA, and a specific process to be offloaded is selected based on the execution result. Then, a program for the selected specific processing FPGA is created and loaded into the FPGA. Thereafter, the application program is actually executed in a system including the CPU and the FPGA.

  Patent Documents 2 and 3 describe that an FPGA is dynamically reconfigured according to the processing content and data processing amount of data input to a system including a CPU and an FPGA.

JP 2003-241975 A JP 2007-183726 A JP 2013-171435 A

  The device described in Patent Document 2 is configured to allocate a software module (function executed by a CPU) that is frequently used to a hardware module (function executed by an FPGA) (Patent Document). 2 paragraphs 0019 and 0020). As described above, in the method in which a specific process to be offloaded is selected in advance, a process for selecting a specific process (for example, execution of a test program) is required. A system including an FPGA has an advantage that an offload target can be easily determined. However, in the apparatus described in Patent Document 2, such an effect is not considered. The device described in Patent Document 2 performs dynamic hardware module allocation, but hardware module allocation is performed based only on the frequency of use of the module.

  In the device described in Patent Document 3, a function realized by a CPU is a software (SW) function, and a function realized by an FPGA is a hardware (HW) function. Then, the resource manager manages information on the usage status of SW resources and HW resources and information on processing contents. That is, the resource manager can grasp how much software resources are used. Moreover, the resource manager can grasp how much hardware resources are used. Therefore, it is said that efficient function assignment can be performed for processing functions necessary for executing an application (see paragraph 0026 of Patent Document 3).

  However, even the apparatus described in Patent Document 3 does not take into account the effect of executing a process for selecting a specific process in advance.

  The present invention eliminates the necessity of determining a function to be offloaded in consideration of the scale of the hardware accelerator when using a hardware accelerator, and makes it possible to efficiently determine the function to be offloaded. Objective.

  An information processing apparatus having an accelerator according to the present invention is an information processing apparatus having an accelerator including a processor and a hardware accelerator capable of reconfiguring an internal configuration, and converts an application source program into a program for a processor, Source program conversion means for generating a program for a hardware accelerator from a commandable offloadable program in the source program, execution status monitoring means for monitoring the execution status of the program, and an accelerator for determining the spare capacity of the hardware accelerator Based on the determination means, the monitoring result of the execution status monitoring means, and the determination result of the accelerator determination means, a program to be offloaded to the hardware accelerator during execution of the application program is determined. Characterized by comprising a offload determining means for.

  An information processing method according to the present invention is an information processing method executed by an information processing apparatus including a processor and a hardware accelerator capable of reconfiguring an internal configuration, and converts an application source program into a program for a processor. Generate a hardware accelerator program from the offloadable program commanded in the source program, monitor the execution status of the program, determine the spare capacity of the hardware accelerator, monitor the execution status of the program and the hardware A program to be offloaded to the hardware accelerator is determined during execution of the application program based on the determination result of the spare capacity of the hardware accelerator.

  According to the present invention, it is possible to eliminate the necessity of determining the function to be offloaded in consideration of the scale of the hardware accelerator and to efficiently determine the function to be offloaded.

1 is a block diagram illustrating a first embodiment of an information processing device. It is a schematic diagram for demonstrating the process of a compiler. It is explanatory drawing for demonstrating the process of OS, and the process of the hardware containing a FPGA accelerator. It is explanatory drawing which shows a mode that the program for FPGA is integrated in an FPGA accelerator. It is a flowchart which shows an example of operation | movement of the information processing apparatus in execution of the application performed based on an application program. It is a flowchart which shows an example of operation | movement of the information processing apparatus which produces | generates the program for FPGAs during execution of an application program. It is a block diagram which shows the principal part of the information processing apparatus by this invention.

Embodiment 1. FIG.
Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a block diagram showing a first embodiment of an information processing apparatus according to the present invention. As illustrated in FIG. 1, the information processing apparatus includes a CPU 11 and an FPGA accelerator 12. The FPGA accelerator 12 is an FPGA serving as a hardware accelerator, but may include a plurality of FPGA elements. For example, the CPU 11 and the FPGA accelerator 12 transmit and receive data via a PCI Express (registered trademark) standard bus.

  The information processing apparatus further includes a compiler 13, an execution status monitoring unit 21, an FPGA program management table 22, a function table 31, a function table management unit 32, an FPGA resource management unit 41, an FPGA resource management table 42, an FPGA program management unit 43, And a dynamic offload unit 51.

  The compiler 13 converts the source program of the application program into a CPU program (CPU object program) that can be executed by the CPU 11. Further, in the present embodiment, when the compiler 13 determines that the process can be offloaded to the FPGA accelerator 12 by the syntax analysis of the source code, the compiler 13 generates an FPGA program (FPGA object program). The FPGA program is a collection of data for reconfiguring the configuration of the FPGA accelerator 12 so that the FPGA accelerator 12 realizes the same function as the function realized by the corresponding CPU program.

  The execution status monitoring unit 21 monitors the execution status of the function group and records the execution status in the FPGA program management table 22. A function is a group of processes (routines) in an application program. The execution status includes, for example, an offload state (whether or not offloading is performed), an execution frequency, a capacity of a function FPGA program, and a priority. As for the priority, for example, a high priority is set for a function with a high execution frequency, or a function with a high execution frequency is implicitly considered to have a high priority, or is embedded in a source program. Priorities are set at compile time based on data.

  The function table 31 is a jump table to functions constituting the application program. Data (entries) recorded in the function table 31 is generally created by the compiler 13 or linker and stored in the main memory of the information processing apparatus. Specifically, data indicating which of the CPU program and the FPGA program should be used for each function is set in the function table 31 as an entry. FIG. 1 illustrates functions Func1, Func2, Func3, and Func4. In addition, when “y” of Funxx-y (x: 1 to 4) at the end of the arrow is “C”, a CPU program is indicated, and when “F” is indicated, an FPGA program is indicated. Indicates.

  The function table management unit 32 manages whether to call an FPGA program or a CPU program.

  The FPGA resource management unit 41 monitors the number of unused gate arrays (free capacity) of the FPGA accelerator 12 and records the monitoring result in the FPGA resource management table 42.

  The FPGA program management unit 43 controls the dynamic offload unit 51 and the function table management unit 32 based on the data recorded in the FPGA program management table 22 and the data recorded in the FPGA resource management table 42.

  The dynamic offload unit 51 loads a designated FPGA program or the like into the FPGA accelerator 12 and performs control for incorporating a necessary device driver into an OS (Operating System: not shown in FIG. 1).

  Next, the operation of the information processing apparatus will be described. FIG. 2 is a schematic diagram for explaining the processing of the compiler 13. In the present embodiment, the source program 101 includes a syntax that can specify whether the processing can be offloaded to the FPGA accelerator 12. For example, as shown in FIG. 2, a pragma such as “#FPGA_OFFLOAD” (pragma: an identifier (command) used to pass specific information to the compiler) is attached to a process that can be offloaded. Note that other compiler options may be used as long as it can be specified that it is possible to specify whether the processing can be offloaded.

  The compiler 13 inputs the source program 101 and performs syntax analysis (step S11).

  When a command indicating that the process can be offloaded is found (step S12), an FPGA program (FPGA object) is generated from the source code (step S13), and the FPGA program 102 is supported by the information processing apparatus. Store in memory. In the present embodiment, the function Func1 is a process that cannot be offloaded. For example, processing that cannot be offloaded is processing that cannot be accelerated even when offloaded, or processing that consumes a large amount of resources of the FPGA accelerator 12.

  Thereafter, the compiler 13 converts the source code into a CPU program (step S14), and stores the CPU program 103 in the main memory or auxiliary memory of the information processing apparatus.

  FIG. 3 is an explanatory diagram for explaining the processing of the OS 61 executed by the CPU 11 and the processing of the hardware 81 including the FPGA accelerator 12.

  The hardware 81 includes an FPGA program incorporation function unit 82 (not shown in FIG. 1) that is a mechanism for incorporating the FPGA program 102 into the FPGA accelerator 12. In response to an FPGA program incorporation request from the dynamic offload unit 51, the FPGA program incorporation function unit 82 incorporates the FPGA program 102 stored in the storage unit 91 such as auxiliary storage into the FPGA accelerator 12. Specifically, the configuration of the FPGA accelerator 12 is reconstructed.

  The OS 61 also includes a device driver built-in function 62. For example, in response to a CPU program incorporation request from the dynamic offload unit 51, the OS 61 incorporates a device driver 72 stored in the storage unit 71 into the OS 61 using the device driver incorporation function 62.

  FIG. 4 is an explanatory diagram showing how the FPGA program is incorporated (loaded) into the FPGA accelerator 12. In the example illustrated in FIG. 4, the dynamic offload unit 51 satisfies the predetermined condition based on the monitoring result of the execution status monitoring unit 21, so that the Func2-F corresponding to the FPGA program of the function Func2 and the function Func4 and It is illustrated that Func4-F is loaded into the FPGA accelerator 12. At the same time, the corresponding device driver is incorporated into the OS 61.

  FIG. 5 is a flowchart illustrating an example of the operation of the information processing apparatus during execution of an application executed based on the application program.

  During execution of the application, the execution status monitoring unit 21 determines the execution frequency of each function (the execution frequency in the CPU 11 and the execution frequency in the FPGA accelerator 12) (step S101). The execution frequency is, for example, the number of executions per predetermined time, but may simply be a cumulative value of the number of executions. Furthermore, the execution status monitoring unit 21 may measure the execution time of the function. After updating the execution frequency, the execution status monitoring unit 21 records the updated execution frequency in the FPGA program management table 22 (step S102).

  For example, when the function execution frequency becomes equal to or lower than a predetermined threshold, the dynamic offload unit 51 cancels offload for the function. As a result, the free capacity (the number of unused gate arrays) of the FPGA accelerator 12 increases.

  The FPGA resource management unit 41 calculates, for example, the free capacity of the FPGA accelerator 12 when the function is offloaded and when the offload is released (step S103). Then, the execution status monitoring unit 21 records the free capacity in the FPGA resource management table 42 (step S104).

  Note that the FPGA resource management unit 41 may always monitor the free space or calculate the free space every predetermined time.

  The FPGA program management unit 43 determines to offload the function when a predetermined condition regarding the function is satisfied (step S105). The predetermined condition is, for example, that the execution frequency exceeds a predetermined threshold and the number of gate arrays required for executing the FPGA program of the function is equal to or less than the free capacity. Even if the execution frequency does not exceed a predetermined threshold, the execution time of the function is longer than the predetermined time, and the number of gate arrays required for executing the FPGA program of the function is less than the free capacity. If there is, the FPGA program management unit 43 may decide to offload the function. Further, the FPGA program management unit 43 decides to offload a function having a high execution frequency or a function having a long execution time when the offload is not executed for a predetermined time and the free space is sufficient. May be.

  If the FPGA program management unit 43 decides to offload, it requests the dynamic offload unit 51 to offload the function. The dynamic offload unit 51 executes offload of the function in response to the request (step S106). Specifically, the dynamic offload unit 51 issues an FPGA program incorporation request to the FPGA program incorporation function unit 82 (see FIG. 3). If the offload target function is, for example, Func2, the FPGA program built-in function unit 82 loads the FPGA program Func2-F into the FPGA accelerator 12. Further, the dynamic offload unit 51 makes a device driver incorporation request for the device driver corresponding to the FPGA program Func2-F to the OS 61 (see FIG. 3).

  Further, the FPGA program management unit 43 requests the function table management unit 32 to change an entry for, for example, Func2. The function table management unit 32 changes the entry so that the FPGA program Func2-F is called for Func2.

  In this embodiment, it is not necessary to define a function for offloading in advance according to the scale of the FPGA. In other words, an FPGA scale can be designed and an FPGA element can be selected independently of software.

  In addition, a developer (designer) can develop an application without being aware of the presence or absence of a hardware accelerator and the scale of the hardware accelerator.

  Furthermore, it becomes possible to preferentially offload a process having a high offload effect.

  In this embodiment, the case where the FPGA is used as a hardware accelerator of the processor is taken as an example, but the case where a GPU (Graphics Processing Unit), a DSP (Digital Signal Processor), or the like is used as a hardware accelerator is also exemplified. This embodiment can be applied. However, in that case, since the GPU and DSP are generally not reconfigurable devices whose internal configuration can be reconfigured, the “free capacity” in the above embodiment is expressed not by the number of gate arrays but by a margin capacity or the like. Is done. The margin capacity is also a superordinate concept including “free capacity”.

  Although it is preferable to use an FPGA as a hardware accelerator, this embodiment can be applied even when another device (for example, CPLD: Complex Programmable Logic Device) whose internal configuration can be reconfigured is used. it can.

Embodiment 2. FIG.
In the first embodiment, the FPGA program is generated by the compiler before the execution of the application program. However, the FPGA program may be generated during the execution of the application program.

  FIG. 6 is a flowchart illustrating an example of the operation of the information processing apparatus that generates the FPGA program during execution of the application program. The configuration of the information processing apparatus is the same as that of the first embodiment shown in FIG.

  In FIG. 6A, the information processing apparatus executes the process # 1 by the CPU program (step S201), repeatedly executes the process # 2 by the CPU program (steps S202 and S204), and then for the CPU. An example in which process # 3 is executed by a program (step S205) is shown.

  FIG. 6B shows an example in which the process # 2 is executed by the FPGA program (step S203). Specifically, in the information processing apparatus, when the FPGA program management unit 43 decides to offload the function, the dynamic offload unit 51 instructs the compiler to compile the source code of process # 2 ( Request generation of an FPGA program). The generated FPGA program is stored in an auxiliary storage or the like of the information processing apparatus as in the case of the first embodiment.

  Then, the dynamic offload unit 51 issues an FPGA program incorporation request to the FPGA program incorporation function unit 82 (see FIG. 3). The FPGA program built-in function unit 82 loads the FPGA program into the FPGA accelerator 12. Further, the dynamic offload unit 51 makes a device driver incorporation request for the device driver corresponding to the FPGA program to the OS 61 (see FIG. 3).

  Further, the FPGA program management unit 43 requests the function table management unit 32 to change the entry for the FPGA program. The function table management unit 32 changes the entry so that the FPGA program is called.

  FIG. 7 is a block diagram showing a main part of the information processing apparatus according to the present invention. As illustrated in FIG. 7, the information processing apparatus 1 includes a processor 2 (for example, a CPU 11) and a hardware accelerator 3 (for example, an FPGA accelerator 12) whose internal configuration can be reconfigured, and a source program of an application as a processor. Source program conversion means 4 (for example, a program for FPGA) that generates a program for hardware accelerator (for example, a program for FPGA) from an offloadable program instructed in the source program. And the execution status monitoring means 5 (for example, realized by the execution status monitoring unit 21) for monitoring the execution status of the program, and the spare capacity of the hardware accelerator (for example, the empty space of the FPGA). Capacity) Based on the monitoring unit 6 (for example, realized by the FPGA resource management unit 41), the monitoring result of the execution status monitoring unit 5, and the determination result of the accelerator determining unit 6, Offload determination means 7 (for example, realized by the FPGA program management unit 43) for determining a program (for example, a function) to be offloaded to the accelerator 3 is provided.

  The information processing apparatus may include a table (for example, a function table 31) for specifying which of a processor program and a hardware accelerator program is used.

DESCRIPTION OF SYMBOLS 1 Information processing apparatus 2 Processor 3 Hardware accelerator 4 Source program conversion means 5 Execution condition monitoring means 6 Accelerator determination means 7 Offload determination means 11 CPU
DESCRIPTION OF SYMBOLS 12 FPGA accelerator 13 Compiler 21 Execution condition monitoring part 22 FPGA program management table 31 Function table 32 Function table management part 41 FPGA resource management part 42 FPGA resource management table 43 FPGA program management part 51 Dynamic offload part 61 OS
62 Device Driver Embedded Function 71 Storage Unit 72 Device Driver 81 Hardware 82 FPGA Program Embedded Function Unit 91 Storage Unit 101 Source Program 102 FPGA Program 103 Source Program

Claims (8)

An information processing apparatus having an accelerator including a processor and a hardware accelerator capable of reconfiguring an internal configuration,
Source program conversion means for converting a source program of an application into a program for a processor and generating a program for a hardware accelerator from a commandable offloadable program in the source program;
Execution status monitoring means for monitoring the execution status of the program;
Accelerator determination means for determining a margin capacity of the hardware accelerator;
Offload determination means for determining a program to be offloaded to the hardware accelerator during execution of the application program based on the monitoring result of the execution status monitoring means and the determination result of the accelerator determination means An information processing apparatus characterized by the above. The hardware accelerator is realized by FPGA,
The information processing apparatus according to claim 1, wherein a margin capacity of the hardware accelerator is a free capacity of the FPGA. The information processing apparatus according to claim 1, wherein the command in the source program is a pragma. The information processing apparatus according to any one of claims 1 to 3, wherein the execution status monitoring unit monitors the execution frequency of the program as the execution status of the program. The information processing apparatus according to any one of claims 1 to 4, further comprising a table for specifying which of a processor program and a hardware accelerator program is used. An information processing method executed by an information processing apparatus including a processor and a hardware accelerator capable of reconfiguring an internal configuration,
Converting a source program of an application into a program for a processor, generating a program for a hardware accelerator from a command capable of being offloaded in the source program,
Monitor program execution status,
Determine the spare capacity of the hardware accelerator,
Information that determines the program to be offloaded to the hardware accelerator during execution of the application program based on the monitoring result of the execution status of the program and the determination result of the spare capacity of the hardware accelerator Processing method. The information processing method according to claim 6, wherein a free capacity of the FPGA is determined as a margin capability of the hardware accelerator realized by an FPGA. The information processing method according to claim 6 or 7, wherein the command in the source program is a pragma.

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