JP2018129908A - DC / DC converter, control circuit therefor, control method, and in-vehicle electrical equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To detect steady overcurrent state reliably.SOLUTION: A pulse modulator 210 generates a pulse signal Shaving a duty ratio adjusted so that the output signal Vof a DC/DC converter 100 approaches a target voltage V. When the current Iof the DC/DC converter 100 exceeds a prescribed threshold level I, an overcurrent detection circuit 271 asserts an overcurrent detection signal S. When assert of an overcurrent detection signal Soccurs more than a prescribed determination frequency in a prescribed number of cycles, a determination circuit 290 determines that it is over current state.SELECTED DRAWING: Figure 3

Description

  The present invention relates to a DC / DC converter.

In various electronic devices, vehicles, and industrial machines, a DC / DC converter that converts a DC voltage of one voltage value into a DC voltage of another voltage value is used. FIG. 1 is a circuit diagram of a synchronous rectification step-down (Buck) DC / DC converter 900. The DC / DC converter 900 receives a DC input voltage _VIN at an input terminal 902 and generates a stepped down output voltage _VOUT at an output terminal 904. The output stage of the DC / DC converter 900 is provided with a switching transistor M ₁ , a synchronous rectification transistor M ₂ , an inductor (coil) L ₁ , and an output capacitor C ₁ .

The pulse modulator 910 changes the duty ratio, frequency, or combination thereof so that the state of the DC / DC converter 900 or the state of the load (not shown) connected to the output terminal 904 approaches the target state. The pulse signal S _PWM to be generated is generated. Driver 912 switches the switching transistor _{M 1} and the synchronous rectification transistor _{M 2} on the basis of the pulse signal _{S PWM.}

For example, in the DC / DC converter 900 with a constant voltage output, the pulse modulator 910 generates the pulse signal S _PWM so that the output voltage V _OUT approaches the target voltage V _{OUT (REF)} . In the DC / DC converter 900 with constant current output, the pulse signal S _PWM is generated so that the current I _OUT flowing through the load approaches the target value I _REF , but in the following description, the constant voltage output converter will be described. To do.

The DC / DC converter 900 that starts immediately after the order to prevent the inrush current to the output capacitor C _1, the soft-start control is performed to raise gradually the output voltage V _OUT. The soft-start circuit 914 generates a soft start voltage V _SS to change slowly over time. The pulse modulator 910 receives a feedback signal V _FB obtained by dividing the output voltage _VOUT by the resistors R ₁₁ and R ₁₂ . The pulse modulator 910 generates the pulse signal S _PWM so that the feedback signal V _FB follows the soft start voltage V _SS in the soft start period immediately after the start, and after the soft start is completed, the feedback signal V _FB becomes the reference voltage. The pulse signal S _PWM is generated so as to coincide with V _REF .

The DC / DC converter 900 includes a current sense circuit 920 and an overcurrent detection circuit 922. The current sense circuit 920 in the on-period switching transistors _{M 1,} to generate a current sense signal _{V CS} that shows the drain current _{I M1} flowing through the switching transistor _{M 1.} Overcurrent detection circuit 922, the current sense signal _{V CS} to cross the threshold _{V OCP,} the drain current _{I M1} exceeds the threshold _{I OCP,} shifts the pulse signal _{S PWM} off level in other words, The switching transistor in the on state is immediately turned off. This is referred to as pulse-by-pulse (or cycle-by-cycle) overcurrent limitation.

International Publication WO2013 / 165004 JP 2010-110133 A

It is not desirable to keep the DC / DC converter operating in an overcurrent state. Therefore, the DC / DC converter has a stop function (latch stop protection) that stops the operation of the DC / DC converter when an overcurrent state is continuously detected for a plurality of cycles or when the overcurrent state continues for a predetermined time or more. Implemented. 2A and 2B are diagrams for explaining overcurrent protection in the DC / DC converter of FIG. As shown in FIG. 2A, when the overcurrent detection signal S _OCP is continuously asserted, the stop signal OCP_DET is asserted after a predetermined number of cycles N, and the switching operation is stopped.

  As a result of examining the DC / DC converter having such a stop function, the present inventor has come to recognize the following problems.

Depending on the operating state of the DC / DC converter, the overcurrent detection signal S _OCP is not always asserted continuously even when the overcurrent state is maintained. In this case, as shown in FIG. 2B, the overcurrent detection signal _SOCP is intermittently asserted, and the operation continues permanently while repeating the pulse-by-pulse overcurrent protection.

  The present invention has been made in view of such a problem, and one of exemplary purposes of an embodiment thereof is to provide a DC / DC converter that can reliably detect a steady overcurrent state.

  One embodiment of the present invention relates to a control circuit for a DC / DC converter. A pulse modulator that generates a pulse signal whose duty ratio is adjusted so that the output signal of the DC / DC converter approaches the target voltage, and an overcurrent detection signal when the current of the DC / DC converter exceeds a predetermined threshold value And an overcurrent detection circuit that determines an overcurrent state when the overcurrent detection signal is asserted more than a predetermined number of times within a predetermined number of cycles.

  According to this aspect, it is possible to reliably detect a continuous overcurrent state in which the overcurrent detection signal is intermittently asserted, and to achieve appropriate protection.

  The determination circuit may start counting a predetermined number of cycles using the first overcurrent detection signal assertion as a trigger. As a result, the determination circuit does not operate in a normal state in which the overcurrent detection signal is not asserted, so that useless power consumption can be reduced. Further, the detection delay can be reduced by operating the first overcurrent detection signal as a trigger.

  When the determination circuit detects assertion of the overcurrent detection signal in the disabled state, the determination circuit is enabled. Until the predetermined number of cycles is counted, the first counter that asserts the count enable signal and the count enable signal are asserted. A second counter that counts the number of times the overcurrent detection signal is asserted, and asserts an abnormality detection signal indicating an overcurrent state when the count value of the second counter exceeds a threshold value corresponding to the number of determinations May be.

  The determination circuit may start the next predetermined cycle number when one predetermined cycle number ends.

  The pulse modulator may be a peak current mode modulator.

  The control circuit may be integrated on a single semiconductor substrate. “Integrated integration” includes the case where all of the circuit components are formed on a semiconductor substrate and the case where the main components of the circuit are integrated. A resistor, a capacitor, or the like may be provided outside the semiconductor substrate. By integrating the circuit on one chip, the circuit area can be reduced and the characteristics of the circuit elements can be kept uniform.

  Another aspect of the present invention relates to a DC / DC converter. The DC / DC converter includes any one of the control circuits described above.

  Another aspect of this invention is related with a vehicle-mounted electrical equipment. The in-vehicle electrical equipment power source includes the above-described DC / DC converter.

  Note that any combination of the above-described constituent elements and the constituent elements and expressions of the present invention replaced with each other among methods, apparatuses, systems, and the like are also effective as an aspect of the present invention. Further, the description of this item (means for solving the problem) does not explain all the essential features of the present invention, and therefore a sub-combination of these described features can also be the present invention. .

  According to an aspect of the present invention, it is possible to reliably detect a continuous overcurrent state in which the overcurrent detection signal is intermittently asserted.

It is a circuit diagram of a synchronous rectification step-down DC / DC converter. 2A and 2B are diagrams for explaining overcurrent protection in the DC / DC converter of FIG. It is a circuit diagram of the DC / DC converter which concerns on embodiment. It is a circuit diagram which shows the structural example of a determination circuit. It is a figure explaining operation | movement of the overcurrent detection of a DC / DC converter. It is a figure explaining operation | movement of the overcurrent detection of a DC / DC converter. It is a circuit diagram which shows the specific structural example of a DC / DC converter. FIGS. 8A and 8B are diagrams illustrating a modification example of overcurrent detection of a DC / DC converter. It is a block diagram of a vehicle-mounted electrical equipment provided with a DC / DC converter.

  The present invention will be described below based on preferred embodiments with reference to the drawings. The same or equivalent components, members, and processes shown in the drawings are denoted by the same reference numerals, and repeated descriptions are omitted as appropriate. The embodiments do not limit the invention but are exemplifications, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

In this specification, “the state in which the member A is connected to the member B” means that the member A and the member B are physically directly connected, or the member A and the member B are electrically connected. The case where it is indirectly connected through other members that do not affect the state or inhibit the function is also included.
Similarly, “the state in which the member C is provided between the member A and the member B” refers to the case where the member A and the member C or the member B and the member C are directly connected, as well as an electrical condition. This includes cases where the connection is indirectly made through other members that do not affect the connection state or inhibit the function.

  “Signal A (voltage, current) is in response to signal B (voltage, current)” means that signal A has a correlation with signal B. Specifically, (i) signal A Is signal B, (ii) signal A is proportional to signal B, (iii) signal A is obtained by level shifting signal B, and (iv) signal A is obtained by amplifying signal B. If (v) signal A is obtained by inverting signal B, it means (vi) or any combination thereof. It will be understood by those skilled in the art that the “depending” range is determined depending on the type and application of the signals A and B.

  The vertical and horizontal axes of the waveform diagrams and time charts referred to in this specification are enlarged or reduced as appropriate for easy understanding, and each waveform shown is also simplified for easy understanding. Or exaggerated or emphasized.

FIG. 3 is a circuit diagram of the DC / DC converter 100 according to the embodiment. The DC / DC converter 100 is a synchronous rectification step-down (Buck) converter, which receives a DC input voltage _VIN at an input terminal 102 and generates a stepped-down output voltage _VOUT at an output terminal 104. The DC / DC converter 100 includes an output circuit 110 and a control circuit 200. In this embodiment, a DC / DC converter with a constant voltage output will be described as an example.

The output circuit 110 includes a switching transistor M ₁ , a synchronous rectification transistor M ₂ , an inductor L ₁ , an output capacitor C ₁ , and resistors R ₁₁ and R ₁₂ . In the present embodiment, the switching transistor M ₁ is a P-channel MOSFET, the synchronous rectification transistor M ₂ is an N-channel MOSFET, and they are built in the control circuit 200.

The connection point of the switching transistor _{M 1} and the synchronous rectification transistor _{M 2} is referred to as a switching (SW) terminal. The terminal may be read as a pin. The inductor L ₁ is provided between the SW terminal and the output terminal 104. The output capacitor C ₁ is connected to the output terminal 104. The feedback (FB) terminal receives an output voltage V _OUT to be controlled, and the resistors R ₁₁ and R ₁₂ divide the output voltage V _OUT to generate a detection voltage (feedback signal) V _FB . The resistors R ₁₁ and R ₁₂ may be externally attached to the control circuit 200 as shown in FIG.

The control circuit 200 includes a pulse modulator 210, a driver 230, a soft start circuit 240, an oscillator 260, a current sense circuit 270, an overcurrent detection circuit 271 and a determination circuit 290 in addition to the switching transistor M ₁ and the synchronous rectification transistor M _2. Prepare. The control circuit 200 is preferably a functional IC (Integrated Circuit) integrated on a single semiconductor substrate. The source of the switching transistor _{M 1} is a VIN terminal, its drain is connected to the SW terminal. The drain of the synchronous rectification transistor M ₂ is connected to the SW terminal, its source connected to the GND terminal. An enable signal EN for instructing operation and stop of the control circuit 200 (DC / DC converter 100) is externally input to the enable (EN) terminal.

The pulse modulator 210 includes a main logic 218. When the enable signal EN is asserted (for example, at a high level), the main logic 218 activates an internal reference voltage source and a reference current source (not shown) and other circuits. block and operable state, and instructs the production start of the soft-start voltage V _SS to the soft start circuit 240. The soft-start circuit 240 receives an instruction of the start of operation, to generate a soft-start voltage V _SS to time to slowly increase. A period during which the soft start voltage V _SS increases (or before and after it) is referred to as a soft start period T _SS .

Pulse modulator 210, as the state of the state of the DC / DC converter 100, or connected load to the output terminal 104 (not shown) approaches the target value, pulse signal _{S PWM} instructing on and off of the switching transistor _{M 1} (also referred to as a high-side pulse S _H) and to generate a low side pulse S _L for instructing the on-off of the synchronous rectifier transistor M _2.

As described above, the DC / DC converter 100 has a constant voltage output, and the pulse modulator 210 uses the output voltage _VOUT of the DC / DC converter 100 as a control target. Specifically, the pulse modulator 210 generates the pulse signal S _PWM so that the feedback voltage V _FB approaches the target value V _REF .

The pulse modulator 210 may use a known technique, and its control method and configuration are not particularly limited. As a control method, a voltage mode, a peak current mode, an average current mode, a hysteresis control (Bang-Bang control), a bottom detection on-time fixed (COT: Constant On Time) method, or the like can be adopted. The modulation method of the pulse signal S _PWM is not limited to this, but pulse width modulation (PWM) can be adopted. The configuration of the pulse modulator 210 may be configured by an analog circuit using an error amplifier or a comparator, may be configured by a processor that performs digital arithmetic processing, or may be configured by a combination of an analog circuit and a digital circuit. May be. Further, the pulse modulator 210 may switch the control method according to the load state.

The operation mode of the pulse modulator 210 may be variable depending on the load state. For example, the pulse modulator 210 may operate in a PWM mode in a heavy load state, and may operate in a PFM (Pulse Frequency Modulation) mode in a light load state. In PWM mode (especially continuous current mode), the high-side pulse S _H and the low-side pulse S _L becomes complementary signals.

The driver 230 drives the switching transistor _{M 1} based on the pulse signal _{S PWM} (the high-side pulse _{S H),} based on the low-side pulse _{S L} to drive the synchronous rectification transistor _{M 2.}

The oscillator 260 oscillates at a predetermined frequency. The configuration of the oscillator 260 is not particularly limited. For example, the oscillator 260 includes a capacitor, a charging circuit that charges the capacitor with a constant current, a comparator that compares the voltage of the capacitor with a threshold value, and when the voltage of the capacitor reaches the threshold value according to the output of the comparator, And a discharge circuit that discharges the electric charge. The oscillator 260 generates two oscillation signals S _OSC and CLK. They may be the same signal or different signals.

The pulse modulator 210 operates in synchronization with the oscillation signal S _OSC generated by the oscillator 260. Therefore, the pulse signal S _PWM has a frequency corresponding to the oscillation signal S _OSC .

Pulse modulator 210, when starting the DC / DC converter, the feedback signal _{V FB} is, to approach the target voltage corresponding to the lower of the output soft-start voltage _{V SS} and the reference voltage _{V REF,} the pulse signal _{S PWM} Adjust the duty ratio.

The current sense circuit 270, the switching in the transistors _{M 1} on time, detects the coil _{L 1} to the coil current flowing through _{I L} (the drain current _{I M1} of the switching transistor _{M 1} in other words), the current sense showing a drain current _{I M1} A signal _VCS is generated. Structure of the current sensing circuit 270 is not particularly limited, for example, the switching transistor is also may detect the drain current I _M1 by using the on-resistance of M _1, the drain current I _{M1 (or} coil current I _L) on the path of Alternatively, a sense resistor may be inserted to detect a voltage drop of the sense resistor. The current sense circuit 270 may detect the coil current I _L on the basis of the voltage across the inductor L _1.

When the drain current I _M1 of the switching transistor M ₁ exceeds a predetermined threshold value I _OCP , the over current detection circuit 271 asserts an overcurrent detection (OCP) signal S _OCP (for example, high level). The overcurrent detection circuit 271 can be configured with a comparator.

If the assertion of the OCP signal S _OCP exceeds the predetermined number of determinations M within the predetermined number of cycles N, the determination circuit 290 determines an overcurrent state and asserts the overcurrent determination signal OCP_DET (for example, high level). .

  The main logic 218 stops the operation of the DC / DC converter 100 in response to the assertion of the OCP_DET signal.

  The main logic 218 outputs a flag signal FLG for notifying an overcurrent state to an external host controller (microcomputer). Thus, the host controller that has received the notification of the overcurrent state can execute necessary protection processing in relation to the entire system including the DC / DC converter 100 and the DC / DC converter 100.

FIG. 4 is a circuit diagram illustrating a configuration example of the determination circuit 290. The determination circuit 290 includes a first counter 292 and a second counter 294. The determination circuit 290 starts counting a predetermined number of cycles N using the first assertion of the OCP signal S _OCP as a trigger.

The first counter 292 receives the oscillation signal (clock signal) CLK from the oscillator 260 and the OCP signal S _OCP . The first counter 292 is enabled when detecting the assertion of the OCP signal S _{OCP in} the disabled state (non-counting state), and proceeds to count in synchronization with the clock signal CLK until the predetermined number of cycles is counted. The enable signal COUNT_EN is asserted (high level). The first counter 292 may include a shift register.

The second counter 294 counts the number of times the OCP signal S _OCP is asserted while the count enable signal COUNT_EN is asserted. When the count value OCP_COUNT reaches the determination count M, the second counter 294 determines that an overcurrent state occurs and asserts the OCP_DET signal. However, N> M.

The above is the configuration of the DC / DC converter 100. Next, the operation will be described.
FIG. 5 is a diagram for explaining the overcurrent detection operation of the DC / DC converter 100. In this example, N = 8 and M = 4.

The clock signal CLK has an edge every PWM cycle. The OCP signal S _OCP is asserted every time the drain current I _M1 of the switching transistor M ₁ exceeds the threshold value I _OCP . By the assertion of the OCP signal _{S OCP,} (in the figure, indicated by (i)) overcurrent protection pulses by pulse is generated, the switching transistor _{M 1} is turned off.

When the first OCP signal S _OCP is asserted at time t ₀ , the COUNT_EN signal is asserted while the clock signal CLK (negative edge here) is generated N (= 8) times.

The number of assertions of the OCP signal S _OCP is counted while the COUNT_EN signal is at a high level. At time _{t 1,} when the count value OCP_COUNT reaches the threshold K in accordance with the determination count M, OCP_DET signal is asserted. In this example, since the first OCP signal S _OCP is not included in the count of the second counter 294, K = M−1 may be set.

FIG. 6 is a diagram for explaining the overcurrent detection operation of the DC / DC converter 100. When the first OCP signal S _OCP is asserted at time t ₀ , the COUNT_EN signal is asserted thereafter while the clock signal CLK is generated N (= 8) times.

In FIG. 6, while the COUNT_EN signal is at a high level, the OCP signal S _OCP is asserted only once. Therefore, OCP_DET is not asserted. When COUNT_EN signal becomes low level at time _{t 1,} the decision circuit 290 enters a standby state.

Followed by time _{t 2, the} the assertion of first OCP signal _{S OCP} occurs again, it is asserted COUNT_EN signal, in the subsequent determination period _{T DET} thereto, the number of assertion of the OCP signal _{S OCP} is counted.

  The above is the operation of the DC / DC converter 100. According to the DC / DC converter 100, a state in which the OCP signal is intermittently and continuously asserted can be determined as an overcurrent state. Whereas conventional overcurrent protection is processing based on the number of times of continuous overcurrent detection, overcurrent protection in the present embodiment is the occurrence frequency (ratio) of overcurrent detection in a predetermined time. It can be said that it paid attention to.

  The present invention is understood as the block diagram and circuit diagram of FIG. 3 or extends to various devices and circuits derived from the above description, and is not limited to a specific configuration. In the following, more specific configuration examples and modifications will be described in order to help understand the essence and circuit operation of the invention and clarify them, not to narrow the scope of the present invention.

  FIG. 7 is a circuit diagram illustrating a specific configuration example of the DC / DC converter 100.

The pulse modulator 210 is a peak current mode pulse width modulator. The pulse modulator 210 includes an error amplifier 212, a PWM comparator 214, a slope compensator 216, and a main logic 218. The error amplifier 212 amplifies an error between one of the soft start voltage V _SS and the reference voltage V _{REF which} is lower and the feedback voltage V _FB, and generates an error signal V _ERR . The error amplifier 212 may be composed of a three-input operational amplifier. The slope compensator 216 superimposes the slope signal V _SLOPE on the current sense signal V _CS from the current sense circuit 270.

The PWM comparator 214 compares the error signal V _ERR with the current sense signal V _CS ′ after slope compensation, and asserts the reset signal S _RESET (for example, high level) when the current sense signal V _CS ′ crosses the error signal V _ERR. ) In response to the assertion of the reset signal S _RESET , the main logic 218 transitions the pulse signal S _PWM to a level (off level, for example, low) corresponding to the switching transistor M ₁ being turned off.

The oscillator 260 generates a set signal S _SET having a frequency corresponding to the current I _OSC . In response to the edge of the set signal S _SET , the main logic 218 causes the pulse signal S _PWM to transition to a level (on level, eg, high) corresponding to the switching transistor M ₁ being on.

(Modification of overcurrent protection)
FIGS. 8A and 8B are diagrams illustrating a modification example of overcurrent detection of the DC / DC converter 100. FIG. In the overcurrent detection process (FIGS. 5 and 6) according to the embodiment, the determination period _TDET is started using the first OCP signal S _OCP as a trigger. On the other hand, in the modification of FIG. 7, when one predetermined cycle number (determination period) ends, the next predetermined cycle number (determination period) is started without waiting for the trigger of the OCP signal. An overcurrent state can also be detected by this modification.

Comparing the modified examples of FIGS. 8A and 8B with the processes of FIGS. 5 and 6, the advantage of the latter becomes clear. FIG. 8B shows a case where the overcurrent detection process according to the embodiment is applied to the same OCP signal S _OCP as in FIG. As is clear from these comparisons, in the process according to the embodiment, the OCP_DET signal can be asserted at an earlier timing than the process according to the modification.

Further, in the modified example, even when the OCP signal S _OCP is not asserted at all, it is necessary to count the detection period _TDET , so that wasteful power consumption occurs. On the other hand, in the processing according to the embodiment, the operation of the determination circuit 290 is stopped in a state where the OCP signal S _OCP is not asserted at all, so that power consumption can be reduced.

(Use)
FIG. 9 is a block diagram of the in-vehicle electrical equipment 300 including the DC / DC converter 100. In-vehicle electrical equipment 300 includes a battery 302, a microcomputer 304, and a load 306 in addition to the DC / DC converter 100. The battery 302 generates a battery voltage V _BAT of 12V (or 24V), for example. The DC / DC converter 100 receives the battery voltage V _BAT as the input voltage _VIN , and generates an output voltage _VOUT having an optimum voltage level for the load 306. The load 306 is not particularly limited, and various ECUs (Electronic Control Units), audio circuits, car navigation systems, and the like are exemplified. The microcomputer 304 is a host processor that controls the in-vehicle electrical equipment 300 in an integrated manner, and outputs an EN signal to the control circuit 200. When the FLG terminal of the control circuit 200 is monitored and the assertion of the OCP_DET signal is detected, an appropriate protection process is executed.

  The in-vehicle electrical device 300 is required to have higher reliability than the electronic device. The DC / DC converter 100 according to the embodiment is suitable for applications that require high reliability such as the in-vehicle electrical equipment 300.

  The present invention has been described based on the embodiments. This embodiment is an exemplification, and it will be understood by those skilled in the art that various modifications can be made to combinations of the respective constituent elements and processing processes, and such modifications are within the scope of the present invention. is there. Hereinafter, such modifications will be described.

(First modification)
The DC / DC converter is not limited to a step-down type, and the present invention can be applied to a step-up type and a step-up / step-down type. The present invention can also be applied to a converter using a transformer such as a flyback converter.

(Second modification)
Although the embodiment has been described when the switching transistor M ₁ and the synchronous rectification transistor M ₂ is an MOSFET, the present invention is not limited thereto, may be IGBT (Insulated Gate Bipolar Transistor).

  Although the present invention has been described using specific terms based on the embodiments, the embodiments only illustrate the principles and applications of the present invention, and the embodiments are defined in the claims. Many variations and modifications of the arrangement are permitted without departing from the spirit of the present invention.

100 ... DC / DC converter, 102 ... input terminal, 104 ... output terminal, 110 ... output circuit, M 1 _... switching transistor, M 2 _... synchronous rectification transistor, L 1 _... inductor, C 1 _... output capacitor, 200 ... control circuit , 210 ... Pulse modulator, 212 ... Error amplifier, 214 ... PWM comparator, 216 ... Slope compensator, 218 ... Main logic, 230 ... Driver, 240 ... Soft start circuit, 260 ... Oscillator, 270 ... Current sense circuit, S _PWM ... pulse signal, 300 ... in-vehicle electrical equipment, 302 ... battery, 304 ... microcomputer, 306 ... load.

Claims (9)

A control circuit for a DC / DC converter,
A pulse modulator that generates a pulse signal in which a duty ratio is adjusted so that an output signal of the DC / DC converter approaches a target voltage;
An overcurrent detection circuit that asserts an overcurrent detection signal when the current of the DC / DC converter exceeds a predetermined threshold;
A determination circuit for determining an overcurrent state when the overcurrent detection signal is asserted exceeding a predetermined number of determinations within a predetermined number of cycles;
A control circuit comprising:   2. The control circuit according to claim 1, wherein the determination circuit starts counting a predetermined number of cycles N with a first assertion of the overcurrent detection signal as a trigger. The determination circuit includes:
A first counter that asserts a count enable signal until it is enabled when it detects assertion of the overcurrent detection signal in a disabled state; and
A second counter that counts the number of times the overcurrent detection signal is asserted while the count enable signal is asserted;
3. The control circuit according to claim 2, wherein an abnormality detection signal indicating the overcurrent state is asserted when a count value of the second counter exceeds a threshold value corresponding to the number of times of determination.   2. The control circuit according to claim 1, wherein the determination circuit starts the next predetermined cycle number when one predetermined cycle number ends.   5. The control circuit according to claim 1, wherein the pulse modulator is a peak current mode modulator.   6. The control circuit according to claim 1, wherein the control circuit is integrated on a single semiconductor substrate.   A DC / DC converter comprising the control circuit according to claim 1.   An in-vehicle electrical equipment comprising the DC / DC converter according to claim 7. A method for controlling a DC / DC converter, comprising:
Generating a pulse signal whose duty ratio is adjusted so that the output signal of the DC / DC converter approaches a target voltage;
Driving the switching transistor of the DC / DC converter in response to the pulse signal;
Asserting an overcurrent detection signal when a current flowing through the switching transistor exceeds a predetermined threshold;
A step of determining an overcurrent state when the overcurrent detection signal is asserted exceeding a predetermined number of determinations within a predetermined number of cycles;
A control method comprising:

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