JP2018120413A - Maintenance determining device, maintenance determining method, and program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a maintenance determining device that can distinguish whether a hardware error has occurred or a software error has occurred, while limiting the size of the device smaller, and at the same time, without causing the regular information processing to stop.SOLUTION: A maintenance determining device comprises: a first deciding logical unit for, when a correctable failure occurs in a certain memory area when reading data from a memory, causing a first status storage register to retain the information indicating the correctable failure to the memory area has occurred; and a second deciding logical unit for, when the correctable failure has already occurred in the memory area when writing the data into the memory, causing a second status storage register to retain the information indicating the correctable failure to the memory area has occurred.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a maintenance determination device, a maintenance determination method, and a program.

Memory is used in various electrical devices. An error may occur in data in the memory. The error includes a hard error caused by a hardware failure, that is, caused by physical damage, and a soft error caused by data corruption of the storage element. If a hard error occurs, physically damaged parts need to be replaced. However, when a soft error occurs, no hardware failure has occurred. Therefore, if new data is written at the address of data that is garbled, the soft error is eliminated.
Patent Document 1 describes a technique for determining whether a hard error has occurred as a related technique.
Japanese Patent Application Laid-Open No. 2004-228561 describes a related technique that distinguishes whether an error is a hard error or a soft error when an error occurs in data in a memory.

JP2012-103826A Japanese Patent Application Laid-Open No. 64-036352

By the way, in the technique described in Patent Document 1, when an error occurs in the cache, the contents of the main memory are written again into the cache where the error has occurred, and if an error occurs again within a certain time, a hard error occurs. Is determined to have occurred. Here, when an error occurs in the cache, writing the contents of the main memory again into the cache at the location where the error has occurred means stopping the normal processing in the information processing apparatus and correcting the generated error. . In other words, when the technique described in Patent Document 1 is used, it is necessary to stop normal processing in the information processing apparatus in order to determine whether or not a hard error has occurred.
The technique described in Patent Document 2 provides a flag indicating whether or not writing has been performed on an address where a 1-bit error has occurred, and the contents of this flag and the time-series information of the 1-bit error occurrence status Is a technique for distinguishing whether a hard error or a soft error has occurred. Here, an apparatus for determining whether or not writing has been performed to an address where a 1-bit error has occurred is the apparatus shown in FIG. The apparatus shown in FIG. 8 corresponds to one address reading unit (a memory area having a certain data length, for example, a word). Therefore, for example, when the number of read words in the memory array is 256, 256 devices shown in FIG. 8 are required. When the technique described in Patent Document 2 is used, the scale of the information processing device is large. It gets bigger.
Therefore, there has been a demand for a technique capable of distinguishing whether a hard error has occurred or a soft error has occurred without reducing the scale of the apparatus and stopping normal information processing.

  Therefore, an object of the present invention is to provide a maintenance determination device, a maintenance determination method, and a program that can solve the above-described problems.

  In order to achieve the above object, according to one aspect of the present invention, when a correctable failure occurs in a memory area having a certain data length when data is read from the memory, the correctable failure occurs in the memory area. A first decision logic unit that holds information indicating that the error occurred in a first status storage register; and the memory area when a correctable fault has already occurred in the memory area when data is written to the memory. A second determination logic unit that stores information indicating that a correctable failure has occurred in a second status storage register.

  According to another aspect of the present invention, when a correctable failure occurs in a memory area when data is read from the memory, information indicating that a correctable failure has occurred in the memory area is first Indicates that a correctable failure has occurred in the memory area when it has been stored in the status storage register and a correctable failure has already occurred in the memory area when data is written to the memory Holding the information in a second status storage register.

  According to another aspect of the present invention, there is provided information indicating that a correctable fault has occurred in the memory area when a correctable fault has occurred in a memory area when data is read from the memory. Is stored in the first status storage register, and a correctable fault has occurred in the memory area when a correctable fault has already occurred in the memory area when data is written to the memory. Is stored in the second status storage register.

  According to the present invention, it is possible to distinguish whether a hard error has occurred or a soft error has occurred without reducing the scale of the apparatus and stopping normal information processing.

It is a figure which shows the structure of the maintenance judgment system by one Embodiment of this invention. It is a figure which shows the truth table of the STATUS_R [n] decision logic part by one Embodiment of this invention. It is a figure which shows the truth table of the STATUS_W [n] decision logic part by one Embodiment of this invention. It is a figure which shows the processing flow of the maintenance judgment system by one Embodiment of this invention. It is a 1st figure for demonstrating the effect of the maintenance judgment apparatus by one Embodiment of this invention. It is a 2nd figure for demonstrating the effect of the maintenance judgment apparatus by one Embodiment of this invention. It is a figure which shows the minimum structure of the maintenance judgment apparatus by embodiment of this invention. It is a figure which shows the structure of the apparatus using the technique of patent document 2. FIG.

<Embodiment>
Next, the configuration of the maintenance determination system 1 including the maintenance determination device 40 according to one embodiment of the present invention will be described.
In the maintenance determination system 1 according to an embodiment of the present invention, when a correctable failure continues to be output from the same address in the memory, whether the cause is a fixed failure that requires hardware replacement due to a hardware failure This is a system that can determine whether the failure has occurred temporarily because the memory has not been written even after the failure, and does not require hardware replacement. As shown in FIG. 1, the maintenance determination system 1 includes a memory 10, registers 20a, 20b, 20c, 20d, 20e, 20f, 20g, 20h, 20i, and 20j, an error detection / error correction circuit 30, and a maintenance determination. Device 40.
The registers 20a, 20b, 20c, 20d, 20e, 20f, 20g, 20h, 20i, and 20j are collectively referred to as a register 20.

  In one embodiment of the present invention, the memory 10 operates only one of the memory operations per cycle, that is, read, write, or neither (one other than read / write, generally power save). It is a read write type. The one read write type is an example of the memory type of the memory 10. The effect obtained by the maintenance determination device 40 according to the embodiment of the present invention does not depend on the memory type of the memory 10. Therefore, the memory 10 may be any memory type memory.

The maintenance determination system 1 receives a READ / WRITE / ADDRESS signal 001, a WRITE / ENABLE signal 002, a CHIP / ENABLE signal 003, a WRITE / DATA signal 004, a TIME signal 010, and a RESET signal 011.
The error detection / error correction circuit 30 outputs a Syndrome signal 007, a Corrected DATA 008, and an SBE (Single Bit Error) signal 009.
A READ / DATA signal 005 is read from the memory 10.
Each of the READ / WRITE / ADDRESS signal 001, the WRITE / ENABLE signal 002, and the CHIP / ENABLE signal 003 is a control signal of the memory 10, and is similar to a general address signal and an enable signal. That is, the READ / WRITE / ADDRESS signal 001 is a signal for designating an address when the memory 10 is accessed. The WRITE / ENABLE signal 002 is a signal that permits writing. The CHIP / ENABLE signal 003 is a signal that permits the operation of the memory 10.
Each of the WRITE / DATA signal 004 and the READ / DATA signal 005 is an input / output DATA signal of the memory 10 and is the same as a write data signal and a read data signal of an input / output data signal of a general memory. That is, the WRITE / DATA signal 004 is a signal indicating data to be written in the memory 10. The READ / DATA signal 005 is a signal indicating data read from the memory 10.

Each of the registers 20 is a register that holds data for one clock.
The error detection / error correction circuit 30 is a circuit that detects an error from a READ / DATA signal 005 to which an error correction code read from the memory 10 is added by ECC (Error Correction Code) and corrects the detected error. is there. The operation of the error detection / error correction circuit 30 is the same as that of a general error detection circuit and error correction circuit.

The Syndrome signal 007 is a signal indicating information on an error bit detected by the error detection / error correction circuit 30. Corrected DATA 008 is an error-corrected DATA signal. An SBE (Single Bit Error) signal 009 is a signal notifying that a correctable failure has been detected.
Note that the effect obtained by the maintenance determination device 40 according to the embodiment of the present invention does not depend on the error detection / error correction circuit 30.

  As shown in FIG. 1, the maintenance determination device 40 includes a STATUS_R [n] decision logic unit 401, a STATUS_W [n] decision logic unit 402, a time monitoring unit 403, a STATUS_R [n] status storage register 404, A STATUS_W [n] status storage register 405 and a notification unit 406 are provided.

FIG. 2 is a truth table showing the operation of the STATUS_R [n] decision logic unit 401. The truth table shown in FIG. 2 shows the value of the STATUS_R [n] status storage register 404 when the memory operation of the word WD [n] is read and a failure in which the state of the memory can be corrected has occurred. 1 is shown. Further, the truth table shown in FIG. 2 shows that when the memory operation of the word WD [n] is read and there is no failure that can correct the state of the memory, the STATUS_R [n] status storage register 404 Indicates that the value does not change. The truth table shown in FIG. 2 indicates that when the memory operation of the word WD [n] is a write, the value of the STATUS_R [n] status storage register 404 is not changed regardless of the state of the memory. In the truth table shown in FIG. 2, when the memory operation of the word WD [n] is other than read / write, the value of the STATUS_R [n] status storage register 404 is not changed regardless of the state of the memory. Indicates. Also, the truth table shown in FIG. 2 indicates that the value of the STATUS_R [n] status storage register 404 is set to 0 when a preset monitoring time has elapsed or when the RESET signal 011 is input. .
[N] indicates a memory configuration unit. For example, when the memory 10 has an X word configuration, [n] is [0], [1], [2],. Note that a word is an example of a memory area having a certain data length.
The STATUS_R [n] decision logic unit 401 selects STATUS_R [n] by operating like the truth table shown in FIG. 2 based on the read address indicated by the READ / WRITE / ADDRESS signal 001.
Specifically, the READ / WRITE • ADDRESS signal 001 input to the STATUS_R [n] decision logic unit 401 determines whether the STATUS_R [n] decision logic unit 401 is an access to its own word WD [n]. Is an input signal.
The WRITE_ENABLE signal 002 and the CHIP / ENABLE signal 003 input to the STATUS_R [n] determination logic unit 401 indicate whether the memory operation is a read operation, a write operation, or neither. This is an input signal for determination.
An SBE (Single Bit Error) signal 009 input to the STATUS_R [n] decision logic unit 401 is an input for the STATUS_R [n] decision logic unit 401 to determine whether a fault that can be corrected by the memory operation is detected. Signal.
The STATUS_R [n] decision logic unit 401, if the memory operation of the word WD [n] is a read operation and the failure of the status of the memory 10 is correctable in the word WD [n], the STATUS_R [n] Instructs the status storage register 404 to be 1, which is a value indicating that a correctable fault has occurred.

FIG. 3 is a truth table showing the operation of the STATUS_W [n] decision logic unit 402. The truth table shown in FIG. 3 relates to the value of the STATUS_R [n] status storage register 404 when the memory operation of the word WD [n] is a read operation and a failure in which the memory state can be corrected has occurred. STATUS_W [n] indicates that the value of the status storage register 405 is not changed. Also, the truth table shown in FIG. 3 shows the value of the STATUS_R [n] status storage register 404 when the memory operation of the word WD [n] is read and there is no failure in which the memory state can be corrected. Regardless of whether or not the value of the STATUS_W [n] status storage register 405 is not changed. In the truth table shown in FIG. 3, when the memory operation of the word WD [n] is a write and the value of the STATUS_R [n] status storage register 404 is 0, the STATUS_W [ n] Indicates that the value of the status storage register 405 is not changed. In the truth table shown in FIG. 3, when the memory operation of the word WD [n] is a write and the value of the STATUS_R [n] status storage register 404 is 1, the STATUS_W [ n] Indicates that the value of the status storage register 405 is set to 1. Further, the truth table shown in FIG. 3 shows that when the memory operation of the word WD [n] is other than reading / writing, the STATUS_W [n] is independent of the state of the memory and the value of the STATUS_R [n] status storage register 404. ] Indicates that the value of the status storage register 405 is not changed. Also, the truth table shown in FIG. 3 indicates that the value of the STATUS_W [n] status storage register 405 is set to 0 when a preset monitoring time has elapsed or when the RESET signal 011 is input. .
The STATUS_W [n] decision logic unit 402 selects STATUS_W [n] by operating like the truth table shown in FIG. 3 based on the write address indicated by the READ / WRITE / ADDRESS signal 001.
Specifically, the READ / WRITE • ADDRESS signal 001 input to the STATUS_W [n] decision logic unit 402 determines whether the STATUS_W [n] decision logic unit 402 is an access to its own word WD [n]. Is an input signal.
The WRITE_ENABLE signal 002 and the CHIP / ENABLE signal 003 input to the STATUS_W [n] decision logic unit 402 indicate whether the memory operation is a read operation, a write operation, or neither. This is an input signal for determination.
The signal acquired from the STATUS_R [n] status storage register 404 input to the STATUS_W [n] decision logic unit 402 indicates whether or not a previously correctable failure has occurred in the word WD [n]. This is an input signal for determination by the decision logic unit 402.
The STATUS_W [n] determination logic unit 402, when the memory operation is a write to the word WD [n] and the value of the STATUS_R [n] status storage register 404 is 1, the STATUS_W [n] status storage register. Instructs the value of 405 to be 1.

Note that the STATUS_R [n] determination logic unit 401 determines a situation using a signal necessary for a read or write operation of the memory 10 and held in the register 20 at the timing of one clock, and then determines the next one clock. The determination result is stored in the STATUS_R [n] status storage register 404 at the timing. Further, the STATUS_W [n] determination logic unit 402 determines a situation using a signal necessary for a read or write operation of the memory 10 and held in the register 20 at the timing of one clock, and then determines the next one clock. The determination result is stored in the STATUS_W [n] status storage register 405 at the timing.
Therefore, the determination result of the situation by the STATUS_R [n] decision logic unit 401 and the STATUS_W [n] decision logic unit 402 is updated at a timing delayed by one clock from reading and writing. Therefore, when the STATUS_R [n] status storage register 404 or the STATUS_W [n] status storage register 405 is read at the timing when a correctable failure occurs, the situation before the influence of the correctable failure is reflected. Will be read.

The time monitoring unit 403 is, for example, a counter and measures a certain time after a correctable failure of the word WD [n] occurs.
Specifically, the signal from the STATUS_R [n] determination logic unit 401 in the time monitoring unit 403 is an input signal for determining that a correctable failure has occurred in the word WD [n].
The TIME signal 010 in the time monitoring unit 403 is a timer signal such as a real time TOD (Time Of Day) or a 1 microsecond amplitude signal. The TIME signal 010 is a signal for measuring time, and the type is not limited as long as the signal can know the time.
A RESET signal 011 in the time monitoring unit 403 is an initialization of the entire maintenance determination system 1 or a local RESET instruction signal.
If the signal from the STATUS_R [n] decision logic unit 401 is 1 (= a failure that can be corrected by the word WD [n] occurs), the time monitoring unit 403 starts measuring time from 0.
Here, the time monitoring unit 403 is measuring time is referred to as monitoring.
When the time monitoring unit 403 receives a signal with a value of 1 indicating that a correctable failure has occurred in the word WD [n] from the STATUS_R [n] decision logic unit 401 again during monitoring, the time monitoring unit 403 resets the time to 0. Resume time measurement.
The time monitoring unit 403 receives the STATUS_R [n] status storage register 404 of the word WD [n] and the STATUS_W [n when a predetermined time has elapsed during monitoring or when the RESET signal 011 is received. Instructs the status storage register 405 to reset.

  The STATUS_R [n] status storage register 404 is a register that stores the presence or absence of occurrence of a correctable failure for the word WD [n].

  The STATUS_W [n] status storage register 405 is a register that stores the presence / absence of writing of the word after occurrence of a correctable failure with respect to the word WD [n].

When there is a correctable failure, the STATUS_R [n] status storage register 404 and the STATUS_W [n] status storage register 405 store the write history after the occurrence of the correctable failure at the corresponding address. Are stored as a combination of 1 bit of the STATUS_R [n] status storage register 404 and 1 bit of the STATUS_W [n] status storage register 405 corresponding to each word unit.
In FIG. 1, an arbitrary word WD [n] is shown. In the STATUS_R [n] status storage register 404 and the STATUS_W [n] status storage register 405, [n] indicates a status storage register for the word WD [n] in the memory configuration unit. For example, when the memory 10 has an X word configuration, [n] is [0], [1], [2],.
Further, each of the STATUS_R [n] decision logic unit 401, the STATUS_W [n] decision logic unit 402, the time monitoring unit 403, the STATUS_R [n] status storage register 404, and the STATUS_W [n] status storage register 405 includes each word. There are X corresponding to each.

  The notification unit 406 notifies a maintenance determination result based on the value of the STATUS_R [n] status storage register 404 and the value of the STATUS_W [n] status storage register 405.

Next, processing of the maintenance determination system 1 according to an embodiment of the present invention will be described.
Here, a processing flow of the maintenance determination system 1 shown in FIG. 4 will be described.
Here, in order to simplify the description, the process of the maintenance determination system 1 will be described by taking the process for an arbitrary word WD [n] as an example.

When the maintenance determination system 1 starts up, each of the STATUS_R [n] status storage register 404 and the STATUS_W [n] status storage register 405 initializes the value held in the register to 0 (step S1).
Each of the STATUS_R [n] status storage register 404 and the STATUS_W [n] status storage register 405 is a value immediately after initialization or in a state where no correctable fault has occurred for a preset fixed time. Is 0.

  When the maintenance determination system 1 starts up, each of the memory 10, the register 20, the error detection / error correction circuit 30, and the maintenance determination device 40 starts operation.

  The STATUS_R [n] decision logic unit 401 determines whether or not there is a read in the word WD [n]. If it is determined that there is a read, a correctable failure occurs in the word WD [n]. It is determined whether or not (step S2).

  If the STATUS_R [n] decision logic unit 401 determines that a correctable failure has occurred in the word WD [n] (YES in step S2), the STATUS_R [n] determination unit 401 stores 1 in the STATUS_R [n] status storage register 404 (step S2). S3).

The time monitoring unit 403 starts the time measurement from 0 when the signal from the STATUS_R [n] decision logic unit 401 becomes 1 (= a failure that can be corrected by the word WD [n] occurs) (step S4).
Then, the time monitoring unit 403 determines whether monitoring is in progress (step S5).

  If the STATUS_R [n] decision logic unit 401 determines that no correctable failure has occurred in the word WD [n] (NO in step S2), the STATUS_W [n] decision logic unit 402 selects the word WD [n]. n] is determined (step S6).

  If the STATUS_W [n] decision logic unit 402 determines that there is a write to the word WD [n] (YES in step S6), the STATUS_R [n] decision logic unit 401 sets the STATUS_R [n] status storage register 404 to 0. It is determined whether or not (step S7).

When the STATUS_R [n] decision logic unit 401 determines that the STATUS_R [n] status storage register 404 is not 0 (NO in step S7), the STATUS_W [n] decision logic unit 402 is for STATUS_W [n] status storage. 1 is stored in the register 405 (step S8).
Then, the STATUS_W [n] determination logic unit 402 proceeds to the process of step S5.

  If the STATUS_W [n] decision logic unit 402 determines that the word WD [n] is not written (NO in step S6), the STATUS_W [n] determination logic unit 402 proceeds to the process of step S5.

If the STATUS_R [n] determination logic unit 401 determines that the STATUS_R [n] status storage register 404 is 0 (YES in step S7), the process proceeds to step S5.
When time monitoring unit 403 determines that word WD [n] is being monitored (YES in step S5), time monitoring unit 403 determines whether or not a predetermined monitoring time has elapsed for word WD [n]. (Step S9).

When the time monitoring unit 403 determines that a predetermined monitoring time set for the word WD [n] has elapsed (YES in step S9), the STATUS_R [n] decision logic unit 401 stores the STATUS_R [n] status storage. The STATUS_W [n] decision logic unit 402 instructs the STATUS_W [n] status storage register 405 to reset, and the time monitoring unit 403 ends the monitoring, that is, the time measurement. (Step S10).
Then, the time monitoring unit 403 returns to the process of step S2.

If the time monitoring unit 403 determines that the preset monitoring time for the word WD [n] has not elapsed (NO in step S9), the time monitoring unit 403 adds the monitoring time, that is, the measurement time ( Step S11).
Then, the time monitoring unit 403 returns to the process of step S2.

Note that the maintenance determination system 1 repeats one loop of a processing flow that loops with one stroke in each process of the above-described steps S2 to S11 for each cycle of the memory operation.
In addition, when the maintenance determination system 1 detects the occurrence of a correctable failure for the word WD [n] in the state where the measurement time is added in the process of step S11, the maintenance determination system 1 returns the monitoring time to 0 and continues monitoring.
In addition, when there is a reset instruction other than initialization, the maintenance determination system 1 asynchronously sets the values of the STATUS_R [n] status storage register 404 and the STATUS_W [n] status storage register 405 to zero.

The notification unit 406 notifies a maintenance determination result based on the value of the STATUS_R [n] status storage register 404 and the value of the STATUS_W [n] status storage register 405. Further, the notification unit 406 may notify the value of the STATUS_R [n] status storage register 404 and the value of the STATUS_W [n] status storage register 405 as the maintenance determination result.
The notification unit 406 may constantly notify the maintenance determination result while the maintenance determination system 1 is activated.

Next, the effect of the maintenance judgment (replacement judgment) for the corresponding part when a correctable failure occurs will be described with reference to FIGS.
5 and 6, the notification unit 406 reports the maintenance determination result based on the value of the STATUS_R [n] status storage register 404 and the value of the STATUS_W [n] status storage register 405 in the corresponding case. It is an example.

  The values of the STATUS_R [n] status storage register 404 and the STATUS_W [n] status storage register 405 according to an embodiment of the present invention are extracted from the maintenance determination device 40 when a correctable failure occurs and By registering and referring to the log, maintenance personnel and the like use this value to make a maintenance decision (replacement decision).

  Note that the timing at which the values of the STATUS_R [n] status storage register 404 and the STATUS_W [n] status storage register 405 are extracted is when a correctable failure occurs, and the values of these registers are generated this time. It should be noted that this is the situation before the effects of the correctable failure were reflected.

  FIG. 5 shows an example of the relationship between the values of the STATUS_R [n] status storage register 404 and the STATUS_W [n] status storage register 405 and the situation when a correctable failure of the word WD [n] in the memory 10 occurs. FIG.

When the value of the STATUS_R [n] status storage register 404 is 0 and the value of the STATUS_W [n] status storage register 405 is 0, this indicates that there is no history of occurrence of a correctable failure within a certain period.
Therefore, it can be determined that “this failure occurs for the first time after a lapse of a certain time”. This case is defined as (A).

  There is logically no combination in which the value of the STATUS_R [n] status storage register 404 is 0 and the value of the STATUS_W [n] status storage register 405 is 1. This case is defined as (B).

When the value of the STATUS_R [n] status storage register 404 is 1 and the value of the STATUS_W [n] status storage register 405 is 0, the value of the STATUS_R [n] status storage register 404 is 1. There is a history of occurrence of a correctable failure within a certain period, but since the value of the STATUS_W [n] status storage register 405 is 0, writing to the same word WD [n] after a correctable failure occurs Has not been.
Therefore, it can be determined that “the present failure is a correctable failure a plurality of times, and the word WD [n] is not updated after the case (A)”. This case is defined as (C).

When the value of the STATUS_R [n] status storage register 404 is 1 and the value of the STATUS_W [n] status storage register 405 is 1, the value of the STATUS_R [n] status storage register 404 is 1. Since there is a history of occurrence of a correctable failure within a certain period and the value of the STATUS_W [n] status storage register 405 is 1, writing to the same word WD [n] after a correctable failure occurs There is.
Therefore, it can be determined that “the present failure is a correctable failure a plurality of times and the word WD [n] is updated after the case (A)”. This case is defined as (D).

FIG. 6 summarizes the maintenance judgment of cases (A) to (D) shown in FIG.
Case (A) is the first failure after a lapse of a certain time, and is not replaced because the maintenance replacement standard is not reached. The maintenance replacement standard is a standard for replacing parts in which a correctable fault has occurred, and is determined by the number of faults per fixed time. For example, the replacement unit part may be replaced when a failure that can be corrected eight times or more has occurred during the past 8 hours.
Case (B) does not logically occur.
In case (C), a correctable failure has occurred a plurality of times, but no further writing has occurred in the word WD [n]. In this case, there may be a soft error. Since there is a possibility of a soft error even if the maintenance replacement standard is reached during operation of the maintenance judgment system 1, if the maintenance replacement is suspended and the test diagnosis program for the suspected part is executed and there is no abnormality, it is determined as a soft error. Do not perform maintenance replacement.
In case (D), a correctable failure has occurred a plurality of times, but since the word WD [n] has been written thereafter and an error has occurred even if the value is rewritten, Can be determined. Therefore, if the maintenance replacement standard is reached, the part is replaced.
Thus, even if the maintenance replacement standard is reached by the maintenance determination of cases (A) to (D), it is possible to prevent replacement of non-failed parts by adding the following determination as the possibility of a soft error. .

The maintenance determination system 1 according to the embodiment of the present invention has been described above.
The maintenance determination apparatus 40 in the maintenance determination system 1 according to the embodiment of the present invention described above can correct one word when a correctable failure occurs in one word when data is read from the memory 10. A STATUS_R [n] decision logic unit 401 (first decision logic unit) that holds information indicating that a failure has occurred in the STATUS_R [n] status storage register 404 (first status storage register). The maintenance determination device 40, when writing a data in the memory 10, if a correctable failure has already occurred for one word, information indicating that a correctable failure has occurred for one word is stored in STATUS_W [ n] A STATUS_W [n] decision logic unit 402 (second decision logic unit) to be held in the status storage register 405 (second status storage register). In the maintenance determination device 40, the STATUS_R [n] determination logic unit 401 stores the information stored in the STATUS_R [n] status storage register 404, and the STATUS_W [n] determination logic unit 402 stores the information in the STATUS_W [n] status storage register 405. An informing unit 406 is provided for informing a maintenance determination result based on the held information.
In this way, the maintenance determination device 40 can distinguish whether a hard error has occurred or a soft error has occurred without stopping the normal information processing without reducing the scale of the device.

When the time monitoring unit 403 determines that a predetermined monitoring time set for the word WD [n] has elapsed, the STATUS_R [n] determination logic unit 401 stores the STATUS_R [n] status storage register 404. Instructing resetting, the STATUS_W [n] decision logic unit 402 instructs the STATUS_W [n] status storage register 405 to reset, and the time monitoring unit 403 ends monitoring, that is, time measurement.
In this way, the maintenance determination device 40 can more accurately determine whether or not a hardware failure has occurred.

Next, the minimum configuration maintenance determination apparatus 40 according to the embodiment of the present invention will be described.
As shown in FIG. 7, the maintenance determination device 40 having the minimum configuration according to the embodiment of the present invention includes a STATUS_R [n] determination logic unit 401 (first determination logic unit) and a STATUS_W [n] determination logic unit 402 (second determination unit). A decision logic unit).

  The STATUS_R [n] decision logic unit 401 (first decision logic unit) has a correctable failure for one word when a correctable failure occurs in one word when data is read from the memory 10. Information indicating the occurrence is stored in the STATUS_R [n] status storage register 404 (first status storage register).

  The STATUS_W [n] decision logic unit 402 (second decision logic unit) allows the maintenance determination device 40 to process one word when a correctable failure has already occurred for one word when data is written to the memory 10. Is stored in the STATUS_W [n] status storage register 405 (second status storage register).

  In this way, the maintenance determination device 40 can distinguish whether a hard error has occurred or a soft error has occurred without stopping the normal information processing without reducing the scale of the device.

  Note that the storage unit and the storage device (including the register) in the present invention may be provided anywhere within a range where appropriate information is transmitted and received. A plurality of storage units and storage devices may exist within a range where appropriate information is transmitted and received, and data may be distributed and stored.

  In the processing flow in the embodiment of the present invention, the order of processing may be changed within a range where appropriate processing is performed.

  In addition, although embodiment of this invention was described, the above-mentioned maintenance determination system 1 and the maintenance determination apparatus 40 have a computer system inside. The process described above is stored in a computer-readable recording medium in the form of a program, and the above process is performed by the computer reading and executing this program. Here, the computer-readable recording medium means a magnetic disk, a magneto-optical disk, a CD-ROM, a DVD-ROM, a semiconductor memory, or the like. Alternatively, the computer program may be distributed to the computer via a communication line, and the computer that has received the distribution may execute the program.

  The program may be for realizing a part of the functions described above. Furthermore, what can implement | achieve the function mentioned above in combination with the program already recorded on the computer system, what is called a difference file (difference program) may be sufficient.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. Various omissions, replacements, and changes can be made without departing from the scope of the invention.

DESCRIPTION OF SYMBOLS 10 ... Memory 20, 20a, 20b, 20c, 20d, 20e, 20f, 20g, 20h, 20i, 20j ... Register 30 ... Error detection / error correction circuit 40 ... Maintenance judgment device 401 ... STATUS_R [n] decision logic unit 402... STATUS_W [n] decision logic unit 403... Time monitoring unit 404... STATUS_R [n] status storage register 405.

Claims (7)

When a correctable fault has occurred in a memory area having a certain data length when data is read from the memory, information indicating that a correctable fault has occurred in the memory area is held in the first status storage register A first decision logic unit to cause
If a correctable fault has already occurred in the memory area when data is written to the memory, information indicating that a correctable fault has occurred in the memory area is held in the second status storage register A second decision logic unit to cause
A maintenance judgment device comprising: Notification for informing a maintenance determination result based on the information held in the first status storage register by the first decision logic unit and the information held in the second status storage register by the second decision logic unit Part,
The maintenance judgment device according to claim 1 provided with. The first status storage register;
The maintenance judgment device according to claim 1 or 2 provided with. The second status storage register;
The maintenance determination apparatus according to any one of claims 1 to 3, further comprising: A time monitoring unit that instructs the first status storage register and the second status storage register to reset when a predetermined time has elapsed;
The maintenance judgment device according to any one of claims 1 to 4, further comprising: Holding a first status storage register with information indicating that a correctable fault has occurred in the memory area when a correctable fault has occurred in a memory area when reading data from the memory;
If a correctable fault has already occurred in the memory area when data is written to the memory, information indicating that a correctable fault has occurred in the memory area is held in the second status storage register And letting
Maintenance judgment method including. On the computer,
Holding a first status storage register with information indicating that a correctable fault has occurred in the memory area when a correctable fault has occurred in a memory area when reading data from the memory;
If a correctable fault has already occurred in the memory area when data is written to the memory, information indicating that a correctable fault has occurred in the memory area is held in the second status storage register And letting
A program that executes

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