JP2018113283A - Interposer and method of manufacturing the same, and semiconductor device comprising interposer - Google Patents

Abstract

Generation of cracks in a substrate is prevented in an interposer manufacturing process or attachment process.
A protective member is disposed on at least a part of the outer periphery of the substrate of the interposer.
[Selection] Figure 1

Description

  The present disclosure relates to an interposer, a manufacturing method thereof, and a semiconductor device including the interposer.

  In recent electronic devices, a form in which a semiconductor chip is attached to a wiring board via an interposer is often used. Patent Document 1 discloses an interposer using glass as a substrate material.

WO2005 / 034594

  In the above-described interposer manufacturing process, the glass substrate is held by a jig, and a laminated structure is formed on the glass substrate. Further, in the interposer attachment process, bumps or the like are formed and attached to the wiring board or semiconductor chip via the bumps. Conventionally, when handling a glass substrate in the above-described manufacturing process or attachment process, there has been a problem that a crack occurs in the glass substrate.

  The present disclosure provides an interposer that can prevent generation of cracks in a substrate in a manufacturing process or an attachment process.

  The present application includes a plurality of means for solving the above-described problems. For example, the first substrate surface, the second substrate surface opposite to the first substrate surface, and the first substrate are provided. A substrate having a third substrate surface connecting the first substrate surface and the second substrate surface, a through electrode that conducts the first substrate surface and the second substrate surface, and disposed on the first substrate surface, A first conductive layer electrically connected to the through electrode; an insulating layer disposed on the first conductive layer; and a second conductive layer disposed on the insulating layer; An interposer is provided in which a protection member is disposed on at least a part of the outer periphery of the interposer.

  According to another example, the first substrate surface, the second substrate surface opposite to the first substrate surface, and the third substrate surface connecting the first substrate surface and the second substrate surface. A substrate having a substrate surface, the substrate having a through hole connecting the first substrate surface and the second substrate surface, and a protective member disposed on at least a part of the outer periphery of the substrate A step of forming a through electrode that conducts between the first substrate surface and the second substrate surface; and a first conductive layer disposed on the first substrate surface and electrically connected to the through electrode. A process for forming an interposer, comprising: a step of forming an insulating layer disposed on the first conductive layer; and a step of forming a second conductive layer disposed on the insulating layer. A method is provided.

  According to another example, the first substrate surface, the second substrate surface opposite to the first substrate surface, and the third substrate surface connecting the first substrate surface and the second substrate surface. A step of preparing a substrate having a substrate surface, a step of disposing a protective member on at least a part of an outer periphery of the substrate, and after the protective member is disposed on the substrate, the first substrate surface and the second substrate A step of forming a through-hole connecting the substrate surface, a step of forming a through-electrode that conducts the first substrate surface and the second substrate surface, and the through-electrode disposed on the first substrate surface. Forming a first conductive layer connected to each other, forming an insulating layer disposed on the first conductive layer, and forming a second conductive layer disposed on the insulating layer And a method for manufacturing an interposer.

  According to the present disclosure, generation of cracks in the substrate can be prevented in the manufacturing process or the mounting process. Further features related to the present disclosure will become apparent from the description of the present specification and the accompanying drawings. Further, problems, configurations, and effects other than those described above will be clarified by the following description of embodiments.

It is a schematic sectional view showing an interposer according to an embodiment of the present disclosure. It is a schematic plan view which shows the board | substrate and protection member which concern on one Embodiment of this indication. It is a schematic plan view which shows the board | substrate and protection member which concern on one Embodiment of this indication. It is a schematic sectional view showing a substrate and a protection member concerning one embodiment of this indication. It is a schematic sectional view showing a substrate and a protection member concerning one embodiment of this indication. It is a figure explaining the manufacturing process of the interposer concerning one embodiment of this indication. (A) is a figure explaining an example of the manufacturing process using the protection member concerning one embodiment of this indication, and (b) is another of the manufacturing process using the protection member concerning one embodiment of this indication. It is a figure explaining an example. It is a figure explaining the method of manufacturing the interposer concerning one embodiment of this indication. It is a figure explaining the method of manufacturing the interposer concerning one embodiment of this indication.

  Hereinafter, an embodiment of the present disclosure will be described with reference to the drawings. In the drawings attached to the present specification, for the sake of illustration and ease of understanding, the scale, the vertical / horizontal dimension ratio, and the like are appropriately changed and exaggerated from those of the actual product.

  In the present specification and the like, a numerical range expressed using “to” means a range including each of the numerical values described before and after “to” as a lower limit value and an upper limit value.

  An interposer according to an embodiment of the present disclosure has a structure in which an insulating layer is sandwiched between conductive layers containing metal or the like. FIG. 1 is a schematic cross-sectional view illustrating an interposer 10 according to an embodiment of the present disclosure. The interposer 10 has, for example, an MIM (Metal-Insulator-Metal) structure in which an insulating layer is sandwiched between metals. The MIM structure can be used as an MIM capacitor, for example. In this case, a part of the first conductive layer 12 becomes a lower electrode, the first insulating layer 13 becomes a dielectric layer, and the second conductive layer 14 becomes an upper electrode. Note that the interposer 10 may have a multilayer wiring structure in which a wiring layer and an insulating layer are sequentially stacked, in addition to the MIM capacitor.

  As an example, the interposer 10 is disposed on the substrate 11 having the first substrate surface 11a and the second substrate surface 11b opposite to the first substrate surface 11a, and the first substrate surface 11a of the substrate 11. A first conductive layer 12, a first insulating layer 13 disposed on the first conductive layer 12, and a second conductive layer 14 disposed on the first insulating layer 13 are provided. The first conductive layer 12 may be disposed directly on the first substrate surface 11a of the substrate 11, or a conductive or insulating layer may be disposed on the first substrate surface 11a of the substrate 11 via at least one layer. It may be arranged.

  The substrate 11 has a through hole 15 penetrating from the first substrate surface 11a to the second substrate surface 11b. The through electrode 16 is an electrode that conducts the first substrate surface 11a and the second substrate surface 11b. The first conductive layer 12 is electrically connected to the third conductive layer 17 disposed on the second substrate surface 11 b through the through electrode 16 formed in the through hole 15. The shape of the through-hole 15 is not limited to the illustration, and the through-hole 15 has a shape in which the width decreases from the first substrate surface 11 a and the second substrate surface 11 b of the substrate 11 toward the central portion in the thickness direction of the substrate 11. Alternatively, the side wall of the through hole 15 may extend along the normal direction of the first substrate surface 11a of the substrate 11, or a part of the side wall may be curved.

  The first conductive layer 12 and the second conductive layer 14 are connected via a connection hole (not shown). That is, the first insulating layer 13 constitutes an insulating film other than the connection hole between the first conductive layer 12 and the second conductive layer 14.

The substrate 11 is a glass substrate. In general, an interposer has a larger displacement due to thermal deformation in a region closer to its edge. In the case of an interposer using a glass substrate, there is an advantage that this region can be dealt with so as to reduce the difference in coefficient of thermal expansion from wiring boards or the like disposed above and below the interposer. The substrate 11 may be a laminate of a glass substrate and another substrate. Examples of other substrates include a quartz substrate, a sapphire substrate, a resin substrate, a silicon substrate, a silicon carbide substrate, an alumina (Al ₂ O ₃ ) substrate, an aluminum nitride (AlN) substrate, and a zirconia oxide (ZrO ₂ ) substrate. . The thickness of the substrate 11 is, for example, 200 μm to 500 μm.

  More preferably, alkali-free glass is used as the substrate 11. Unlike soda glass, alkali-free glass does not contain alkali components such as Na and K, so that alkali components do not elute on the glass surface. Therefore, this aspect has an advantage that a reliability deterioration factor that corrodes the terminal of the semiconductor chip to be connected to the interposer does not occur in principle. Further, the alkali-free glass has a thermal expansion coefficient comparable to that of silicon, and has good consistency in terms of the thermal expansion coefficient in relation to the semiconductor chip to be connected.

  As materials for the first conductive layer 12, the second conductive layer 14, the through electrode 16, and the third conductive layer 17, a conductive material such as Au, Al, or Cu is used. Among them, it is preferable to use Cu having high conductivity and low material cost. The thickness of the first conductive layer 12 is preferably 0.5 to 20 μm, and the thickness of the second conductive layer 14 is preferably 0.5 to 5 μm. For the wiring pattern, in addition to subtractive formation by etching metal foil (for example, Cu), additive formation such as application of conductive paste (for example, metal nanopaste) or formation by plating should be adopted. You can also.

As the first insulating layer 13, for example, an inorganic material can be used. More specifically, silicon nitride (Si _x N _y ), silicon dioxide (SiO ₂ ), silicon oxynitride (SiO _x N _y ), pentoxide Tantalum (Ta ₂ O ₅ ), aluminum oxide (Al ₂ O ₃ ), or aluminum nitride (AlN) can be used.

  In the embodiment of the present disclosure, chemical vapor deposition (CVD), physical vapor deposition (PVD) (for example, sputtering or vapor deposition), electroplating, or the like is used as the film formation process of the conductive layers 12, 14, 17 and the insulating layer 13. Can be used. Also, photolithography can be used to form the pattern of the conductive layer. Also, an etching process can be used to remove unwanted material. Further, etch back, chemical mechanical polishing (CMP), or the like can be used as a planarization process of the conductive layer and the insulating layer.

  Resin layers 18 are formed on both surfaces of the interposer 10. In the resin layer 18, via holes 19 are formed at positions corresponding to the second conductive layer 14 and the third conductive layer 17. In each of the via holes 19, a conductive connection portion 20 is formed. The interposer 10 may be connected to the wiring board 41 via the bumps 40 formed in the connection part 20. Further, the interposer 10 may be connected to the semiconductor chip 42 via the bumps 40 formed in the connection portion 20. According to the interposer 10 of the present embodiment, the mounting of the semiconductor chip 42 with a narrow terminal pitch on the large-sized wiring board (motherboard or the like) 41 is simplified. According to the above-described embodiment, the interposer 10, the semiconductor chip 42 disposed on the first substrate surface 11 a side of the substrate 11 and electrically connected to the through electrode 16, and the second substrate surface 11 b side of the substrate 11. It is possible to provide a semiconductor device having the wiring substrate 41 that is disposed in the substrate and electrically connected to the through electrode 16.

  In the above-described embodiment, between the substrate 11 and the first conductive layer 12, between the first conductive layer 12 and the first insulating layer 13, between the first insulating layer 13 and the second conductive layer 14, An additional layer (not shown) may be formed between the substrate 11 and the third conductive layer 17. As an example, a base layer may be formed between the substrate 11 and the first conductive layer 12. The underlayer may include one or more layers. For example, the underlayer includes at least one of an adhesion layer and a seed layer.

  Next, the configuration of the protection member 21 will be described. The substrate 11 includes a protective member 21 on at least a part of the outer periphery thereof. The protective member 21 includes a first surface 21a serving as an adhesive surface with the substrate 11, a second surface 21b opposite to the first surface 21a, and a third surface 21c that connects the first surface 21a and the second surface 21b. And have. The protection member 21 is, for example, a tape or a resin film. In the case of the tape protection member 21, the second surface 21 b opposite to the adhesive surface may be composed of polyimide tape Kapton (registered trademark, DuPont) or the like. In the case of the resin film protection member 21, for example, polyimide or the like can be used.

  The protection member 21 includes a first portion 22 that covers the end portion of the first substrate surface 11 a of the substrate 11, a second portion 23 that covers the end portion of the second substrate surface 11 b of the substrate 11, and the first portion of the substrate 11. And a third portion 24 covering the third substrate surface 11c connecting the substrate surface 11a and the second substrate surface 11b.

  According to this embodiment, since the protective member 21 is disposed so as to cover the outer periphery of the glass substrate 11, the protective member 21 does not interfere with the manufacturing process and the mounting process of the interposer 10, and glass Generation of cracks from the edge of the substrate can be prevented.

  FIG. 2 is a schematic plan view showing the substrate 11 and the protection member 21 according to an embodiment of the present disclosure, as viewed from the first substrate surface 11 a side of the substrate 11. In FIG. 2, only the board | substrate 11 and the protection member 21 are shown, and the other component in the interposer 10 is abbreviate | omitted. The substrate 11 has a rectangular shape. In addition, the shape of the board | substrate 11 is not limited to a rectangle, Other shapes, such as a circle, may be sufficient. The outer periphery of the substrate 11 includes a first substrate side 11h and a second substrate side 11i, and a third substrate side 11j and a fourth substrate side 11k substantially orthogonal to the first substrate side 11h and the second substrate side 11i. . In the example of FIG. 2, the protection member 21 is disposed so as to cover all of the first substrate side 11h, the second substrate side 11i, the third substrate side 11j, and the fourth substrate side 11k.

  FIG. 3 is a schematic plan view showing the substrate 11 and the protection member 21 according to an embodiment of the present disclosure, as viewed from the first substrate surface 11 a side of the substrate 11. The protection member 21 may be disposed so as to cover a part of the outer periphery of the substrate 11. When the rectangular substrate 11 is held with a jig in the manufacturing process of the interposer 10, the force from the jig is concentrated on the corner portion without being dispersed over the entire substrate, thereby causing cracks from the corner portion or the vicinity thereof. There is a fear. Therefore, the protection member 21 is preferably arranged so as to cover at least the corner portion of the substrate 11. In the example of FIG. 3, the protection member 21 includes a first corner portion 25a between the first substrate side 11h and the third substrate side 11j, and a second corner between the third substrate side 11j and the second substrate side 11i. So as to cover the portion 25b, the third corner portion 25c between the second substrate side 11i and the fourth substrate side 11k, and the fourth corner portion 25d between the fourth substrate side 11k and the first substrate side 11h. Is arranged.

  FIG. 4 is a schematic cross-sectional view illustrating the substrate 11 and the protection member 21 according to an embodiment of the present disclosure. A first corner portion 11d (see FIG. 1) between the first substrate surface 11a and the third substrate surface 11c of the substrate 11, and a first corner portion 11b between the second substrate surface 11b and the third substrate surface 11c of the substrate 11. The corner 11e (see FIG. 1) may be chamfered. In the example of FIG. 4, a round cross section is formed between the first substrate surface 11 a and the third substrate surface 11 c of the substrate 11 and between the second substrate surface 11 b and the third substrate surface 11 c of the substrate 11. Have. The round-shaped cross section can be produced by, for example, performing an R chamfering process. The chamfered portion may have a linear cross section. The linear chamfered portion can be produced by performing C chamfering or the like. In the example of FIG. 4, the entire third substrate surface 11 c has a round cross section, and the protection member 21 is disposed so as to cover the entire third substrate surface 11 c. According to this configuration, it is possible to protect the end portion of the substrate 11 by the protection member 21 while preventing concentration of force on the corner portion when held by the jig. Thereby, generation | occurrence | production of the crack in the board | substrate 11 can be prevented.

FIG. 5 is a schematic cross-sectional view illustrating the substrate 11 and the protection member 21 according to an embodiment of the present disclosure. The protection member 21 may be disposed so as to cover a part of the third substrate surface 11 c of the substrate 11. In the example of FIG. 5, the protection member 21 includes a first protection member 21-1 and a second protection member 21-2. Preferably, the first protective member 21-1 is disposed so as to cover the boundary points _{P 1} between the first substrate surface 11a and the third substrate surface 11c, the second protective member 21-2, the third substrate surface 11c When placed so as to cover the boundary point P ₂ between the second substrate surface 11b.

  Next, the relationship between the laminated structure on the substrate 11 and the protective member 21 will be described. The formulas described below relate to the protective member 21 on the first substrate surface 11a, but can also be applied to the protective member 21 on the second substrate surface 11b.

As shown in FIG. 1, bumps 40 are formed on the interposer 10 to connect to the wiring board 41 and the semiconductor chip 42, and the interposer 10 is attached to the wiring board 41 and the semiconductor chip 42 via the bumps 40. . At this time, if the thickness of the protection member 21 is large, the protection member 21 becomes an obstacle, and workability at the time of bump formation is deteriorated. Therefore, the height of the protective member 21 on the first substrate surface 11a of the substrate 11 is set to _Hp, and the height from the first substrate surface 11a of the substrate 11 to the outermost layer of the stacked structure formed on the first substrate surface 11a. when the height was H _1, it is preferable to satisfy the following (1).
H _p ≦ H ₁ (1)
The height H ₁ is the laminated structure on the first substrate surface 11a, the distance from the first substrate surface 11a is defined at a position where the maximum. Further, the outermost layer of the wiring structure may be a resin layer as shown in FIG. 1 or may be a layer of another material.

Further, if the end portion of the protective member 21 is too close to the region where the laminated structure is formed on the first substrate surface 11a, there is a possibility that the film formation of the conductive layer or the insulating layer near the protective member 21 may be affected. There is. Therefore, when the distance from the end of the protective member 21 to the end of a structure formed on a first substrate surface 11a and the L _1, preferably satisfies the following (2).
1 mm ≦ L ₁ ≦ 10 mm (2)
The distance L _1, of the periphery of the laminated structure formed on the first substrate surface 11a, the distance between the end portion of the protecting member 21 is defined by the minimum position. Further, FIG. 1 shows the case where the end portion of the structure formed on the first substrate surface 11a is the resin layer 18, but this is not a limitation, and the end portion may be the end portion of a layer of another material.

FIG. 6 is a diagram illustrating a manufacturing process of an interposer according to an embodiment of the present disclosure, and shows a process of forming the first insulating layer 13 on the first conductive layer 12. After the first insulating layer 13 is formed on the first conductive layer 12, the photomask 26 is disposed with a predetermined gap. Thereafter, an exposure process is performed by an exposure apparatus (not shown). At this time, the height H _p of the protection member 21 is large, the gap between the photomask 26 and the first insulating layer 13 is increased, the resolution failure. Therefore, when the height from the substrate 11 to the upper surface of the first insulating layer 13 is H ₂ , the height H _p of the protective member 21 satisfies the following (3) in consideration of the arrangement of the photomask 26 and the like. Is preferred.
H _p ≦ H ₂ +10 μm (3)
The height H ₂ is defined as the height from the first substrate surface 11 a of the substrate 11 to the lower surface of the second conductive layer 14. This is because a plurality of insulating layers may be stacked in the stacked structure on the substrate 11, and it may be difficult to specify the boundary between the first insulating layer 13 and another insulating layer.

More preferably, the height H _p of the protection member 21 satisfies the following (4).
H _p ≦ H ₂ (4)

  FIG. 7 is a diagram for explaining a manufacturing process of the interposer, and shows a process of forming the first conductive layer 12 on the first substrate surface 11 a of the substrate 11. Here, a case where the first conductive layer 12 is formed by forming the resist layer 28 on the base layer (seed layer) 27 and then growing the plating layer will be described. The plating layer is formed by an electrolytic plating method in which the base layer 27 is energized. Specifically, the electrolytic plating jig 30 is disposed at the end of the substrate 11 (position on the protective member 21 side), and power is supplied by the jig 30 through the electrolytic plating seed layer 29.

Fig.7 (a) is a figure explaining an example of the manufacturing process using the protection member 21 which concerns on one Embodiment of this indication. For the protection member 21 in FIG. 7 (a), the angle theta ₁ of the third surface 21c of the first substrate surface 11a and the protective member 21 is greater than 120 ° of the substrate 11. In this case, the base layer 27 and the electroplating seed layer 29 may be divided on the third surface 21 c of the protection member 21. In this case, the base layer 27 cannot be energized by the jig 30, and as a result, the growth of the plating layer does not proceed. When the underlying layer 27 and the electroplating seed layer 29 are not divided by the conductive material deposited / deposited during the manufacturing process, or when the first conductive layer 12 is formed by a film forming process other than the electrolytic plating method described above. In this case, the first conductive layer 12 can be formed regardless of the value of the angle θ ₁ .

Drawing 7 (b) is a figure explaining an example of a manufacturing process using protection member 21 concerning one embodiment of this indication. Considering the above-described FIG. 7A, the angle θ ₁ preferably satisfies the following (5).
θ ₁ ≦ 120 ° (5)
According to this configuration, as shown in FIG. 7B, the base layer 27 and the electroplating seed layer 29 can be energized by the jig 30 without being divided. As a result, the plating layer grows and the first conductive layer 12 can be formed.

  Next, with reference to FIG.8 and FIG.9, it is a figure explaining the method to manufacture the interposer 10 which concerns on one Embodiment of this indication.

  FIG. 8 is a diagram illustrating a method for manufacturing the interposer 10 according to an embodiment of the present disclosure. As shown in FIG. 8A, a substrate 11 having a through hole 15 for connecting the first substrate surface 11a and the second substrate surface 11b is prepared. The through hole 15 is formed by a technique such as laser processing or etching.

  As shown in FIG. 8B, the protective member 21 is disposed on at least a part of the outer periphery of the substrate 11. In this example, the protection member 21 includes an end portion of the first substrate surface 11a, an end portion of the second substrate surface 11b, and a third substrate surface 11c that connects the first substrate surface 11a and the second substrate surface 11b. Arranged to cover. When the protection member 21 is a tape, the protection member 21 can be formed by bonding the tape to the outer periphery of the substrate 11. Further, when the protective member 21 is a resin film, for example, the protective member 21 is formed by applying a photosensitive resin so as to include at least a part of the outer periphery of the substrate 11 and patterning the applied film by photolithography. be able to.

  As shown in FIG. 8C, the through electrode 16 is formed in the through hole 15. In this embodiment, the protective member 21 is disposed after the through electrode 16 is formed. However, the present invention is not limited to this, and the protective member 21 may be disposed before the through electrode 16 is formed.

  As shown in FIG. 8D, the first conductive layer 12 and the third conductive layer 17 electrically connected to the through electrode 16, the first insulating layer 13 disposed on the first conductive layer 12, the first The second conductive layer 14 disposed on the first insulating layer 13 is sequentially formed to manufacture the interposer 10. As described above, by disposing the protective member 21 on at least a part of the outer periphery of the substrate 11, damage to the outer periphery of the substrate 11 can be suppressed.

  In the above-described manufacturing method, even if a process in which the first conductive layer 12, the through electrode 16, and the third conductive layer 17 are simultaneously formed by performing electroplating after forming the resist layer is performed. Good.

  Furthermore, FIG. 9 is a diagram illustrating a method for manufacturing the interposer 10 according to an embodiment of the present disclosure. As shown in FIG. 9A, a substrate 11 having a first substrate surface 11a, a second substrate surface 11b, and a third substrate surface 11c is prepared.

  As shown in FIG. 9B, the protective member 21 is disposed on at least a part of the outer periphery of the substrate 11. In this example, the protection member 21 includes an end portion of the first substrate surface 11a, an end portion of the second substrate surface 11b, and a third substrate surface 11c that connects the first substrate surface 11a and the second substrate surface 11b. Arranged to cover. When the protection member 21 is a tape, the protection member 21 can be formed by bonding the tape to the outer periphery of the substrate 11. Further, when the protective member 21 is a resin film, for example, the protective member 21 is formed by applying a photosensitive resin so as to include at least a part of the outer periphery of the substrate 11 and patterning the applied film by photolithography. be able to.

  As shown in FIG. 9C, a through hole 15 that connects the first substrate surface 11a and the second substrate surface 11b is formed. The through hole 15 is formed by a technique such as laser processing or etching.

  As shown in FIG. 9D, the through electrode 16 is formed in the through hole 15.

  As shown in FIG. 9 (e), the first conductive layer 12 and the third conductive layer 17 electrically connected to the through electrode 16, the first insulating layer 13 disposed on the first conductive layer 12, the first The second conductive layer 14 disposed on the first insulating layer 13 is sequentially formed to produce the interposer 10. As described above, by disposing the protective member 21 on at least a part of the outer periphery of the substrate 11, damage to the outer periphery of the substrate 11 can be suppressed.

In addition, in embodiment shown in FIGS. 1-9, the protection member 21 may be comprised by two or more layers. When the protection member 21 includes a plurality of layers, the protection member 21 may include a first layer that contacts the substrate 11 and a second layer on the first layer. In this case, the second layer may be configured to be peelable from the first layer. For example, the second layer may be an additional layer that is attached to the first layer after the interposer 10 is manufactured and can be peeled off from the first layer before bump formation. In this case, the height of the first layer that actually affects the manufacturing process and the mounting process corresponds to the height H _p of the protective member 21 in the above-described formula.

  Note that the present disclosure is not limited to the above-described embodiment, and includes other various modifications. For example, the above-described embodiments have been described in detail in order to easily understand the present disclosure, and are not necessarily limited to those having all the configurations described. In addition, a part of the configuration of an embodiment may be replaced with the configuration of another embodiment, and the configuration of another embodiment may be added to the configuration of an embodiment. In addition, it is possible to add, delete, and replace other configurations for a part of the configuration of each embodiment.

DESCRIPTION OF SYMBOLS 10 ... Interposer 11 ... Board | substrate 12 ... 1st conductive layer 13 ... 1st insulating layer 14 ... 2nd conductive layer 15 ... Through-hole 16 ... Through-electrode 17 ... 3rd conductive layer 18 ... Resin layer 19 ... Via hole 20 ... Connection part DESCRIPTION OF SYMBOLS 21 ... Protection member 22 ... 1st part 23 of a protection member ... 2nd part 24 of a protection member ... 3rd part 40 of a protection member ... Bump 41 ... Wiring board 42 ... Semiconductor chip

Claims (12)

A substrate having a first substrate surface, a second substrate surface opposite to the first substrate surface, and a third substrate surface connecting the first substrate surface and the second substrate surface;
A through electrode that conducts between the first substrate surface and the second substrate surface;
A first conductive layer disposed on the first substrate surface and electrically connected to the through electrode;
An insulating layer disposed on the first conductive layer;
A second conductive layer disposed on the insulating layer,
An interposer in which a protective member is disposed on at least a part of the outer periphery of the substrate.   The protective member includes a first portion that covers an end portion of the first substrate surface, a second portion that covers an end portion of the second substrate surface, and a third portion that covers at least a part of the third substrate surface. The interposer according to claim 1, comprising: When the height of the protective member on the first substrate surface is H _p and the height from the substrate to the outermost layer of the structure formed on the substrate is H ₁ ,
H _p ≦ H ₁
The interposer according to claim 1 or 2, wherein When the height from the substrate to the upper surface of the insulating layer and H _2,
H _p ≦ H ₂ +10 μm
The interposer according to claim 3, wherein The interposer according to claim 4, wherein H _p ≦ H ₂ . When the distance from the end of the protective member to the end portion of the structures formed on the first substrate surface and the L _1,
1 mm ≦ L ₁ ≦ 10 mm
The interposer according to any one of claims 1 to 5, wherein The protective member has a first surface that contacts the substrate, a second surface opposite to the first surface, and a third surface that connects the first surface and the second surface;
When an angle between the third surface of the protective member and the first substrate surface and the theta _1,
θ ₁ ≦ 120 °
The interposer according to any one of claims 1 to 6.   The section between the first substrate surface and the third substrate surface of the substrate and between the second substrate surface and the third substrate surface of the substrate have a round or linear cross section. Item 8. The interposer according to any one of Items 1 to 7.   The interposer according to any one of claims 1 to 8, wherein the substrate includes a glass substrate. The interposer according to any one of claims 1 to 9,
A semiconductor chip disposed on the first substrate surface side of the substrate of the interposer and electrically connected to the through electrode;
A semiconductor device comprising: a wiring substrate disposed on the second substrate surface side of the substrate and electrically connected to the through electrode. A substrate having a first substrate surface, a second substrate surface opposite to the first substrate surface, and a third substrate surface connecting the first substrate surface and the second substrate surface. Preparing the substrate having a through hole connecting the first substrate surface and the second substrate surface;
Arranging a protective member on at least a part of the outer periphery of the substrate;
Forming a through electrode that conducts between the first substrate surface and the second substrate surface;
Forming a first conductive layer disposed on the first substrate surface and electrically connected to the through electrode;
Forming an insulating layer disposed on the first conductive layer;
Forming a second conductive layer disposed on the insulating layer. A substrate having a first substrate surface, a second substrate surface opposite to the first substrate surface, and a third substrate surface connecting the first substrate surface and the second substrate surface is prepared. Process,
Arranging a protective member on at least a part of the outer periphery of the substrate;
Forming a through-hole connecting the first substrate surface and the second substrate surface after the protective member is disposed on the substrate;
Forming a through electrode that conducts between the first substrate surface and the second substrate surface;
Forming a first conductive layer disposed on the first substrate surface and electrically connected to the through electrode;
Forming an insulating layer disposed on the first conductive layer;
Forming a second conductive layer disposed on the insulating layer.

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