JP2018107663A - Digital signal offset adjustment device and digital signal offset adjustment method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a device and method for performing digital signal offset adjustment.SOLUTION: The digital signal offset adjustment device comprises: a capacitor 3 provided between an input terminal 2 and an output terminal 4; a coil 8 for bias application having one end side connected to the output terminal 4; a coil 6 for low frequency extraction for allowing DC components and low frequency components of a digital signal input to the input terminal 2 to pass; a DC voltage generator 5 for outputting a DC signal having an arbitrary voltage; and a synthesis circuit 7 for synthesizing the DC signal output from the DC voltage generator 5 with a signal output from the other end of the coil 6 for low frequency extraction, and for supplying a signal obtained by synthesis to the other end side of the coil 8 for bias application. A switching part 9 constituted of a switch circuit 9a including a series circuit composed of a contact S1 to be ON/OFF controlled and a first resistance R1 and a first capacitor C1 connected in parallel with the series circuit is connected in series between the coil 6 for low frequency extraction and the synthesis circuit 7.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a digital signal offset adjusting apparatus and a digital signal offset adjusting method for outputting an arbitrary bias voltage to a digital signal.

  Various digital communication devices in recent years are required to have a larger capacity transmission capability with the increase in the number of users and the spread of multimedia communication. One of the indexes for evaluating the quality of digital signals in these digital communication devices. A bit error rate (hereinafter abbreviated as an error rate) defined as a comparison between the number of received code errors and the total number of received data is known.

  Therefore, when a desired digital communication device is a device under test and an error rate of the device under test is measured, for example, an error rate measuring device disclosed in Patent Document 1 below is used. In this type of error rate measurement device, in order to measure how much electrical stress can be tolerated by the device under test, an electrical stress signal of a known pattern is applied as a test signal from the pattern generator, and this test signal is applied. Jitter tolerance measurement is performed in which a loopback is performed inside or outside the object to be measured, received by an error detector, and compared with a test signal to measure the presence or absence of an error with respect to an applied amount of stress.

  Also, when receiving a digital signal that is looped back inside or outside the object to be measured by the error detector of the error rate measuring apparatus described above, an arbitrary bias voltage is applied to the digital signal for output, and digital signal offset adjustment is performed. As an apparatus, for example, one disclosed in Patent Document 2 below is known.

JP 2007-274474 A Japanese Patent No. 4261555

  By the way, the digital signal offset adjusting device of the above-mentioned patent document 2 is adopted as the signal receiving unit in the error rate measuring device of the above-mentioned patent document 1, and an object to be measured is assumed to be an AC connection for connection between input and output. In the digital signal offset adjusting device of Patent Document 2, the DC signal is always connected, and if the DC component of the output signal from the object to be measured is 0, there is no problem with the DC connection, but the output signal from the object to be measured When the direct current component is not 0, current continues to flow from the object to be measured, which has a problem of adversely affecting the measurement. For this reason, as a countermeasure, for example, a configuration in which a DC block circuit typified by a capacitor or the like is separately provided as an external circuit is adopted, and AC connection is made between the input and output.

  However, in the configuration in which the DC block circuit is provided as an external circuit, the transmission loss of the DC block circuit itself may adversely affect the measurement result when AC connection is made. For this reason, there has been a demand for a digital signal offset adjusting device that can realize direct current connection and alternating current connection with a simple configuration without adversely affecting measurement results.

  Therefore, the present invention has been made in view of the above-described problems, and provides a digital signal offset adjustment device and a digital signal offset adjustment method capable of realizing a DC connection and an AC connection with a simple configuration. It is aimed.

In order to achieve the above object, a digital signal offset adjusting device according to claim 1 of the present invention includes an input terminal 2 and an output terminal 4,
A capacitor 3 provided between the input terminal and the output terminal and transmitting an alternating current component of the digital signal Di input to the input terminal to the output terminal;
A bias applying coil 8 having one end connected to the output terminal;
A low frequency extraction coil 6 having one end connected to the input terminal and passing a DC component and a low frequency component of the digital signal input to the input terminal;
A DC voltage generator 5 for outputting a DC signal of an arbitrary voltage;
The signal output from the other end of the low frequency extraction coil is combined with the DC signal output from the DC voltage generator, and the resultant signal is combined with the other end of the bias applying coil. In the digital signal offset adjusting device 1 provided with the synthesizing circuit 7 to be supplied to
A switching unit 9 including a switch circuit 9a made of a semiconductor relay is connected in series between the low-frequency extraction coil and the synthesis circuit.

The digital signal offset adjusting device according to claim 2 is the digital signal offset adjusting device according to claim 1,
An auxiliary circuit 9b comprising a capacitor C2 or a series circuit of the capacitor and a resistor R2 is connected in parallel to the switch circuit 9a of the switching unit 9.

The digital signal offset adjustment method according to claim 3 includes an input terminal 2 and an output terminal 4;
A capacitor 3 provided between the input terminal and the output terminal and transmitting an alternating current component of the digital signal Di input to the input terminal to the output terminal;
A bias applying coil 8 having one end connected to the output terminal;
A low frequency extraction coil 6 having one end connected to the input terminal and passing a DC component and a low frequency component of the digital signal input to the input terminal;
A DC voltage generator 5 for outputting a DC signal of an arbitrary voltage;
The signal output from the other end of the low frequency extraction coil is combined with the DC signal output from the DC voltage generator, and the resultant signal is combined with the other end of the bias applying coil. In the digital signal offset adjustment method using the digital signal offset adjustment device 1 provided with the synthesis circuit 7 to be supplied to
The switching part 9 provided with the switch circuit 9a which consists of a semiconductor relay includes the step connected in series between the said low frequency extraction coil and the said synthetic | combination circuit, It is characterized by the above-mentioned.

The digital signal offset adjustment method according to claim 4 is the digital signal offset adjustment method according to claim 3,
The switch circuit 9a of the switching unit 9 includes a step of connecting in parallel an auxiliary circuit 9b composed of a capacitor C2 or a series circuit of the capacitor and a resistor R2.

  According to the present invention, the switching unit includes a switch circuit including a semiconductor relay including an on-resistance and an off-capacitance, and the switching unit is connected in series between the low-frequency extraction coil and the synthesis circuit. DC connection can be realized with a simple configuration.

  In addition, if an auxiliary circuit consisting of a capacitor or a series circuit of a capacitor and a resistor is connected in parallel to the switch circuit as a switching unit, the possibility of causing waveform distortion and oscillation of the digital signal offset adjustment device is reduced, and the AC current is close to ideal. Connection can be realized.

It is a figure which shows 1st Embodiment of the digital signal offset adjustment apparatus which concerns on this invention. It is a figure which shows 2nd Embodiment of the digital signal offset adjustment apparatus which concerns on this invention. It is a figure which shows a frequency characteristic when the switch circuit in the digital signal offset adjustment apparatus of FIG.1 and FIG.2 is ON. It is a figure which shows the frequency characteristic when the switch circuit in the digital signal offset adjustment apparatus of FIG. 1 is OFF. It is a figure which shows the frequency characteristic when the switch circuit in the digital signal offset adjustment apparatus of FIG. 2 is OFF.

  Hereinafter, embodiments for carrying out the present invention will be described in detail with reference to the accompanying drawings.

  A digital signal offset adjusting device (hereinafter, abbreviated as an offset adjusting device) according to the present invention outputs a digital signal by applying an arbitrary bias voltage to the first embodiment shown in FIG. 1 or FIG. The second embodiment is configured. Each embodiment will be described below.

[First Embodiment]
As shown in FIG. 1, the offset adjusting apparatus 1 (1A) of the first embodiment includes an input terminal 2, a capacitor 3, an output terminal 4, a DC voltage generator 5, a first coil 6, a synthesis circuit 7, a first circuit 2 coil 8, switching part 9 (9A), and control part 10 are comprised roughly.

  A digital signal Di having a broadband frequency characteristic including a low frequency component, a direct current component, and a high frequency component is input to the input terminal 2.

  The capacitor 3 is connected between the input terminal 2 and the output terminal 4 and allows the high-frequency component (AC component) of the digital signal Di input from the input terminal 2 to pass through the output terminal 4.

  The output terminal 4 receives the AC component of the digital signal Di input from the input terminal 2 and passed through the capacitor 3, and the DC voltage generator 5 converts the signal input from the input terminal 2 and extracted by the first coil 6. A digital signal Do to which a synthesized signal obtained by synthesizing the generated offset voltage is added is output. The digital signal Do is a device under test (DUT: Device Under Test) such as a PCIe device (for example, a video card, SSD (Solid State Drive), network card, graphics card, etc.) as a test signal. Is input.

  The DC voltage generator 5 generates and outputs an offset voltage based on a desired DC voltage fixed or variably set in advance under the control of the control unit 10.

  The first coil 6 is a low frequency extraction coil connected between the input terminal 2 and the synthesis circuit 7. The first coil 6 passes the low frequency component and the direct current component of the digital signal Di input from the input terminal 2 to the other end side (switching unit 9 side).

  The synthesizing circuit 7 includes a low-frequency component signal and a direct-current component signal of the digital signal Di input from the input terminal 2 via the first coil 6 and the switching unit 9, and an offset voltage output from the DC voltage generator 5. A composite signal obtained by combining is output. The synthesis circuit 7 can be configured by a known circuit such as Patent Document 2, for example.

  The second coil 8 is a bias application coil connected between the synthesis circuit 7 and the output terminal 4. The second coil 8 passes the combined signal input from the combining circuit 7 to the output terminal 4. The first coil 6 and the second coil 8 are inductors used in a general bias T circuit.

  The switching unit 9 (9A) is connected between the first coil 6 and the synthesis circuit 7 in order to switch between direct current connection and alternating current connection with a simple configuration.

  The switching unit 9A is configured by a semiconductor relay including a switch circuit 9a. As shown in FIG. 1, the switch circuit 9 a is an equivalent circuit including a contact S <b> 1 that is switched and controlled by the control unit 10, a resistor (on-resistance: about several Ω), a resistor R <b> 1, and a capacitor (off-capacitance: about 1 to 100 pF) C <b> 1. Consists of.

  Since the DC level of the semiconductor relay is not always constant, the switch circuit 9a needs to use a circuit that does not need to match the DC level with the control system. At this time, for example, a semiconductor relay represented by a photo MOS relay may be used as the switch circuit 9a.

  However, as shown in FIG. 1, the presence of the on-resistance due to the resistor R1 and the off-capacitance due to the capacitor C1 in the equivalent circuit of the switch circuit 9a cannot be ignored. In particular, when the contact S1 of the semiconductor relay is OFF, series resonance occurs due to the input impedance of the first coil 6, the capacitor C1, and the synthesis circuit 7.

  Here, in the offset adjusting apparatus 1A of the first embodiment, FIG. 3 shows frequency characteristics when the semiconductor relay of the switch circuit 9a is turned on, and the semiconductor when the semiconductor relay of the switch circuit 9a is turned off. FIG. 4 shows frequency characteristics based only on the equivalent circuit of the relay. Note that the two-dot chain line in FIGS. 3 and 4 is the frequency characteristic of only the capacity through which 100 kHz or more passes.

  In the offset adjustment apparatus 1A of the first embodiment, when the semiconductor relay of the switch circuit 9a is on (contact S1: closed), the original offset adjustment for transmitting signals from DC to high frequency is performed as in the conventional case. The device operates as a device and is connected to the input and output by a direct current connection, and exhibits flat characteristics from low frequency to high frequency as shown in FIG.

  In the case of DC connection, only the resistor R1 is affected. Therefore, for example, by selecting a component having a small on-resistance of about several Ω as the resistor R1, the performance deterioration can be reduced.

  Further, in the offset adjustment device 1A of the first embodiment, when the semiconductor relay of the switch circuit 9a is off (contact S1: open), the transmission of the DC component transmitted from the input terminal 2 is cut, and the high frequency It operates as a level shift circuit for the purpose of transmitting only the components, and the connection between the input and output is AC-connected via the capacitor C1.

  By the way, in the first embodiment described above, in the case of AC connection, series resonance occurs due to the input impedance of the first coil 6, the capacitor C1, and the synthesis circuit 7, and the dip due to unnecessary resonance occurs in the pass characteristics (for example, FIG. 4). (Frequency around 5 MHz) may occur, which may cause deterioration due to waveform distortion of a signal to be transmitted and oscillation of the offset adjusting apparatus 1A. An offset adjusting apparatus that solves this problem is a second embodiment described below.

[Second Embodiment]
As shown in FIG. 2, the offset adjustment device 1 (1B) of the second embodiment includes an input terminal 2, a capacitor 3, an output terminal 4, a DC voltage generator 5, a first coil 6, a synthesis circuit 7, 2 coil 8, the switching part 9 (9B), and the control part 10 are comprised roughly.

  The offset adjustment device 1B according to the second embodiment is different from the offset adjustment device 1A according to the first embodiment described above in the internal configuration of the switching unit 9, and other configurations are the same as those in the first embodiment. Therefore, the same number is assigned and the description thereof is omitted.

  The switching unit 9B in the offset adjusting device 1B is connected between the first coil 6 and the synthesis circuit 7 in order to switch the DC connection and the AC connection with a simple configuration, similarly to the switching unit 9A of the first embodiment. Is done.

  The switching unit 9A includes a switch circuit 9a and an auxiliary circuit 9b. As shown in FIG. 2, the switch circuit 9a is an equivalent circuit including a contact S1, a resistance (on-resistance: about several ohms) R1, and a capacitor (off-capacitance: about 1 to 100 pF) C1, as shown in FIG. It consists of a semiconductor relay consisting of

  The auxiliary circuit 9b is connected in parallel to the switch circuit 9a, and is constituted by a series circuit in which a resistor R2 and a capacitor C2 are connected in series as shown in FIG. In this example, it is assumed that the resistor R2 has a capacity of, for example, about several Ω to several tens of Ω and the capacitor C2 has a capacity that allows a high frequency of 100 kHz or more to pass. However, the resistor R2 and the capacitor C2 consider the influence of the peripheral circuit. It is preferable to design.

  The auxiliary circuit 9b is provided to solve the problem of waveform distortion and oscillation at the time of AC connection in the first embodiment described above, and lowers the resonance frequency to a low band outside the transmission band that is not affected, and By lowering the resonance Q, the influence on the frequency characteristics is minimized.

  Here, in the offset adjusting apparatus 1B of the second embodiment, FIG. 3 shows frequency characteristics when the semiconductor relay of the switch circuit 9a is on, and the frequency when the semiconductor relay of the switch circuit 9a is off. The characteristics are shown in FIG. In addition, the dashed-two dotted line in FIG.3 and FIG.5 is a frequency characteristic only of the capacity | capacitance which 100 kHz or more passes.

  In the offset adjustment device 1B of the second embodiment, when the semiconductor relay of the switch circuit 9a is on (contact S1: closed), a signal from direct current to high frequency is transmitted as in the first embodiment. It operates as an original offset adjusting device, and is DC-connected between the input and output, and exhibits flat characteristics from low frequency to high frequency as shown in FIG.

  In the case of DC connection, the resistor R2 and the capacitor C2 are short-circuited, and only the resistor R1 is affected. For example, by selecting a component having a small on-resistance of about several Ω as the resistor R1, performance degradation can be reduced. it can.

  Further, in the offset adjustment device 1B of the second embodiment, when the semiconductor relay of the switch circuit 9a is off (contact S1: open), the auxiliary circuit 9b transmits the DC component transmitted from the input terminal 2. It operates as a level shift circuit for cutting and transmitting only high-frequency components, and the connection between input and output is AC-connected via a capacitor C1. Then, as shown in FIG. 5, a pass characteristic close to the frequency characteristic of only the capacity indicated by the two-dot chain line is obtained, and an AC connection close to ideal can be realized.

  In the example of FIG. 2, the auxiliary circuit 9b is configured by a series circuit in which a capacitor C2 and a resistor R2 are connected in series. However, the auxiliary circuit 9b may be configured by only the capacitor C2.

  Thus, according to the present embodiment, the switching unit 9 is connected between the first coil 6 and the synthesis circuit 7, and the semiconductor relay of the switching unit 9 is turned on (the contact S1 of the switch circuit 9a is opened). Then, the transmission of the DC component of the signal input from the input terminal 2 is cut, and it operates as a level shift circuit for the purpose of transmitting only the high frequency component, and the connection between the input and output is connected via the capacitor C1. AC connection is possible. Further, when the semiconductor relay of the switching unit 9 is turned off (the contact S1 of the switch circuit 9a is closed), it operates as an original offset adjusting device that transmits signals from DC to high frequency, as in the prior art. DC connections can be made between the outputs. Thereby, AC connection and DC connection can be realized with a simple configuration.

  Further, when the switching unit 9B in which the auxiliary circuit 9b is connected in parallel to the switch circuit 9a is adopted as the switching unit 9, a pass characteristic close to the frequency characteristic of only the capacitance indicated by the two-dot chain line is obtained as shown in FIG. The possibility of causing waveform distortion and oscillation of the offset adjustment device is reduced, and an almost ideal AC connection can be realized.

  By the way, the offset adjusting apparatus according to the present invention is not limited to the configuration shown in FIGS. That is, in FIGS. 1 and 2, an isolation circuit may be connected between the capacitor and the output terminal. In this case, the AC component of the input digital signal Di input to the input terminal 2 is transmitted to the output terminal 4 via the capacitor 3 and the isolation circuit, and the DC component and the low frequency component are extracted by the first coil 6. Are combined with the bias DC signal and supplied to the output terminal 4 via the second coil 8. In addition, backflow of low frequency components to the input terminal 2 side is blocked by an isolation circuit. Thereby, the influence of the circuit connected to the output side, for example, reflection due to mismatch or the like does not return to the input side, and wide-band waveform transmission with less distortion is enabled.

  Moreover, it is preferable that the synthesis circuit 7 of FIG. 1 and FIG. 2 includes a current limiting circuit that protects against overcurrent at the moment of short circuit. Further, an output matching resistor may be connected between the synthesis circuit 7 and the second coil 8. In this case, the resistor passes the combined signal output from the combining circuit 7 to the output terminal 4 via the second coil 8.

  Further, each of the synthesis circuit 7 and the isolation circuit is configured to include a variable gain amplifier, and each of the synthesis circuit 7 and the isolation circuit is output so that a digital signal having a specified amplitude value is output from the output terminal. The control unit 10 may control the variable gain amplifier. Thereby, not only an arbitrary DC offset can be given to the digital signal to be output, but also its amplitude can be set arbitrarily.

  The best mode of the offset adjustment apparatus and method according to the present invention has been described above, but the present invention is not limited by the description and drawings according to this mode. That is, it is a matter of course that all other forms, examples, operation techniques, and the like made by those skilled in the art based on this form are included in the scope of the present invention.

1 (1A, 1B) Offset adjustment device 2 Input terminal 3 Capacitor 4 Output terminal 5 DC voltage generator 6 First coil 7 Composite circuit 8 Second coil 9 (9A, 9B) Switching unit 9a Switch circuit 9b Auxiliary circuit 10 Control unit Di Digital signal (input)
Do Digital signal (output)
R1, R2 resistor C1, C2 capacitor S1 contact

Claims (4)

An input terminal (2) and an output terminal (4);
A capacitor (3) provided between the input terminal and the output terminal and transmitting an alternating current component of the digital signal (Di) input to the input terminal to the output terminal;
A bias applying coil (8) having one end connected to the output terminal;
A low-frequency extraction coil (6) that is connected at one end to the input terminal and passes a DC component and a low-frequency component of the digital signal input to the input terminal;
A DC voltage generator (5) for outputting a DC signal of an arbitrary voltage;
The signal output from the other end of the low frequency extraction coil is combined with the DC signal output from the DC voltage generator, and the resultant signal is combined with the other end of the bias applying coil. In a digital signal offset adjustment device (1) comprising a synthesis circuit (7) for supplying to
A digital signal offset adjusting device, wherein a switching unit (9) having a switch circuit (9a) made of a semiconductor relay is connected in series between the low frequency extraction coil and the synthesis circuit. The auxiliary circuit (9b) comprising a capacitor (C2) or a series circuit of the capacitor and a resistor (R2) is connected in parallel to the switch circuit (9a) of the switching unit (9). The digital signal offset adjusting device as described. An input terminal (2) and an output terminal (4);
A capacitor (3) provided between the input terminal and the output terminal and transmitting an alternating current component of the digital signal (Di) input to the input terminal to the output terminal;
A bias applying coil (8) having one end connected to the output terminal;
A low-frequency extraction coil (6) that is connected at one end to the input terminal and passes a DC component and a low-frequency component of the digital signal input to the input terminal;
A DC voltage generator (5) for outputting a DC signal of an arbitrary voltage;
The signal output from the other end of the low frequency extraction coil is combined with the DC signal output from the DC voltage generator, and the resultant signal is combined with the other end of the bias applying coil. In the digital signal offset adjustment method using the digital signal offset adjustment device (1) provided with the synthesis circuit (7) to be supplied to
A digital signal offset adjustment method comprising a step of connecting a switching unit (9) having a switch circuit (9a) made of a semiconductor relay in series between the low-frequency extraction coil and the synthesis circuit. The method includes a step of connecting in parallel a capacitor (C2) or an auxiliary circuit (9b) comprising a series circuit of the capacitor and a resistor (R2) to the switch circuit (9a) of the switching unit (9). The digital signal offset adjustment method according to claim 3.

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