JP2018107525A - Signal processing apparatus, method for controlling the same, transmission system, and imaging device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To evaluate an opening of an eye pattern of serial data without increasing a circuit scale. A receiving circuit 100 includes a communication unit 101, an adjusting unit 102, a clock output unit 103, a detection unit 104, and a control unit 110. The signal received by the communication unit 101 that receives the signal outputs the first clock CLK_A by the adjustment unit 102 that adjusts based on the setting parameter. The clock output unit 103 switches and outputs CLK_A and the second inspection clock CLK_B having a different frequency. The detection unit 104 transmits to the control unit 110 based on the value of the signal at the timing specified by the CLK_A and the inspection clock CLK_B. The control unit 110 outputs a setting parameter and controls the adjustment unit 102 of. [Selection diagram] Fig. 4

Description

  The present invention relates to a signal processing device, a control method thereof, a transmission system including the signal processing device, and an imaging device including the signal processing device.

  In communication between modules that exchange image data and the like, a differential transmission method is known in which a transmission-side module transmits data as a differential signal in order to transmit data at high speed. On the receiving side, data is acquired from the received differential signal according to the recovered clock.

  In the differential transmission method, as the transmission speed increases, the influence of deterioration in waveform quality due to the transmission path or the like becomes greater. For example, there is a case where data cannot be obtained accurately because the eye pattern opening of the differential signal is closed as the transmission speed increases. For this reason, a receiving circuit that receives signals by a differential transmission system includes an adjusting circuit such as an equalizer or a differential amplifier that adjusts the waveform of the received signal.

  In Patent Document 1, the waveform of a received signal is a value of data acquired according to a clock generated from the received signal, and data acquired according to a clock whose phase is different from that of the clock generated from the received signal. A transmission device for comparing values with each other is disclosed. The transmission device (signal processing device) of Patent Document 1 controls a setting value by which the adjustment circuit adjusts the waveform of the reception signal using the comparison result.

JP2015-39154A

  In the transmission apparatus disclosed in Patent Document 1, it is necessary to provide a plurality of circuits for generating a clock from a received signal in a module. Therefore, there is a concern that the circuit scale of the module or the transmission device increases.

  An object of the present invention is to provide a signal processing device capable of controlling the waveform of a received differential signal without providing a circuit for simultaneously generating a plurality of clocks in order to evaluate the opening of an eye pattern. And

  In order to achieve the above object, a signal processing apparatus of the present invention is adjusted by a receiving unit that receives a signal, an adjusting unit that adjusts a waveform of a signal from the receiving unit based on a set value, and the adjusting unit. A clock output means capable of switching and outputting a first clock based on the signal and a second clock having a predetermined frequency different from the first clock, and a clock output by the clock output means. A detection unit that acquires a value of the signal adjusted by the adjustment unit at a timing, and the detection unit controls the set value based on the value of the signal acquired at a timing specified by the second clock. And a control means.

  According to the signal processing device of the present invention, it is possible to control the waveform of the received differential signal without providing a circuit for simultaneously generating a plurality of clocks.

It is a device block diagram of an imaging device. It is a block diagram which shows the functional block of a transmission circuit. It is a schematic diagram which shows serial data and the differential signal produced | generated from serial data. It is a block diagram which shows the functional block of a receiving circuit. It is a block diagram which shows the functional block of an adjustment part. It is a schematic diagram which shows the function of an equalizer. It is a block diagram which shows the functional block of a differential amplifier. It is a 1st schematic diagram which shows a differential signal, Iout, and Vout. It is a 2nd schematic diagram which shows a differential signal, Iout, and Vout. It is a block diagram which shows the functional block of a clock generation part. It is a schematic diagram which shows a detection part. It is the schematic which showed the signal and clock which are input into a detection part, and the detection value which a detection part outputs. It is a flowchart which shows the evaluation flow of opening of an eye pattern. It is a schematic diagram which shows the determination result of the determination part with respect to a test | inspection signal. It is a schematic diagram which shows the detection timing determined with the test | inspection clock with respect to an eye pattern. It is a flowchart which shows an adjustment process.

[Example 1]
FIG. 1 is a device configuration diagram of an imaging device 1 including a receiving circuit 100.

  The imaging device 1 includes an optical system 10, an imaging sensor 11, a transmission circuit 12, a reception circuit 100, an output unit 13, and a storage unit 14.

  The optical system 10 includes an optical lens and inputs input light input from a subject through the optical lens to the imaging sensor 11. In addition to the optical lens, the optical system 10 includes a focus adjustment mechanism that operates the focal length of the optical lens, and a shutter that controls light input.

  The imaging sensor 11 is a sensor that outputs a plurality of photoelectric elements corresponding to a plurality of pixels in a matrix and outputs image data obtained by converting input light into an electrical signal. For example, it is assumed that the image sensor 11 outputs image data in which the pixel value of each pixel is represented by 8-bit data. Therefore, the optical system 10 and the imaging sensor 11 capture a subject and generate image data.

  The transmission circuit 12 is a circuit that outputs the image data acquired from the imaging sensor 11 to the reception circuit 100. FIG. 2 is a block diagram illustrating functional blocks of the transmission circuit 12. The transmission circuit 12 includes an 8b10b conversion unit 121, a P / S conversion unit 122, an inspection signal output unit 123, a selector 124, a transmission unit 125, a control unit 126, and a memory 127.

  The 8b10b conversion unit 121 is a conversion circuit that performs 8b10b conversion on pixel values of received image data. The 8b10b conversion is a data signal conversion method for converting the original 8-bit data so that 0 or 1 is appropriately included without being continuous in the converted data. The 8b10b conversion unit 121 converts 8-bit data into 10-bit data based on a table indicating correspondence between predetermined 8-bit data and 10-bit data. Therefore, in 10-bit data generated by the 8b10b conversion unit 121 by the 8b10b conversion, the possibility of taking a data value not included in the table is lower than the possibility of taking a data value included in the table.

  Further, by converting the data subjected to the 8b10b conversion into the serial data format, it is possible to suppress the occurrence of 0 or 1 continuously, and to generate serial data in which switching between 0 and 1 occurs frequently. . In such serial data, the rising and falling edges of the signal frequently appear. Therefore, the receiving circuit 100 described later can generate a corresponding clock from the serial data. In other words, it can be said that the clock is embedded in the data by performing the 8b10b conversion.

  The P / S conversion unit 122 is a conversion circuit that converts image data acquired from the 8b10b conversion unit 121 into a serial data format by parallel-serial conversion. The P / S converter 122 converts the image data so as to indicate a state of 0 or 1 at a predetermined clock frequency.

  The inspection signal output unit 123 is an output circuit that outputs inspection data set in advance in order to inspect the transmission state between the transmission circuit 12 and the reception circuit 100. The inspection signal is, for example, an inspection signal in a serial data format in which 1 and 0 are output alternately.

  The selector 124 is a selection circuit that selects serial data to be output to the receiving circuit 100 via the communication unit 125 in accordance with an instruction from the control unit 126. The selector 124 outputs serial data output from either the P / S conversion unit 122 or the inspection signal output unit 123 to the communication unit 125 in accordance with an instruction from the control unit 126.

  The communication unit 125 is a communication interface that performs differential communication serial communication with the receiving circuit 100. The communication unit 125 transmits the serial data output from the selector 124 to the reception circuit 100 using a differential transmission method. It is assumed that the transmission circuit 12 of this embodiment transmits image data by an embedded clock system that transmits serial data in which a clock is embedded.

  Here, a method of transmitting serial data by the differential transmission method will be described.

  FIG. 3 is a schematic diagram showing serial data and a differential signal generated from the serial data. The differential transmission method is a transmission method in which data is transmitted using differential signals (D +, D−) having opposite phases to each other with two signal lines.

  FIG. 3A is a schematic diagram showing serial data to be transmitted. The horizontal axis indicates time. The serial data shown in FIG. 2A is data in which 1 and 0 are alternately arranged.

  FIG. 3B is a schematic diagram showing differential signals (D +, D−) generated from the serial data shown in FIG. Each differential signal is generated so that the difference between the D + and D− signals corresponds to the serial data of the conversion source. D + is a signal that is in a high potential state (High) when the serial data is 1. D + transitions from a low potential state (Low) to a high potential state in response to the timing when the serial data changes from 0 to 1. D− is a signal that is in a low potential state (Low) when serial data is “1”. D- transitions from a high potential state to a low potential state in response to the timing at which the serial data changes from 0 to 1. The waveform shape formed by the differential signals (D +, D−) is called an eye pattern. Further, in the eye pattern, a region where the difference between D + and D− is equal to or greater than a predetermined value is called an opening.

  The circuit that has received the differential signal detects a value corresponding to the difference between D + and D− at a timing specified by the clock, and acquires a data value of 0 or 1. Therefore, by adjusting the differential signal so that the timing specified by the clock is included in the opening of the eye pattern of the differential signal, it is possible to detect the data value with higher accuracy.

  FIG. 3C is a schematic diagram showing a differential signal having a long rising (falling) period of each signal with respect to the differential signal shown in FIG. The period of rising (falling) of each signal is called a toggle period. The longer the toggle period, the shorter the period during which each signal maintains a high potential state or a low potential state. Therefore, the opening of the eye pattern becomes narrow. When the aperture is narrow, it is more likely that the clock timing is not included in the eye pattern aperture when the clock phase is shifted than when the aperture is wide. Therefore, data may not be acquired normally.

  The transmission circuit 12 and the reception circuit 100 are circuits mounted on different semiconductor integrated circuits (IC, chip). When analog signal transmission / reception is performed across chips, it is possible to suppress the influence of noise generated in the transmission path by transmitting / receiving signals using the differential transmission method.

  The control unit 126 is an arithmetic processing circuit that controls each functional block of the transmission circuit 12. For example, it is assumed that the control unit 126 is a central processing unit (CPU). The control unit 126 controls each functional block by reading and executing a program stored in the memory 127. The control unit 126 communicates with the control unit 110 of the receiving circuit 100 and receives information instructing to operate in the operation mode for inspecting the opening of the eye pattern from the control unit 110. The control unit 126 receives a signal output from the inspection signal output unit 123 as an input signal when the selector 124 receives information instructing to operate in the operation mode for inspecting the opening of the eye pattern from the control unit 110. To control.

  The memory 127 is a storage medium that stores a program used by the control unit 126. Note that the control unit 126 and the memory 127 may be provided outside the transmission circuit 12. Further, the control unit 126 and the memory 127 may be composed of electronic circuits common to the control unit 110 and the memory 108 of the receiving circuit 100, respectively. Further, the transmission circuit 12 may include the imaging sensor 11.

  The receiving circuit 100 is a signal processing device that receives the 10-bit image data transmitted from the transmitting circuit 12 and outputs the image data to the output unit 13. The receiving circuit 100 generates a clock from the received image data. Then, the reception circuit 100 performs serial / parallel conversion processing of the received 10-bit image data using the generated clock. Further, the receiving circuit 100 performs 10b8b conversion processing on the image data subjected to the serial / parallel conversion processing to generate 8-bit image data.

  Further, the receiving circuit 100 evaluates the opening of the eye pattern of the received differential signal using a clock generated from the received image data. The reception circuit 100 includes an adjustment unit 102 that adjusts the waveform of the received differential signal, and the adjustment unit 102 adjusts the differential signal according to the evaluation result of the eye pattern opening of the received differential signal. Set the adjustment parameters. Details of the operation of the receiving circuit 100 will be described later.

  The transmission circuit 12 and the reception circuit 100 are composed of different chips, and constitute a transmission system that transmits image data acquired by the imaging sensor 11 to the output unit 103.

  The output unit 13 outputs the image data output from the receiving circuit 100 to an external device or a storage unit 14 described later. For example, it is assumed that the output unit 13 is an output terminal provided on the same chip as the receiving circuit 100. The external device is, for example, a display device that displays an image based on image data or a storage device that stores image data. Note that the output unit 13 may include a conversion circuit for converting the image data into a data format that can be used by a destination device that outputs the image data.

  The storage unit 14 is a storage medium that stores the image data output from the output unit 13. For example, it is assumed that the storage unit 14 is a nonvolatile storage medium such as a hard disk.

FIG. 4 is a block diagram illustrating functional blocks of the receiving circuit 100. The receiving circuit 100
A communication unit 101, an adjustment unit 102, a clock output unit 103, a detection unit 104, an S / P conversion unit 105, a communication unit 106, a determination unit 107, a memory 108, a count unit 109, and a control unit 110 are provided.

  The communication unit 101 is an input interface that receives a signal transmitted from the transmission circuit 12. The signal received by the communication unit 101 is serial data transmitted by the transmission circuit 12 using the differential transmission method. The communication unit 101 outputs the received signal to the adjustment unit 102.

  The adjustment unit 102 is a waveform adjustment circuit that adjusts a received signal based on a set adjustment parameter (set value). For example, the adjustment unit 102 includes an equalizer 1021 and a differential amplifier 1022.

  FIG. 5 is a block diagram illustrating an example of functional blocks of the adjustment unit 102. The adjustment unit 102 includes an equalizer 1021, a differential amplifier 1022, and a termination resistor 1023.

  The equalizer 1021 is a circuit that adjusts the frequency characteristic of the signal received by the communication unit 101 using a set adjustment parameter. Specifically, the equalizer 1021 compensates for the frequency component attenuated by the filter characteristic of the transmission path from the transmission circuit 12 to the adjustment unit 102 of the reception circuit 100, and adjusts the waveform of the received signal.

  FIG. 6 is a schematic diagram showing the function of the equalizer 1021. FIG. 6A is a configuration diagram showing the configuration of the equalizer 1021. The equalizer 1021 includes a first filter 1021a and a second filter 1021b made of a variable capacitor and a variable resistor.

  FIG. 6B is a schematic diagram showing filter characteristics indicating the relationship between the frequency band of the signal input to the equalizer 1021 and the corresponding gain value. It is assumed that the equalizer 1021 can change the filter characteristics by changing the resistance value of the variable resistor and the capacitance of the variable capacitor of each filter. The filter characteristic 1 is a characteristic in which the gain value up to the first frequency fa is constant and the gain value attenuates with respect to the frequency equal to or higher than the first frequency fa. The filter characteristic 2 is a characteristic having a gain value higher than that of the filter characteristic 1 at the second frequency fb smaller than the first frequency fa. Therefore, the filter characteristic 2 has a characteristic that emphasizes the frequency band near the second frequency fb as compared with the filter characteristic 1. For example, the second frequency fb is assumed to be a frequency corresponding to the toggle period of the differential signal generated by the transmission circuit 12.

  The adjustment parameters of the equalizer 1021 are the resistance value of the variable resistor and the capacitance value of the variable capacitor of the first filter and the second filter. The equalizer 1021 changes the filter characteristic of the equalizer 1021 by changing the resistance value of the variable resistor and the capacitance value of the variable capacitor of the first filter and the second filter according to the adjustment parameter set in the control unit 110. Change. Note that the adjustment parameter of the equalizer 1021 may be a set value indicating filter characteristics. In this case, the equalizer 1021 sets the resistance value of the variable resistor and the capacitance value of the variable capacitor, which are predetermined according to the set value, in each filter.

  A specific frequency component may be suppressed in a transmission path through which a signal transmitted from the transmission circuit 12 in a differential manner passes from the transmission circuit 12 to the adjustment unit 102 of the reception circuit 100. For example, when the transmission line has a low-pass filter characteristic, high frequency components are suppressed. When the high-frequency component of the differential signal is suppressed, the signal acquired by the adjustment unit 102 takes a long time to transition from High to Low (or Low to High). In other words, the signal waveform is dull. For example, when data such that 0 and 1 are alternately repeated is transmitted, some signals may not be able to transition and may move to the next transition state.

  FIG. 6C is a schematic diagram in which a plurality of eye patterns obtained by using a differential signal clock as a timing trigger are superimposed on a differential signal in which a high-frequency component is suppressed in the transmission path. As a method for evaluating the opening of the eye pattern, as described above, a plurality of eye patterns may be overlapped to evaluate the stability of the size of the opening. The signal used for evaluation is not a signal in which 1 and 0 are alternately arranged as shown in FIG. 3, but various transition states such as a case where a plurality of 1s are transmitted after a plurality of 0s. It is desirable that the signal includes. By superimposing eye patterns in various transition states, it is possible to evaluate the stability of the aperture in signal transmission / reception.

  As shown in FIG. 6C, when the eye patterns in which the high-frequency component is suppressed are superimposed, the region where the opening stably exists becomes small. This is because the state transition between High and Low is not sufficiently performed in some eye patterns.

  FIG. 6D is a schematic diagram showing an output signal after the equalizer 1021 adjusts the waveform with respect to the differential signal shown in FIG. As shown in FIG. 6B, the state transition is quickly performed by performing the process of increasing the frequency component in the frequency band near the high frequency fb. Therefore, High and Low are stably switched, and the shape of the opening is also stably increased. The equalizer 1021 outputs a signal whose waveform is adjusted to the differential amplifier 1022.

  The differential amplifier 1022 is an adjustment circuit that outputs serial data based on the difference between the differential signals adjusted by the equalizer 1021. By taking the difference between the differential signals, it is possible to remove the in-phase noise components superimposed on the differential signals.

  FIG. 7 is a block diagram showing functional blocks of the differential amplifier 1022. The differential amplifier 1022 includes a V / I converter 1022a, a current offset unit 1022b, and an I / V converter 1022c.

  The V / I conversion unit 1022a is a voltage / current conversion circuit that converts the differential voltage of two signals (D +, D−) of the reception signal into a current and outputs the current as a current Io to the current / voltage conversion unit. Note that the V / I conversion unit 1022a assumes that the current value that flows when the D + signal is High and the D− signal is Low is a positive current value.

  The current offset unit 1022b is an offset circuit that outputs an output current Iout obtained by adding an offset value (offset current Iofs) according to a set setting parameter to the current Io. Details of adding the offset current Iofs by the current offset unit 1022b will be described later.

  The I / V conversion unit 1022c is a current-voltage conversion circuit that outputs a voltage Vout according to Iout. For example, the I / V converter 1022c sets the output voltage Vout to 0 when Iout is a source current equal to or higher than the source threshold, and sets the output voltage Vout to 1 when Iout is a sink current equal to or lower than the sink threshold. Here, the source current is a current having a positive current value of 0 or more, and the sink current is a negative current value smaller than 0. The source threshold value and the sink threshold value can be arbitrarily set according to the range of the current value to be transmitted and the circuit configuration. When Iout is larger than the sink threshold and smaller than the source threshold, Vout corresponding to Iout is output.

  FIG. 8 is a schematic diagram showing signals (D +, D−), Iout, and Vout when the balance between two received signals (D +, D−) is ideal. The case where the balance between the two received signals (D +, D−) is ideal indicates that the voltage values of the two signals (D +, D−) shift symmetrically with respect to 0V. The two signals (D +, D−) are signals that alternately transition between High and Low in a predetermined cycle.

  FIG. 8B is a schematic diagram showing the current Io generated by the V / I converter 1022a. The V / I converter 1022a converts the differential voltage of the two signals (D +, D−) into a current Io and outputs the current Io. Therefore, when the voltage values of the two signals (D +, D−) change symmetrically with respect to 0V, the current Io passes 0 (A) at a timing corresponding to a predetermined cycle.

  FIG. 8C is a schematic diagram illustrating the voltage Vout output from the I / V conversion unit 1022c based on the current Io. Since the current Io alternately repeats a positive current value and a negative current value in a predetermined cycle, the voltage Vout repeats 1 and 0 in a predetermined cycle. In addition, the period in which the voltage Vout is 1 and the period in which the voltage Vout is 0 are approximately the same length.

  In the transmission circuit 12 or the transmission path between the transmission circuit 12 and the differential amplifier 1022, the balance between the voltage values of the two signals may be lost due to circuit manufacturing variations or temperature changes. For example, an offset may be added to the voltage level of the D + signal. The differential amplifier 1022 adds an offset current Iofs to the current Io so as to reduce the influence of the offset between the two signals (D +, D−).

  FIG. 9 is a schematic diagram showing signals (D +, D−), Iout, and Vout when an offset occurs in the voltage value of the D− signal among the two signals. FIG. 9A shows the signals (D +, D−). Assume that the voltage value of the D + signal shown in FIG. 9A is a value obtained by adding the offset Vofs to the voltage value of the D− signal shown in FIG.

  In FIG. 9B, based on the signals (D +, D−) shown in FIG. 9A, the current Io output from the V / I converter 1022a and the offset current Iofs are added by the current offset unit 1022b. It is a schematic diagram which shows the electric current Iout. The solid line indicates the current Io. The dotted line indicates the current Iout.

  The current Io in FIG. 9B causes a switching point shift between positive and negative directions with respect to the current Io in FIG. 8B. Since the offset is added to the D− signal, the current Io corresponding to the differential voltage of the two signals is shifted in the positive direction. Therefore, the period during which the current Io is a positive current value is relatively long, and the period during which the current Io is negative is relatively short.

  FIG. 9C is a schematic diagram illustrating the voltage Vout output from the I / V conversion unit 1022c based on the current Io in FIG. 9B. As shown in FIG. 9C, the shift in the positive / negative direction switching point generated in the current Io is output as a 1/0 time-direction shift in the voltage Vout output from the I / V conversion unit 1022c. Specifically, the period in which the voltage Vout is maintained at 0 is relatively shorter than the period in which the voltage Vout is maintained at 1.

  As described above, when the balance in the time direction of 1/0 is lost, the same effect as that in which the opening width of the eye pattern is narrowed is exhibited. In the detection unit 104 described later, there are cases where data cannot be acquired normally according to the clock. In such a case, communication quality deteriorates.

  The current offset unit 1022b adds the offset current Iofs corresponding to the setting parameter set by the control unit 110 to the current Io and outputs the current Iout in order to correct the deviation of the current Io as described above. The current in the direction to cancel the offset voltage is added to the current Io output from the current balance adjustment unit to correct the balance between the two signals (D +, D−) of the received signal. As shown in FIG. 9B, by adding Iofs, the current Iout is corrected to a positive / negative balance comparable to the current Io in FIG. 8B. As a result, Vout output based on the current Iout can transition between the states of 1 and 0 in a predetermined cycle, similarly to Vout shown in FIG. 8C. Therefore, it is possible to suppress degradation of communication quality.

  As described above, the adjustment unit 102 converts the signal transmitted by the differential transmission method and received by the communication unit 101 into a serial data format, and outputs the serial data to the clock output unit 103 and the detection circuit 104.

  The clock output unit 103 is a clock output circuit that generates and outputs a clock for capturing a received signal. The clock output unit 103 is a CDR circuit that can regenerate a clock from a received signal by a so-called clock data recovery method. In this case, the clock output unit 103 multiplies the reference clock based on the received signal to generate and output the reception clock CLK_A. The clock output unit 103 can also generate and output a clock with an arbitrary frequency in accordance with an instruction from the control unit 110.

  FIG. 10 is a block diagram showing functional blocks of the clock output unit 103. The clock output unit 103 includes a VCO control loop including a phase comparison unit 1031, a charge pump 1032, a loop filter 1033, a VCO unit 1034, and a selector 1035. The clock output unit 103 is a circuit that generates a clock synchronized with the timing at which the received signal is toggled. Here, VCO is Voltage Controlled Oscillator.

  The phase comparison unit 1031 is a circuit that compares the rising edge of the received signal with the rising edge of the clock output from the VCO unit 1034 and outputs a phase control signal output to the charge pump 1032. When the rising edge of the received signal arrives before the rising edge of the clock output from the VCO unit 1034, the phase comparison unit 1031 outputs a phase advance signal. When the rising edge of the received signal arrives after the rising edge of the clock output from the VCO unit 1034, the phase comparison unit 1031 outputs a phase delay signal.

  The charge pump 1032 is a circuit that outputs a current to the loop filter 1033 based on the phase control signal acquired from the phase comparison unit 1031. The charge pump 1032 passes a current for charging the loop filter 1033 when the phase advance signal is input. The charge pump 1032 passes a current for discharging the loop filter 1033 when a phase delay signal is input.

  The loop filter 1033 is a circuit including a capacitor that integrates the current input / output by the charge pump 1032, converts the current to a DC voltage, and outputs the DC voltage. The loop filter 1033 outputs the DC voltage to the VCO unit 1034 via the selector 1035.

  The VCO unit 1034 is a voltage controlled oscillator that outputs a clock signal having a frequency corresponding to an input voltage. The VCO unit 1034 outputs a clock to the phase comparison unit 1031 and the detection unit 104.

  The selector 1035 selects a voltage input to the VCO unit 1034 according to the clock regeneration control signal input from the control unit 110. For example, when the clock regeneration control signal is an ON signal, the selector 1035 switches the path so that the voltage output from the loop filter 1033 is input to the VCO unit 1034. When the clock regeneration control signal is an off signal, the selector 1035 switches the path so that the voltage (VCO control signal) output from the control unit 110 is input to the VCO unit 1034.

  The control unit 110 switches the clock generated by the clock output unit 103 using a clock reproduction control signal. When the clock regeneration control signal is on, the clock output unit 103 outputs the received clock CLK_A that has the same frequency as the received signal and has a rising edge at the center of the received signal. On the other hand, when the clock regeneration control signal is off, the VCO unit 1034 outputs a test clock CLK_B having a predetermined frequency based on the VCO control signal output from the control unit 110.

  The clock output unit 103 may have a configuration other than the above-described configuration as long as it can generate the reception clock CLK_A having a frequency synchronized with the serial signal and the inspection clock CLK_B having an arbitrary frequency.

  Note that the clock output unit 103 may acquire information indicating the clock (reference clock) of the signal transmitted by the transmission circuit 12 from the transmission circuit 12 and output the reception clock CLK_A. For example, when the transmission circuit 12 transmits a signal to the reception circuit 100 by the source synchronous method, the transmission circuit 12 includes a clock output unit that outputs a reference clock to the reception circuit 100. The clock output unit 103 may output the reference clock acquired from the transmission circuit 12 as the reception clock CLK_A, and generate and output the inspection clock CLK_B having an arbitrary frequency difference with respect to the reception clock CLK_A.

  The detection unit 104 is a circuit that detects the value of the received signal at the timing synchronized with the clock acquired from the clock output unit 103 and outputs detection data DATA_B. The detection value is 0 or 1 bit data. The detection data DATA_B is serial data that the detection unit 104 includes detection values.

  FIG. 11 is a schematic diagram showing the detection unit 104. For example, it is assumed that the detection unit 104 is a D-type flip-flop circuit. The detection unit 104 includes a clock terminal to which the clock output from the clock output unit 103 is input and a D terminal to which a serial signal is input. The detection unit 104 includes an output terminal that outputs a Q output corresponding to the input of the clock and the serial signal.

  FIG. 12 is a schematic diagram illustrating a serial signal (D) and a clock (CLK) input to the detection unit 104 and a detection value (Q) output from the detection unit 104. FIG. 12A shows the serial signal (D) input to the detection unit 104. FIG. 12B shows a clock (CLK) input to the detection unit 104. FIG. 12C shows the detection value (Q) output from the detection unit 104. The detection unit 104 outputs the value of the signal input to the D terminal at the timing when the rising edge of the clock is input to the clock terminal from the output terminal.

  The S / P conversion unit 105 performs processing for converting the detection data DATA_B into parallel data, and outputs 10-bit image data DATA_C. When data is ideally transmitted between the transmission circuit 12 and the reception circuit 100, the image data transmitted by the transmission circuit 12 and the image data DATA_C are the same image data.

  The communication unit 106 is a communication interface that outputs the image data DATA_C output from the S / P conversion unit 105 to the output circuit 13. For example, the communication unit 106 performs 10b8b conversion on the image data DATA_C and outputs 8-bit image data to the output circuit 13.

  The determination unit 107 is a determination circuit that determines an error when the input signal is different from the expected value read from the memory 108. The determination unit 107 determines whether or not the expected value and the detection data DATA_B are the same. The determination unit 107 outputs an error signal to the count unit 109 when the expected value and the detection data DATA_B are not the same. Note that the determination unit 107 may output a success signal when the expected value and the detection data DATA_B are the same. The determination unit 107 determines the value acquired at the timing of each clock and the expected value for each clock.

  The memory 108 is a storage medium that stores data indicating an expected value used by the determination unit 107. For example, when an inspection signal used in the operation mode for inspecting the opening of the eye pattern is determined in advance, information indicating the inspection signal is stored in the memory 108. For example, when the inspection signal is 2-bit data in which 1 and 0 are alternately repeated, information indicating the same signal is stored in the memory 108.

  The count unit 109 is a counter that measures the number of times an error is determined in a predetermined period based on the determination result output from the determination unit 107. The count unit 109 outputs a count result indicating the result of counting the number of errors to the control unit 110. Specifically, the count unit 109 measures the number of error signal inputs. Count unit 109 outputs the number of errors to control unit 110.

  In response to receiving the reset signal from the control unit 110, the count unit 109 resets the count number to 0 and resumes counting. Since the determination result of the determination unit 107 is two types, that is, an error or not, the count unit 109 may count the number of times (not an error) that matches the expected value. The count unit 109 may reset the error count to 0 when a predetermined period has elapsed.

  The control unit 110 is an arithmetic processing device (processor) that controls each functional block of the receiving circuit 100. For example, it is assumed that the control unit 110 is a CPU. The control unit 110 executes a program stored in the memory 108, controls each functional block, and realizes processing executed by the receiving circuit 100. The control unit 110 outputs a clock recovery loop control signal and a VCO control signal to the clock output unit 103. Further, the control unit 110 outputs a signal for setting the adjustment parameter of the adjustment unit 102 according to the count result acquired from the count unit 109.

  In addition, the control unit 110 outputs information instructing to operate in the operation mode for inspecting the opening of the eye pattern to the control unit 126 of the transmission circuit 12. It is assumed that the control unit 110 executes an adjustment process described later after the imaging device 1 is turned on by an operation unit (not shown) and before the imaging sensor 11 starts outputting image data.

  For example, it is assumed that the control unit 110 outputs information instructing to operate in the operation mode for inspecting the opening of the eye pattern in response to the activation of the imaging device 1. Control unit 110 may output the above instruction every time a predetermined period elapses. Further, the control unit 110 may output the above instruction when there is no output of image data from the imaging sensor for a predetermined period.

  Next, a method for evaluating an eye pattern opening in the present embodiment will be described. FIG. 13 is a flowchart showing an evaluation flow of the eye pattern opening in this embodiment. For example, it is assumed that this flow is executed in response to the power of the imaging apparatus 1 being turned on from the off state.

  In S600, the control unit 110 executes an inspection start process for outputting information instructing the control unit 126 to operate in an operation mode for inspecting the opening of the eye pattern.

  In step S601, the control unit 126 executes processing for controlling the selector 124 so that an inspection signal is output. Thereby, serial data based on the inspection signal is output from the transmission circuit 12 by the differential transmission method. The communication unit 101 receives serial data based on the inspection signal transmitted from the transmission circuit 12. After S601, the transmission circuit 12 continues to transmit serial data based on the inspection signal to the reception circuit 100, and stops outputting the inspection signal in response to the completion of the inspection processing.

  In S602, the clock output unit 103 executes processing for generating the reception clock CLK_A based on the reception signal. The reception clock CLK_A generated by the clock output unit 103 is output to the detection unit 104. The reception clock CLK_A is stored in the memory 108. For example, it is assumed that the frequency f1 of the reception clock CLK_A is 1 GHz.

  In S <b> 603, the detection unit 104 executes a process of acquiring the detection data DATA_Ba with the reception clock CLK_A.

  In step S <b> 604, the determination unit 107 determines whether the detection data DATA_Ba is the same as the expected value, and outputs the determination result to the count unit 109. It should be noted that the processing of S603 and S604 may be executed for each predetermined inspection period to be described later, or whether the determination unit 107 is the same as the expected value every time the detection unit 104 acquires the detection data DATA_Ba. It may be determined.

  In step S <b> 605, the count unit 109 measures the number of error data in a predetermined inspection period and outputs it to the control unit 110.

  FIG. 14 is a schematic diagram illustrating a determination result of the determination unit 107 with respect to the inspection signal. FIG. 14A shows a determination result of the determination unit 107 when the detection circuit 104 acquires the detection data DATA_Ba based on the reception clock CLK_A. When there is no phase variation in the received signal, the reception clock CLK_A has the same frequency as the received signal, so that detection data DATA_Ba equivalent to the inspection signal is obtained.

  In addition, since the process from S603 to S605 is a process for confirming the transmission state between the transmission circuit 12 and the reception circuit 100 at the time of opening evaluation processing start, when the transmission state is known in advance, It can be omitted.

  In S606, the clock output unit 103 executes processing for generating the inspection clock CLK_B. Specifically, the control unit 110 executes a process of outputting a clock recovery control signal for turning off the clock recovery function to the clock output unit 103. Then, the control unit 110 outputs a VCO control signal for generating the inspection clock CLK_B to the clock output unit 103.

  With the above-described control, the clock output unit 103 generates the inspection clock CLK_B. For example, it is assumed that the frequency f2 of the inspection clock CLK_B is 1.01 GHz. The clock output unit 103 generates the inspection clock CLK_B and outputs it to the detection unit 104.

  In S <b> 607, the detection unit 104 executes a process of acquiring the detection data DATA_Bb with the inspection clock CLK_B.

  In step S <b> 608, the determination unit 107 determines whether the detection data DATA_Bb is the same as the expected value, and outputs the determination result to the count unit 109.

  In step S <b> 609, the count unit 109 measures the number of error data in a predetermined inspection period and outputs the error data to the control unit 110.

  FIG. 14B shows a determination result of the determination unit 107 when the detection circuit 104 acquires the detection data DATA_Bb based on the inspection clock CLK_B. Since the frequency of the reception signal is different from the frequency of the inspection clock CLK_B, the acquisition timing is shifted from the phase of the reception signal every time the detection unit 104 acquires the detection data DATA_Bb. Therefore, the detection data DATA_Bb is obtained at a timing that is not an opening of the reception signal.

  Since the detection data DATA_Bb acquired at a timing that is not an opening of the reception signal takes a value different from the inspection signal, the determination unit 107 determines that the detection data DATA_Bb and the expected value are not the same (error).

  The count unit 109 determines the inspection period so that the error is measured at least in a period corresponding to one cycle in which the error occurs.

  For the detection data DATA_Bb, the number of times the detected error is measured depends on the length of the non-opening period in the received signal. The narrower the opening (the longer the non-opening period), the higher the error count.

  The control unit 110 stores the count number of errors for the measured detection data DATA_Bb in the memory 108. The eye pattern opening evaluation flow ends.

  A method for determining the frequency f2 of the inspection clock CLK_B will be described. FIG. 15 is a schematic diagram illustrating an eye pattern of a signal adjusted by the adjustment unit 102 and a detection timing (detection point) determined by the inspection clock CLK_B.

  Since the frequency f2 of the inspection clock CLK_B is different from the frequency f1 of the reception clock CLK_A, the rising timing of the inspection clock CLK_B is different for each clock with respect to the eye pattern of the received signal. In other words, it can be said that the detection points determined by the inspection clock CLK_B correspond to different phases of the corresponding eye patterns.

  There can be a plurality of detection points based on the inspection clock CLK_B with a ΔT [s] interval between 1 unit interval (UI) of the received signal. 1 UI is the period of the received signal and is the reciprocal of the received clock CLK_A. ΔT [s] satisfies Expression (1).

  The number P of inspection points for 1 UI is obtained by equation (2).

  In other words, it can be said that the phase of the rising edge of the test clock CLK_B is shifted by ΔT / 1UI with respect to the UI of the received signal for each test clock CLK_B. Therefore, by repeating the check clock CLK_B by 1 UI / ΔT, that is, a number P, the phase of the received signal again matches the phase of the check clock CLK_B. The time required for the phase of the received signal and the phase of the inspection clock CLK_B to coincide again becomes the time T1 necessary for evaluating the eye pattern opening for one period using the inspection clock CLK_B. . T1 is P / f2.

  In order to promptly transmit data, it is desirable that the time T1 required for evaluation of the eye pattern opening is short. However, as the number P of inspection points increases, it becomes possible to evaluate the opening of the eye pattern with finer time resolution, and the accuracy can be improved. The frequency f2 of the inspection clock CLK_B is determined in consideration of the above situation.

  The frequency f2 of the inspection clock CLK_B satisfies Expression (3) from the number P of inspection points and the frequency f1 of the reception clock CLK_A.

  For example, assume that about 100 points are secured as the number P of inspection points. For example, when f1 is 1 GHz, if P is 100 points and f1 <f2, f2 is about 1.01 GHz. At this time, T1 is about 100 / 1.01 [GHz] ≈0.99 [ns]. In order to evaluate the opening of the eye pattern in a shorter time, it is desirable that f2 is a value larger than f1.

  Further, in order to increase the accuracy of the evaluation of the aperture, it is desirable to count the evaluation of the aperture of the eye pattern for 10 cycles and average it.

  In the present embodiment, the waveform adjustment process for adjusting the adjustment parameter of the differential amplifier 1022 included in the adjustment unit 102 is executed using the above-described evaluation of the eye pattern opening so that the eye pattern opening is maximized. Specifically, the control unit 110 adjusts so that the offset current Iofs of the differential amplifier 1022 becomes an optimum value. FIG. 15 is a flowchart showing the waveform adjustment processing in this embodiment.

  In S800, the control unit 110 sets the offset current Iofs (m) of the differential amplifier 1022 to an initial value (Iofs (1). For example, the offset current Iofs is a parameter that can be changed in steps. The current value in each of Iofs (m) is stored in the memory 108 in advance, and the control unit 110 reads out from the memory 108 and controls the differential amplifier 1022.

  In step S801, the eye pattern opening evaluation process shown in FIG. 13 is executed.

  In step S802, the control unit 110 determines whether or not the opening evaluation process has been completed for the offset current Iofs to be evaluated. Specifically, it is determined whether or not m is the maximum value mMAX that can be taken. If it is determined in S802 that the aperture evaluation process has not been completed for the offset current Iofs to be evaluated, the process proceeds to S803. If the opening evaluation process is completed for the offset current Iofs to be evaluated in S802, the process proceeds to S804.

  In S803, control unit 110 changes offset current Iofs. Specifically, the control unit 110 executes a process of setting m = m + 1. The process returns to S801.

  By executing the loop from S800 to S803, the eye pattern opening evaluation process is executed for all combinations of adjustment parameters.

  If it is determined in S802 that the aperture evaluation process has been completed for the offset current Iofs to be evaluated, an eye pattern aperture evaluation result is acquired for each of the offset currents Iofs to be evaluated in S804. Is possible.

  In step S <b> 805, the control unit 110 executes a process of acquiring the offset current Iofs that minimizes the error measurement result among the eye pattern opening evaluation results stored in the memory 108.

  In step S <b> 806, the control unit 110 executes processing for setting the offset current Iofs that minimizes the error measurement result in the differential amplifier 1022.

  This is the end of the waveform adjustment process in the present embodiment.

  In the above flow, the offset current Iofs of the differential amplifier 1022 is used as a parameter for waveform adjustment, but the parameter to be adjusted is not limited thereto. For example, the filter characteristics of the equalizer 1021, the resistance value of the variable resistor, and the capacitance of the variable capacitor may be adjusted. Further, the delay amount of one of the two signals (D +, D−) of the reception signal transmitted by the differential transmission method may be adjusted. Moreover, you may perform an adjustment process with respect to several parameters among these parameters.

  It is also possible to obtain an optimum value of the adjustment parameter by evaluating the eye pattern opening for a combination of some adjustment parameters among possible adjustment parameters. The result of evaluation performed in the past may be stored in advance, and the adjustment process may be executed for a combination of parameters for which an optimum parameter is considered to exist. It is assumed that a combination of parameters that are considered to have an optimum parameter is determined, for example, centering on a value determined as an optimum parameter in the previous inspection.

  In this embodiment, in order to evaluate the opening of the eye pattern of the received signal for each bit, an inspection signal in which 0 and 1 are alternately repeated is used. However, the inspection signal is not limited to the above, for example, 0 and 1 A signal that repeats every two may be used as the inspection signal.

  In the signal processing apparatus of the present embodiment, it is possible to evaluate the opening of the eye pattern of the acquired serial data using a CDR circuit for regenerating the clock by the clock data recovery method. Therefore, it is possible to evaluate the opening of the eye pattern with high accuracy without providing a dedicated circuit for evaluating the opening of the eye pattern.

  Further, it is possible to obtain a suitable input signal waveform by executing waveform adjustment processing on the input signal of the signal processing device in accordance with the evaluation result of the eye pattern opening.

[Example 2]
The signal processing apparatus according to the second embodiment is characterized in that the detection value detected by the inspection clock is determined using the expected value corresponding to the format of the transmitted data, and the eye pattern opening is evaluated.

  The receiving circuit of the second embodiment is different from the receiving circuit described in the first embodiment in the expected value stored in the memory 108 and the data that the determination unit 107 compares with the expected value. Since the functions of the other functional blocks are the same as those in the first embodiment, description thereof is omitted.

  In the receiving circuit of the second embodiment, the format of data output from the transmitting circuit 12 is stored in the memory 108 in advance. For example, it is assumed that data output from the transmission circuit 12 is image data that has undergone 8b10b conversion.

  The 8b10b conversion is a data signal conversion method for converting the original 8-bit data so that 0 or 1 is appropriately included without being continuous in the converted data. The 8b10b conversion unit 121 converts 8-bit data into 10-bit data based on a table indicating correspondence between predetermined 8-bit data and 10-bit data. Therefore, the 10-bit data generated by the 8b10b conversion unit 121 by the 8b10b conversion does not take a data value not included in the table.

  The memory 108 stores a table used for the 8b10b conversion as information indicating an expected value.

  The determination unit 107 determines whether or not the expected value held in the memory 108 is the same as the image data DATA_C acquired from the S / P conversion unit 105. The determination unit 107 acquires an expected value from the memory 108 and compares it with image data DATA_C. For example, when the image data DATA_A transmitted by the transmission circuit 12 is 10-bit data generated by 8b10b conversion, the value that can be taken by the image data DATA_C is 10-bit data included in a table that can be taken by the data after 8b10b conversion. Is the value of

  Therefore, when the image data DATA_C has a data value not included in the table, the determination unit 107 determines that the image data DATA_C is not the same as the expected value (is an error). The determination unit 107 outputs the determination result to the count unit 109.

  According to the signal processing apparatus of the present embodiment, it is not necessary to provide the transmission circuit 12 with a circuit that outputs an inspection signal for eye pattern opening evaluation. Therefore, the circuit scale of the transmission circuit 12 can be reduced.

  The signal output from the transmission circuit 12 at the time of inspection may be a signal obtained by converting an arbitrary signal by 8b10b. For example, it is possible for the P / S conversion unit 122 to continuously send data arranged at the delimiter positions of 10-bit data.

DESCRIPTION OF SYMBOLS 1 Imaging device 10 Optical system 11 Imaging sensor 12 Transmission circuit 13 Output part 14 Storage part 100 Reception circuit 101 Communication part 102 Adjustment part 103 Clock output part 104 Detection part 105 S / P conversion part 106 Communication part 107 Determination part 108 Memory 109 Count Unit 110 Control unit

Claims (16)

Receiving means for receiving a signal;
Adjusting means for adjusting the waveform of the signal from the receiving means based on a set value;
Clock output means capable of switching and outputting a first clock based on the signal adjusted by the adjusting means and a second clock having a predetermined frequency different from the first clock;
Detecting means for acquiring a value of the signal adjusted by the adjusting means at a timing specified by a clock output by the clock output means;
Control means for controlling the set value based on the value of the signal acquired by the detection means at a timing designated by the second clock;
A signal processing apparatus comprising: A determination means for determining whether or not a value acquired by the detection means at a timing designated by the second clock is equal to a predetermined expected value;
The signal processing apparatus according to claim 1, wherein the control unit controls the set value according to a determination result of the determination unit. The determination means further includes a counting means for counting the number of times that the detection means determines that the value acquired at the timing specified by the second clock and the expected value are not the same;
The signal processing apparatus according to claim 2, wherein the control unit controls the set value in accordance with a count result of the counting unit.   The determining unit acquires the number of times from the counting unit for a plurality of setting values, and sets the setting value having the smallest number of times among the plurality of setting values to the adjusting unit. The signal processing apparatus according to claim 3. The signal is a signal generated from predetermined inspection data,
The signal processing apparatus according to claim 2, wherein the expected value is a value indicating the inspection data.   6. The signal processing apparatus according to claim 5, wherein the inspection data is serial data in which 1 and 0 are alternately arranged. The signal is a signal generated based on data composed of values included in a predetermined table,
The signal processing apparatus according to claim 2, wherein the expected value is a value included in the predetermined table.   The signal processing apparatus according to claim 7, wherein the predetermined table is a table used for 8b10b conversion for converting 8-bit data into 10-bit data. The signal is data embedded with a clock;
The signal processing according to claim 1, wherein the clock output unit compares the signal with a reference clock to generate and output the first clock. apparatus.   The clock output means acquires information indicating the first clock from a transmission circuit that transmits the signal, and outputs the first clock. The signal processing device according to item.   The signal processing apparatus according to claim 1, wherein the predetermined frequency is higher than a frequency of the first clock.   The signal processing apparatus according to claim 1, wherein the signal is data transmitted by a differential transmission method. The adjustment means includes conversion means for converting and outputting serial data consisting of a difference between the signals transmitted by a differential transmission method,
The signal processing apparatus according to claim 12, wherein the setting value includes an offset value used by the adjustment unit to acquire a difference. The signal processing device according to any one of claims 1 to 13,
A transmission circuit for transmitting the signal to the signal processing device;
A transmission system comprising: Imaging means for capturing a subject and acquiring image data;
The signal processing device according to any one of claims 1 to 13,
A transmission circuit that generates the signal based on the image data and transmits the signal to the signal processing device;
An imaging apparatus comprising: A receiving means for receiving a signal, an adjusting means for adjusting a waveform of a signal from the receiving means based on a set value, a first clock based on the signal adjusted by the adjusting means, and a difference from the first clock A clock output means capable of switching and outputting a second clock having a predetermined frequency, and a control method of a signal processing device comprising:
A detection step of acquiring a value of the signal adjusted by the adjustment unit at a timing specified by a clock output by the clock output unit;
A control step of controlling the set value based on the value of the signal acquired by the detection means at a timing specified by the second clock;
A control method for a signal processing device, comprising:

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