JP2018107232A - Semiconductor device and manufacturing method for the same - Google Patents

Abstract

A MISFET having a constant channel length in a vertical direction is provided. A pair of SiGe layers (first semiconductor layers) are provided on a Si substrate, and one side surface is in contact with each other between the SiGe layers. A pair of SiGe layers 6 (second semiconductor layers) are provided, and the side surfaces facing each other between the SiGe layers 6 are in contact with each other and the strained Si layer 7 (third semiconductor layer) is sandwiched between the gates on the strained Si layer 7. A gate electrode 14 having a ridge structure extending on a sidewall 12 provided on the SiGe layer 6 is provided via an insulating film 13, and the buried Ge layer 5 is embedded in the Si substrate 1 immediately below the SiGe layer 6 and the strained Si layer 7. The n + -type source / drain regions (8, 11) are provided in the SiGe layer 2 and the n-type source / drain regions (9, 10) are provided in the SiGe layer 6 having end portions that are perpendicular to the main surface of the Si substrate 1. Each with a strain MISFET channel length is provided a constant (equal to) the channel region in the direction perpendicular to the Si layer 7. [Selection] Figure 1

Description

  The present invention relates to a semiconductor integrated circuit, and in particular, a structure in which a channel length (interval between source and drain regions) is constant (equal) in a direction perpendicular (depth) to a main surface of a semiconductor substrate by an easy manufacturing process. And forming a semiconductor integrated circuit including a high-speed, low-power, high-performance, high-reliability, and highly-integrated short channel MIS field effect transistor.

FIG. 48 is a schematic sectional side view of a conventional semiconductor device, showing a part of a semiconductor integrated circuit including an N-channel MIS field effect transistor formed on a semiconductor substrate by using an epitaxial growth method of a semiconductor layer. A p-type silicon substrate, 62 is a p-type SiGe layer, 63 is a p-type strained Si layer, 64 is a silicon oxide film in a trench element isolation region, 65 is an n ⁺ -type source region, 66 is an n-type source region, 67 Is an n-type drain region, 68 is an n ⁺ -type drain region, 69 is a gate oxide film, 70 is a gate electrode, 71 is a sidewall, 72 is a PSG film, 73 is a silicon nitride film, 74 is a barrier metal, 75 is a conductive plug , 76 are interlayer insulating films, 77 is a barrier metal, 78 is a Cu wiring, and 79 is a barrier insulating film.
In the figure, a p-type SiGe layer 62 is selectively provided on a p-type silicon substrate 61, a p-type strained Si layer 63 is provided immediately above the p-type SiGe layer 62, and a stacked SiGe layer is formed. 62 and the strained Si layer 63 are insulated and isolated by a trench for forming an element isolation region and a buried silicon oxide film (SiO ₂ ) 64. A gate electrode 70 is provided on the strained Si layer 63 via a gate oxide film 69, a sidewall 71 is provided on the side wall of the gate electrode 70, and the strained Si layer 63 is n-aligned in self-alignment with the gate electrode 70. The n ⁺ -type source / drain regions (65, 68) are provided in self-alignment with the source / drain regions (66, 67) and the sidewalls 71, and the barrier metal 74 is provided in each of the n ⁺ -type source / drain regions (65, 68). An N-channel MIS field effect transistor having a conventional LDD (Lightly Doped Drain) structure is formed in which a Cu wiring 78 having a barrier metal 77 is connected through a conductive plug 75 having a conductive layer.
Therefore, in comparison with an N channel MIS field effect transistor having a conventional LDD structure formed directly on a silicon substrate, a Si layer having a small lattice constant is stacked on a SiGe layer having a large lattice constant on the silicon substrate. Since a semiconductor substrate can be formed and an N-channel MIS field effect transistor having a conventional LDD structure can be formed on this semiconductor substrate, the lattice spacing of the Si layer can be widened by the tensile stress from the SiGe layer. It was possible to increase the speed by increasing the mobility.
However, since impurities are implanted from the upper surface of the semiconductor substrate having a stacked structure in self-alignment with the gate electrode to form low-concentration and high-concentration source / drain regions, the lateral diffusion of impurities is large in the upper part and approaches the lower part. (The deeper the impurity diffusion layer), the smaller (the channel length is the minimum distance between the source and drain regions in the vicinity of the semiconductor substrate surface is called the effective channel length, and the channel length gradually increases in deeper regions) Since the same channel length (constant channel length) cannot be obtained in the vertical (depth) direction, an ideal (no loss) current value could not be obtained for the voltage applied to the gate electrode. The gate electrode and the source / drain region overlap each other, the stray capacitance is large, and the withstand voltage between the source / drain regions is sufficient. There has been a problem such as that there is no.

JP-A-54-044282 (Japanese Patent No. 1718981) JP2012-142492 (Patent No. 5592281)

The problem to be solved by the present invention is that when a source / drain region of a MIS field effect transistor is formed on a semiconductor substrate, impurities are implanted from the upper surface of the semiconductor substrate in a self-aligned manner with the gate electrode, and heat treatment is performed to activate the impurities. Since the source / drain region is formed by diffusion and diffusion, the deeper the impurity diffusion layer, the greater the lateral diffusion near the surface of the semiconductor substrate.
(1) Since a channel region having an equal (constant) channel length in the perpendicular (depth) direction with respect to the main surface of the semiconductor substrate was not obtained, an ideal (loss) with respect to the voltage applied to the gate electrode The current value could not be obtained.
(2) Since the diffusion layer is formed as deeply as possible in order to reduce the resistance of the source / drain region, the overlap between the gate electrode and the source / drain region is large, and it is difficult to reduce the stray capacitance.
(3) Since a channel region having the same (constant) channel length could not be obtained, it was difficult to obtain a source / drain region having a stable breakdown voltage as the size was reduced.
Such a problem is becoming more prominent, and a method for forming a source / drain region that can obtain an equal (constant) channel length with little lateral diffusion regardless of the depth of the diffusion layer is expected.

  The object is to provide a semiconductor substrate, a pair of first semiconductor layers selectively provided on the semiconductor substrate, and a pair of first semiconductor layers provided in contact with one side surface between the pair of first semiconductor layers. A second semiconductor layer, a third semiconductor layer provided between the pair of second semiconductor layers so that opposing side surfaces are in contact with each other, and a gate insulating film provided on the third semiconductor layer A gate electrode provided through the gate insulating film, a high-concentration source or drain region provided in the pair of first semiconductor layers, and a low concentration provided in the pair of second semiconductor layers. A source or drain region having a concentration and a channel region provided in the third semiconductor layer, wherein at least the side surfaces of the source and drain regions facing each other are perpendicular to the main surface of the semiconductor substrate. Have and Yaneru length is solved by a semiconductor device of the present invention which is constant in the vertical direction.

As described above, according to the present invention, a normal inexpensive semiconductor substrate (Si) is used, and a pair of first semiconductor layers (SiGe layers) are formed on the semiconductor substrate by using a selective epitaxial growth method of the semiconductor layer. A pair of second semiconductor layers (SiGe layers) are provided in contact with one side surface between the pair of first semiconductor layers, and third surfaces are provided in contact with the opposing side surfaces between the pair of second semiconductor layers. A side wall having a reverse structure (on the conventional side wall) provided on the second semiconductor layer via a gate insulating film on the third semiconductor layer with a semiconductor layer (strained Si layer) interposed therebetween. A gate electrode having a ridge structure (a gate electrode having a structure having a longer gate length than the lower part) extending on the side wall having the opposite direction of the bent part, and the second semiconductor layer and the third semiconductor layer Embedded in the semiconductor substrate directly below An e layer is provided, the first semiconductor layer is provided with a high-concentration source / drain region in which the opposing side faces are perpendicular to the main surface of the semiconductor substrate, and the opposing side faces are provided in the second semiconductor layer. Is provided with a low concentration source / drain region having a plane perpendicular to the main surface of the semiconductor substrate, and the third semiconductor layer is provided with a channel region having an equal (constant) channel length in the vertical (depth) direction. The MIS field effect transistor having the above structure can be formed extremely finely in a self-aligned manner with the third semiconductor layer forming the channel region.
Further, since the opposite side surfaces of the low-concentration and high-concentration source / drain regions can be formed in a plane perpendicular to the main surface of the semiconductor substrate, the breakdown voltage between the source / drain regions can be improved and the vertical can be prevented. Since it is possible to obtain equal (constant) channel lengths in the (depth) direction, it is possible to increase the speed by being able to obtain an ideal (lossless) driving current with respect to the voltage applied to the gate electrode. It is.
Further, since the channel region independent of the depth of the diffusion layer in the source / drain region can be formed, the speed can be increased by reducing the resistance of the source / drain region.
In addition, since low-concentration and high-concentration source / drain regions can be formed while suppressing lateral impurity diffusion, the overlap between the gate electrode and the source / drain regions can be suppressed (substantially zero), resulting in high speed due to a reduction in stray capacitance. And miniaturization by further reducing the channel length.
In addition, since a strained Si layer (third semiconductor layer) having a small lattice constant can be formed in a structure sandwiched by SiGe layers (first and second semiconductor layers) having a large lattice constant from the left and right, the left and right SiGe layers (first and second semiconductor layers) can be formed. The lattice spacing from the strained Si layer (third semiconductor layer, channel region) from the first and second semiconductor layers can be increased, and the carrier mobility can be increased, thereby increasing the speed.
Further, by providing a high-concentration buried Ge layer on the semiconductor substrate, an epitaxially grown SiGe layer or strained Si layer can be grown only in the lateral direction, and a semiconductor layer with extremely few crystal defects can be formed.
In addition, the drain region can be formed in an LDD structure with improved hot electron effect, and the source region can be formed in a self-aligned high-concentration source region structure where there is no unnecessary low-concentration region, thereby reducing the resistance of the source region. It is also possible to form a faster asymmetric MIS field effect transistor.
In addition, the high-concentration source / drain region is formed by phosphorus forming an inclined junction in which the impurity distribution gradually changes instead of arsenic forming the stepped junction, and the channel length tends to be slightly shortened. It is also possible to form a fine N-channel MIS field effect transistor having no LDD structure and improved hot electron effect without providing a layer and a low concentration source / drain region.
In other words, high-speed, high-reliability, high-performance, low-power, and high-speed that enable the manufacture of semiconductor integrated circuits that can handle high-speed, large-capacity communication, portable information terminals, in-vehicle devices, various electronic mechanical devices, space-related devices, etc. An MIS field effect transistor having integration can be obtained.
The present inventors have in this technology (vertical (depth) direction) unchanged designated (fixed) MIS field effect transistor having a channel length (MISFET with I nvariable C hannel L ength), ICL ( Icy El) Abbreviated as structure.
Note that the details of the structure of the source / drain region will be described in the description of the manufacturing method. However, the impurity region formed in the semiconductor layer provided in advance is formed as a gate electrode (precisely, an opening for forming the gate electrode). Since the source and drain regions are formed by being divided into two by holes), the opposing side surfaces of the source region and the drain region can be opposed to each other in a plane perpendicular to the main surface of the semiconductor substrate.

Schematic side sectional view of the first embodiment of the semiconductor device of the present invention (channel length direction) Schematic side sectional view of the first embodiment of the semiconductor device of the present invention (channel width direction) Process sectional drawing (channel length direction) of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing (channel length direction) of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing (channel length direction) of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing (channel length direction) of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing (channel length direction) of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing (channel length direction) of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing (channel length direction) of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing (channel length direction) of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing (channel length direction) of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing (channel length direction) of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing (channel length direction) of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing (channel length direction) of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing (channel length direction) of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing (channel length direction) of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing (channel length direction) of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing (channel length direction) of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing (channel length direction) of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing (channel length direction) of the manufacturing method of 1st Example in the semiconductor device of this invention Schematic side sectional view of the second embodiment of the semiconductor device of the present invention (channel length direction) Process sectional drawing (channel length direction) of the manufacturing method of 2nd Example in the semiconductor device of this invention Process sectional drawing (channel length direction) of the manufacturing method of 2nd Example in the semiconductor device of this invention Process sectional drawing (channel length direction) of the manufacturing method of 2nd Example in the semiconductor device of this invention Process sectional drawing (channel length direction) of the manufacturing method of 2nd Example in the semiconductor device of this invention Process sectional drawing (channel length direction) of the manufacturing method of 2nd Example in the semiconductor device of this invention Process sectional drawing (channel length direction) of the manufacturing method of 2nd Example in the semiconductor device of this invention Process sectional drawing (channel length direction) of the manufacturing method of 2nd Example in the semiconductor device of this invention Process sectional drawing (channel length direction) of the manufacturing method of 2nd Example in the semiconductor device of this invention Process sectional drawing (channel length direction) of the manufacturing method of 2nd Example in the semiconductor device of this invention Process sectional drawing (channel length direction) of the manufacturing method of 2nd Example in the semiconductor device of this invention Process sectional drawing (channel length direction) of the manufacturing method of 2nd Example in the semiconductor device of this invention Process sectional drawing (channel length direction) of the manufacturing method of 2nd Example in the semiconductor device of this invention Process sectional drawing (channel length direction) of the manufacturing method of 2nd Example in the semiconductor device of this invention Schematic side sectional view of the third embodiment of the semiconductor device of the present invention (channel length direction) Process sectional drawing (channel length direction) of the manufacturing method of the 3rd Example in the semiconductor device of this invention Process sectional drawing (channel length direction) of the manufacturing method of the 3rd Example in the semiconductor device of this invention Process sectional drawing (channel length direction) of the manufacturing method of the 3rd Example in the semiconductor device of this invention Process sectional drawing (channel length direction) of the manufacturing method of the 3rd Example in the semiconductor device of this invention Process sectional drawing (channel length direction) of the manufacturing method of the 3rd Example in the semiconductor device of this invention Process sectional drawing (channel length direction) of the manufacturing method of the 3rd Example in the semiconductor device of this invention Process sectional drawing (channel length direction) of the manufacturing method of the 3rd Example in the semiconductor device of this invention Schematic side sectional view of the fourth embodiment in the semiconductor device of the present invention (channel length direction) Schematic side sectional view of the fifth embodiment in the semiconductor device of the present invention (channel length direction) Schematic side sectional view of the sixth embodiment in the semiconductor device of the present invention (channel length direction) Schematic side sectional view of the seventh embodiment in the semiconductor device of the present invention (channel length direction) Schematic side sectional view of the eighth embodiment in the semiconductor device of the present invention (channel length direction) Schematic side sectional view of a conventional semiconductor device (channel length direction)

In particular, the present invention
(1) Formation of the entire surface of the first semiconductor layer (SiGe layer) by epitaxial growth in the vertical (vertical) direction on a semiconductor substrate (Si) made of a complete single crystal.
(2) Formation of an element isolation region by patterning the first semiconductor layer and embedding an insulating film in the opening.
(3) Formation of an activated high concentration impurity region in the first semiconductor layer.
(4) Lamination of a mask material on the entire surface including on the first semiconductor layer.
(5) Formation of a high-concentration source region and a high-concentration drain region by dividing the first semiconductor layer in which the high-concentration impurity region is formed into two by an opening for forming a gate electrode.
(6) Formation of a buried Ge layer in the exposed semiconductor substrate by ion implantation of impurities into the opening.
(7) Formation of a second semiconductor layer (SiGe layer) containing low-concentration impurities by lateral epitaxial growth between the side surfaces of the remaining first semiconductor layer.
(8) Formation of side walls (SiO ₂ ) on the side walls of the mask material.
(9) Formation of a low concentration source region and a low concentration drain region by dividing the second semiconductor layer into two using the sidewall (SiO ₂ ) as a mask layer.
(10) Formation of a third semiconductor layer (strained Si layer) by lateral epitaxial growth between the side surfaces of the remaining second semiconductor layer.
(11) Formation of a gate electrode through a gate insulating film in the third semiconductor layer in which the threshold voltage is controlled.
(12) Formation of a wiring body to the high concentration source / drain region and the gate electrode.
Using technology such as
A pair of first semiconductor layers (SiGe layers) is provided on the semiconductor substrate, a pair of second semiconductor layers (SiGe layers) are provided between the pair of first semiconductor layers so that one side surface is in contact with each other, and a pair of first semiconductor layers is provided. Provided between the two semiconductor layers with the opposite side surfaces in contact with each other with a third semiconductor layer (strained Si layer) sandwiched therebetween, and provided on the second semiconductor layer over the third semiconductor layer with a gate insulating film interposed therebetween. A gate electrode having a saddle structure extending on the opposite sidewall is provided, a buried Ge layer is provided in a semiconductor substrate immediately below the second semiconductor layer and the third semiconductor layer, and the first semiconductor layer has A high-concentration source / drain region having a plane perpendicular to the main surface of the semiconductor substrate is provided, and the second semiconductor layer has a plane perpendicular to the main surface of the semiconductor substrate. A low concentration source / drain region having The semiconductor layer is obtained by forming a MIS field effect transistor having a vertical (depth) channel length is equal to the direction provided (fixed) channel region structure.

Hereinafter, the present invention will be described in detail with reference to the illustrated embodiments.
Throughout the drawings, the same object is denoted by the same reference numeral. However, the diagonal lines in the side cross-sectional view are shown only on the main insulating film, and the wiring is drawn with some forward and backward misalignment, and the size in the horizontal and vertical directions is accurate to show the main part of the invention. Dimensions are not shown. A dot indicates a buried Ge layer introduced into the semiconductor substrate.
1 to 20 show a first embodiment of the semiconductor device of the present invention. FIG. 1 is a schematic side sectional view in the channel length direction, FIG. 2 is a schematic side sectional view in the channel width direction, and FIGS. It is process sectional drawing of a method.

FIGS. 1 and 2 show a part of a semiconductor integrated circuit including an N-channel MIS field effect transistor formed in an ICL structure using a silicon (Si) substrate, where 1 is a p of about 10 ¹⁶ cm ^−3. Type silicon (Si) substrate, 2 is a p-type epitaxial SiGe layer of about 10 ¹⁷ cm ⁻³ (first semiconductor layer, high-concentration source / drain region forming portion), and 3 is a p of about 10 ¹⁸ cm ^{−3. +} Type channel stopper region, 4 is a buried silicon oxide film (SiO ₂ ) of trench element isolation region having a depth of about 100 nm, 5 is a buried Ge layer of about 5 × 10 ¹⁷ cm ⁻³ , and 6 is 5 × 10 ¹⁷ cm ^−. N-type epitaxial SiGe layer of about ³ (second semiconductor layer, low-concentration source / drain region forming portion), 7 is p-type epitaxial strain of about 10 ¹⁷ cm ⁻³ Si layer (third semiconductor layer, channel region forming portion), 8 is an n ⁺ type source region of about 10 ²⁰ cm ⁻³ , 9 is an n type drain region of about 5 × 10 ¹⁷ cm ⁻³ , and 10 is 5 × An n-type source region of about 10 ¹⁷ cm ⁻³ , 11 is an n ⁺ -type drain region of about 10 ²⁰ cm ⁻³ , 12 is a sidewall (SiO ₂ ) of about 20 nm, and 13 is a gate oxide film (SiO _{2 of} about 5 nm). ), 14 is a gate electrode (WSi) having a gate length of about 20 nm and a film thickness of about 100 nm, 15 is a phosphosilicate glass (PSG) film of about 300 nm, 16 is a silicon nitride film (Si ₃ N ₄ ) of about 20 nm, and 17 is Barrier metal (TiN) of about 10 nm, 18 is a conductive plug (W), 19 is an interlayer insulating film (SiOC) of about 500 nm, 20 is a barrier metal (TaN) of about 10 nm, 1 (including Cu seed layer) 500 nm of approximately Cu wiring 22 shows the 20nm approximately barrier insulating film _(Si 3 _{N 4).}

In FIG. 1 (channel length direction), a pair of p-type SiGe layers 2 (first semiconductor layers) are selectively provided immediately above a part of the p-type silicon substrate 1, and between the pair of SiGe layers 2. Is provided with a pair of n-type SiGe layers 6 (second semiconductor layers) in contact with one side surface, and a p-type strained Si layer 7 (first layer) between the pair of SiGe layers 6 in contact with opposite side surfaces. 3 semiconductor layers), and a semiconductor layer composed of a pair of SiGe layers 2, a pair of SiGe layers 6 and a strained Si layer 7 is formed into an island shape by a silicon oxide film (SiO ₂ ) 4 in the trench element isolation region. Isolated. The pair of SiGe layers 2 are provided with an n ⁺ -type source region 8 or an n ⁺ -type drain region 11 whose upper surface, lower surface, and four side surfaces are all flat, and the pair of SiGe layers 6 have an upper surface, a lower surface, and all four side surfaces. A planar n-type source region 9 or n-type drain region 10 is provided, a strained Si layer 7 is provided with a channel region, a gate oxide film (SiO ₂ ) 13 provided on the strained Si layer 7 and a pair of A gate electrode (WSi) 14 having a structure having a longer gate length is provided on the SiGe layer 6 through an inverted structure side wall (SiO ₂ ) 12 provided on the SiGe layer 6, and a pair of SiGe layer 6 and a strained Si layer are provided. 7 Ge layer 5 embedded on the upper portion of the silicon substrate 1 is provided immediately below, the silicon oxide film (SiO 2) ₄ directly below the trench isolation region p ⁺ -type channel list Par region 3 is provided on the ^{n +} -type source and drain regions (8, 11), Cu having a barrier metal (TaN) 20 via a conductive plug (W) 18 with a barrier metal (TiN) 17, respectively A side sectional view in the channel length direction of an N-channel MIS field effect transistor having an LDD structure to which the wiring 21 is connected is shown. (Details regarding the structure of the source / drain region will be described in the manufacturing method.)

In FIG. 2 (channel width direction), a p-type strained Si layer 7 (third semiconductor layer) is selectively provided immediately above a part of the p-type silicon substrate 1, and a p ⁺ -type channel stopper region is provided at the bottom. 3 is insulated and isolated in an island shape by a silicon oxide film (SiO ₂ ) 4 in the trench element isolation region. A buried Ge layer 5 is provided on the upper portion of the silicon substrate 1 immediately below the strained Si layer 7, and a silicon oxide film (SiO ₂ ) in the trench element isolation region is interposed on the strained Si layer 7 via a gate oxide film (SiO ₂ ) 13. ₂ ) A gate electrode (WSi) 14 having a structure with a longer gate length extending toward the top is provided, extending on 4 and having oppositely structured sidewalls (SiO ₂ ) 12 at both ends. Is a part of an N channel MIS field effect transistor to which a Cu wiring 21 having a barrier metal (TaN) 20 is connected via a conductive plug (W) 18 having a barrier metal (TiN) 17 in the channel width direction. A side sectional view is shown.

Therefore, a pair of first semiconductor layers (SiGe layers) is provided on a semiconductor substrate by using a normal inexpensive semiconductor substrate (Si) and a selective epitaxial growth method of the semiconductor layer, and the pair of first semiconductors. A pair of second semiconductor layers (SiGe layers) are provided in contact with each other between the side surfaces, and a third semiconductor layer (strained Si layer) is provided in contact with the opposing side surfaces between the pair of second semiconductor layers. On the opposite side wall (side wall opposite to the conventional side wall) provided on the second semiconductor layer via the gate insulating film on the third semiconductor layer. A gate electrode having a ridge structure (a gate electrode having a longer gate length above the lower portion) extending to the second semiconductor layer, a buried Ge layer on the semiconductor substrate immediately below the second semiconductor layer and the third semiconductor layer, 1 semiconductor layer A high-concentration source / drain region having a plane perpendicular to the main surface of the semiconductor substrate is provided, and the second semiconductor layer has a plane perpendicular to the main surface of the semiconductor substrate. A MIS field effect transistor having a structure in which a channel region having a constant channel length in the vertical (depth) direction is provided in the third semiconductor layer. It can be formed very finely in a self-aligned manner with the third semiconductor layer to be formed.
Further, since the opposite side surfaces of the low-concentration and high-concentration source / drain regions can be formed in a plane perpendicular to the main surface of the semiconductor substrate, the breakdown voltage between the source / drain regions can be improved and the vertical can be prevented. Since it is possible to obtain equal (constant) channel lengths in the (depth) direction, it is possible to increase the speed by being able to obtain an ideal (lossless) driving current with respect to the voltage applied to the gate electrode. It is.
Further, since the channel region independent of the depth of the diffusion layer in the source / drain region can be formed, the speed can be increased by reducing the resistance of the source / drain region.
In addition, since low-concentration and high-concentration source / drain regions can be formed while suppressing lateral impurity diffusion, the overlap between the gate electrode and the source / drain regions can be suppressed (substantially zero), resulting in high speed due to a reduction in stray capacitance. And miniaturization by further reducing the channel length.
In addition, since a strained Si layer (third semiconductor layer) having a small lattice constant can be formed in a structure sandwiched by SiGe layers (first and second semiconductor layers) having a large lattice constant from the left and right, the left and right SiGe layers (first and second semiconductor layers) can be formed. The lattice spacing from the strained Si layer (third semiconductor layer, channel region) from the first and second semiconductor layers can be increased, and the carrier mobility can be increased, thereby increasing the speed.
Further, by providing a high-concentration buried Ge layer on the semiconductor substrate, an epitaxially grown SiGe layer or strained Si layer can be grown only in the lateral direction, and a semiconductor layer with extremely few crystal defects can be formed.
In other words, high-speed, high-reliability, high-performance, low-power, and high-speed that enable the manufacture of semiconductor integrated circuits that can handle high-speed, large-capacity communication, portable information terminals, in-vehicle devices, various electronic mechanical devices, space-related devices, etc. An MIS field effect transistor having integration can be obtained.

  Next, the manufacturing method of the first embodiment of the semiconductor device according to the present invention will be described with reference to FIGS. 1 to 20 mainly using the drawings showing the channel length direction. However, here, only the manufacturing method related to the formation of the semiconductor device of the present invention is described, and the description of the manufacturing method related to the formation of various elements (other transistors, resistors, capacitors, etc.) mounted on a general semiconductor integrated circuit is omitted. To do.

Figure 3 (channel length direction)
A p-type longitudinal (vertical) direction epitaxial SiGe layer 2 (first semiconductor layer, Ge concentration of about 20%) of about 100 nm is grown on the p-type silicon substrate 1.

Fig. 4 (channel length direction)
Next, using a normal lithography technique by an exposure drawing apparatus, the SiGe layer 2 is anisotropically etched using a resist (not shown) as a mask layer to form a shallow trench exposing a part of the silicon substrate 1.

Figure 5 (channel length direction)
Next, boron is implanted into the exposed silicon substrate 1 to form the channel stopper region 3 using a resist (not shown) as a mask layer. Next, the resist (not shown) is removed.

Fig. 6 (channel length direction)
Next, a silicon oxide film (SiO ₂ ) of about 100 nm is grown by chemical vapor deposition. Next, chemical mechanical polishing (hereinafter abbreviated as CMP) is performed, the silicon oxide film (SiO ₂ ) on the flat surface of the SiGe layer 2 is removed, and the silicon oxide film (SiO ₂ ) 4 is flatly embedded in the trench.

Fig. 7 (channel length direction)
Next, a silicon oxide film (SiO ₂ , not shown) for ion implantation of about 5 nm is grown by chemical vapor deposition. Next, ion implantation of arsenic for forming an n ⁺ -type impurity region is performed. Next, annealing is performed at about 1000 ° C. to form an n ⁺ -type impurity region 23 (finally a high-concentration source / drain region) of about 50 nm in the SiGe layer 2. Next, the silicon oxide film (SiO ₂ , not shown) for ion implantation is removed by etching.

Fig. 8 (channel length direction)
Next, a silicon nitride film (Si ₃ N ₄ ) 24 of about 100 nm is grown by chemical vapor deposition.

Figure 9 (channel length direction)
Next, the silicon nitride film (Si ₃ N ₄ ) 24 and the SiGe layer 2 are anisotropically etched sequentially using a resist (not shown) as a mask layer using a normal lithography technique by an exposure drawing apparatus, An opening (a shortest opening width is about 50 nm) that exposes part of the surface is formed. At this time, the n ⁺ -type impurity region 23 is divided into two, the end portion has a side surface perpendicular to the main surface of the silicon substrate 1, and becomes the n ⁺ -type source region 8 and the n ⁺ -type drain region 11 that face each other. Next, the resist (not shown) is removed.

Figure 10 (channel length direction)
Next, germanium (Ge) ions are implanted into the surface of the silicon substrate 1 exposed through the opening. This is to fill the exposed surface of the silicon substrate 1 with a high concentration germanium (Ge) layer 5.

FIG. 11 (channel length direction)
Next, an n-type lateral (horizontal) epitaxial SiGe layer 6 between the side surfaces of the exposed SiGe layer 2 by an ECR plasma CVD enhanced chemical vapor deposition deposition system capable of low temperature growth (500 ° C. or less) ( A second semiconductor layer, Ge concentration of about 20%) is grown. At this time, the SiGe layer 6 does not grow in the vertical (vertical) direction from the silicon substrate 1 whose surface is filled with the germanium (Ge) layer 5 having a high concentration. Thus, the epitaxial SiGe layer 6 is grown only in the lateral (horizontal) direction, thereby preventing crystal defects in the crystal growth. Since this n-type SiGe layer 6 is divided into two portions to form a low-concentration source / drain region, the n-type SiGe layer 6 is formed at about 5 × 10 ¹⁷ cm ⁻³ .

Figure 12 (channel length direction)
Next, a silicon oxide film (SiO ₂ ) of about 15 nm is grown by chemical vapor deposition. Next, the entire surface is anisotropically etched to form a side wall (SiO ₂ ) 12 only on the side wall of the opening.

FIG. 13 (channel length direction)
Next, the SiGe layer 6 is anisotropically etched using the sidewall (SiO ₂ ) 12 and the silicon nitride film (Si ₃ N ₄ ) 24 as a mask layer, and the surface is filled with the germanium (Ge) layer 5 having a high concentration. A part of the substrate 1 is exposed. At this time, the n-type SiGe layer 6 is divided into two, and the end portion has a plane perpendicular to the main surface of the silicon substrate 1 and becomes an n-type source region 9 and an n-type drain region 10 which face each other.

Fig. 14 (channel length direction)
Next, a p-type lateral (horizontal) epitaxial strained Si layer 7 (third semiconductor layer) is grown between the exposed side surfaces of the SiGe layer 6 by an ECR plasma CVD apparatus capable of low temperature growth (500 ° C. or less). At this time, the strained Si layer 7 does not grow in the vertical (vertical) direction from the silicon substrate 1 whose surface is filled with the germanium (Ge) layer 5 having a high concentration. Thus, by growing the epitaxial strained Si layer 7 only in the lateral (horizontal) direction, crystal defects in the crystal growth are prevented.

FIG. 15 (channel length direction)
Next, the exposed surface of the strained Si layer 7 is thermally oxidized to grow a gate oxide film (SiO ₂ ) 13 of about 5 nm. Next, boron ions for controlling the threshold voltage are implanted into the strained Si layer 7. (When the strained Si layer 7 is epitaxially grown, it may be epitaxially grown to a concentration in which the threshold voltage is controlled.) Next, annealing is performed at a relatively low temperature, and boron for controlling the threshold voltage of the strained Si layer 7 serving as the channel region is used. Activate.

FIG. 16 (channel length direction)
Next, a tungsten silicide film (WSi) of about 100 nm is grown by chemical vapor deposition. Next, chemical mechanical polishing (CMP) is performed to remove the tungsten silicide film (WSi) grown on the silicon nitride film (Si ₃ N ₄ ) 24, and the gate electrode (WSi) 14 in which the opening is flatly buried is formed. Form. At this time, the gate electrode (WSi) 14 has a sidewall (SiO ₂ ) 12 having an inverse structure on the side wall, and is formed in a longer structure (effective gate length is the lowermost portion) as the gate length is higher. In the strained Si layer 7, channel regions having the same channel length are formed in the vertical (depth) direction. (In other words, the distance between the source region and the drain region is equal in the vertical (depth) direction.)

FIG. 17 (channel length direction)
Next, the silicon nitride film (Si ₃ N ₄ ) 24 is removed by etching using the gate electrode (WSi) 14 as a mask layer.

FIG. 18 (channel length direction)
Next, a phosphosilicate glass (PSG) film 15 of about 300 nm is grown by chemical vapor deposition. Then, chemical mechanical polishing (CMP) is performed and planarization is performed. Next, a silicon nitride film (Si ₃ N ₄ ) 16 of about 20 nm is grown by chemical vapor deposition.

FIG. 19 (channel length direction)
Next, using a normal lithography technique by an exposure drawing apparatus, the silicon nitride film (Si ₃ N ₄ ) 16 and the PSG film 15 are sequentially anisotropically etched using a resist (not shown) as a mask layer to form a via. . Next, the resist (not shown) is removed.

FIG. 20 (channel length direction)
Next, TiN 17 serving as a barrier metal is grown by chemical vapor deposition. Next, tungsten (W) 18 is grown by chemical vapor deposition. Next, a conductive plug (W) 18 having a barrier metal (TiN) 17 is formed by chemical mechanical polishing (CMP).

Fig. 1 (channel length direction), Fig. 2 (channel width direction)
Next, an interlayer insulating film (SiOC) 19 having a thickness of about 500 nm is grown by chemical vapor deposition. Next, using an ordinary lithography technique by an exposure drawing apparatus, the interlayer insulating film (SiOC) 19 is anisotropically etched using a resist (not shown) as a mask layer to form an opening. (At this time, the silicon nitride film (Si ₃ N ₄ ) 16 becomes an etching stopper film.) Next, the resist (not shown) is removed. Next, a barrier metal (TaN) 20 of about 10 nm is grown by chemical vapor deposition. Next, a Cu seed layer is grown by sputtering. Next, Cu of about 500 nm is grown by electrolytic plating. Next, chemical mechanical polishing (CMP) is performed, and Cu is embedded in the opening portion flatly to form a Cu wiring 21 having a barrier metal (TaN) 20. Next, a silicon nitride film (Si ₃ N ₄ ) 22 serving as a Cu barrier insulating film is grown by chemical vapor deposition to complete the ICL structure semiconductor device (N-channel MIS field effect transistor) of the present invention.

  FIGS. 21 to 34 show a second embodiment of the semiconductor device of the present invention. FIG. 21 is a schematic side sectional view in the channel length direction, and FIGS. 22 to 34 are a part of process sectional views of the manufacturing method.

FIG. 21 (channel length direction) is a schematic cross-sectional side view of the second embodiment of the semiconductor device of the present invention, which shows an asymmetric N-channel MIS field effect transistor formed in an ICL structure using a silicon (Si) substrate. 1 to 8 and 10 to 22 are the same as those in FIG. 1, and 25 is a silicon nitride film (Si ₃ N ₄ ).
This figure is almost the same as FIG. 1 except that the side wall (SiO ₂ ) 12 is not provided on the side wall of the gate electrode (WSi) 14 on the source region side and the n-type source region 9 is not provided. An N-channel asymmetric MIS field effect transistor having a structure is formed.
In this embodiment, the same effect as that of the first embodiment can be obtained. Further, the drain region can be formed in an LDD structure with improved hot electron effect, and the source region has no unnecessary low concentration region. Since it can be formed in a self-aligned manner with the concentration source region structure, it is possible to increase the speed by reducing the resistance of the source region, and it is also possible to form a fine MIS field-effect transistor because no n-type source region is provided. Is possible.

Next, a manufacturing method of the second embodiment of the semiconductor device according to the present invention will be described with reference to FIGS.
After performing the steps of FIGS. 3 to 6 shown in the first embodiment, the step of FIG. 22 is performed.

FIG. 22 (channel length direction)
Next, the silicon oxide film (SiO ₂ ) 4 is anisotropically etched by about 10 nm to form minute steps. Next, a silicon nitride film (Si ₃ N ₄ ) 25 of about 10 nm is grown by chemical vapor deposition. Next, chemical mechanical polishing (CMP) is performed, the silicon nitride film (Si ₃ N ₄ ) 25 on the flat surface of the SiGe layer 2 is removed, and a silicon nitride film (Si ₃ N ₄ ) 25 is embedded and planarized in a minute step. To do.

FIG. 23 (channel length direction)
Next, a silicon oxide film (SiO ₂ , not shown) for ion implantation of about 5 nm is grown by chemical vapor deposition. Next, ion implantation of arsenic for forming an n ⁺ -type impurity region is performed. Next, annealing is performed at about 1000 ° C. to form an n ⁺ -type impurity region 23 (finally a high-concentration source / drain region) of about 50 nm in the SiGe layer 2. Next, the silicon oxide film (SiO ₂ , not shown) for ion implantation is removed by etching.

FIG. 24 (channel length direction)
Next, a silicon oxide film (SiO ₂ ) 26 of about 90 nm is grown by chemical vapor deposition. Next, a silicon nitride film (Si ₃ N ₄ ) 27 of about 10 nm is grown by chemical vapor deposition.

FIG. 25 (channel length direction)
Next, using a normal lithography technique by an exposure drawing apparatus, the silicon nitride film (Si ₃ N ₄ ) 27, the silicon oxide film (SiO ₂ ) 26, and the SiGe layer 2 are sequentially different using a resist (not shown) as a mask layer. Isotropic etching is performed to form an opening (a shortest opening width is about 50 nm) exposing a part of the surface of the silicon substrate 1. At this time, the n ⁺ -type impurity region 23 is divided into two, the end portion has a side surface perpendicular to the main surface of the silicon substrate 1, and becomes the n ⁺ -type source region 8 and the n ⁺ -type drain region 11 that face each other. Next, the resist (not shown) is removed.

FIG. 26 (channel length direction)
Next, germanium (Ge) ions are implanted into the surface of the silicon substrate 1 exposed through the opening. This is to fill the exposed surface of the silicon substrate 1 with a high concentration germanium (Ge) layer 5.

FIG. 27 (channel length direction)
Next, an n-type lateral (horizontal) epitaxial SiGe layer 6 (second semiconductor layer, Ge concentration of about 20%) is formed between the exposed side surfaces of the SiGe layer 2 by an ECR plasma CVD apparatus capable of low temperature growth (500 ° C. or less). ) Grow. At this time, the SiGe layer 6 does not grow in the vertical (vertical) direction from the silicon substrate 1 whose surface is filled with the germanium (Ge) layer 5 having a high concentration. Thus, the epitaxial SiGe layer 6 is grown only in the lateral (horizontal) direction, thereby preventing crystal defects in the crystal growth. Since this n-type SiGe layer 6 is divided thereafter to form a low-concentration drain region, the n-type SiGe layer 6 is formed at about 5 × 10 ¹⁷ cm ⁻³ .

FIG. 28 (channel length direction)
Next, a silicon oxide film (SiO ₂ ) of about 15 nm is grown by chemical vapor deposition. Next, the entire surface is anisotropically etched to form a side wall (SiO ₂ ) 12 only on the side wall of the opening.

FIG. 29 (channel length direction)
Next, a resist (not shown) and a silicon nitride film (Si ₃ N ₄ ) (27, 25) are formed as mask layers on the side wall of the opening portion on the source region side using a normal lithography technique by an exposure drawing apparatus. The etched sidewall (SiO ₂ ) 12 is anisotropically etched. Next, the resist (not shown) is removed.

FIG. 30 (channel length direction)
Next, the SiGe layer 6 is anisotropically etched using the sidewall (SiO ₂ ) 12 and the silicon nitride film (Si ₃ N ₄ ) (27, 25) left on the drain region side as a mask layer, and the surface has a high concentration. A part of the silicon substrate 1 filled with the germanium (Ge) layer 5 is exposed. At this time, the n-type SiGe layer 6 is left only directly under the sidewall (SiO ₂ ) 12 on the drain region side to become the n-type drain region 10.

Figure 31 (channel length direction)
Next, a p-type lateral (horizontal) epitaxial strained Si layer 7 (third semiconductor layer) is formed between the exposed side surfaces of the SiGe layer 2 and the SiGe layer 6 by an ECR plasma CVD apparatus capable of low temperature growth (500 ° C. or lower). To grow. At this time, the strained Si layer 7 does not grow in the vertical (vertical) direction from the silicon substrate 1 whose surface is filled with the germanium (Ge) layer 5 having a high concentration. Thus, by growing the epitaxial strained Si layer 7 only in the lateral (horizontal) direction, crystal defects in the crystal growth are prevented.

Figure 32 (channel length direction)
Next, the exposed surface of the strained Si layer 7 is thermally oxidized to grow a gate oxide film (SiO ₂ ) 13 of about 5 nm. Next, boron ions for controlling the threshold voltage are implanted into the strained Si layer 7. (When the strained Si layer 7 is epitaxially grown, it may be epitaxially grown to a concentration in which the threshold voltage is controlled.) Next, annealing is performed at a relatively low temperature, and boron for controlling the threshold voltage of the strained Si layer 7 serving as the channel region is used. Activate.

FIG. 33 (channel length direction)
Next, a tungsten silicide film (WSi) of about 100 nm is grown by chemical vapor deposition. Next, chemical mechanical polishing (CMP) is performed to remove the tungsten silicide film (WSi) grown on the silicon nitride film (Si ₃ N ₄ ) 27, and the gate electrode (WSi) 14 in which the opening is flatly buried is formed. Form. At this time, the gate electrode (WSi) 14 has a side wall (SiO ₂ ) 12 having an inverted structure only on the side wall on the drain region side, and has a longer structure (effective gate length is the lowest) as the gate length becomes higher. Although formed, in the strained Si layer 7, channel regions having the same channel length are formed in the vertical (depth) direction. (In other words, the distance between the source region and the drain region is equal in the vertical (depth) direction.)

FIG. 34 (channel length direction)
Next, using the gate electrode (WSi) 14 as a mask layer, the silicon nitride film (Si ₃ N ₄ ) 27 and the silicon oxide film (SiO ₂ ) 26 are sequentially anisotropically etched.

  Thereafter, the steps of FIGS. 18 to 20 and FIG. 1 shown in the first embodiment are performed to complete the ICL structure semiconductor device (N-channel asymmetric MIS field effect transistor) of the present invention. (Completed drawing, Fig. 21 (channel length direction))

FIG. 35 is a schematic sectional side view of the third embodiment of the semiconductor device of the present invention, which is a part of a semiconductor integrated circuit including an N-channel MIS field effect transistor formed in an ICL structure using a silicon (Si) substrate. 1 to 11 and 13 to 22 are the same as in FIG. 1, 25 is the same as in FIG. 21, 28 is a buried silicon oxide film (SiO ₂ ), and 29 is a void.
In the figure, the side wall (SiO ₂ ) 12 is not formed, and a fine gate electrode having a gate length substantially equal to the distance (channel length) between the n-type source region 9 and the n-type drain region 10 is provided. 1 except that a buried silicon oxide film (SiO ₂ ) 28 is provided under the n-type source / drain regions (9, 10) and a hole 29 is formed immediately below the channel region. An N-channel MIS field effect transistor having the same structure is formed.
In this embodiment, the same effect as in the first embodiment can be obtained, and a hole can be formed immediately below the channel region, so that the capacity between the channel region and the semiconductor substrate during operation can be reduced, and the speed can be increased. It is.

Next, a manufacturing method of the third embodiment of the semiconductor device according to the present invention will be described with reference to FIGS. 36 to 42 and FIG.
After performing the steps of FIGS. 3 to 6 shown in the first embodiment and FIGS. 22 to 25 shown in the second embodiment, the steps of FIG. 36 are performed.

FIG. 36 (channel length direction)
Next, the exposed silicon substrate 1 is isotropically etched by about 30 nm to form an opening portion having a ridge structure.

FIG. 37 (channel length direction)
Next, a silicon oxide film (SiO ₂ ) of about 15 nm is grown by chemical vapor deposition. Next, the entire surface of the silicon oxide film (SiO ₂ ) is anisotropically etched, and the silicon oxide film (SiO ₂ ) 28 is embedded only in the flange portion of the opening.

FIG. 38 (channel length direction)
Next, germanium (Ge) ions are implanted into the surface of the silicon substrate 1 exposed through the opening. This is to fill the exposed surface of the silicon substrate 1 with a high concentration germanium (Ge) layer 5.

FIG. 39 (channel length direction)
Next, the SiGe layer 2 whose side surface is exposed is isotropically etched by about 20 nm to form a hole portion having a ridge structure.

FIG. 40 (channel length direction)
Next, an n-type lateral (horizontal) epitaxial SiGe layer 6 (second semiconductor layer, Ge concentration of about 20%) is formed between the exposed side surfaces of the SiGe layer 2 by an ECR plasma CVD apparatus capable of low temperature growth (500 ° C. or less). ) Grow. At this time, the SiGe layer 6 does not grow in the vertical (vertical) direction from the silicon substrate 1 whose surface is filled with the germanium (Ge) layer 5 having a high concentration. Thus, the epitaxial SiGe layer 6 is grown only in the lateral (horizontal) direction, thereby preventing crystal defects in the crystal growth. Since this n-type SiGe layer 6 is divided into two portions to form a low-concentration source / drain region, the n-type SiGe layer 6 is formed at about 5 × 10 ¹⁷ cm ⁻³ . At this time, vacancies 29 are formed in a part under the SiGe layer 6.

FIG. 41 (channel length direction)
Next, using the silicon nitride film (Si ₃ N ₄ ) (27, 25) as a mask layer, the SiGe layer 6 is anisotropically etched through the opening, and the surface is filled with the germanium (Ge) layer 5 having a high concentration. A part of the substrate 1 is exposed. At this time, the n-type SiGe layer 6 is divided into two, and the end portion has a plane perpendicular to the main surface of the silicon substrate 1 and becomes an n-type source region 9 and an n-type drain region 10 which face each other.

Fig. 42 (channel length direction)
Next, a p-type lateral (horizontal) epitaxial strained Si layer 7 (third semiconductor layer) is grown between the exposed side surfaces of the SiGe layer 6 by an ECR plasma CVD apparatus capable of low temperature growth (500 ° C. or less). At this time, the strained Si layer 7 does not grow in the vertical (vertical) direction from the silicon substrate 1 whose surface is filled with the germanium (Ge) layer 5 having a high concentration. Thus, by growing the epitaxial strained Si layer 7 only in the lateral (horizontal) direction, crystal defects in the crystal growth are prevented. At this time, vacancies 29 are re-formed just below the strained Si layer 7.

  Thereafter, the steps of FIGS. 32 to 34 shown in the second embodiment, FIGS. 18 to 20 and FIG. 1 shown in the first embodiment are performed, and the ICL structure semiconductor device of the present invention (N-channel MIS electric field). Effect transistor). (Completed drawing, Fig. 35 (channel length direction))

FIG. 43 is a schematic sectional side view of the fourth embodiment of the semiconductor device of the present invention, which is a part of a semiconductor integrated circuit including an N-channel MIS field effect transistor formed in an ICL structure using a silicon (Si) substrate. 1, 3 to 5, and 8 to 22 are the same as in FIG. 1, 30 is an n-type epitaxial Si layer (second semiconductor layer, low-concentration source / drain region forming portion), and 31 is p A type epitaxial Si layer (third semiconductor layer, channel region forming portion) is shown.
In the figure, the SiGe layer 2 is not provided on the silicon substrate 1, but the n ⁺ type source region 8 and the n ⁺ type drain region 11 are provided directly on the silicon substrate 1, and the n type epitaxial SiGe. An n-type epitaxial Si layer 30 (second semiconductor layer, low concentration source / drain region formation portion) is provided instead of the layer 6 (second semiconductor layer, low concentration source / drain region formation portion). In addition, a p-type epitaxial Si layer 31 (third semiconductor layer, channel region forming portion) is provided instead of the p-type epitaxial strained Si layer 7 (third semiconductor layer, channel region forming portion). Is formed with an N-channel MIS field effect transistor having substantially the same structure as in FIG.
In this embodiment, substantially the same effect as in the first embodiment can be obtained, and since the channel region is not formed in a strained structure, high speed cannot be achieved by improving mobility, but the manufacturing process is somewhat It can be simplified.

FIG. 44 is a schematic sectional side view of a fifth embodiment of the semiconductor device of the present invention, which is a part of a semiconductor integrated circuit including an N-channel MIS field effect transistor formed in an ICL structure using a silicon (Si) substrate. 1-5, 7, 8, 11, 13-22 show the same thing as FIG.
In the figure, the sidewall (SiO ₂ ) 12 is not formed, the n-type epitaxial SiGe layer 6 (second semiconductor layer, low-concentration source / drain region forming portion) is not provided, and n Except that the source region 9 and the n-type drain region 10 are not provided (that is, not the LDD structure) and that the n ⁺ -type source region 8 and the n ⁺ -type drain region 11 are formed of high-concentration phosphorus. An N-channel MIS field effect transistor having substantially the same structure as that of FIG. 1 is formed.
In this embodiment, the same effect as that of the first embodiment can be obtained, and a high concentration source / drain region can be formed by phosphorus capable of a slanted junction whose impurity distribution changes gradually. Since a short channel MIS field effect transistor with improved hot electron effect can be formed without providing a drain region, miniaturization and simplification of the manufacturing process are possible.

FIG. 45 is a schematic sectional side view of a sixth embodiment of the semiconductor device of the present invention, which is a part of a semiconductor integrated circuit including an N-channel MIS field effect transistor formed in an ICL structure using a silicon (Si) substrate. 1-5, 7, 8, 11, 13-22 are the same as in FIG. 1, and 28, 29 are the same as in FIG.
In the figure, the sidewall (SiO ₂ ) 12 is not formed, the n-type epitaxial SiGe layer 6 (second semiconductor layer, low-concentration source / drain region forming portion) is not provided, and n The n-type source region 9 and the n-type drain region 10 are not provided (that is, not the LDD structure), the n ⁺ -type source region 8 and the n ⁺ -type drain region 11 are formed of high-concentration phosphorus, p Embedded silicon oxide film (SiO ₂ ) 28 is provided below part of the epitaxial SiGe layer 2 (first semiconductor layer, high-concentration source / drain region forming portion), and vacancies 29 are provided immediately below the channel region. An N-channel MIS field effect transistor having substantially the same structure as that shown in FIG. 1 is formed except that it is formed.
In this embodiment, the same effect as in the first embodiment can be obtained, and since a hole can be formed immediately below the channel region, the speed between the channel region and the semiconductor substrate during operation can be reduced. In addition, it is possible to form a high-concentration source / drain region by using phosphorus that can be graded junction with a gradual change in impurity distribution, so that a short channel improved in hot electron effect without providing a low-concentration source / drain region. Since the MIS field effect transistor can be formed, miniaturization and simplification of the manufacturing process are possible.

FIG. 46 is a schematic sectional side view of a seventh embodiment of the semiconductor device of the present invention, which is a part of a semiconductor integrated circuit including an N-channel MIS field effect transistor formed in an ICL structure using a silicon (Si) substrate. 1, 3 to 5, 8, 11, 13 to 22 are the same as in FIG. 1, and 31 is the same as in FIG.
In the figure, the side wall (SiO ₂ ) 12 is not formed, the SiGe layer 2 is not provided on the silicon substrate 1, and the n ⁺ type source made of high-concentration phosphorus directly on the silicon substrate 1. The region 8 and the n ⁺ -type drain region 11 are provided, the n-type epitaxial SiGe layer 6 (second semiconductor layer, low-concentration source / drain region forming portion) is not provided, and the n-type source region 9 and the n-type drain region 10 are not provided (that is, not an LDD structure), and a p-type epitaxial Si layer is used instead of the p-type epitaxial strained Si layer 7 (third semiconductor layer, channel region forming portion). An N-channel MIS field effect transistor having substantially the same structure as that in FIG. 1 is formed except that 31 (third semiconductor layer, channel region forming portion) is provided. The
In this embodiment, substantially the same effect as in the first embodiment can be obtained, and since the channel region is not formed in a strained structure, high speed cannot be achieved by improving mobility, but the manufacturing process is somewhat High concentration source / drain regions can be formed with phosphorus, which can be simplified, and can be graded junctions with a gradual change in impurity distribution, improving hot electron effect without providing low concentration source / drain regions Since the short channel MIS field effect transistor can be formed, miniaturization and simplification of the manufacturing process are possible.

FIG. 47 is a schematic sectional side view of an eighth embodiment of the semiconductor device of the present invention, which is a part of a semiconductor integrated circuit including an N-channel MIS field effect transistor formed in an ICL structure using a silicon (Si) substrate. 1 to 4 and 6 to 22 are the same as in FIG. 1, 25 is the same as in FIG. 21, 32 is a buried silicon oxide film (SiO ₂ ), and 33 is a hole.
In the figure, the buried Ge layer 5 is not formed on the semiconductor substrate, and a vacancy 33 is formed immediately below the p-type epitaxial strained Si layer 7 (third semiconductor layer, channel region forming portion). And embedded silicon under the n-type epitaxial SiGe layer 6 (second semiconductor layer, low-concentration source / drain region forming portion) and the p-type epitaxial strained Si layer 7 (third semiconductor layer, channel region forming portion). An N-channel MIS field effect transistor having substantially the same structure as that of FIG. 1 is formed except that an oxide film (SiO ₂ ) 32 is formed.
In this embodiment, the same effect as in the first embodiment can be obtained, and since a hole can be formed immediately below the channel region, the speed between the channel region and the semiconductor substrate during operation can be reduced. It is also possible to provide high-performance second and third semiconductor layers that prevent crystal defects without providing a buried Ge layer.

In the above embodiment, chemical vapor deposition is used when growing the semiconductor layer. However, the present invention is not limited to this, and molecular beam epitaxy (MBE) or metal organic chemical vapor deposition (MOCVD) is also used. Alternatively, atomic layer crystal growth (ALE) or any other crystal growth method may be used.
All of the above embodiments describe the case where a single channel (N channel or P channel) MIS field effect transistor is formed. However, a CMOS in which N channel and P channel MIS field effect transistors coexist is formed. However, the present invention is established.
The gate electrode, the gate oxide film, the barrier metal, the conductive plug, the wiring, the insulating film, and the like are not limited to the above embodiments, and any material may be used as long as it has the same characteristics.
In addition, although all of the above embodiments describe the case where an enhancement type MIS field effect transistor is formed, a depletion type MIS field effect transistor may be formed. In this case, an epitaxial semiconductor layer having the opposite conductivity type is grown, or an epitaxial semiconductor layer having a similar structure is formed by growing an epitaxial semiconductor layer and then ion-implanting an impurity of the opposite conductivity type to convert the conductivity type. A MIS field effect transistor may be formed.
In the above embodiment, a MIS field effect transistor that operates at a standard power supply voltage is used. However, the offset region (distance from the high concentration drain region to the end of the gate electrode, the length of the low concentration drain region). ) Can be applied to a high breakdown voltage MIS field effect transistor.
In the above embodiment, a single element semiconductor substrate is used. However, it is also possible to form the semiconductor device using a compound semiconductor substrate (or a compound semiconductor layer formed on the single element semiconductor substrate). is there.

The present invention is particularly aimed at a high-speed, high-performance and highly-integrated MIS field effect transistor. However, the present invention is not limited to high-speed, and can be used for all semiconductor integrated circuits equipped with a MIS field-effect transistor. It is.
Moreover, it can be used not only as a semiconductor integrated circuit but also as a single individual semiconductor element.
In addition to the MIS field effect transistor, it may be used for other field effect transistors.

1 p-type silicon (Si) substrate 2 p-type epitaxial SiGe layer (first semiconductor layer, high-concentration source / drain region forming portion)
3 p ⁺ type channel stopper region 4 Trench element isolation region buried silicon oxide film (SiO ₂ )
5 buried Ge layer 6 n-type epitaxial SiGe layer (second semiconductor layer, low concentration source / drain region forming part)
7 p-type epitaxial strained Si layer (third semiconductor layer, channel region forming portion)
8 n ⁺ type source region 9 n type source region 10 n type drain region 11 n ⁺ type drain region 12 Side wall (SiO ₂ )
13 Gate oxide film (SiO ₂ )
14 Gate electrode (WSi)
15 Phosphorsilicate glass (PSG) film 16 Silicon nitride film (Si ₃ N ₄ )
17 Barrier metal (TiN)
18 Conductive plug (W)
19 Interlayer insulation film (SiOC)
20 Barrier metal (TaN)
21 Cu wiring (including Cu seed layer)
22 Barrier insulating film (Si ₃ N ₄ )
23 n ⁺ type impurity region 24 Silicon nitride film (Si ₃ N ₄ )
25 Silicon nitride film (Si ₃ N ₄ )
26 Silicon oxide film (SiO ₂ )
27 Silicon nitride film (Si ₃ N ₄ )
28 Embedded silicon oxide film (SiO ₂ )
29 vacancy 30 n-type epitaxial Si layer (second semiconductor layer, low concentration source / drain region forming portion)
31 p-type epitaxial Si layer (third semiconductor layer, channel region forming portion)
32 buried silicon oxide film (SiO ₂ )
33 holes

Claims (8)

  A semiconductor substrate, a pair of first semiconductor layers selectively provided on the semiconductor substrate, and a pair of second semiconductor layers provided in contact with one side surface between the pair of first semiconductor layers A third semiconductor layer provided between the pair of second semiconductor layers so that opposite side surfaces are in contact with each other, a gate insulating film provided on the third semiconductor layer, and the gate A gate electrode provided by being stacked with an insulating film interposed therebetween, a high-concentration source or drain region provided in the pair of first semiconductor layers, and a low electrode provided in the pair of second semiconductor layers A source region or a drain region having a concentration and a channel region provided in the third semiconductor layer, wherein at least the side surfaces of the source region and the drain region facing each other are perpendicular to the main surface of the semiconductor substrate Have One channel length is constant in the vertical (depth) direction (equivalent) wherein a.   The semiconductor device according to claim 1, wherein an introduction layer made of a group 4 element different from the semiconductor substrate is provided at least on the semiconductor substrate immediately below the third semiconductor layer.   2. The semiconductor device according to claim 1, wherein a lattice constant of the first and second semiconductor layers is larger than a lattice constant of the third semiconductor layer.   2. The semiconductor device according to claim 1, wherein at least one end portion of the gate electrode is provided in a ridge structure, and a sidewall is provided by embedding the ridge structure.   The semiconductor device according to claim 1, wherein the second semiconductor layer is not provided and the third semiconductor layer is provided between the first semiconductor layers.   The semiconductor device according to claim 1, wherein a hole is provided immediately below the third semiconductor layer.   In a first semiconductor layer provided with an activated impurity region selectively provided on a semiconductor substrate, a mask material is formed on the first semiconductor layer, and the mask material and the impurity region are The first semiconductor layer thus formed is selectively and anisotropically etched to form an opening, thereby forming a source region and a drain region in which the impurity region is divided into left and right, and then exposing the first and second regions. Forming a Group 4 element introduction layer on the semiconductor substrate, and then epitaxially forming a second semiconductor layer between the exposed side surfaces of the first semiconductor layer, and then on the second semiconductor layer. A method of manufacturing a semiconductor device, comprising: forming a gate electrode that embeds the opening portion through a gate insulating film in a self-aligned manner with the gate electrode and the source / drain region.   In the first semiconductor layer in which the activated high-concentration impurity region is selectively provided on the semiconductor substrate, a mask material is formed on the first semiconductor layer, and the mask material and the mask The first semiconductor layer in which the high concentration impurity region is formed is selectively and sequentially anisotropically etched to form the first opening portion, whereby the high concentration impurity region is divided into left and right portions. After forming the concentration source region and drain region, a Group 4 element introduction layer is formed on the exposed semiconductor substrate, and then a low concentration impurity is formed between the exposed side surfaces of the first semiconductor layer. And epitaxially forming a second semiconductor layer containing a sidewall, forming a sidewall on a sidewall of the first opening, and anisotropically etching the second semiconductor layer exposed between the sidewalls To form the second aperture As a result, a low-concentration source region and a drain region in which the low-concentration impurity region is divided into left and right are formed, and then a third semiconductor layer is epitaxially formed between the exposed side surfaces of the second semiconductor layer. Thereafter, a gate electrode is formed on the third semiconductor layer to fill the first opening portion in which the sidewall is formed via a gate insulating film, thereby forming the gate electrode and the low concentration and A method of manufacturing a semiconductor device, wherein a high concentration source / drain region is formed in a self-aligned manner.