JP2018101738A - Substrate processing device, substrate processing system and substrate processing method - Google Patents

Abstract

A substrate processing apparatus effective for further flattening the surface of a film formed on a substrate is provided. A film forming apparatus (2) has a hot plate (20) including a plurality of heating regions (21, 22, 23, 24, 25), and uses the hot plate (20) to apply a CMP process to a surface of a wafer (W). obtaining first information about the thickness of the hard mask before the CMP process and second information about the thickness of the hard mask after the CMP process for a plurality of portions of the wafer W in a processing block 12 for forming a mask; deriving information about the amount of change in the thickness of the hard mask due to the CMP process based on the first information and the second information; , 24, 25, and a controller 200 configured to perform: [Selection drawing] Fig. 1

Description

  The present disclosure relates to a substrate processing apparatus, a substrate processing system, and a substrate processing method.

  Patent Document 1 discloses a substrate processing method in which after a film is formed on the surface of the substrate, the surface of the film is planarized by chemical mechanical polishing.

JP 2005-44910 A

  It is an object of the present disclosure to provide a substrate processing apparatus, a substrate processing system, and a substrate processing method that are effective for further planarizing the surface of a film formed on a substrate.

  A substrate processing apparatus according to an aspect of the present disclosure includes a thermal processing plate including a plurality of heating regions, and a film forming processing unit that forms a film to be subjected to a chemical mechanical polishing process on the surface of the substrate using the thermal plate The first information on the thickness of the film before the chemical mechanical polishing process and the second information on the thickness of the film after the chemical mechanical polishing process are obtained for the plurality of parts of the substrate. Deriving information on the amount of change in the film thickness due to the chemical mechanical polishing process, and adjusting the temperature setting for each heating region so as to correct the amount of change in each of the plurality of regions. And a control unit configured to execute.

  For example, when adjusting the temperature setting to correct the amount of change in each of the plurality of parts, the control unit adjusts the temperature setting for each heating region so as to reduce the difference in the amount of change between the parts. May be.

  Even if chemical mechanical polishing is performed on a film formed on the surface of the substrate, the surface of the film may not be flattened to a desired level. As a result of investigating and studying the cause, the inventors of the present application have a difference in film polishing resistance (hereinafter referred to as “film quality”) for each part of the substrate, and the chemical mechanical polishing process is caused by the difference. It was found that there is a possibility that the degree of progress of the variation is different. Based on this knowledge, the substrate processing apparatus derives information on the variation in the degree of progress of the chemical mechanical polishing process, and then adjusts the film formation conditions (conditions for forming the film) so as to reduce the variation. Is configured to do. That is, the control unit derives information on the change amount of the film thickness due to the chemical mechanical polishing process based on the first information and the second information, and corrects the change amount in each of the plurality of parts. The temperature setting for each heating region is adjusted. Thereby, the dispersion | variation in the progress of the chemical mechanical polishing process resulting from film quality can be reduced. Therefore, it is effective for further planarization of the surface of the film formed on the substrate.

  The plurality of heating regions may be arranged concentrically. The difference in film quality tends to vary depending on the distance from the center of the substrate. On the other hand, according to the configuration in which the plurality of heating regions are arranged concentrically, the temperature distribution of the hot plate can be adjusted according to the above tendency. Therefore, it is further effective for flattening the surface of the film formed on the substrate.

  The control unit acquires the pixel value in the captured image of the surface of the substrate as the first information and the second information, and the pixel before and after the chemical mechanical polishing process as information on the amount of change in the film thickness due to the chemical mechanical polishing process. The temperature setting for each heating region may be adjusted so that the amount of change in value is derived and the amount of change in pixel value in each of the plurality of parts is corrected. In this case, it is easy to simplify the apparatus configuration for acquiring the first information and the second information by using the pixel value in the captured image of the surface of the substrate as the substitute characteristic of the film thickness.

  A substrate processing system according to another aspect of the present disclosure includes a heat plate including a plurality of heating regions, and a film formation processing unit that forms a film on the surface of the substrate, and a film formed by the film formation processing unit. Acquires first information on film thickness before chemical mechanical polishing and second information on film thickness after chemical mechanical polishing for polishing parts that perform mechanical polishing and multiple parts of the substrate And deriving information on the amount of change in the film thickness due to the chemical mechanical polishing process based on the first information and the second information, and correcting the amount of change in each of the plurality of regions, for each heating region And a controller configured to perform the temperature setting adjustment.

  A substrate processing method according to another aspect of the present disclosure uses a hot plate including a plurality of heating regions, forms a film on the surface of the substrate, performs chemical mechanical polishing on the film, The first information on the thickness of the film before the chemical mechanical polishing process and the second information on the thickness of the film after the chemical mechanical polishing process are acquired for the part, and the chemical machine is based on the first information and the second information. Deriving information on the amount of change in film thickness due to the polishing process and adjusting the temperature setting for each heating region so as to correct the amount of change in each of the plurality of regions.

  According to the present disclosure, it is possible to provide a substrate processing apparatus, a substrate processing system, and a substrate processing method that are effective for further planarizing the surface of a film formed on a substrate.

It is a schematic diagram which shows the structure of a substrate processing system. It is a top view of a hot platen. It is sectional drawing of an inspection apparatus. It is a block diagram which shows the structure on the function of a control part. It is a table which illustrates the data memorized by a correlation data storage part. It is a block diagram which illustrates the hardware constitutions of a control part. It is a flowchart which shows a substrate processing procedure. It is a flowchart which shows the film-forming process order. It is a flowchart which shows a grinding | polishing processing procedure. It is a flowchart which shows the adjustment procedure of the temperature setting of a hot platen. It is a schematic diagram which shows the modification of a substrate processing system. It is a schematic diagram which shows the other modification of a substrate processing system.

  Hereinafter, embodiments will be described in detail with reference to the drawings. In the description, the same elements or elements having the same functions are denoted by the same reference numerals, and redundant description is omitted.

[Substrate processing system]
The substrate processing system 1 according to the present embodiment is an apparatus that forms a protective film on a substrate and smoothes the surface of the protective film by chemical mechanical polishing (CMP) processing. The substrate to be processed is, for example, a semiconductor wafer W. The protective film is a so-called hard mask such as spin-on-carbon (SOC). The chemical mechanical polishing process (hereinafter referred to as “CMP process”) is a process of polishing the surface with a polishing pad while supplying a polishing liquid (slurry) to the surface of the wafer W.

  As shown in FIG. 1, the substrate processing system 1 includes a film forming apparatus 2 and a polishing apparatus 3.

(Deposition system)
The film forming apparatus 2 (substrate processing apparatus) forms a hard mask to be subjected to CMP processing on the surface of the wafer W. For example, the film forming apparatus 2 includes a carrier block 11 and a processing block 12 that are adjacent to each other, and a control unit 200.

  The carrier block 11 introduces the wafer W into the film forming apparatus 2 and leads the wafer W from the film forming apparatus 2. For example, the carrier block 11 can support a plurality of carriers C1 for the wafer W, and incorporates a delivery arm A1. The carrier C1 accommodates a plurality of circular wafers W, for example. The delivery arm A1 takes out the wafer W from the carrier C1 and delivers it to the processing block 12, receives the wafer W from the processing block 12, and returns it into the carrier C1.

  The processing block 12 (film formation processing unit) forms a hard mask on the surface of the wafer W carried by the delivery arm A1. The processing block 12 includes a plurality of liquid processing units U1, a plurality of heat treatment units U2, an inspection unit U3, and a transfer arm A2 that transfers the wafer W to these units.

  The liquid processing unit U1 performs a process (hereinafter referred to as “coating process”) in which a hard mask forming process liquid is supplied to the surface of the wafer W to form a film. For example, the liquid processing unit U1 forms a film on the surface of the wafer W by so-called spin coating (supplying the processing liquid to the surface of the wafer W while rotating the wafer W and spreading the processing liquid by centrifugal force).

  The heat treatment unit U <b> 2 includes a hot plate 20, and performs a heat treatment for making the film into a hard mask using the hot plate 20. As shown in FIG. 2, the hot plate 20 includes a plurality of (for example, five) heating regions 21, 22, 23, 24, and 25. The heating areas 21, 22, 23, 24, and 25 are arranged concentrically. In other words, the heating regions 21, 22, 23, 24, and 25 have a circular outer shape with a common center, and are arranged in order from the center side to the outer peripheral side in the radial direction. Each of the heating regions 21, 22, 23, 24, and 25 has a built-in heater (for example, a heating wire) whose temperature can be individually adjusted.

  Returning to FIG. 1, the inspection unit U3 acquires first data relating to the film thickness of the hard mask formed by the liquid processing unit U1 and the heat treatment unit U2. For example, the inspection unit U3 includes an inspection device 30.

  As illustrated in FIG. 3, the inspection apparatus 30 includes a holding unit 31, a linear drive unit 32, an imaging unit 33, and a light projecting / reflecting unit 34. The holding unit 31 holds the wafer W horizontally. The linear drive unit 32 uses, for example, an electric motor as a power source, and moves the holding unit 31 along a horizontal linear path. The imaging unit 33 includes a camera 35 such as a CCD camera, for example. The camera 35 is provided on one end side in the inspection apparatus 30 in the moving direction of the holding unit 31 and is directed to the other end side in the moving direction. The light projecting / reflecting unit 34 projects light into the imaging range and guides reflected light from the imaging range to the camera 35 side. For example, the light projecting / reflecting unit 34 includes a half mirror 36 and a light source 37. The half mirror 36 is provided at an intermediate portion of the movement range of the linear drive unit 32 at a position higher than the holding unit 31, and reflects light from below to the camera 35 side. The light source 37 is provided on the half mirror 36 and irradiates illumination light downward through the half mirror 36.

  The inspection apparatus 30 operates as follows to acquire image data of the surface of the wafer W. First, the linear drive unit 32 moves the imaging unit 33. As a result, the wafer W passes under the half mirror 36. In this passing process, reflected light from each part of the surface of the wafer W is sequentially sent to the camera 35. The camera 35 forms an image of reflected light from each part on the surface of the wafer W, and acquires image data on the surface of the wafer W.

  Returning to FIG. 1, the control unit 200 controls the carrier block 11 and the processing block 12. The configuration of the control unit 200 will be described later collectively as the control unit 100 of the substrate processing system 1.

(Polishing equipment)
The polishing apparatus 3 performs a CMP process on the hard mask formed by the film forming apparatus 2. For example, the polishing apparatus 3 includes a carrier block 13 and a processing block 14 that are adjacent to each other, and a control unit 300.

  The carrier block 13 introduces the wafer W into the polishing apparatus 3 and leads the wafer W from the polishing apparatus 3. For example, the carrier block 13 can support the carrier C1 and incorporates a delivery arm A11. The transfer arm A11 takes out the wafer W from the carrier C1 and transfers it to the processing block 14, receives the wafer W from the processing block 14, and returns it to the carrier C1.

  The processing block 14 (polishing processing unit) performs CMP processing on the hard mask on the surface of the wafer W carried by the transfer arm A11. The processing block 14 includes a plurality of CMP units U11, a plurality of cleaning units U12, an inspection unit U13, and a transfer arm A12 that transfers the wafer W to these units.

  The CMP unit U11 performs a CMP process on the hard mask on the surface of the wafer W. The cleaning unit U12 cleans the wafer W after the CMP process.

  The inspection unit U13 acquires second data relating to the film thickness of the hard mask polished and cleaned by the CMP unit U11 and the cleaning unit U12. For example, the inspection unit U13 includes the above-described inspection device 30 in the same manner as the inspection unit U3.

  The control unit 300 controls the carrier block 13 and the processing block 14. The configuration of the control unit 300 will be described later collectively as the control unit 100 of the substrate processing system 1.

(Control part)
The substrate processing system 1 includes a control unit 100. The control unit 100 includes, for example, the control unit 200 of the film forming apparatus 2 and the control unit 300 of the polishing apparatus 3 described above.

  The control unit 200 controls the carrier block 11 and the processing block 12 so as to form a hard mask on the surface of the wafer W, and first relates to the thickness of the hard mask before CMP processing for a plurality of portions of the wafer W. Obtaining information and second information regarding the thickness of the hard mask after the CMP process, and deriving information regarding the amount of change in the thickness of the hard mask due to the CMP process based on the first information and the second information; Adjusting the temperature setting for each of the heating regions 21, 22, 23, 24, and 25 so as to correct the amount of change in each of the plurality of portions is performed.

  The information related to the thickness of the hard mask means information that is correlated with the thickness of the hard mask and has reproducibility in the correlation. For example, the information regarding the thickness of the hard mask may be a numerical value indicating the thickness of the hard mask itself, or may be another numerical value that can be a substitute characteristic of the thickness of the hard mask. The information related to the amount of change in the thickness of the hard mask means information that is correlated with the amount of change in the thickness and has reproducibility in the correlation. For example, the information regarding the amount of change in the thickness of the hard mask may be the difference between the first information and the second information, or the ratio of the second information to the first information (or the ratio of the first information to the second information). ). Correction means to bring it close to an appropriate state.

  The control unit 300 controls the carrier block 13 and the processing block 14 so as to perform CMP processing on the hard mask formed by the film forming apparatus 2.

  FIG. 4 is a block diagram illustrating a functional configuration of the control units 200 and 300. As shown in FIG. 4, the control unit 200 includes functional units (hereinafter referred to as “functional blocks”) as an access control unit 211, a film formation control unit 212, a pixel value acquisition unit 213, and a pixel. A value acquisition unit 214, a pixel value storage unit 215, a change amount calculation unit 216, a correlation data storage unit 217, and a hot plate temperature adjustment unit 218 are included.

  The entry / exit control unit 211 controls the delivery arm A1 so that the wafer W is taken out from the carrier C1 and transferred to the processing block 12, and the wafer W is received from the processing block 12 and returned into the carrier C1.

  The film formation control unit 212 controls the processing block 12 to form a hard mask on the surface of the wafer W. For example, the film formation control unit 212 controls the transfer arm A2 to transfer the wafer W to the liquid processing unit U1 and the heat treatment unit U2, and controls the liquid processing unit U1 to perform the above-described coating process. The heat treatment unit U2 is controlled so as to perform the heat treatment on the wafer W.

  The pixel value acquisition unit 213 acquires the first information for a plurality of parts of the wafer W after the heat treatment. The pixel value acquisition unit 213 acquires a pixel value in a captured image of the surface of the wafer W (that is, the surface of the hard mask) as an example of the first information. The pixel value is a numerical value indicating the state of each pixel constituting the image. For example, the pixel value is a numerical value indicating a light and shade level of the pixel color (for example, a gray level in a black and white image). In the image captured by the camera 35, the pixel value correlates with the height of the imaging target portion corresponding to the pixel. That is, since the pixel value correlates with the height of the hard mask surface in the imaging target portion corresponding to the pixel, it also correlates with the thickness of the hard mask in the imaging target portion.

  For example, the pixel value acquisition unit 213 controls the transfer arm A2 so as to transfer the wafer W to the inspection unit U3, and controls the inspection unit U3 so as to acquire the pixel value of each part on the surface of the wafer W.

  The pixel value acquisition unit 214 acquires the second information for a plurality of parts of the wafer W after the CMP process. The pixel value acquisition unit 214 acquires a pixel value in a captured image of the surface of the wafer W (that is, the surface of the hard mask) as an example of the second information. For example, the pixel value acquisition unit 214 acquires the pixel value via the control unit 300.

  The pixel value storage unit 215 stores the pixel values acquired by the pixel value acquisition unit 213 and the pixel value acquisition unit 214.

  The change amount calculation unit 216 derives information regarding the change amount of the thickness of the hard mask by the CMP process for a plurality of portions of the wafer W. The change amount calculation unit 216 derives information related to the change amount of the pixel value before and after the CMP process as an example of the information related to the change amount.

  The correlation data storage unit 217 stores data (hereinafter referred to as “consultation data”) indicating the relationship between the temperature set value and the pixel value change amount for each of the heating regions 21, 22, 23, 24, and 25. For example, the correlation data storage unit 217 stores a table illustrated in FIG.

  FIG. 5 includes a list of preset temperature values and a pixel value change amount at each preset temperature. The pixel value change amount includes data for each of the heating regions 21, 22, 23, 24, and 25. CH1 to CH5 in the figure correspond to the heating regions 21 to 25, respectively. The correlation data illustrated in FIG. 5 is acquired in advance by an actual machine test or simulation. Instead of storing the table, the correlation data may store a regression equation obtained from the configuration data of the table as a function.

  Returning to FIG. 4, the hot plate temperature adjustment unit 218 adjusts the temperature setting for each of the heating regions 21, 22, 23, 24, and 25 so as to correct the change amount of the pixel value in each of the plurality of portions.

  The control unit 300 includes an access control unit 311, a polishing control unit 312, a pixel value acquisition unit 313, and a pixel value storage unit 314 as functional blocks.

  The entry / exit control unit 311 controls the delivery arm A11 so that the wafer W is taken out from the carrier C1 and transferred to the processing block 14, and the wafer W is received from the processing block 14 and returned into the carrier C1.

  The polishing control unit 312 controls the processing block 14 to perform the CMP process on the surface of the wafer W. For example, the polishing control unit 312 controls the transfer arm A12 to transfer the wafer W to the CMP unit U11 and the cleaning unit U12, controls the CMP unit U11 to perform the CMP process, and cleans the wafer W after the CMP process. Then, the cleaning unit U12 is controlled.

  The pixel value acquisition unit 313 acquires the second information for a plurality of parts of the wafer W after the CMP process. The pixel value acquisition unit 313 acquires a pixel value in a captured image of the surface of the wafer W (that is, the surface of the hard mask) as an example of the second information. For example, the pixel value acquisition unit 313 controls the transfer arm A12 to transfer the wafer W to the inspection unit U13, and controls the inspection unit U13 to acquire the pixel value of each part on the surface of the wafer W.

  The pixel value storage unit 314 stores the pixel value acquired by the pixel value acquisition unit 313.

  FIG. 6 is a block diagram illustrating a hardware configuration of the control unit 100. As illustrated in FIG. 6, the control unit 200 includes a circuit 220, and the control unit 300 includes a circuit 320. That is, the control unit 100 includes a circuit 120 including a circuit 220 and a circuit 320.

  The circuit 220 includes one or more processors 221, a memory 222, a storage 223, an input / output port 224, and a communication port 225. The storage 223 is a storage medium, and records a program for configuring each functional block of the control unit 200. The storage 223 may be anything that can be read by a computer. Specific examples include a hard disk, a nonvolatile semiconductor memory, a magnetic disk, and an optical disk. The memory 222 temporarily stores the program loaded from the storage 223, the calculation result of the processor 221, and the like. The processor 221 configures each functional block by executing a program in cooperation with the memory 222.

  The input / output port 224 inputs and outputs electrical signals between the delivery arm A1, the transfer arm A2, the liquid processing unit U1, the heat treatment unit U2, and the inspection unit U3 in response to a command from the processor 221. The communication port 225 performs information communication with a communication port 325 (described later) of the control unit 300 in response to a command from the processor 221.

  The circuit 320 includes one or a plurality of processors 321, a memory 322, a storage 323, an input / output port 324, and a communication port 325. The storage 323 is a storage medium, and records a program for configuring each functional block of the control unit 300. The storage 323 may be anything as long as it can be read by a computer. Specific examples include a hard disk, a nonvolatile semiconductor memory, a magnetic disk, and an optical disk. The memory 322 temporarily stores the program loaded from the storage 323, the calculation result of the processor 321, and the like. The processor 321 configures each functional block by executing a program in cooperation with the memory 322.

  The input / output port 324 inputs and outputs electrical signals between the delivery arm A11, the transfer arm A12, the CMP unit U11, the cleaning unit U12, and the inspection unit U13 in response to a command from the processor 321. The communication port 325 performs information communication with the communication port 225 of the control unit 200 in response to a command from the processor 321.

  Note that the hardware configuration of the control unit 100 is not necessarily limited to the configuration of each functional block by a program. For example, at least a part of the functional blocks of the control units 200 and 300 may be configured by a dedicated logic circuit or an ASIC (Application Specific Integrated Circuit) in which the logic circuits are integrated.

[Substrate processing method]
Subsequently, a substrate processing procedure executed by the substrate processing system 1 will be described as an example of the substrate processing method. In this substrate processing procedure, a hot mask 20 is used to form a hard mask on the surface of the wafer W, a CMP process is performed on the hard mask, and the thickness of the hard mask obtained by the CMP process is applied to a plurality of portions of the wafer W. Deriving information on the amount of change in height, and adjusting the temperature setting for each of the heating regions 21, 22, 23, 24, and 25 so as to correct the amount of change in each of the plurality of portions. .

  FIG. 7 is a flowchart showing a control procedure executed by the control unit 100 in the substrate processing procedure. As shown in FIG. 7, the control unit 100 first executes step S01. In step S01, the control unit 200 controls the carrier block 11 and the processing block 12 so as to execute a film forming process (a process for forming a hard mask) on the surfaces of all the wafers W accommodated in the carrier C1.

  Next, the control part 100 performs step S02. In step S02, the control unit 300 controls the carrier block 13 and the processing block 14 so as to perform the hard mask CMP process on all the wafers W accommodated in the carrier C1.

  Next, the control part 100 performs step S03. In step S03, the control unit 200 derives information regarding the amount of change in the thickness of the hard mask by CMP processing for a plurality of portions of the wafer W, and corrects the amount of change in each of the plurality of portions. , Adjusting the temperature setting for each of the heating regions 21, 22, 23, 24, 25 (hereinafter referred to as “temperature adjustment”).

  Next, the control unit 100 confirms whether or not the processing for all the carriers C1 has been completed (step S04). If it is determined in step S04 that an unprocessed carrier C1 remains, the control unit 100 returns the process to step S01. Thereafter, the processing for forming a hard mask on the surface of the wafer W, the CMP processing for the hard mask, and the processing for adjusting the temperature setting of the hot plate 20 are repeated for each carrier C1 until the processing for all the carriers C1 is completed. It is.

  In step S04, when it is determined that the processing for all the carriers C1 is completed, the control unit 100 completes the control of the carrier blocks 11 and 13 and the processing blocks 12 and 14. Thus, the substrate processing procedure is completed.

(Deposition process procedure)
Subsequently, the contents of step S01 will be described in more detail. FIG. 8 is a flowchart showing a control procedure executed by the control unit 200 in step S01. As shown in FIG. 8, the control unit 200 first executes step S11. In step S <b> 11, the access control unit 211 controls the delivery arm A <b> 1 so that the wafer W in the carrier C <b> 1 is taken out and transferred to the processing block 12.

  Next, the control part 200 performs step S12. In step S12, the film formation control unit 212 executes control for performing the coating process on the wafer W transferred in step S11. Specifically, the film formation control unit 212 controls the transfer arm A2 so that the wafer W transferred by the delivery arm A1 is transferred to the liquid processing unit U1. Thereafter, the film formation control unit 212 controls the liquid processing unit U1 so as to perform a coating process (a process of coating a processing liquid) on the surface of the wafer W.

  Next, the control part 200 performs step S13. In step S <b> 13, the film formation control unit 212 executes control for performing heat treatment on the wafer W after the coating process. Specifically, the film formation control unit 212 controls the transfer arm A2 so that the wafer W after the coating process is transferred from the liquid processing unit U1 to the heat treatment unit U2. Thereafter, the film formation control unit 212 controls the heat treatment unit U2 to perform heat treatment on the wafer W after the coating process. This heat treatment includes heat treatment by placing the wafer W on the hot plate 20. When placing the wafer W on the hot plate 20, the heat treatment unit U <b> 2 makes the rotation center of the wafer W in the coating process coincide with the center of the hot plate 20.

  Next, the control part 200 performs step S14. In step S <b> 14, the pixel value acquisition unit 213 acquires first information related to the thickness of the hard mask before the CMP process for a plurality of portions of the wafer W after the heat treatment. The pixel value acquisition unit 213 acquires a pixel value in a captured image of the surface of the wafer W (that is, the surface of the hard mask) as an example of the first information. Specifically, the pixel value acquisition unit 213 controls the transfer arm A2 to transfer the heat-treated wafer W from the heat treatment unit U2 to the inspection unit U3. Thereafter, the pixel value acquisition unit 213 controls the inspection unit U3 so that the surface of the wafer W is imaged by the inspection device 30, acquires image data of the surface of the wafer W from the inspection unit U3, and stores it in the pixel value storage unit 215. Write. The image data includes pixel values of each part on the surface of the wafer W.

  Next, the control part 200 performs step S15. In step S15, the entrance / exit control unit 211 controls the transfer arm A2 and the delivery arm A1 so that the wafer W after imaging in the inspection apparatus 30 is returned to the carrier C1.

  Next, the control unit 200 confirms whether or not the processing for all the wafers W in the carrier C1 has been completed (step S16). If it is determined in step S16 that an unprocessed wafer W remains, the control unit 200 returns the process to step S11. Thereafter, the process of forming a hard mask on the surface of the wafer W and the process of acquiring the pixel values of each part on the surface of the wafer W are repeated until the processes for all the wafers W are completed.

  If it is determined in step S16 that the processing for all the wafers W has been completed, the control unit 200 completes the control of the carrier block 11 and the processing block 12. Thus, the film forming process procedure is completed.

(Polishing procedure)
Subsequently, the contents of step S02 will be described in more detail. FIG. 9 is a flowchart showing a control procedure executed by the control unit 300 in step S02. As shown in FIG. 9, the control unit 300 first executes step S21. In step S <b> 21, the access control unit 311 controls the delivery arm A <b> 11 so that the wafer W in the carrier C <b> 1 is taken out and transferred to the processing block 14.

  Next, the control part 300 performs step S22. In step S22, the polishing control unit 312 executes control for performing CMP processing on the surface of the wafer W (that is, the surface of the hard mask) transferred in step S21. Specifically, the polishing controller 312 controls the transfer arm A12 so as to transfer the wafer W transferred by the transfer arm A11 to the CMP unit U11. Thereafter, the polishing control unit 312 controls the CMP unit U11 to perform the CMP process on the surface of the wafer W.

  Next, the control part 300 performs step S23. In step S23, the polishing control unit 312 executes control for cleaning the wafer W after the CMP process. Specifically, the polishing controller 312 controls the transfer arm A12 to transfer the CMP-processed wafer W from the CMP unit U11 to the cleaning unit U12. Thereafter, the polishing control unit 312 controls the cleaning unit U12 to perform the cleaning process on the wafer W after the CMP process.

  Next, the control part 300 performs step S24. In step S <b> 24, the pixel value acquisition unit 313 acquires second information related to the thickness of the hard mask after the CMP process for a plurality of portions of the wafer W. The pixel value acquisition unit 313 acquires a pixel value in a captured image of the surface of the wafer W (that is, the surface of the hard mask) as an example of the second information. Specifically, the pixel value acquisition unit 313 controls the transfer arm A12 so that the wafer W after the cleaning process is transferred from the cleaning unit U12 to the inspection unit U13. Thereafter, the pixel value acquisition unit 313 controls the inspection unit U13 so that the surface of the wafer W is imaged by the inspection device 30, acquires the image data of the surface of the wafer W from the inspection unit U13, and stores it in the pixel value storage unit 314. Write. The image data includes pixel values of each part on the surface of the wafer W.

  Next, the control part 300 performs step S25. In step S25, the entrance / exit control unit 311 controls the transfer arm A12 and the transfer arm A11 so that the wafer W after imaging in the inspection apparatus 30 is returned to the carrier C1.

  Next, the control unit 300 confirms whether or not the processing for all the wafers W in the carrier C1 has been completed (step S26). If it is determined in step S26 that an unprocessed wafer W remains, the control unit 300 returns the process to step S21. Thereafter, until the processing on all the wafers W is completed, the CMP process on the surface of the wafer W, the cleaning process on the wafer W after the CMP process, and the process of acquiring the pixel values of each part on the surface of the wafer W are repeated. .

  If it is determined in step S <b> 26 that the processing for all the wafers W has been completed, the control unit 300 completes the control of the carrier block 13 and the processing block 14. This completes the polishing procedure.

(Temperature adjustment procedure)
Subsequently, the contents of step S03 will be described in more detail. FIG. 10 is a flowchart showing a calculation procedure executed by the control unit 200 in step S03. As shown in FIG. 10, the control unit 200 first executes step S31. In step S <b> 31, the pixel value acquisition unit 214 transfers the image data stored in the pixel value storage unit 314 to the pixel value storage unit 215. In other words, the pixel value acquisition unit 214 acquires second information related to the thickness of the hard mask after the CMP process for a plurality of portions of the wafer W. The pixel value acquisition unit 214 acquires a pixel value in a captured image of the surface of the wafer W (that is, the surface of the hard mask) as an example of the second information. Hereinafter, the pixel value acquired by the pixel value acquisition unit 213 before the CMP process is referred to as a “first pixel value”, and the pixel value acquired by the pixel value acquisition unit 214 after the CMP process is referred to as a “second pixel value”.

  Next, the control part 200 performs step S32. In step S <b> 32, the change amount calculation unit 216 derives information on the change amount of the hard mask thickness due to the CMP process for a plurality of portions of the wafer W. The plurality of parts include a plurality of parts respectively positioned on the plurality of heating regions 21, 22, 23, 24, and 25 in the heat treatment in step S13. The change amount calculation unit 216 derives information related to the change amount of the pixel value before and after the CMP process as an example of the information related to the change amount. For example, the change amount calculation unit 216 calculates the difference between the first pixel value and the second pixel value stored in the pixel value storage unit 215 as information regarding the change amount of the pixel value. The change amount calculation unit 216 may calculate the ratio of the second pixel value to the first pixel value or the ratio of the first pixel value to the second pixel value as information regarding the change amount of the pixel value.

  Next, the control part 200 performs step S33. In step S33, the hot plate temperature adjustment unit 218 derives a temperature correction value for each of the heating regions 21, 22, 23, 24, and 25 so as to correct the amount of change in the pixel value in each of the plurality of portions. The hot plate temperature adjustment unit 218 uses the correlation data stored in the correlation data storage unit 217 to correct the amount of change in the pixel value in the portion located on the own region for each of the heating regions 21, 22, 23, 24, and 25. Thus, the temperature correction value is derived.

  The temperature correction value is an amount for correcting the current temperature set value. For example, the temperature correction value may be a numerical value to be added to the current temperature setting value (hereinafter referred to as “addition type correction value”), or a numerical value to be multiplied by the current temperature setting value (hereinafter referred to as “multiplication type”). It may also be referred to as “correction value”.

  The hot plate temperature adjustment unit 218 derives a temperature correction value for each of the heating regions 21, 22, 23, 24, and 25 so that the change amount of the pixel value in each of the plurality of parts approaches a predetermined target change amount. Also good. The target change amount is set in advance for each of a plurality of parts by an actual machine test or simulation.

  Instead of bringing the change amount of the pixel value close to the target change amount, the hot plate temperature adjustment unit 218 reduces the difference in the change amount of the pixel value between the plurality of regions, so that the heating regions 21, 22, 23, A temperature correction value for each of 24 and 25 may be derived. In this case, a plurality of portions having the same height before formation of the hard mask (the height when the back surface of the wafer W is horizontally disposed) may be the execution targets of steps S32 and S33.

  Next, the control part 200 performs step S34. In step S34, the hot plate temperature adjustment unit 218 adjusts the temperature setting for each of the heating regions 21, 22, 23, 24, and 25 using the temperature correction value derived in step S33. When the temperature correction value is the addition type correction value, the hot plate temperature adjustment unit 218 adds the temperature correction value to the current temperature setting value. When the temperature correction value is the multiplication type correction value, the hot plate temperature adjustment unit 218 multiplies the current temperature setting value by the temperature correction value. Thus, the temperature adjustment procedure of the hot plate 20 is completed.

[Modification]
FIG. 11 is a schematic diagram showing a modification of the substrate processing system 1. As illustrated in FIG. 11, the control unit 100 may further include a server 101 connected to the control unit 200 and the control unit 300 in addition to the control unit 200 and the control unit 300. In this case, at least a part of the functional blocks related to adjustment of the temperature setting of the hot plate may be provided in the server 101. For example, the pixel value storage unit 215, the change amount calculation unit 216, and the correlation data storage unit 217 described above may be provided in the server 101.

  FIG. 12 is a schematic diagram showing another modification of the substrate processing system. As shown in FIG. 12, the substrate processing system 1 may include a film forming apparatus 2 and a coating and developing apparatus 4. The coating and developing apparatus 4 further forms a resist film on the surface (on the hard mask) of the wafer W after the CMP process in the polishing apparatus 3, sends the wafer W to the exposure apparatus 5, and after the exposure process in the exposure apparatus 5 A development process is performed on the wafer W to form a resist pattern. The coating and developing apparatus 4 includes a controller 400, and the control unit 100 includes a control unit 200 of the film forming apparatus 2 and a controller 400 of the coating and developing apparatus 4.

  In such a configuration, the inspection unit U13 may be provided in the coating and developing apparatus 4. In this case, the controller 400 acquires the pixel values of the respective portions on the surface of the wafer W before forming another film (for example, a resist film) on the surface (hard mask) of the wafer W after the CMP process. It may be configured. The control unit 200 may be configured to acquire the pixel value of each part on the surface of the wafer W after the CMP process from the controller 400. In other words, the pixel value acquisition unit 313 and the pixel value storage unit 314 may be provided in the controller 400.

[Effect of this embodiment]
The film forming apparatus 2 includes a hot plate 20 including a plurality of heating regions 21, 22, 23, 24, and 25, and forms a hard mask to be subjected to CMP processing on the surface of the wafer W using the hot plate 20. First information on the thickness of the hard mask before the CMP process and second information on the thickness of the hard mask after the CMP process are obtained for the processing block 12 and a plurality of parts of the wafer W, and the first information and Based on the second information, information on the amount of change in the thickness of the hard mask by the CMP process is derived, and the heating regions 21, 22, 23, 24, and 25 are corrected so as to correct the amount of change in each of the plurality of portions. And a control unit 200 configured to perform adjustment of the temperature setting for each.

  Even if CMP polishing is performed on the hard mask formed on the surface of the wafer W, the surface of the film may not be flattened to a desired level. As a result of investigating and studying the cause, the inventors of the present application have a difference in hard mask polishing resistance (hereinafter referred to as “film quality”) for each portion of the wafer W, and the CMP process is caused by the difference. It was found that there is a possibility that the degree of progress of the variation is different. Based on this knowledge, the film forming apparatus 2 derives information on the variation in the degree of progress of the CMP process, and adjusts the film forming conditions (conditions for forming the hard mask) so as to reduce the variation. It is configured as follows. That is, the control unit 200 derives information on the amount of change in the thickness of the hard mask due to the CMP process based on the first information and the second information, and corrects the amount of change in each of the plurality of parts. The temperature setting for each of the heating regions 21, 22, 23, 24, and 25 is configured to be adjusted. Thereby, variation in the degree of progress of the CMP process due to the film quality can be reduced. Therefore, it is effective for further planarization of the surface of the hard mask formed on the wafer W.

  The plurality of heating regions 21, 22, 23, 24, and 25 may be arranged concentrically. The difference in film quality tends to vary depending on the distance from the center of the wafer W (rotation center in spin coating). In contrast, according to the configuration in which the plurality of heating regions 21, 22, 23, 24, and 25 are arranged concentrically, the temperature distribution of the hot plate 20 can be adjusted according to the above tendency. Therefore, it is further effective for planarizing the surface of the hard mask formed on the wafer W.

  The control unit 100 acquires the pixel value in the captured image of the surface of the wafer W as the first information and the second information, and the pixel value before and after the CMP process as information on the amount of change in the thickness of the hard mask by the CMP process. The temperature setting for each of the heating regions 21, 22, 23, 24, and 25 may be adjusted so as to derive the amount of change and correct the amount of change in the pixel value in each of the plurality of parts. In this case, it is easy to simplify the apparatus configuration for acquiring the first information and the second information by using the pixel value in the captured image of the surface of the substrate as the substitute characteristic of the film thickness.

  Although the embodiments have been described above, the present disclosure is not necessarily limited to the above-described embodiments, and various modifications can be made without departing from the scope of the disclosure. The substrate to be processed is not limited to a semiconductor wafer, and may be, for example, a glass substrate, a mask substrate, an FPD (Flat Panel Display), or the like.

  DESCRIPTION OF SYMBOLS 1 ... Substrate processing system, W ... Wafer (substrate), 2 ... Film-forming apparatus (substrate processing apparatus), 12 ... Processing block (film-forming processing part), 100, 200 ... Control part, 20 ... Heat plate, 21, 22 , 23, 24, 25 ... heating region, 14 ... processing block (polishing processing part).

Claims (6)

A film formation processing unit having a heat plate including a plurality of heating regions, and forming a film to be subjected to a chemical mechanical polishing process on the surface of the substrate using the heat plate;
For a plurality of portions of the substrate, first information on the thickness of the film before the chemical mechanical polishing treatment and second information on the thickness of the film after the chemical mechanical polishing treatment are obtained, Deriving information on the amount of change in the thickness of the film by the chemical mechanical polishing process based on the information and the second information, and correcting the amount of change in each of the plurality of regions. A substrate processing apparatus comprising: a control unit configured to perform adjustment of a temperature setting for each.   The control unit adjusts the temperature setting so as to correct the amount of change in each of the plurality of regions, so that the difference in the amount of change between the plurality of regions is reduced for each heating region. The substrate processing apparatus according to claim 1, wherein the temperature setting is adjusted.   The substrate processing apparatus according to claim 1, wherein the plurality of heating regions are arranged concentrically.   The control unit acquires a pixel value in a captured image of the surface of the substrate as the first information and the second information, and uses the chemical as information on a change amount of the film thickness by the chemical mechanical polishing process. The temperature setting for each of the heating regions is adjusted so as to derive a change amount of the pixel value before and after a mechanical polishing process and correct the change amount of the pixel value in each of the plurality of portions. The substrate processing apparatus as described in any one of -3. A film formation processing unit having a heat plate including a plurality of heating regions, and forming a film on the surface of the substrate using the heat plate;
A polishing processing unit for performing chemical mechanical polishing on the film formed by the film forming processing unit;
For a plurality of portions of the substrate, first information on the thickness of the film before the chemical mechanical polishing treatment and second information on the thickness of the film after the chemical mechanical polishing treatment are obtained, Deriving information on the amount of change in the thickness of the film by the chemical mechanical polishing process based on the information and the second information, and correcting the amount of change in each of the plurality of regions. A substrate processing system comprising: a controller configured to perform a temperature setting for each; Using a hot plate including a plurality of heating regions, forming a film on the surface of the substrate using the hot plate;
Performing chemical mechanical polishing on the film;
For a plurality of portions of the substrate, first information on the thickness of the film before the chemical mechanical polishing treatment and second information on the thickness of the film after the chemical mechanical polishing treatment are obtained, Deriving information on the change in thickness of the film by the chemical mechanical polishing process based on the information and the second information;
Adjusting a temperature setting for each heating region so as to correct the amount of change in each of the plurality of portions.

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