JP2018182944A - Power converter - Google Patents

Description

  The present technology relates to a power converter.

  A multi-level inverter represented by a three-level inverter as a direct current converter (DC (Direct Current) / AC (Alternate Current) converter) can miniaturize the system and increase the efficiency compared to the previous two-level inverter. It attracts attention as a power converter to realize.

  As a prior art of a three-level inverter, for example, a voltage drop characteristic of a free wheeling diode connected in reverse parallel to at least two switching elements connected in series between a positive electrode terminal and a negative electrode terminal is A technique has been proposed in which the power loss is reduced by making the voltage drop characteristic of a free-wheeling diode connected in anti-parallel to the switching element connected between the AC terminals in reverse (Patent Document 1).

JP, 2013-116020, A

  However, when driving an inductive load such as a motor by switching operation of a switching element included in a three-level inverter, if load current flows back to the body diode in the switching element, the body diode is degraded and power loss increases Have the problem of

  The present invention has been made in view of these points, and it is an object of the present invention to provide a power conversion device in which deterioration of a body diode is suppressed and power loss is reduced.

  In order to solve the above-mentioned subject, a power converter is provided. The power converter includes an orthogonal first switching element including a first transistor and a first body diode, and a second switching element connected in series to the first switching element. A conversion unit and a control circuit that turns on the first switching element for a predetermined period during a period from the turn-off operation of the second switching element to the turn-on operation.

  Moreover, another power converter is provided in order to solve the said subject. This power conversion device includes a first switching element on the positive electrode side including a first body diode, a second switching element on the negative electrode side connected in series to the first switching element, and a parallel connection to the first switching element. And a control circuit which turns on the switch circuit for a predetermined period of time during the turn-on operation of the second switching element after the turn-off operation of the second switching element.

  It is possible to suppress the deterioration of the body diode and to reduce the power loss.

It is a figure which shows the structural example of the power converter device of this invention. It is a figure which shows the structural example of a 3 level inverter. It is a figure which shows an example of the switching pattern of a 3 level inverter. It is a figure which shows the output waveform of 3 level inverter. It is a figure which shows the path | route through which load current flows. It is a figure which shows the path | route through which load current flows, when the both-ends voltage of the switching element by the side of a negative electrode exceeds a threshold level. It is a figure for demonstrating the state at the time of conduction | electrical_connection of a body diode. It is a figure which shows the structural example of a power converter device. It is a figure for demonstrating the operation | movement of a power converter device. It is a figure which shows the structural example of the power converter device of a modification. It is a figure for demonstrating the operation | movement of the power converter device of a modification.

Embodiments will be described below with reference to the drawings.
FIG. 1 is a view showing a configuration example of a power conversion device of the present invention. The power converter 1 includes an orthogonal transformer 1 a and a control circuit 1 b. The orthogonal converter 1a includes switching elements T1 to T4, diodes D1 and D2 (first and second diodes), a positive power supply V1 and a negative power supply V2 as DC power supplies.

  The switching element T1 (first switching element) on the positive side includes an N-channel NMOS transistor M1 (first transistor) as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), and further a body diode Dp1 (first 1) body diode). The switching element T2 (second switching element) on the negative electrode side is connected in series to the switching element T1.

  Describing the connection in the orthogonal transformer 1a, the positive terminal of the positive power supply V1 is connected to the drain of the NMOS transistor M1 and the cathode of the body diode Dp1, and the negative terminal of the negative power supply V2 is a switching element Connect to one end of T2.

  The negative terminal of the positive power supply V1 is connected to the positive terminal of the negative power V2, one end of the switching element T3, and the anode of the diode D1. The other end of the switching element T3 is connected to the cathode of the diode D1, the cathode of the diode D2, and one end of the switching element T4.

  The other end of the switching element T4 is connected to the anode of the diode D2, the source of the NMOS transistor M1, the anode of the body diode Dp1, the other end of the switching element T2, and the midpoint U. Further, the load 3 is connected to the middle point U via a filter (not shown).

  The control circuit 1b performs switching drive control of the switching elements T1 to T4. In this case, the control circuit 1b turns on the switching element T2, which is in the off state during the switching operation, during a switching operation of the switching element T2 for a predetermined period. Do.

  By performing such switching control, the control circuit 1b causes the load current (first load current) traveling from the load 3 to the switching element T1 to flow to the NMOS transistor M1 side in the switching element T1, and the switching element T1. The load current is made non-conductive to the internal body diode Dp1 (restriction of the load current flow toward the body diode Dp1).

  Thereby, it is possible to suppress the return current of the load current to the body diode Dp1 in the switching element T1, so it is possible to suppress the deterioration of the body diode Dp1, and it is possible to achieve the reduction of the power loss.

  Next, before describing the details of the present invention, a three-level inverter which is an application example of the present invention will be described with reference to FIGS. First, the configuration of the three-level inverter will be described. FIG. 2 is a diagram showing a configuration example of a three-level inverter. The three-level inverter 100 includes switching elements T1 to T4, diodes D1 and D2, a positive power supply V1 and a negative power supply V2.

  For the switching elements T1 and T2, for example, NMOS transistors M1 and M2 are used. In this case, for example, a MOSFET made of SiC (silicon carbide) is used. The SiC-MOSFET has smaller switching loss and better electrical characteristics even in a high temperature region than a MOSFET made of Si (silicon).

  Further, parasitic diodes are connected to the NMOS transistors M1 and M2, and the parasitic diode of the NMOS transistor M1 is a body diode Dp1, and the parasitic diode of the NMOS transistor M2 is a body diode Dp2.

Furthermore, for example, IGBT (Insulated Gate Bipolar Transistor) made of Si is used for the switching elements T3 and T4.
On the other hand, since there is a wiring inductor (floating inductor) in the wiring of the three-level inverter 100, the wiring inductor is clearly shown in FIG.

  Specifically, in the positive electrode side wiring between the positive electrode side terminal of the positive electrode side power supply V1 and the positive electrode point P, there is a wiring inductor Lp. A wiring inductor Ln is provided on the negative electrode side wiring between the negative electrode side terminal of the negative electrode side power supply V2 and the negative electrode point N.

  Furthermore, there is a wiring inductor Lm at the middle point C between the positive power supply V1 and the negative power supply V2 and at the middle wiring between the emitter of the switching element T3 and the anode of the diode D1.

  Regarding the connection of the components of the three-level inverter 100, the positive terminal of the positive power supply V1 is connected to the drain of the NMOS transistor M1 and the cathode of the body diode Dp1 through the wiring inductor Lp.

The negative terminal of the negative power supply V2 is connected to the source of the NMOS transistor M2 and the anode of the body diode Dp2 through the wiring inductor Ln.
The negative terminal of the positive power supply V1 is connected to the positive terminal of the negative power V2, and is further connected to the emitter of the switching element T3 and the anode of the diode D1 through the wiring inductor Lm.

The collector of the switching element T3 is connected to the cathode of the diode D1, the cathode of the diode D2, and the collector of the switching element T4.
The emitter of the switching element T4 is connected to the anode of the diode D2, the source of the NMOS transistor M1, the anode of the body diode Dp1, the drain of the NMOS transistor M2, and the cathode of the body diode Dp2.

  A filter 101 (for example, an LC filter) is connected to an intermediate point (AC output point) U, and a load is connected to an output stage of the filter 101. A control circuit (not shown) is connected to the gates of the switching elements T1 to T4. In addition, you may apply the structure of RB (Reverse Blocking) -IGBT to the location of switching element T3, T4 and diode D1, D2.

Next, the switching pattern of the three-level inverter 100 will be described. FIG. 3 is a diagram showing an example of a switching pattern of the three-level inverter.
[Period t (+)] In period t (+) in which the reference sine wave (output voltage command of the inverter) S0 is in a positive period, the amplitude of the reference sine wave S0 is a positive potential side triangular wave signal of the carrier signal S1. If it is larger than the amplitude, the gate drive signal g1 of the switching element T1 is at the high potential level, and the switching element T1 is turned on.

When the amplitude of the reference sine wave S0 is smaller than the amplitude of the carrier signal S1, the gate drive signal g1 is at a low potential level, and the switching element T1 is turned off.
On the other hand, the gate drive signal g3 of the switching element T3 is a signal obtained by inverting the level of the gate drive signal g1. Therefore, when the switching element T1 is on, the switching element T3 is off, and when the switching element T1 is off, the switching element T3 is on.

  Furthermore, during the switching operation of the switching elements T1 and T3 (period t (+)), the gate drive signal g2 of the switching element T2 maintains the low potential level, and the switching element T2 is turned off.

  Furthermore, during the switching operation of the switching elements T1 and T3 (period t (+)), the gate drive signal g4 of the switching element T4 maintains the high potential level, and the switching element T4 is turned on.

  [Period t (−)] In period t (−) in which reference sine wave S0 is in a negative period, switching is performed when the amplitude of reference sine wave S0 is smaller than the amplitude of carrier signal S2 that is a negative potential side triangular wave The gate drive signal g2 of the element T2 is at the high potential level, and the switching element T2 is turned on.

When the amplitude of the reference sine wave S0 is larger than the amplitude of the carrier signal S2, the gate drive signal g2 is at a low potential level, and the switching element T2 is turned off.
On the other hand, the gate drive signal g4 of the switching element T4 is a signal obtained by inverting the level of the gate drive signal g2. Therefore, when the switching element T2 is on, the switching element T4 is off, and when the switching element T2 is off, the switching element T4 is on.

  Furthermore, during the switching operation of the switching elements T2 and T4 (period t (−)), the gate drive signal g1 of the switching element T1 maintains the low potential level, and the switching element T1 is turned off.

  Furthermore, during the switching operation of the switching elements T2 and T4 (period t (−)), the gate drive signal g3 of the switching element T3 maintains the high potential level, and the switching element T3 is turned on.

  As described above, while the reference sine wave S0 is positive, the switching elements T1 and T3 alternately switch. At this time, the switching element T2 is maintained in the off state, and the switching element T4 is maintained in the on state.

  Conversely, while the reference sine wave S0 is negative, the switching elements T2 and T4 switch alternately. At this time, the switching element T1 is maintained in the off state, and the switching element T3 is maintained in the on state.

  Power supply to the load is implemented by the switching elements T1 to T4 performing such switching operation. The gate drive signals g1 to g4 described above are generated in a control circuit that performs drive control of the switching elements T1 to T4.

  FIG. 4 is a diagram showing an output waveform of the three-level inverter. Assuming that the total power supply voltage of the three-level inverter 100 is Ed, the output of the middle point U of the three-level inverter 100 is a pulse width modulation (PWM) pulse waveform of ± Ed / 2 and ± Ed around zero. .

  As described above, since the output waveform becomes closer to a sine wave, the three-level inverter 100 can miniaturize the filter 101 for converting the output waveform into a sine wave. In addition, since the voltage fluctuation range per switching operation is half that of the two-level inverter, the switching loss generated in the switching element is approximately halved, and the noise generated from the device is also reduced. .

  Next, problems to be solved by the present invention will be described with reference to FIGS. FIG. 5 is a diagram showing a path through which a load current flows. During switching operation of the switching element T2 on the negative electrode side (period t (-)), when the switching element T2 is turned on and then turned off, a back electromotive force is generated from an inductive load such as a motor. Load current flows inside.

  When the switching element T2 is off during the switching operation of the switching element T2, as shown in FIG. 3, the switching element T1 is off, the switching element T3 is on, and the switching element T4 is on.

  When the switching element T2 is turned off, the load current flows in the paths r1 and r2. The route r1 is a route flowing from the midpoint U to the negative pole N, and the route r2 is a route flowing from the midpoint U to the midpoint C.

  The load current flowing through the path r1 decreases with time (decreases at -di / dt). Also, looking at the voltage polarity of the wiring inductor Ln, the wiring inductor Ln works to keep the original current flowing, so the power supply side of the wiring inductor Ln becomes positive and the switching element T2 side of the wiring inductor Ln becomes negative. Become.

  On the other hand, the load current flowing through the path r2 increases with time (increases with di / dt). Further, when looking at the voltage polarity of the wiring inductor Lm, the switching element T3 side of the wiring inductor Lm becomes positive, and the power supply side of the wiring inductor Lm becomes negative.

FIG. 6 is a diagram showing a path through which a load current flows when the voltage across the switching element on the negative electrode side exceeds the threshold level.
Here, both the power supply voltages of the positive power supply V1 and the negative power supply V2 are Edc, the load current is di / dt, and the inductances of the wiring inductors Lm and Ln are represented by the same symbols Lm and Ln, respectively. In this case, the voltage VT2 across the switching element T2 is calculated by the following equation (1).

VT2 = Edc + (Lm + Ln) × di / dt (1)
Further, a voltage (2 × Edc) twice as high as the power supply voltage Edc is taken as a threshold level. After the switching element T2 on the negative electrode side is turned off, the voltage VT2 across the switching element T2 rises, and when the voltage VT2 across the switching element T2 exceeds the threshold level, the body diode Dp1 of the switching element T1 is forward biased and becomes conductive. Therefore, as shown in FIG. 6, the load current also flows in the path r3 from the middle point U to the positive point P.

  FIG. 7 is a diagram for explaining a state of conduction of the body diode. When the inductances of the wiring inductors Lm and Ln are large and the reduction rate of the load current IT2 flowing through the switching element T2 is large, the voltage VT2 from the above equation (1) increases.

  At this time, in a period ta in which the voltage VT2 across the switching element T2 exceeds twice the power supply voltage Edc (2 × Edc), the body diode Dp1 of the switching element T1 is forward biased and becomes conductive.

  Then, a load current I1 flows in the body diode Dp1. As described above, when the load current I1 returned from the load flows through the body diode Dp1, the failure rate of the body diode Dp1 is increased, and the body diode Dp1 may be deteriorated. Further, since the on voltage of the body diode Dp1 is high, when the load current I1 flows in the body diode Dp1, the power loss increases.

  SUMMARY OF THE INVENTION In view of the above-described points, the present invention provides a power conversion device in which the load current to the body diode is made non-conductive to suppress the deterioration of the body diode and reduce the power loss.

  Next, a power converter of the present invention applicable to a three-level inverter will be described using FIGS. 8 and 9. FIG. FIG. 8 is a view showing a configuration example of a power conversion device. The power conversion device 1-1 includes an orthogonal transformer 10 and a control circuit 20, and the load 3 is connected to the middle point U of the orthogonal transformer 10 via a filter (not shown).

  The orthogonal transformer 10 includes switching elements T1 to T4, diodes D1 and D2, a positive power supply V1 and a negative power supply V2. The switching element T1 includes an NMOS transistor M1 and a body diode Dp1, and the switching element T2 includes an NMOS transistor M2 (second transistor) and a body diode Dp2 (second body diode). The basic circuit configuration of the orthogonal transformer 10 is the same as that of the three-level inverter 100 shown in FIG. 2, and therefore the description of the circuit configuration is omitted.

The control circuit 20 inputs gate drive signals g1 to g4 to the gates of the switching elements T1 to T4, and performs switching control of the switching elements T1 to T4.
Here, in the three-level inverter 100 shown in FIG. 2, the switching element T1 is in the continuous off state during the switching operation of the switching element T2 and in the off period from the turning off of the switching element T2 to the turning on. The

  On the other hand, the power conversion device 1-1 applies a gate drive signal of high potential level to the switching element T 1 for the switching element T 1 which is normally in the continuous off state during this off period and turns on for a predetermined period. Control to More specifically, a gate drive signal of a high potential level is applied to the gate of the NMOS transistor M1 in the switching element T1, and the NMOS transistor M1 is turned on for a predetermined period.

FIG. 9 is a diagram for explaining the operation of the power conversion device.
[Period t0] The control circuit 20 applies a gate drive signal g2 at a high potential level to the gate of the switching element T2. At this time, the switching element T2 is turned on. Further, the control circuit 20 applies a gate drive signal g1 at a low potential level to the gate of the NMOS transistor M1. At this time, the NMOS transistor M1 (switching element T1) is turned off.

  The switching elements T3 and T4 are also switched based on the gate drive signals g3 and g4 output from the control circuit 20. In this case, the switching element T3 is on and the switching element T4 is off.

  On the other hand, in a period t0 in which the switching element T1 is off and the switching element T2 is on, the voltage VT2 (voltage across the switching element T2 between the middle point U and the negative point N) is 0V. At this time, the load current IT2 flowing through the switching element T2 is assumed to have a current value Imax. Furthermore, no load current flows to the switching element T1.

[Time t1] The control circuit 20 applies a gate driving signal g2 at a low potential level to the gate of the switching element T2 to turn off the switching element T2.
[Period t2] The voltage VT2 starts to rise.

  [Time t3] When the voltage VT2 is increasing, the load current IT2 flowing through the switching element T2 starts to decrease from the current value Imax. At this timing, the control circuit 20 applies a gate drive signal g1 of a high potential level to the gate of the NMOS transistor M1 in the switching element T1.

  [Period t4] The voltage VT2 at both ends is rising, and the load current IT2 flowing through the switching element T2 is falling. Also, the NMOS transistor M1 is turned on (the gate drive signal g1 maintains the high potential level).

  [Time t5] The voltage VT2 at both ends reaches 2 × Edc (threshold level) which is the total voltage of the power supply voltage of the positive power supply V1 and the power supply voltage of the negative power supply V2. Also, the NMOS transistor M1 is maintained in the on state.

  In this case, the load current I1 flowing through the path r3 does not flow to the body diode Dp1 in the switching element T1, but flows to the NMOS transistor M1 in the switching element T1. Even if the NMOS transistor M1 is turned on, the switching element T2 is already in the turn-off operation, so the power supply will not be shorted.

  [Time t6] The voltage VT2 at both ends starts to fall from the peak and reaches the voltage (2 × Edc), and the time period at which the voltage VT2 becomes equal to or higher than the voltage (2 × Edc) ends. At this timing, the control circuit 20 applies a gate drive signal g1 at a low potential level to the gate of the NMOS transistor M1 to turn off the NMOS transistor M1.

  As described above, according to the power conversion device 1-1 of the present invention, the control circuit 20 sets the switching element T1 (NMOS transistor M1) in the off period until the switching element T2 is turned off and then turned on. Turn on the period.

  Then, the control circuit 20 causes a load current directed to the switching element T1 to flow to the NMOS transistor M1 in the switching element T1 to make the load current nonconductive to the body diode Dp1 in the switching element T1. This makes it possible to suppress the deterioration of the body diode Dp1 and reduce the power loss.

  In the above description, although the positive electrode side switching device is turned on for a predetermined period during the period when the negative electrode side switching device is turned off, the negative electrode side switching is performed during the period when the positive electrode side switching device is turned off. The element may be turned on for a predetermined period.

  Next, a modification of the power converter will be described with reference to FIGS. 10 and 11. FIG. 10 is a diagram showing a configuration example of a power conversion device according to a modification. The power converter 1-2 of the modification includes an orthogonal transformer 10a and a control circuit 20a.

  The orthogonal transformer 10a includes switching elements T1 to T4, a switch circuit SW, diodes D1 and D2, a positive power supply V1 and a negative power supply V2. The switching element T1 includes an NMOS transistor M1 and a body diode Dp1, and the switching element T2 includes an NMOS transistor M2 and a body diode Dp2.

The switch circuit SW includes an NMOS transistor Ms (third transistor) and a diode D3 (third diode), and is connected in parallel to the switching element T1.
Denoting the connection relationship around the switch circuit SW, the anode of the diode D3 is the source of the NMOS transistor M1, the anode of the body diode Dp1, the anode of the diode D2, the emitter of the switching element T4, the drain of the NMOS transistor M2, and the body diode Dp2. Connect to the cathode.

  The cathode of the diode D3 is connected to the drain of the NMOS transistor Ms. The source of the NMOS transistor Ms is connected to the positive terminal of the positive power supply V1, the drain of the NMOS transistor M1, and the cathode of the body diode Dp1. The other circuit configuration is the same as that of the orthogonal transformer 10 of the power conversion device 1-1 shown in FIG.

  The control circuit 20a inputs gate drive signals g1 to g4 to the gates of the switching elements T1 to T4, and performs switching control of the switching elements T1 to T4. Further, the control circuit 20a inputs the gate drive signal gs to the gate of the NMOS transistor Ms in the switch circuit SW, and performs switching of the switch circuit SW (switching of the NMOS transistor Ms).

  Here, in the power converter 1-2, the switching element T1 is continuously turned off while the switching element T1 is continuously turned off during the off period from the turn-off to the turn-on during the switching operation of the switching element T2. Control to turn on the period. That is, the gate drive signal gs of high potential level is applied to the gate of the NMOS transistor Ms in the switch circuit SW, and the switch circuit SW is turned on for a predetermined period.

FIG. 11 is a diagram for explaining the operation of the power conversion device of the modification.
[Period t10] The control circuit 20a applies a gate drive signal g2 at a high potential level to the gate of the switching element T2. At this time, the switching element T2 is turned on. Further, the control circuit 20a applies a gate drive signal gs at a low potential level to the gate of the NMOS transistor Ms in the switch circuit SW. At this time, the NMOS transistor Ms is turned off.

  The switching elements T1, T3 and T4 are also switched based on the gate drive signals g1, g3 and g4 output from the control circuit 20a. In this case, the switching element T1 is off, the switching element T3 is on, and the switching element T4 is off.

  On the other hand, in a period t10 in which the switching element T1 is off and the switching element T2 is on, the voltage VT2 is 0V. At this time, the load current IT2 flowing through the switching element T2 is assumed to have a current value Imax. Furthermore, no load current flows to the switching element T1.

[Time t11] The control circuit 20a applies a gate driving signal g2 at a low potential level to the gate of the switching element T2 to turn off the switching element T2.
[Period t12] The voltage VT2 starts to rise.

  [Time t13] When the voltage VT2 is increasing, the load current IT2 flowing through the switching element T2 starts to decrease from the current value Imax. At this timing, the control circuit 20a applies a gate driving signal gs of high potential level to the gate of the NMOS transistor Ms to turn on the NMOS transistor Ms.

  [Period t14] The voltage VT2 at both ends is rising, and the load current IT2 flowing through the switching element T2 is falling. Also, the NMOS transistor Ms is in the on state (the gate drive signal gs maintains the high potential level).

  [Time t15] The voltage VT2 at both ends reaches 2 × Edc (threshold level) which is a total voltage of the power supply voltage of the positive power supply V1 and the power supply voltage of the negative power supply V2. Also, the NMOS transistor Ms remains on.

  In this case, the load current I1 flowing in the path r3 does not flow in the body diode Dp1 in the switching element T1, but flows in the NMOS transistor Ms in the switch circuit SW. Even when the switch circuit SW is turned on, the switching element T2 is already in the turn-off operation, so the power supply will not be shorted.

  [Time t16] The voltage VT2 at both ends starts to fall from the peak and reaches the voltage (2 × Edc), and the time slot at which the voltage VT2 becomes equal to or higher than the voltage (2 × Edc) ends. At this timing, the control circuit 20a applies a gate drive signal gs of a low potential level to the gate of the NMOS transistor Ms to turn off the NMOS transistor Ms.

  As described above, according to power conversion device 1-2 of the modification of the present invention, control circuit 20a is connected in parallel to switching element T1 during the off period until switching element T2 is turned off and then turned on. The switch circuit SW is turned on for a predetermined period.

  Then, the control circuit 20a diverts the load current toward the switching element T1 to the switch circuit SW to make the load current nonconductive to the body diode Dp1 in the switching element T1. This makes it possible to suppress the deterioration of the body diode Dp1 and reduce the power loss.

  Although not shown in FIGS. 8 and 10, the power conversion devices 1-1 and 1-2 are switched from the load 3 connected via the intermediate point U where the switching element T1 and the switching element T2 are connected. It includes a current monitoring circuit that monitors a load current flowing to the element T2, and a voltage monitoring circuit that monitors a voltage across the switching element T2.

  As a current monitoring circuit, for example, a current transformer can be used (the current transformer is disposed on the wiring from the middle point U to the load 3). Further, as a voltage monitor circuit, a comparator using an operational amplifier can be used. The voltage monitor circuit monitors the voltage between the midpoint U and the negative pole N.

  The control circuits 20 and 20a recognize the timing at which the load current flowing through the switching element T2 starts to decrease based on the monitor results transmitted from these monitor circuits, and recognize whether or not the both-end voltage is higher than the threshold level. can do.

  As mentioned above, although embodiment was illustrated, the structure of each part shown by embodiment can be substituted to the other thing which has the same function. Also, any other components or steps may be added.

DESCRIPTION OF SYMBOLS 1 Power converter 1a Orthogonal converter 1b Control circuit 3 Load T1 to T4 Switching element M1 NMOS transistor Dp1 Body diode D1, D2 diode V1 Positive power supply V2 Negative power supply U Mid point

Claims (8)

A first switching element on the positive electrode side including a first transistor and a first body diode;
A second switching element on the negative electrode side connected in series to the first switching element;
An orthogonal transform unit including
A control circuit which turns on the first switching element for a predetermined period during a period from the turn-off operation of the second switching element to the turn-on operation;
A power converter characterized by having.   The control circuit turns on the first transistor for a predetermined time during a period in which the voltage across the second switching element is greater than or equal to a predetermined threshold, and continues until the period ends. The power converter according to claim 1, wherein the transistor is maintained in the on state.   The orthogonal transformation unit further includes a positive side power supply and a negative side power supply as a power supply, and the control circuit sets a voltage of a sum of a power supply voltage of the positive side power supply and a power supply voltage of the negative side power supply as the threshold. The power converter according to claim 2, characterized in that: The orthogonal transform unit includes the first switching element including the first transistor and the first body diode, the second switching element including a second transistor and a second body diode, a third, and a third. 4 switching elements, first and second diodes, a positive side power supply and a negative side power supply,
The positive electrode side terminal of the positive electrode side power supply is connected to the drain of the first transistor and the cathode of the first body diode,
The negative terminal of the negative power supply is connected to the source of the second transistor and the anode of the second body diode.
The negative terminal of the positive power supply is connected to the positive terminal of the negative power, the emitter of the third switching element, and the anode of the first diode,
The collector of the third switching element is connected to the cathode of the first diode, the cathode of the second diode and the collector of the fourth switching element,
An emitter of the fourth switching element is an anode of the second diode, a source of the first transistor, an anode of the first body diode, a drain of the second transistor, and the second body diode. Connect to cathode and midpoint
The power converter according to claim 1, characterized in that. A first switching element on the positive electrode side including a first body diode, a second switching element on the negative electrode side connected in series to the first switching element, and a switch circuit connected in parallel to the first switching element An orthogonal transform unit including
A control circuit for turning on the switch circuit for a predetermined period during a period from the turn-off operation of the second switching element to the turn-on operation;
A power converter characterized by having.   The control circuit turns on the switch circuit and turns on the switch circuit during a period in which the voltage across the second switching element is greater than or equal to a threshold, until the period ends. The power converter according to claim 5, wherein the switch circuit is maintained in the on state.   The orthogonal transformation unit further includes a positive side power supply and a negative side power supply as a power supply, and the control circuit sets a voltage of a sum of a power supply voltage of the positive side power supply and a power supply voltage of the negative side power supply as the threshold. The power converter according to claim 6, characterized in that: The orthogonal transform unit includes the first switching element including a first transistor and the first body diode, the second switching element including a second transistor and a second body diode, and third and fourth elements. And the switch circuit including the first transistor, the second diode, the positive power supply, the negative power supply, and the third transistor and the third diode,
The positive terminal of the positive power supply is connected to the drain of the first transistor, the cathode of the first body diode, and the source of the third transistor.
The negative terminal of the negative power supply is connected to the source of the second transistor and the anode of the second body diode.
The negative terminal of the positive power supply is connected to the positive terminal of the negative power, the emitter of the third switching element, and the anode of the first diode,
The collector of the third switching element is connected to the cathode of the first diode, the cathode of the second diode and the collector of the fourth switching element,
The emitter of the fourth switching element is the anode of the second diode, the source of the first transistor, the anode of the first body diode, the anode of the third diode, the drain of the second transistor Connected to the cathode of the second body diode and to the intermediate point,
The cathode of the third diode is connected to the drain of the third transistor,
The power converter according to claim 5, characterized in that:

Images