JP2018170378A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having a small area for both a high withstand voltage bipolar transistor and a bipolar transistor functioning as an ESD protection element at low cost. SOLUTION: A first bipolar transistor is interposed between a first diffusion layer which is a base region and a second diffusion layer which is a collector region, and has a trench insulation region deeper than the first diffusion layer. The second bipolar transistor, which functions as an ESD protection element, is interposed between the third diffusion layer, which is the base region, and the fourth diffusion layer, which is the collector region, and is a trench shallower than the third diffusion layer. Has an insulated area. [Selection diagram] Fig. 1

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device provided with a high breakdown voltage bipolar transistor.

Currently, for example, a semiconductor device used as an in-vehicle product is required to have an element having a high breakdown voltage, a small area, and high reliability.
However, high breakdown voltage transistors are often designed such that the distance on the drain (or collector) side is long in order to prevent electric field concentration, and the element area tends to increase.

  In order to solve this problem, in a high voltage bipolar transistor, there is a method of reducing the area so that the current path is mainly in the vertical direction by providing a deep trench insulating region between the emitter and the collector in order to reduce the element area. It is known (see, for example, Patent Document 1).

Japanese Patent Laid-Open No. 06-232149

However, in order to reduce the area of the semiconductor device, even if the element area is reduced by forming a bipolar transistor using a deep trench insulating region as in Patent Document 1, it is possible to reduce the area from electrostatic discharge (ESD). Unless the elements to be protected are made small, the area of the entire semiconductor device cannot be reduced so much.
Generally, an ESD protection element needs to have a large area in order to flow a large amount of current due to ESD, and has a high area occupation ratio among semiconductor devices.

  In addition, the ESD protection element must satisfy the two conditions of reducing the parasitic resistance in the ESD protection element and facilitating the parasitic bipolar operation in order to prevent a surge current from flowing through the element to be protected. There is. In the bipolar transistor, in order to satisfy the former condition of the two conditions, it is necessary to shorten the current path from the emitter to the collector or increase the impurity concentration of at least one of the emitter, base, and collector. . To satisfy the latter condition, it is necessary to shorten the base current path, lower the base impurity concentration, or increase the emitter impurity concentration.

  In a semiconductor device having a bipolar transistor using a deep trench insulating region as shown in the cited document 1, if an ESD protection element having a small area is produced by a bipolar transistor using a deep trench insulating region, Since the length of the current path is determined by the depth of the region, even if the depth of the implantation for forming the emitter, base, and collector regions is changed, the current path becomes longer and shorter However, it is impossible to satisfy both the shortening of the current path from the emitter to the collector and the shortening of the current path of the base.

In addition, if the impurity concentration of the emitter is increased, both of the above two conditions can be satisfied. However, the impurity concentration of the emitter is often close to the limit that can be activated in order to increase the capability of the bipolar transistor. It is difficult to increase the concentration.
As a result, in order to make an ESD protection element with a small area, it is necessary to add two photomasks for increasing the impurity concentration of the collector and for decreasing the impurity concentration of the base, which greatly increases the cost. End up.

  Therefore, an object of the present invention is to provide a semiconductor device having a small area for both a high voltage bipolar transistor and a bipolar transistor functioning as an ESD protection element at low cost.

  The semiconductor device of the present invention is provided adjacent to each other on the first conductivity type first buried layer provided in the first region of the first conductivity type semiconductor substrate and the first buried layer. The first conductivity type first diffusion layer and the second conductivity type second diffusion layer, and the first diffusion layer interposed between the first diffusion layer and the second diffusion layer. A first trench insulating region provided deeper than the diffusion layer; a first conductivity type first base contact region and a second conductivity type first emitter region provided on a surface of the first diffusion layer; And a first bipolar transistor having a second collector type first collector contact region provided on the surface of the second diffusion layer, and a second bipolar transistor different from the first region of the semiconductor substrate. A second buried layer of the second conductivity type provided in the region, and the second buried A first conductive type third diffusion layer and a second conductive type fourth diffusion layer provided adjacent to each other, and between the third diffusion layer and the fourth diffusion layer. A second trench insulating region provided shallower than the third diffusion layer so as to intervene; a second base contact region of the first conductivity type provided on the surface of the third diffusion layer; And a second bipolar transistor having a second conductivity type second emitter region and a second conductivity type second collector contact region provided on a surface of the fourth diffusion layer. .

  According to the present invention, the first and second bipolar transistors have the same diffusion layer configuration, and therefore have the same collector-emitter breakdown voltage. Further, the second bipolar transistor can shorten the path of the current flowing in the fourth diffusion layer serving as the collector and the third diffusion layer serving as the base, as compared with the first bipolar transistor. That is, the second bipolar transistor has a low parasitic resistance and easily enters a parasitic bipolar operation. Therefore, it is not necessary to make the diffusion layer concentration of the second bipolar transistor different from that of the first bipolar transistor, and the second bipolar transistor can be made to be the first bipolar transistor by simply adjusting the depth of the second trench insulating region. It can be an ESD protection element of a transistor.

In addition, since both the first and second bipolar transistors have current paths mainly in the vertical direction (depth direction), it is possible to realize a semiconductor device having a small area as a whole.
Furthermore, in order to make the depths of the first trench insulating region and the second trench insulating region different from each other, it is only necessary to add one photomask, so that an increase in cost can be suppressed.

1 is a schematic cross-sectional view showing a semiconductor device according to a first embodiment of the present invention. It is a typical sectional view showing a semiconductor device by a 2nd embodiment of the present invention. It is a typical sectional view showing a semiconductor device by a 3rd embodiment of the present invention. It is a typical sectional view showing a semiconductor device by a 4th embodiment of the present invention. FIG. 6 is a schematic cross-sectional view showing a semiconductor device according to a fifth embodiment of the present invention. It is a typical sectional view showing a semiconductor device by a 6th embodiment of the present invention. It is a typical sectional view showing a semiconductor device by a 7th embodiment of the present invention.

Hereinafter, embodiments for carrying out the present invention will be described in detail with reference to the drawings.
[First Embodiment]
FIG. 1 is a schematic cross-sectional view showing a semiconductor device 100 according to the first embodiment of the present invention.
As shown in FIG. 1, the semiconductor device 100 according to this embodiment includes a bipolar transistor 10 provided in a region A of a P-type semiconductor substrate 1 and a bipolar transistor provided in a region B different from the region A of the semiconductor substrate 1. And a transistor 20.
The regions A and B are partitioned by the trench element isolation region 2.

The bipolar transistor 10 includes an N type buried layer 11 provided on the semiconductor substrate 1, a P type diffusion layer 12 and an N type diffusion layer 13 provided adjacent to each other on the buried layer 11, and a diffusion layer. 12 and a diffusion insulating layer 14 provided deeper than the diffusion layer 12, a P-type base contact region 15 provided on the surface of the diffusion layer 12, It has an N-type emitter region 16 provided on the surface and an N-type collector contact region 17 provided on the surface of the diffusion layer 13.
In the bipolar transistor 10, the diffusion layer 12 functions as a base, and the diffusion layer 13 and the buried layer 11 function as a collector.

The bipolar transistor 20 includes an N type buried layer 21 provided on the semiconductor substrate 1, a P type diffusion layer 22 and an N type diffusion layer 23 provided adjacent to each other on the buried layer 21, and a diffusion layer. Trench insulating region 24 provided shallower than diffusion layer 22 so as to be interposed between diffusion layer 23 and diffusion layer 23, P-type base contact region 25 provided on the surface of diffusion layer 22, and diffusion layer 22 An N-type emitter region 26 provided on the surface and an N-type collector contact region 27 provided on the surface of the diffusion layer 23 are provided.
In the bipolar transistor 20, the diffusion layer 22 functions as a base, and the diffusion layer 23 and the buried layer 21 function as a collector.

  Although not shown, an interlayer insulating film is formed on the emitter regions 16 and 26, the base contact regions 15 and 25, and the collector contact regions 17 and 27, and contacts connected to the respective regions through the interlayer insulating film. Further, a metal wiring, a passivation film, and the like are formed thereon.

In this embodiment, the buried layers 11 and 21, the diffusion layers 12 and 22, the diffusion layers 13 and 23, the base contact regions 15 and 25, the emitter regions 16 and 26, and the collector contact regions 17 and 27 are each made of the same implanter. Is possible. Therefore, the bipolar transistors 10 and 20 can be formed separately only by adding one photomask for forming the trench insulating region 24 having a depth different from that of the trench insulating region 14.
Moreover, in this embodiment, the trench element isolation region 14 and the trench element isolation region 2 have the same depth, and these can be simultaneously formed with one photomask.

  When the bipolar transistor 20 is used as an ESD protection element for the bipolar transistor 10, the parasitic resistance of the bipolar transistor 20 is lower than that of the bipolar transistor 10 and the bipolar transistor 20 is more likely to enter a parasitic bipolar operation than the bipolar transistor 10. Need to be.

In the bipolar transistor 20, the distance between the emitter region 26 and the diffusion layer 23 is the base length, and the distance between the diffusion layer 22 and the collector contact region 27 is the collector length. By changing the depth of the region 24, the base length and the collector length can be expanded and contracted simultaneously. As described above, if the collector length is shortened, the parasitic resistance can be lowered, and if the base length is shortened, the parasitic resistance can be lowered and the parasitic bipolar operation can be easily performed. Therefore, by adjusting the depth of the trench isolation region 24 to provide the desired parasitic resistance and ease of entry into the parasitic bipolar operation, the bipolar transistor 20 is optimal for protecting the bipolar transistor 10 from ESD. It can be a protective element.
Further, it is desirable to determine the depth of the trench insulating region 14 so that the bipolar transistor 10 has a desired performance.

  In this embodiment, the emitter region 16 and the collector contact region 17 are adjacent to the trench insulating region 14, and the emitter region 26 and the collector contact region 27 are adjacent to the trench insulating region 24. Such an arrangement is particularly desirable because it is the arrangement that can best produce the difference in base length and collector length between the bipolar transistor 10 and the bipolar transistor 20.

  In the present embodiment, the region A and the region B are disposed adjacent to each other via the trench element isolation region 2, but are not necessarily adjacent to each other, and may be disposed at separate locations. . For example, another region partitioned by the trench element isolation region 2 may be provided between the regions A and B (that is, between the bipolar transistors 10 and 20), and another device may be formed there. In that case, the other element may not have the embedded layer.

Next, second to seventh embodiments of the present invention will be described with reference to FIGS.
2 to 7, the same components as those of the semiconductor device 100 according to the first embodiment shown in FIG.

[Second Embodiment]
FIG. 2 is a schematic cross-sectional view showing a semiconductor device 200 according to the second embodiment of the present invention.
As shown in FIG. 2, the semiconductor device 200 of this embodiment includes a MOS transistor 30 provided in a region C different from the regions A and B of the semiconductor substrate 1 in addition to the semiconductor device 100 shown in FIG. 1. Yes.

The MOS transistor 30 includes a P-type diffusion layer 32 provided on the N-type buried layer 31, a gate electrode 34 provided on the diffusion layer 32 via a gate oxide film 33, and the surface of the diffusion layer 32. , An N-type source diffusion layer 35 and a drain diffusion layer 36 provided on both sides of the gate electrode 34, respectively.
Note that the buried layer 31 may not be provided because it does not particularly affect the operation of the MOS transistor 30.

  Thus, not only the bipolar transistor but also a MOS transistor or the like can be protected from ESD by the bipolar transistor 20 as well as the bipolar transistor as long as it has a higher breakdown voltage than the bipolar transistor 20.

[Third Embodiment]
FIG. 3 is a schematic cross-sectional view showing a semiconductor device 300 according to the third embodiment of the present invention.
As shown in FIG. 3, in the semiconductor device 300 of this embodiment, the gate electrode 20g is embedded in the trench insulating region 24 in the semiconductor device 100 shown in FIG. Thus, the insulating film in the trench insulating region 24 is a gate insulating film, the diffusion layer 22 is a well and a channel, the diffusion layer 23 is a drain electric field relaxation layer, the base contact region 25 is a well contact region, and the emitter region 26 is As the source diffusion layer, the collector contact region 27 functions as a drain diffusion layer, and the element in the region B can be used as the MOS transistor 20m.

  Although not shown, a contact is formed on the gate electrode 20g embedded in the trench insulating region 24 through an interlayer insulating film formed thereon, and a potential is applied via a metal wiring formed thereon. Is done.

  According to the present embodiment, the MOS transistor 20m is normally turned off by wiring so that the gate electrode 20g and the source diffusion layer (emitter region) 26 have the same potential (for example, ground potential). It becomes an ESD protection element that allows a current to flow only when. Here, the presence of the gate electrode 20g suppresses the spread of the depletion layer that extends from the boundary between the diffusion layer 22 and the diffusion layer 23 in the direction of the source diffusion layer (emitter region). The voltage for the parasitic bipolar operation becomes lower than that of the bipolar transistor 20 in FIG. Therefore, this embodiment is particularly effective when it is desired to cause a parasitic bipolar operation more easily than the bipolar transistor 20 in the semiconductor device 100.

[Fourth Embodiment]
FIG. 4 is a schematic cross-sectional view showing a semiconductor device 400 according to the fourth embodiment of the present invention.
As shown in FIG. 4, in addition to the semiconductor device 100 shown in FIG. 1, the semiconductor device 400 of this embodiment includes an N-type diffusion layer 18 provided between the buried layer 11 and the diffusion layers 12 and 13, An N-type diffusion layer 28 provided between the buried layer 21 and the diffusion layers 22 and 23 is further provided. The diffusion layers 18 and 28 have a lower impurity concentration than the buried layers 11 and 21.

  According to this embodiment, the collector-emitter breakdown voltage of the bipolar transistor 10 and the bipolar transistor 20 can be increased. Therefore, an element having a higher breakdown voltage than that of the semiconductor device 100 can be obtained.

[Fifth Embodiment]
FIG. 5 is a schematic cross-sectional view showing a semiconductor device 500 according to the fifth embodiment of the present invention.
As shown in FIG. 5, in the semiconductor device 500 of the present embodiment, the buried layer 11 and the buried layer 21 are separately provided in the semiconductor device 100 shown in FIG. An N-type buried layer 501 is provided.

  In the semiconductor device 100, since the buried layer 11 and the buried layer 21 are provided separately, when the regions A and B are arranged adjacent to each other, a large distance must be taken according to the space rule between the buried layers. Often not.

  On the other hand, according to the present embodiment, the bipolar transistor 10 and the bipolar transistor 20 are formed on the common buried layer 501 in which the buried layer 11 and the buried layer 21 provided separately are integrally formed. Therefore, the area can be further reduced as compared with the semiconductor device 100.

[Sixth Embodiment]
FIG. 6 is a schematic cross-sectional view showing a semiconductor device 600 according to the sixth embodiment of the present invention.
As shown in FIG. 6, the semiconductor device 600 of this embodiment is different from the semiconductor device 200 shown in FIG. 2 in that the buried layer 11, the buried layer 21, and the buried layer 31 are provided separately. The N-type buried layer 601 is integrally formed.

  In the semiconductor device 200, since the buried layer 11, the buried layer 21, and the buried layer 31 are separately provided, when the regions A, B, and C are arranged adjacent to each other, the space rule between the buried layers increases. In many cases, distance must be taken.

  On the other hand, according to the present embodiment, the bipolar transistor 10 and the bipolar transistor 20 are provided on the common buried layer 601 in which the buried layer 11, the buried layer 21, and the buried layer 31 are separately formed. Since the MOS transistor 30 is formed, the area can be further reduced as compared with the semiconductor device 200.

[Seventh Embodiment]
FIG. 7 is a schematic cross-sectional view showing a semiconductor device 700 according to the seventh embodiment of the present invention.
As shown in FIG. 7, in the semiconductor device 700 of this embodiment, the diffusion layer 13 and the diffusion layer 23 are unified into one N-type diffusion layer 703 in the semiconductor device 500 shown in FIG. A collector contact region 707 that unifies the collector contact region 27 is provided on the surface of the diffusion layer 703. Thereby, the diffusion layer 703 and the collector contact region 707 are shared by the bipolar transistor 10 and the bipolar transistor 20.

In the present embodiment, the bipolar transistor 20 operates only when a surge due to ESD occurs.
According to the present embodiment, by sharing the diffusion layer 703 that is a collector, it is possible to omit one of the diffusion layer 13 and the diffusion layer 23 and an area necessary for the space rule between the active areas. In addition, the area can be further reduced as compared with the semiconductor device 500.

As mentioned above, although embodiment of this invention was described, it cannot be overemphasized that this invention is not limited to the said embodiment, A various change is possible in the range which does not deviate from the meaning of this invention.
For example, in the above-described embodiment, the first conductivity type is P type and the second conductivity type is N type. However, the first conductivity type is N type, and the second conductivity type is P type. It is also possible to do.
Further, in order to appropriately change the concentration of each diffusion layer, a diffusion layer having the same conductivity type as each diffusion layer may be introduced in an overlapping manner.

DESCRIPTION OF SYMBOLS 1 P type semiconductor substrate 2 Trench element isolation region 10, 20 Bipolar transistor 20m, 30 MOS transistors 11, 21, 31, 501 N type buried layers 12, 22, 32 P type diffusion layers 13, 23, 703 N type diffusion layer 14 , 24 Trench insulating regions 15, 25 P-type base contact regions 16, 26 N-type emitter regions 17, 27, 707 N-type collector contact regions 18, 28 Lightly doped N-type diffusion layer 33 Gate oxide film 20g, 34 Gate electrode 35 Source Diffusion layer 36 Drain diffusion layer

Claims (8)

A second conductivity type first buried layer provided in the first region of the first conductivity type semiconductor substrate;
A first conductivity type first diffusion layer and a second conductivity type second diffusion layer provided adjacent to each other on the first buried layer;
A first trench insulating region provided deeper than the first diffusion layer so as to be interposed between the first diffusion layer and the second diffusion layer;
A first conductivity type first base contact region and a second conductivity type first emitter region provided on a surface of the first diffusion layer;
A first bipolar transistor having a first collector contact region of a second conductivity type provided on the surface of the second diffusion layer;
A second conductivity type second buried layer provided in a second region different from the first region of the semiconductor substrate;
A first conductivity type third diffusion layer and a second conductivity type fourth diffusion layer provided adjacent to each other on the second buried layer;
A second trench insulation region provided shallower than the third diffusion layer so as to be interposed between the third diffusion layer and the fourth diffusion layer;
A first conductivity type second base contact region and a second conductivity type second emitter region provided on a surface of the third diffusion layer;
A semiconductor device comprising: a second bipolar transistor having a second collector contact region of a second conductivity type provided on a surface of the fourth diffusion layer. A first conductivity type fifth diffusion layer provided in a third region different from the first region and the second region of the first conductivity type semiconductor substrate;
A gate electrode provided on the fifth diffusion layer via a gate insulating film;
The MOS transistor having a source diffusion layer and a drain diffusion layer of a second conductivity type provided so as to be positioned on both sides of the gate electrode on the surface of the fifth diffusion layer, respectively. 2. The semiconductor device according to 1.   The semiconductor device according to claim 2, further comprising a third buried layer of a second conductivity type provided under the fifth diffusion layer. An electrode embedded in the second trench insulating region via an insulating film;
MOS having the electrode as a gate electrode, the insulating film in the second trench insulating region as a gate insulating film, and the second emitter region and the second collector contact region as a source diffusion layer and a drain diffusion layer The semiconductor device according to claim 1, wherein a transistor is configured. A sixth diffusion layer of a second conductivity type having a lower concentration than that of the first buried layer, provided between the first buried layer and the first and second diffusion layers;
And a seventh conductivity type second diffusion layer having a lower concentration than that of the second buried layer, which is provided between the second buried layer and the third and fourth diffusion layers. The semiconductor device according to claim 1, wherein:   6. The semiconductor device according to claim 1, wherein the first buried layer and the second buried layer are integrally formed.   4. The semiconductor device according to claim 3, wherein the first buried layer, the second buried layer, and the third buried layer are integrally formed. The second diffusion layer and the fourth diffusion layer are one diffusion layer, and are shared by the first bipolar transistor and the second bipolar transistor,
2. The first collector contact region and the second collector contact region are one region and are shared by the first bipolar transistor and the second bipolar transistor. The semiconductor device as described in any one of thru | or 7.

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