JP2018166155A - FCBGA substrate and manufacturing method thereof - Google Patents

Abstract

An object of the present invention is to remove a part of a surface insulating resin layer (solder resist layer) in a region immediately below where a semiconductor device is mounted except for a conductor land portion of an FCBGA substrate, thereby exposing a base. It is an object of the present invention to provide an FCBGA substrate capable of suppressing warpage that occurs at the time of solder reflow without impairing typical insulation properties. An FC pad electrode that is solder-bonded to a terminal electrode of an array of semiconductor chips is provided on a surface on which a semiconductor chip is mounted, and an array of terminal electrodes of a printed wiring board is provided on the other surface. An FCBGA substrate 1 having a solder bonding electrode, which is covered with a solder resist layer 3 except for the FC pad electrode of the FCBGA substrate and the solder bonding electrode on the back surface thereof, on the surface of the solder resist layer on the FC pad electrode side. Is an FCBGA substrate in which lattice-shaped recesses 5 are formed. [Selection] Figure 1

Description

  The present invention relates to an FCBGA (Flip Chip Ball Grid Array) substrate and a manufacturing method thereof.

  Electronic devices are becoming smaller, thinner, and higher in performance, and the number of connection electrodes (pad electrodes) with external circuits of IC chips used for them has been increasing. As the number of pad electrodes increases, the miniaturization of pad electrodes is progressing. Since the size of the pad electrode of such an IC chip differs from the size of the electrode that can be formed on the printed wiring board, it is first mounted on an interposer that is a substrate for matching the electrode dimensions. After mounting on an interposer, mounting on a printed wiring board has become the mainstream.

  As an interposer, pattern miniaturization advances with an increase in the number of electrodes, and an FCBGA substrate is used for an IC chip having a large number of electrodes. As the FCBGA board, BGA is used for both connection with a printed wiring board and connection with an IC chip.

  The dimensions of the electrodes formed on such an FCBGA substrate are the minimum dimensions that can be handled, and the mounting yield is reduced due to the warpage of the substrate that occurs during solder reflow heating. FIG. 3 is a cross-sectional view illustrating the state of poor solder connection with the printed wiring board 6 when the conventional FCBGA board 1 ′ is warped. Since the FCBGA substrate 1 ′ is warped, the solder ball 7 at the warped portion cannot be connected.

  In order to suppress the occurrence of such warping, various techniques have been studied. Even if stress occurs inside the substrate, to reduce the amount of warping, adopt a highly rigid core substrate as the material that constitutes the substrate, or evenly distribute the wiring pattern formed on the front and back surfaces of the substrate, As a laminated structure of the substrate, various studies have been made such as arranging the thermal expansion coefficients symmetrically on the front and back surfaces.

  For example, in Patent Document 1, as a printed wiring board capable of preventing warpage during solder reflow, a conductor wiring layer and an interlayer insulating resin layer are laminated on at least one surface of a core substrate, and the uppermost conductive wiring layer is a surface insulating resin. In a multilayer printed wiring board covered with a layer (solder resist layer), in a region where a semiconductor device such as a semiconductor package is mounted and directly under the semiconductor device excluding a conductor land portion joined to an external electrode of the semiconductor device In this area, a printed wiring board is disclosed in which a part of the surface insulating resin layer (solder resist layer) formed on the interlayer insulating resin layer or the conductor wiring layer is removed.

  This printed circuit board is an excellent technology that can prevent warping that occurs during solder reflow, but since the surface insulating resin layer (solder resist layer) has been partially removed, the substrate is exposed at that site. Yes. For this reason, the base is exposed at that portion and comes into contact with the molten solder, which may impair the electrical insulation.

  In particular, for an interposer and a thin printed wiring board for a semiconductor package that are likely to be warped during solder reflow, an FCBGA substrate that is a thin printed circuit board for a semiconductor package has been expected to have a technique capable of suppressing the occurrence of warpage.

JP 2008-16630 A

  In view of the above circumstances, an object of the present invention is to provide an FCBGA substrate capable of suppressing the occurrence of warp without impairing semi-electrical insulation.

As a means for solving the above-mentioned problems, the invention according to claim 1 of the present invention includes an FC pad electrode that is solder-bonded to a terminal electrode of an array of semiconductor chips on the surface on which the semiconductor chip is mounted. An FCBGA board having solder joint electrodes with terminal electrodes arranged in an array of printed wiring boards on the surface,
Other than the FC pad electrode of the FCBGA substrate and the solder joint electrode on the back side, it is covered with a solder resist layer.
The FCBGA substrate is characterized in that a grid-like recess is formed on the surface of the solder resist layer on the FC pad electrode side.

The invention according to claim 2 is a method for manufacturing an FCBGA substrate according to claim 1,
Forming a conductor wiring layer on the front and back surfaces of the core substrate; and
Forming an interlayer insulating layer on the conductor wiring layers on the front and back surfaces and forming a via hole; and
A step of producing a wiring board having a conductor wiring layer formed on the outermost surface by repeating step A and step B;
Forming a solder resist layer on the outermost conductor wiring layer;
Removing the solder resist layer at a desired position on the surface on which the semiconductor chip is mounted, exposing the FC pad electrode, and forming a lattice-shaped recess;
And a step of exposing a solder bonding electrode to the printed wiring board by removing the solder resist layer at a desired position of the solder resist layer formed on the other surface. It is a manufacturing method.

  According to a third aspect of the present invention, the FC pad electrode is exposed and the lattice-shaped recess is formed by removing the solder resist layer at a desired position on the surface on which the semiconductor chip is mounted. 3. The method of manufacturing an FCBGA substrate according to claim 2, wherein the step of performing is a step of exposing and developing with a halftone mask using a photosensitive solder resist.

  According to a fourth aspect of the present invention, the FC pad electrode is exposed and the lattice-shaped recesses are formed by removing the solder resist layer at a desired position on the surface on which the semiconductor chip is mounted. 3. The method of manufacturing an FCBGA substrate according to claim 2, wherein the step of performing is a step of exposing and developing with a halftone mask using a photosensitive solder resist.

  According to the FCBGA substrate of the present invention, the surface of the solder resist on the side where the semiconductor chip is mounted is provided with a lattice-shaped recess, so that the FCBGA substrate warps even when exposed to high temperatures during solder reflow. Is suppressed. Therefore, the occurrence of poor connection between the semiconductor chip and the FCBGA substrate and poor connection between the FCBGA substrate and the printed wiring board is suppressed.

  Moreover, according to the manufacturing method of the FCBGA substrate of the present invention, the FCBGA substrate of the present invention can be provided.

It is explanatory drawing which illustrated the one aspect | mode of the FCBGA board | substrate of this invention, Comprising: (a) is a schematic top view of the recessed part provided in the grid | lattice shape provided in the surface which mounts a semiconductor chip, (b) is (a). The schematic sectional drawing in the AA 'cutting line is shown. It is the schematic sectional drawing which illustrated the state where the FCBGA board of the present invention was connected with the printed wiring board with the solder ball, and illustrated the situation where the FCBGA board is not warped. FIG. 6 is a schematic cross-sectional view illustrating a state in which a conventional FCBGA substrate is connected to a printed wiring board with solder balls, where the FCBGA substrate is warped and some solder balls are connected, but some solder The ball | bowl has illustrated the condition which is not connected.

<FCBGA substrate>
As a result of earnestly researching the form of the solder resist layer, which is the outermost insulating resin layer of the wiring board, and the warping of the board that occurs when the multilayer wiring board is exposed to a high temperature environment such as solder reflow, As a result of obtaining knowledge about the effect of the lattice-shaped recesses formed in the solder resist to reduce warpage, the present invention has been completed.

The FCBGA substrate of the present invention will be described with reference to FIGS.
The FCBGA substrate 1 of the present invention includes FC (flip chip) pad electrodes (not shown) which are solder-bonded to the arrayed terminal electrodes of the semiconductor chip 2 on the surface on which the semiconductor chip is mounted, and the other surface. This is an FCBGA substrate 1 provided with solder joint electrodes (not shown) with terminal electrodes arranged in an array on the printed wiring board 6.

  The FCBGA substrate 1 of the present invention has an insulation on the outermost surface on the outermost conductor wiring layer of the wiring substrate 4 produced by alternately forming a conductor wiring layer and an interlayer insulating layer on the front and back surfaces of the core substrate. The solder resist layer 3 which is a resin layer is formed. The FC pad electrode provided on the surface on which the semiconductor chip 2 is mounted and the solder bonding electrode on the back side thereof are covered with the solder resist layer 3, and the surface of the solder resist layer 3 on the FC pad electrode side is in a lattice shape It is the feature that the recessed part of this is formed (refer FIG.1 (b)).

  Since the grid-like recesses 5 are formed in the solder resist layer 3 on the surface on which the semiconductor chip 2 is mounted, the FCBGA substrate 1 of the present invention may warp even after a high-temperature processing step such as solder reflow. It is suppressed.

  The grid-like recesses 5 are not removed from the solder resist layer 3 but are removed halfway to form recesses.

<Manufacturing method of FCBGA substrate>
Next, a method for manufacturing the FCBGA substrate of the present invention will be described.
The manufacturing method of the FCBGA substrate of the present invention includes a step A of forming a conductor wiring layer on the front and back surfaces of the core substrate, a step B of forming an interlayer insulating layer on the conductor wiring layer on the front and back surfaces, and forming a via hole; By repeating step A and step B, a step of manufacturing a wiring board having a conductor wiring layer formed on the outermost surface, a step of forming a solder resist layer on the outermost conductor wiring layer, and a semiconductor chip By removing the solder resist layer at a desired position on the surface to be mounted, the step of exposing the FC pad electrode and forming a lattice-shaped recess, and the desired solder resist layer formed on the other surface And removing the solder resist layer at the position to expose the solder joint electrode with the printed wiring board.

By removing the solder resist layer at a desired position on the surface on which the semiconductor chip is mounted, a means for exposing the FC pad electrode and forming a lattice-shaped recess is formed using a photosensitive solder resist. A means for exposing and developing with a halftone mask may be used.

  In addition, by removing the solder resist layer at a desired position on the surface on which the semiconductor chip is mounted, the means for exposing the FC pad electrode and forming the lattice-shaped recess is irradiated with a laser beam to the solder. It may be a means for removing the resist layer.

(Process A for forming a conductor wiring layer)
As a means for forming the conductor wiring layer, a conventional manufacturing process of a multilayer printed wiring board can be suitably used. Moreover, as a board | substrate used as a core, the copper produced by, for example, heat-pressing the rough surface of electrolytic copper foil to the both surfaces of the prepreg which made the glass cloth impregnate the epoxy resin of B stage FR-4 face each other. A tension laminate can be used.

  After through holes are formed by drilling or the like at desired positions on the front and back copper foils, a copper plating layer is formed inside the through holes through a through hole plating step. Thereafter, a photosensitive dry film is laminated on both the front and back surfaces, exposed using a photomask having a desired exposure pattern, and developed. Thereafter, unnecessary copper foil is removed by etching using the dry film pattern as an etching mask, and the etching mask is peeled off to form a conductor wiring layer (also referred to as a conductor pattern or wiring pattern) having the copper foil layer as a conductor. be able to.

  As an example of the conductor wiring layer, a copper-clad laminate was used to pattern and form a copper foil. However, the present invention is not limited to this. For example, an aluminum foil formed on an insulating substrate is patterned. It is also possible to use a conductive pattern formed by printing metal ink or conductive ink. Further, instead of copper plating in the through hole, metal ink or conductor ink may be filled in the through hole to conduct with the conductor wiring layer formed on the front and back surfaces of the substrate.

(Process B in which an interlayer insulating layer is formed on a conductor wiring layer and a via hole is formed)
As a means for forming an interlayer insulating layer on the conductor wiring layer, a conventional multilayer printed wiring board manufacturing process can be suitably used.

  As the interlayer insulating layer, for example, an organic insulating resin sheet can be bonded using a vacuum laminator. Moreover, it can form by apply | coating and drying a liquid insulating resin on a conductor wiring layer.

  Materials for the interlayer insulation layer include epoxy, acrylic, urethane, epoxy acrylate, phenol epoxy, polyimide, polyamide, cyanate, polymer liquid crystal sheets, glass, polyamide, and liquid crystal. A material impregnated with a reinforcing fiber made of silica, a filler such as silica, a butyl organic material, or calcium carbonate may be included.

As means for forming a via hole in the interlayer insulating layer, a conventional multilayer printed wiring board manufacturing process can be suitably used. Specifically, a method of removing an interlayer insulating layer at a desired site using a laser (CO ₂ , UV, excimer) can be mentioned. Further, a via hole can be formed in the interlayer insulating layer by a process of using a photosensitive resin material as the interlayer insulating layer and exposing and developing using a photomask having a desired pattern.

(Process of forming solder resist layer on conductor wiring layer on front and back)
After forming the uppermost conductor wiring layer, a solder resist layer is formed thereon. As a means for applying the solder resist ink to be the solder resist layer on the conductor wiring layers on the front and back surfaces, for example, it can be applied to a desired thickness using a roll coater. The means for applying is not limited to a roll coater, and screen printing, curtain coater, spray coater and the like can be used as appropriate.

  It can be set as a soldering resist layer by drying after application | coating. As a drying means, it is usually stored in warm air in a clean oven and dried by volatilizing the solvent in the solder resist. Therefore, what is necessary is just to set drying temperature and processing time according to the solvent currently used.

(Means for removing solder resist layer)
The means for removing the solder resist layer at a desired position differs depending on whether or not a photosensitive material is used as the solder resist layer.

  When a photosensitive solder resist is used, a solder resist layer at a desired site can be removed by performing exposure and development using a photomask having a desired pattern. By using a halftone mask as a photomask, all the solder resist layers of the FC pad electrode part and the solder joint electrode part on the back surface are removed to expose the base, while the exposure amount is adjusted in the recess of the present invention. By doing so, it is removed by development from the surface of the solder resist layer to a certain depth, but the solder resist layer at a depth higher than that can be left.

Further, when a solder resist having no photosensitivity is used, means for removing an interlayer insulating layer at a desired site using a laser (CO ₂ , UV, excimer) can be used. Since the parts other than the electrodes need to be covered with the solder resist, the solder resist layer is removed at a certain depth, but in order to leave the solder resist layer deeper than that, the laser output is lowered. By irradiating, a recess can be formed at a desired portion of the solder resist layer.

  As described above, on the surface where the semiconductor chip is mounted, an opening for exposing the electrode to the portion of the FC pad electrode to be soldered to the terminal electrode of the array arrangement of the semiconductor chip, and the printed wiring on the other surface A solder resist layer is formed on the portion of the electrode to be soldered with the terminal electrode in the array arrangement on the substrate, except for the opening that exposes the electrode, and the semiconductor chip of the solder resist layer is mounted On the surface, an FCBGA substrate having a lattice-shaped recess can be manufactured.

  By using an FCBGA substrate with a grid-like recess on the surface on which this semiconductor chip is mounted, even when high-temperature processing such as solder reflow is performed, warping is suppressed and defects such as poor solder connection It is possible to provide an FCBGA substrate capable of suppressing the occurrence of the above.

DESCRIPTION OF SYMBOLS 1 ... FCBGA board 2 ... Semiconductor chip 3 ... Solder resist layer 4 ... Wiring board 5 ... Recess 6 ... Printed wiring board 7 ... Solder ball

Claims (4)

The surface on which the semiconductor chip is mounted has FC pad electrodes that are solder-bonded to the arrayed terminal electrodes of the semiconductor chip, and the other surface has solder-bonded electrodes to the arrayed terminal electrodes of the printed wiring board FCBGA board,
Other than the FC pad electrode of the FCBGA substrate and the solder joint electrode on the back side, it is covered with a solder resist layer.
An FCBGA substrate characterized in that a grid-like recess is formed on the surface of the solder resist layer on the FC pad electrode side. It is a manufacturing method of the FCBGA board according to claim 1,
Forming a conductor wiring layer on the front and back surfaces of the core substrate; and
Forming an interlayer insulating layer on the conductor wiring layers on the front and back surfaces and forming a via hole; and
A step of producing a wiring board having a conductor wiring layer formed on the outermost surface by repeating step A and step B;
Forming a solder resist layer on the outermost conductor wiring layer;
Removing the solder resist layer at a desired position on the surface on which the semiconductor chip is mounted, exposing the FC pad electrode, and forming a lattice-shaped recess;
And a step of exposing a solder bonding electrode to the printed wiring board by removing the solder resist layer at a desired position of the solder resist layer formed on the other surface. Manufacturing method.   The step of exposing the FC pad electrode and forming the lattice-shaped recess by removing the solder resist layer at a desired position on the surface on which the semiconductor chip is mounted uses a photosensitive solder resist. The method for producing an FCBGA substrate according to claim 2, wherein the step of exposing and developing with a halftone mask.   The step of exposing the FC pad electrode and forming the lattice-shaped recess by removing the solder resist layer at a desired position on the surface on which the semiconductor chip is mounted comprises irradiating a solder with a laser beam. The method for producing an FCBGA substrate according to claim 2, wherein the method is a step of removing the resist layer.