JP2018160588A - Electronic device and method for manufacturing electronic device - Google Patents

Abstract

An object of the present invention is to improve heat dissipation of an electronic device mounted with high density. An electronic device includes a stacked body in which a second electronic component is stacked on a first electronic component and electrically connected by a plurality of joints, and at least the joints An insulating layer covering the surface; a coating covering the insulating layer; and a metal material filled between the plurality of joints covered by the coating. Have [Selection] Figure 1

Description

  The present invention relates to an electronic device and a method for manufacturing the electronic device.

  Due to the miniaturization of portable terminals, the spread of high performance computing (HPC), and the enhancement of server functions, there is still a high demand for miniaturization of semiconductor elements and electronic components. Transistor miniaturization has reached a physical limit, and further enhancement in performance cannot be expected. Therefore, highly integrated technologies such as 2.5D mounting and 3D mounting are attracting attention. In 2.5-dimensional mounting and 3-dimensional mounting, LSIs (Large-Scale Integration) are connected in the stacking direction without interposing a package substrate to increase the mounting density. With the increase in heat density due to high integration, there is a concern about deterioration of heat dissipation performance, and improvement of heat dissipation performance due to structures and materials is desired.

There is an increasing demand for high heat resistance and downsizing for in-vehicle components, but it is difficult to secure a space for arranging an external cooling mechanism such as a fan and a cooling plate. Therefore, a technique of cooling by filling an underfill material between terminals is used to improve heat dissipation.
As a configuration for reducing the thermal resistance between the semiconductor element and the circuit board, an arrangement is known in which an insulating film is formed on the bump surface and a gap between the semiconductor element and the circuit board is filled with a conductive material without gaps (for example, patents) Reference 1).

JP-A-8-115947

  As electronic parts such as integrated circuit chips are miniaturized, the arrangement pitch of micro bumps for electrically joining stacked electronic parts or between electronic parts and a relay substrate is shifting to a narrow pitch of 40 μm or less. When a heat-dissipating underfill material is filled between electrode terminals with a fine pitch, there is a limit to improving the thermal conductivity by increasing the diameter and amount of the filler. Even when a known method of filling a conductive material between a semiconductor element and a circuit board is applied to a high-density mounting electronic device, it is difficult to fill the gap with no gap in the conductive material.

  An object of the present invention is to improve heat dissipation of an electronic device mounted with high density.

In one aspect, the electronic device includes a stacked body in which the second electronic component is stacked on the first electronic component and is electrically connected at a plurality of joints.
An insulating layer covering at least the surface of the joint;
A coating covering the insulating layer;
A metal material filled between the plurality of joints covered with the coating;
Have

  As one aspect, the heat dissipation of an electronic device mounted with high density can be improved.

It is the schematic of the electronic device of embodiment. It is a manufacturing process figure of the electronic device of a 1st embodiment. It is a manufacturing process figure of an electronic device. It is a manufacturing process figure of an electronic device. It is a manufacturing process figure of an electronic device. It is a schematic diagram of the sample used for evaluation of thermal conductivity improvement. It is a figure which shows the evaluation result of the heat conductivity improvement by the filling material of embodiment. It is a manufacturing process figure of the electronic device of a 2nd embodiment. It is a manufacturing process figure of the electronic device of a 2nd embodiment. It is a manufacturing process figure of the electronic device of a 2nd embodiment. It is a manufacturing process figure of the electronic device of a 2nd embodiment.

  Generally, as an underfill material having a cooling function, a material in which particles having high thermal conductivity are dispersed in an insulating resin material is used. However, even if the amount of thermally conductive filler is increased, it is difficult to expect a great improvement in thermal conductivity because it is basically based on a resin material. Therefore, in the embodiment, a metal material having a higher thermal conductivity than the underfill material is used as the filler.

  FIG. 1 is a schematic diagram of an electronic device 1 according to an embodiment. The electronic device 1 is a semiconductor package in which a plurality of electronic components are stacked in a direction perpendicular to a substrate, for example. In the example of FIG. 1, a first electronic component 10 and a second electronic component 20 are stacked in this order on the package substrate 3. The second electronic component 20 is, for example, an integrated circuit chip. When the first electronic component 10 is an integrated circuit chip, it is three-dimensionally mounted, and when it is a relay substrate such as an interposer, it is 2.5-dimensionally mounted.

  The package substrate 3 and the first electronic component 10 are electrically connected by a joint 6 having a relatively large pitch and diameter. The second electronic component 20 and the first electronic component 10 are electrically connected by a joint portion 15 having a smaller pitch and diameter than the joint portion 6. The joint portion 6 is, for example, a C4 (Control Collapse Chip Connection) bump using a solder ball, and is arranged at a pitch of 100 to 150 μm. The joint 15 is, for example, a micro bump having a configuration in which the metal pillar 13 of the connection terminal of the first electronic component 10 and the metal terminal 23 of the connection terminal of the second electronic component 20 are joined by the solder layer 31. It arrange | positions with the pitch of 40-80 micrometers. For higher-density mounting, the pitch of the joints 6 may be 60 to 100 μm, and the pitch of the joints 15 may be 10 to 40 μm.

  The outer surface of the joint 15 and the outer surface of the joint 6 are covered with an insulating layer 41. The insulating layer 41 continuously covers the entire surface of the laminate including the first electronic component 10, the second electronic component 20, and the package substrate 3, but at least each of the bonding portions 15 and the bonding portions 6. It is only necessary that each of them can be electrically insulated.

  A metal material 45 is filled between the package substrate 3 and the first electronic component 10 and between the first electronic component 10 and the second electronic component 20. Metals have a much higher thermal conductivity and higher heat dissipation effect than resins. Since each of the joint portions 15 and each of the joint portions 6 is covered with the insulating material 41, even if the metal material 45 is filled, a short circuit is prevented.

  As the insulating layer 41, any insulating material can be used as long as it is a material that can cover the outer periphery of the junction 15 with a fine pitch at a temperature that does not adversely affect the operating characteristics of the electronic component 10 or 20. As the insulating layer 41, a thin film of insulating resin may be used. For example, a thin film having a thickness of 80 nm to 150 nm may be formed using a polymer material such as polyimide resin, acrylic resin, epoxy resin, or polycarbonate resin. When the thickness is 80 nm or less, there may be a case where reliable insulation with respect to the metal material 45 cannot be realized. When the thickness exceeds 200 nm, the interval between the adjacent joint portions 16 becomes narrower, and smooth filling of the metal material 45 becomes difficult.

  The surface of the insulating layer 41 is preferably covered with a coating 42 made of a material having wettability to the metal material 45. In order to fill the metal material 45 in the narrow space existing between the joint portions 6 and between the joint portions 15, the wettability with respect to the metal material 45 is increased on the surfaces of the joint portions 15 and 6. It is desirable to promote the introduction of

  The metal material 45 is not limited as long as it can be filled into the space between the joints 15 at a temperature that does not adversely affect the operating characteristics of the electronic component 10 or 20. As an example, gold (Au), silver (Ag), palladium (Pd), tin (Sn), indium (In), nickel (Ni), copper (Cu), bismuth (Bi), alloys thereof, or these A solder material containing the material can be used as the filling metal material 45. When a metal paste material is used as the metal material 45, it is desirable to use a material having a melting point lower than that of the metal material used for the joint 6 and the joint 15.

  As the coating 42, any material can be used as long as the material has wettability to the metal material 45. When the above-described solder material is used as the metal material 45, nickel (Ni), Au (gold), palladium (Pd), or the like can be used for the coating 42. A metal having a higher stress relaxation effect than the coating 42 may be used for the metal material 45.

  By filling the inside of the laminated structure of the electronic device 1 with a metal material, heat dissipation can be improved as compared with a conventional resin-based underfill. Further, by covering the outer surfaces of the joints 6 and 15 with a coating 42 for improving wettability, the gap between the joints 15 arranged at a fine pitch and the gap between the joints 6 are filled with a metal material. can do.

  From the viewpoint of improving the heat dissipation by the metal material 45, the insulating layer 41 and the coating 42 may be formed at least on the outer periphery of the joint 15 and the joint 6. However, in the case where the insulating layer 41 and the coating 42 are each easily formed in one step, the insulating layer 41 and the coating 42 continuously form the entire surface of the laminate from the outer surfaces of the bonding portion 15 and the bonding portion 6. It may be covered. The entire side surface and bottom surface of the package substrate 3, the side surfaces of the first electronic component 10 and the second electronic component 20, and the upper surface of the second electronic component 20 are covered with an insulating layer 41 and a coating 42. When the entire laminate is covered with the metal coating 42 via the insulating layer 41, heat can be radiated from the back surface and the top surface of the electronic device 1, so that the heat radiation effect is good. Such a configuration of the electronic device 1 is advantageous for an electronic device arranged in a narrow space such as an on-vehicle electronic device.

<First Embodiment>
2A to 2D are manufacturing process diagrams of the electronic device 1 according to the first embodiment. In FIG. 2A, a stacked body 5 in which a first electronic component 10 and a second electronic component 20 are stacked in this order on a package substrate 3 is assembled. In this example, the first electronic component 10 and the second electronic component 20 are silicon chips having a planar size of 10 mm × 10 mm. The laminate 5 is assembled in the following procedure. The Sn-Ag alloy C4 bump formed on the first main surface of the first electronic component 10 is temporarily mounted on the electrode pad formed on the surface of the package substrate 3 by the flip-chip method. The second main surface opposite to the first main surface of the first electronic component is provided with electrode terminals having a narrower pitch than the C4 bump, and the second electronic surface is connected to the electrode terminals of the first electronic component. The electrode terminals of the component 20 are temporarily mounted after being aligned by a flip chip method. Solder bumps are provided at the tips of the electrode terminals of the first electronic component 10 and the second electronic component 20.

  More specifically, the first electronic component 10 is formed with a plurality of electrode terminals in which Sn-Ag solder bumps are formed at the tips of the Cu pillars 13 (see FIG. 1). The diameter of the Sn—Ag solder bump is 40 μm and the bump pitch is 80 μm. The second electronic component 20 is formed with a plurality of electrode terminals having Sn-Ag solder bumps formed at the tips of the Cu pillars 23 (see FIG. 1). The diameter of the Sn—Ag solder bump is 40 μm and the bump pitch is 80 μm. The first electronic component 10 and the second electronic component 20 each have 15129 electrode terminals. The corresponding electrode terminals of the first electronic component 10 and the second electronic component 20 are aligned to face each other, and the solder bumps of the second electronic component 20 are temporarily placed on the solder bumps of the first electronic component 10. Mount.

  By reflow heating the assembly in which the first electronic component 10 and the second electronic component 20 are temporarily mounted on the package substrate 3, the solder material for the C4 bump and the solder material for the electrode terminal are melted to join the joint portion. 6 and the joint 15 are formed. The final height of the bonded portion 15 after the reflow bonding is 45 μm. The first electronic component 10 and the second electronic component are joined by the joint portion 15, and the package substrate 3 and the first electronic component 10 are joined by the joint portion 6, whereby the laminate 5 is obtained.

  The finely divided mist-like polyimide is electrostatically sprayed on the surface of the conduction part including the joint part 6 and the joint part 15. A first polarity voltage is applied to the nozzle of the electrostatic sprayer, and the mist 34 sprayed from the nozzle is charged to a polarity opposite to the first polarity. A voltage having the first polarity is applied to the stacked body 5.

  In FIG. 2B, the electrostatic sprayed polyimide mist 34 adheres to the surface of the laminate 5, and the solvent volatilizes on the surface of the laminate 5 to leave the target polyimide fine particles on the surface of the laminate 5. As a result, an insulating layer 41 having an average thickness of 100 nm is formed on the surface of the multilayer body 5 including the joint portion 6 and the joint portion 15. As a material of the insulating layer 41, in addition to polyimide, a resin material such as an epoxy resin or a silicone resin or a ceramic material may be used as a mist. The insulating layer 41 formed by electrostatic spraying may become thinner as it goes from the outer periphery of the electrode array of the joint 15 and the joint 6 toward the center. An insulating layer 41 covering the portion 16 can be formed.

  In FIG. 2C, a film 42 having a thickness of 200 nm is formed on the surface of the insulating layer 41 by vapor deposition. Deposition is preferably performed at a low temperature of 300 ° C. or lower. The coating 42 is, for example, an Au film. The vaporized Au molecules enter the gap between the joint 15 and the joint 6 covered with the insulating layer 41 and adhere to the surface of the laminate 5 including the joints 6 and 15 and aggregate. By vapor deposition, the coating 42 can be formed on the entire surface of the laminate including the surface of the joint 15 in one step.

  In FIG. 2D, Sn—Ag solder paste is injected from the side surface of the stacked body 5. Sn-Ag solder has high wettability to the Au coating 42 and is introduced between the joints 6 and 15. Thereby, the electronic device 1 is produced.

  FIG. 3 is a schematic diagram of a sample 100 used for evaluation of improvement in thermal conductivity. The sample 100 is manufactured by the above-described process, and is obtained by stacking silicon chips 10 s and 20 s having a planar size of 10 mm × 10 mm and electrically joining them at the joint 15. The pitch of the junctions 15 is 80 μm, and the number of terminals is 15129. The joint 15 is obtained by joining a Cu pillar 13 having a height h1 and a Cu pillar 23 having a height h2 by a SnAg solder layer 31 having a height h3. h1 is 15 μm, h2 is 15 μm, and h3 is 15 μm. Different types of fillers are arranged in the gaps between the joints 15 of the sample 100, and the thermal conductivity [W / m · K] of a layer including the joints 15 (referred to as “bump layer”) is measured.

  FIG. 4 shows the evaluation results when different filler materials are applied to the sample 100 and when no filler is used. When no filling material is used, an air layer exists between the stacked silicon chip 10s and the silicon chip 20s. The thermal conductivity of the air layer is 0.0257 W / m · K. As a comparative example, when a high heat dissipation underfill is used, the thermal conductivity of the underfill material is 1.5 W / m · K. When the Sn—Ag solder material is filled as the metal material as in the example, the thermal conductivity of the Sn—Ag solder material is 62.8 W / m · K.

  Comparing the thermal conductivity of the entire bump layer including the joint 15, the thermal conductivity when filled with Sn—Ag solder is improved to about three times as compared with when filled with a high heat dissipation underfill material. Yes. The same effect can be achieved even when a metal material having high thermal conductivity and low rigidity such as an aluminum alloy or a zinc alloy is used instead of the Sn—Ag alloy.

Second Embodiment
5A to 5D are manufacturing process diagrams of the electronic device 2 according to the second embodiment. In FIG. 5A, a stacked body 5 in which a first electronic component 10 and a second electronic component 20 are stacked in this order on a package substrate 3 is assembled. As in the first embodiment, the first electronic component 10 and the second electronic component 20 are silicon chips having a planar size of 10 mm × 10 mm. The first electronic component 10 and the second electronic component 20 are joined by a plurality of joints 15, and the second electronic component and the package substrate 3 are joined by a plurality of joints 6. In a state after the laminate 5 is completed, the diameter of the joint 15 is 40 μm, the height is 45 μm, the pitch is 80 μm, and the number of terminals is 15129.

  The laminate 5 is immersed in the epoxy resin 8 in the tank 7. The epoxy resin 8 is a low viscosity epoxy resin for dip coating.

  In FIG. 5B, the laminated body 5 is pulled up from the tank 7 and dried, whereby the insulating layer 61 having an average thickness of 100 nm is formed on the surface of the conducting part including the joining part 15 and the joining part 6. The film thickness of the insulating layer 61 can be controlled by controlling the viscosity and temperature of the epoxy resin 8 in the tank 7 and the pulling speed of the laminated body 5. As the material of the insulating layer 61, other insulating resin materials such as polyimide resin and silicone resin may be used in addition to the epoxy resin. Further, the insulating layer 61 may be formed by dip coating using an aqueous solution of an inorganic ceramic material such as titanium oxide in addition to the polymer material. By dip coating, the insulating layer 61 can be formed on the entire surface of the laminate including the surface of the joint 15 in a single step.

  In FIG. 5C, a palladium (Pd) film 62 having a thickness of 200 nm is formed on the surface of the insulating layer 61 by electroless plating. As the coating 62, a thin film such as Au or Ni other than Pd may be formed by electroless plating. The plating solution wraps around the gap between the joints 15 to form the coating 62. Thereby, the film 62 can be formed on the insulating layer 61 in a single step.

  In FIG. 5D, Sn—Bi solder is discharged from the side surface of the multilayer body 5 using the dispenser 9, and the interior of the multilayer body 5 is filled with the metal material 45. The Sn—Bi solder has high wettability with respect to the Pd film 62, and the Sn—Bi solder discharged by pressurization is introduced between the joint portions 6 and between the joint portions 15. Thereby, the electronic device 2 is produced.

  The electronic device 1 according to the first embodiment and the electronic device 2 according to the second embodiment have a heat dissipation effect due to the metal material 45 filled in the stacked body, and the junction 15 is miniaturized to reduce the current density. The cooling function can be exerted even in a configuration in which the increase is increased. The electronic device 1 or 2 is particularly effective when it is disposed in a narrow space and an external fan or cooling plate cannot be used. For example, the present invention can be applied to smartphones, vehicle-mounted electronic devices, wearable electronic devices, and the like.

  In the above-described embodiment, the 2.5-dimensional mounting or the three-dimensional mounting has been described as an example. However, the present invention is applied to any electronic device having a stacked body of the first electronic component 10 and the second electronic component 20. The Further, the present invention can also be applied to a package in which one or more second electronic components 20 are arranged in the surface on the main surface of the first electronic component 10.

  The film formation and filling method used in each step of the first embodiment and each step of the second embodiment may be arbitrarily combined. For example, after the insulating layer 41 is formed by electrostatic spraying, the film 62 may be formed by electroless plating, or after the insulating layer 61 is formed by dip coating, the film 42 may be formed by low temperature vapor deposition. In addition to the dispenser 9, the metal material 45 can be filled into the laminated body 5 by any means using pressure, such as a nozzle or an injector.

The following notes are presented for the above explanation.
(Appendix 1)
In an electronic device having a laminate in which a second electronic component is laminated on the first electronic component and electrically connected at a plurality of joints,
An insulating layer covering at least the surface of the joint;
A coating covering the insulating layer;
A metal material filled between the plurality of joints covered with the coating;
An electronic device comprising:
(Appendix 2)
The electronic device according to appendix 1, wherein the insulating layer continuously covers a surface of the joint and a surface of the laminated body.
(Appendix 3)
The electronic device according to appendix 1 or 2, wherein the coating film has wettability to the metal material.
(Appendix 4)
The first electronic component is bonded to the substrate at a plurality of second bonding portions arranged at a different pitch from the bonding portion on the surface opposite to the bonding portion,
The surface of the second joint is covered with the insulating layer and the coating,
The electronic device according to any one of appendices 1 to 3, wherein the metal material is filled between the plurality of second joint portions.
(Appendix 5)
The joint connects the first metal pillar connected to the first electronic component, the second metal pillar connected to the second electronic component, and the first metal pillar and the second metal pillar. 5. The electronic device according to any one of appendices 1 to 4, wherein the electronic device is a microbump having a solder layer.
(Appendix 6)
The electronic device according to any one of appendices 1 to 5, wherein the metal material is a solder material having a melting point equal to or lower than a melting point of solder used for the joint portion.
(Appendix 7)
The electronic device according to any one of appendices 1 to 6, wherein the coating is selected from Au, Pd, or Ni.
(Appendix 8)
A second electronic component is stacked on the first electronic component, and a laminate in which the first electronic component and the second electronic component are electrically connected at a plurality of joints is manufactured.
Forming an insulating layer covering at least the surface of the joint,
Forming a coating on the insulating layer;
Filling a metal material between the plurality of joints covered with the coating;
A method for manufacturing an electronic device.
(Appendix 9)
9. The method of manufacturing an electronic device according to appendix 8, wherein the insulating layer is formed so as to continuously cover a surface of the joint portion and a surface of the laminated body.
(Appendix 10)
10. The method of manufacturing an electronic device according to appendix 8 or 9, wherein the insulating layer is formed by electrostatic spraying or dip coating.
(Appendix 11)
The method for manufacturing an electronic device according to any one of appendices 8 to 10, wherein the coating is formed by low-temperature vapor deposition or electroless plating.
(Appendix 12)
The method for manufacturing an electronic device according to any one of appendices 8 to 11, wherein the coating is formed of a material having wettability to the metal material.
(Appendix 13)
The method for manufacturing an electronic device according to any one of appendices 8 to 12, wherein the coating is formed of a material selected from Au, Pd, or Ni.
(Appendix 14)
14. The method for manufacturing an electronic device according to any one of appendices 8 to 13, wherein the metal material is filled between the plurality of joints by pressurization.
(Appendix 15)
15. The method of manufacturing an electronic device according to any one of appendices 8 to 14, wherein a solder material having a melting point lower than that of the material of the joint portion is selected as the metal material.
(Appendix 16)
The first electronic component is laminated on a substrate on a surface opposite to the joint, and joined by a plurality of second joints arranged at a different pitch from the joint to produce the laminate.
Forming the insulating layer and the coating in this order on the surface of the second joint;
The method for manufacturing an electronic device according to any one of appendices 8 to 15, wherein a space between the plurality of second joint portions is filled with the metal material.

1, 2 Electronic device 3 Package substrate 6 Junction (second junction)
10 1st electronic component 15 Joining part (1st joining part)
20 Second electronic component 41, 61 Insulating layer 42, 62 Film 45 Metal material

Claims (7)

In an electronic device having a laminate in which a second electronic component is laminated on the first electronic component and electrically connected at a plurality of joints,
An insulating layer covering at least the surface of the joint;
A coating covering the insulating layer;
A metal material filled between the plurality of joints covered with the coating;
An electronic device comprising:   The electronic device according to claim 1, wherein the insulating layer continuously covers a surface of the bonding portion and a surface of the stacked body.   The electronic device according to claim 1, wherein the coating film has wettability with respect to the metal material. The first electronic component is bonded to the substrate at a plurality of second bonding portions arranged at a different pitch from the bonding portion on the surface opposite to the bonding portion,
The surface of the second joint is covered with the insulating layer and the coating,
The electronic device according to claim 1, wherein the metal material is filled between the plurality of second joint portions. A second electronic component is stacked on the first electronic component, and a laminate in which the first electronic component and the second electronic component are electrically connected at a plurality of joints is manufactured.
Forming an insulating layer covering at least the surface of the joint,
Forming a coating on the insulating layer;
Filling a metal material between the plurality of joints covered with the coating;
A method for manufacturing an electronic device.   The method for manufacturing an electronic device according to claim 5, wherein the insulating layer is formed so as to continuously cover a surface of the bonding portion and a surface of the stacked body.   The method for manufacturing an electronic device according to claim 5, wherein the insulating layer is formed by electrostatic spraying or dip coating.

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