JP2018152754A - D / A conversion circuit, circuit device, oscillator, electronic device, and moving object - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a D-A inversion circuit, circuit arrangement, oscillator, electronic apparatus and mobile body, capable of achieving high precision of D-A inversion by reducing a non-linearity error caused by an offset voltage.SOLUTION: A D-A inversion circuit 80 includes: a voltage formation circuit 30 for forming a plurality of voltages; a voltage selection circuit 40 which executes voltage selection from a plurality of voltages on the basis of input data and outputs a Kth voltage VK and an Lth voltage VL; a first operational amplifier OPA input with the Kth voltage VK; and a second operational amplifier OPB input with the Lth voltage VL. The first and the second operational amplifiers OPA, OPB are chopper type operational amplifiers.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a D / A conversion circuit, a circuit device, an oscillator, an electronic device, a moving object, and the like.

  Conventionally, in a circuit device for an oscillator, a circuit device of a display driver for a liquid crystal panel, a D / A conversion circuit that converts digital data into an analog voltage is used. For example, in a circuit device for a temperature compensated oscillator, a D / A conversion circuit is used for D / A conversion of frequency control data. Alternatively, a D / A conversion circuit is used in an A / D conversion circuit that A / D converts the temperature detection voltage. As a conventional technique of such a D / A conversion circuit, there is a technique disclosed in Patent Document 1, for example. Patent Document 1 discloses a digitally controlled oscillator using a resistance voltage dividing D / A converter circuit.

Japanese Patent Laid-Open No. 2006-134738

  In the prior art of Patent Document 1, as shown in FIG. 4, the first and second voltages generated by the first D / A converter are input to the first and second operational amplifiers, The output of the second operational amplifier is input to the second D / A converter. In such a configuration, it has been found that the non-linearity error of the D / A conversion increases due to the difference in the offset voltage between the first and second operational amplifiers. For this reason, the precision of D / A conversion fell and the subject that a highly accurate temperature compensation etc. were not realizable occurred.

  SUMMARY An advantage of some aspects of the invention is to solve at least a part of the problems described above, and the invention can be implemented as the following forms or modes.

  According to one embodiment of the present invention, a voltage generation circuit that generates a plurality of voltages and voltage selection from the plurality of voltages based on input data are performed, and a Kth voltage and an Lth voltage (K and L are the selection voltages) are selected. A voltage selection circuit that outputs an integer of 1 or more different from each other, a first operational amplifier to which the Kth voltage is input, and a second operational amplifier to which the Lth voltage is input, The first and second operational amplifiers relate to a D / A conversion circuit which is a chopper type operational amplifier.

  In one embodiment of the present invention, D / A conversion is realized by generating a plurality of voltages and selecting a voltage from the plurality of voltages based on input data. Then, the Kth and Lth voltages are output as selection voltages and input to the chopper type first and second operational amplifiers. Thus, if the chopper type first and second operational amplifiers are used as the operational amplifiers to which the Kth and Lth voltages are input, the first and second output voltages of the first and second operational amplifiers are used. As a result, it is possible to output a voltage subjected to offset cancellation and low frequency band noise reduction. Therefore, it is possible to realize a D / A conversion circuit or the like that can reduce the non-linearity error caused by the offset voltage and improve the D / A conversion accuracy.

  According to another aspect of the present invention, the first D / A converter includes a first D / A converter configured by the voltage generation circuit and the voltage selection circuit, and the first D / A converter includes the first D / A converter. The voltage selection circuit of the A / A converter performs voltage selection based on the higher-order bits of the input data, and the second D / A converter uses the first output voltage of the first operational amplifier and the first output voltage. A second voltage generation circuit configured to generate a plurality of voltages obtained by dividing a voltage between the second output voltages of the second operational amplifier; and the second voltage generation circuit based on lower-order bits of the input data. And a second voltage selection circuit for selecting a voltage from the plurality of voltages.

  In this way, a plurality of voltages are generated by the second voltage generation circuit using the first and second output voltages that have been subjected to offset cancellation, low frequency band noise reduction, and the like. It becomes possible to perform voltage selection based on.

  Further, according to one embodiment of the present invention, it may include a third operational amplifier to which an output voltage of the second voltage selection circuit is input, and the third operational amplifier may be a chopper type operational amplifier.

  This makes it possible to cancel the offset, reduce the low frequency band noise, and the like for the output voltage of the second voltage selection circuit.

  In one embodiment of the present invention, the voltage generation circuit includes a first ladder resistor circuit that resistance-divides the high-potential-side power supply voltage and the low-potential-side power supply voltage, the high-potential-side power supply voltage, and the low-potential-side power supply voltage. The first operational amplifier includes a voltage selected from a plurality of divided voltages of the first ladder resistor circuit as the Kth voltage. And a voltage selected from a plurality of divided voltages of the second ladder resistor circuit may be output to the second operational amplifier as the Lth voltage.

  In this way, the supply of the Kth voltage to the first operational amplifier and the supply of the Lth voltage to the second operational amplifier are performed using separate first and second ladder resistor circuits. It becomes possible to do.

  In one embodiment of the present invention, when the sth divided voltage (s is an integer of 1 or more) of the first ladder resistor circuit is supplied to the first operational amplifier as the Kth voltage. , A t-th divided voltage (t is an integer equal to or greater than 1) of the second ladder resistor circuit is supplied to the second operational amplifier as the L-th voltage, and the s + 1th of the first ladder resistor circuit Is supplied to the first operational amplifier as the Kth voltage, the tth divided voltage of the second ladder resistor circuit is the second voltage as the Lth voltage. And the second ladder resistor circuit is supplied when the s + 1-th divided voltage of the first ladder resistor circuit is supplied to the first operational amplifier as the Kth voltage. T + 1-th divided voltage is the second voltage as the L-th voltage. It may be supplied to the operational amplifier.

  In this way, it is possible to prevent a situation in which the connection destinations of both the first and second operational amplifiers change at the same time and the D / A conversion characteristics deteriorate.

  According to another aspect of the present invention, a processing circuit that performs temperature compensation processing of the oscillation frequency based on the temperature detection data and outputs the frequency control data of the oscillation frequency, and a D / D of the input data that is the frequency control data. Using the D / A conversion circuit described above having the filter circuit that performs A conversion and smoothes the voltage obtained by D / A conversion, the output voltage of the D / A conversion circuit, and the vibrator And an oscillation circuit that generates an oscillation signal having the oscillation frequency set by the frequency control data.

  In this way, it becomes possible to perform D / A conversion of the frequency control data using a D / A conversion circuit with a small non-linearity error, so that the performance of the circuit device can be improved.

  In another aspect of the present invention, the D / A converter circuit receives the frequency control data of i = n + m bits from the processing circuit, and based on the m-bit data of the frequency control data, the frequency control data A modulation circuit that modulates the n-bit data may be included.

  In this way, a D / A conversion with a high resolution of i = (n + m) bits can be performed using a D / A converter with an n-bit resolution only by providing a modulation circuit and a filter circuit in the D / A conversion circuit. A circuit can be realized.

  In one embodiment of the present invention, when the modulation frequency of the modulation circuit is fm and the chopping frequency of the chopper type operational amplifier is fp, fm = fp may be satisfied.

  In this way, the modulation filter circuit and the chopper filter circuit can be shared, and the circuit device can be reduced in size.

  According to another aspect of the present invention, a processing circuit that performs temperature compensation processing of the oscillation frequency based on the temperature detection data and outputs the frequency control data of the oscillation frequency, and D / A of the input data that is the frequency control data It is set by the frequency control data using a D / A conversion circuit having a filter circuit for performing conversion and smoothing a voltage obtained by D / A conversion, and an output voltage and a vibrator of the filter circuit. An oscillation circuit for generating an oscillation signal of the oscillation frequency, wherein the D / A conversion circuit receives the frequency control data of i = n + m bits from the chopper type operational amplifier and the processing circuit, and A modulation circuit for modulating n-bit data of the frequency control data based on m-bit data of the control data, and a modulation frequency of the modulation circuit And fm, the chopping frequency of the chopper type operational amplifier when the fp, relate to the circuit device is fm = fp.

  According to another aspect of the present invention, only by providing a modulation circuit or a filter circuit in the D / A conversion circuit, a high resolution of i = (n + m) bits can be obtained while using a D / A converter with n bit resolution. A D / A conversion circuit can be realized. The modulation filter circuit and the chopper filter circuit can be shared, and the circuit device can be reduced in scale.

  In another aspect of the present invention, the modulation frequency of the modulation circuit is fm, and the frequency of the modulation pattern having the lowest frequency among the modulation patterns of the modulation circuit is fmmin = fm / N (N is an integer of 2 or more). When the cut-off frequency of the filter circuit is fc, fc <fmmin may be satisfied.

  In this way, the ripple voltage due to the modulation pattern having the lowest frequency is attenuated by the filter circuit, so that the accuracy of D / A conversion can be improved.

  In another aspect of the present invention, fc <fmmin <fp may be satisfied when the chopping frequency of the chopper type operational amplifier is fp.

  In this way, the ripple voltage due to modulation and the ripple voltage due to chopping can be appropriately attenuated using the filter circuit.

  Another aspect of the invention relates to an oscillator including the circuit device described above and the vibrator.

  Another aspect of the invention relates to an electronic device including the D / A conversion circuit described above.

  Another aspect of the present invention relates to a moving body including the D / A conversion circuit described above.

2 is a configuration example of a D / A conversion circuit according to the present embodiment. 3 is a detailed configuration example of a D / A conversion circuit according to the present embodiment. 2 shows a configuration example of an upper D / A converter and a lower D / A converter. Explanatory drawing of the offset voltage of an operational amplifier. A configuration example of a chopper type operational amplifier. Explanatory drawing about the non-linearity error of D / A conversion. Explanatory drawing about the modulation and demodulation of a chopper. A configuration example of a rail-to-rail operational amplifier. A configuration example of a rail-to-rail chopper type operational amplifier. 2 shows a configuration example of a voltage selection circuit. 3 shows a detailed configuration example of a voltage selection circuit. Explanatory drawing of the voltage selection method in the structure which provided two ladder resistance circuits in the voltage generation circuit. Explanatory drawing of the voltage selection method in the structure which provided two ladder resistance circuits in the voltage generation circuit. Explanatory drawing of the voltage selection method in the structure which provided two ladder resistance circuits in the voltage generation circuit. 1 is a configuration example of a circuit device according to the present embodiment. Explanatory drawing of PWM modulation. Explanatory drawing of PWM modulation. Explanatory drawing of PWM modulation. Explanatory drawing of the modulation pattern of PWM. An example of the frequency characteristics of a low-pass filter. Operation | movement explanatory drawing when a chopping mode is OFF. Explanatory drawing when the chopping mode is on. 2 is a configuration example of an oscillator according to the present embodiment. 1 is a configuration example of an electronic apparatus according to an embodiment. The structural example of the moving body of this embodiment.

  Hereinafter, preferred embodiments of the present invention will be described in detail. The present embodiment described below does not unduly limit the contents of the present invention described in the claims, and all the configurations described in the present embodiment are indispensable as means for solving the present invention. Not necessarily.

1. Configuration of D / A Conversion Circuit FIG. 1 shows a configuration example of the D / A conversion circuit 80 of the present embodiment. The D / A conversion circuit 80 includes a voltage generation circuit 30, a voltage selection circuit 40, operational amplifiers OPA and OPB (first and second operational amplifiers). The D / A conversion circuit 80 is not limited to the configuration shown in FIG. 1, and various modifications such as omitting some of the components or adding other components are possible.

  The voltage generation circuit 30 generates a plurality of voltages V1 to Vj (j is an integer of 2 or more). The voltage generation circuit 30 has a plurality of resistors connected in series between power sources (between VDDA and VSS), and outputs voltages divided by these resistors as V1 to Vj. These voltages V1 to Vj are voltages obtained by equally dividing the voltage between the power sources, for example. However, the voltages V1 to Vj may be gradation voltages for image display on a display panel such as a liquid crystal panel. In this case, the voltages V1 to Vj are voltages corresponding to the gradation characteristics of the display panel. become.

  The voltage selection circuit 40 performs voltage selection from the voltages V1 to Vj based on the input data DI, and the voltage VK (Kth voltage) and the voltage VL (Lth voltage; K and L are different from each other) as selection voltages. (Integer above) is output. Specifically, the voltage selection circuit 40 outputs voltages corresponding to the input data DI from among the voltages V1 to Vj as voltages VK and VL based on the voltages V1 to Vj from the voltage generation circuit 30 and the input data DI. To do. For example, the voltage selection circuit 40 has a decoder that decodes the input data DI, and the voltage selection circuit 40 selects a voltage corresponding to the input data DI from the voltages V1 to Vj based on a control signal from the decoder. The voltages VK and VL are selected and output. The voltages VK and VL are adjacent voltages (divided voltages) among the voltages V1 to Vj, for example. For example, when VK is one of the adjacent voltages V1 to Vj, VL is the other voltage. For example, when VK is one of the adjacent voltages V1 and V2, VL is the other voltage, for example, VK = V1 and VL = V2. When VK is one of the adjacent voltages V3 and V4, VL is the other voltage, for example, VK = V3 and VL = V4. The same applies to the other voltages V5 to Vj.

  The operational amplifier OPA (first operational amplifier) receives the voltage VK from the voltage selection circuit 40 and outputs the voltage VX. The operational amplifier OPA has, for example, a voltage follower connection, and outputs a voltage corresponding to the voltage VK as VX. The operational amplifier OPB (second operational amplifier) receives the voltage VL from the voltage selection circuit 40 and outputs the voltage VY. The operational amplifier OPB has, for example, a voltage follower connection, and outputs a voltage corresponding to the voltage VL as VY.

  In this embodiment, the operational amplifiers OPA and OPB are chopper type operational amplifiers. A chopper type operational amplifier (chopper stabilized amplifier) is an operational amplifier that performs a chopping operation at a chopping frequency fp. In a chopper type operational amplifier, a DC input signal is converted into an AC input signal by chopping modulation and input to the operational amplifier. The AC output signal of the operational amplifier is smoothed by the filter circuit and returned to the DC signal.

  Specifically, the first and second input signals are modulated by the modulation chopper circuit and input to the amplification stage (input differential stage) of the operational amplifier. In the operational amplifier OPA of FIG. 1, the first input signal is a signal of the voltage VK, and the second input signal is a feedback signal from the output terminal of the OPA. In the operational amplifier OPB, the first input signal is a signal of voltage VL, and the second input signal is a feedback signal from the output terminal of OPB. The first and second output signals of the amplification stage are demodulated by a demodulating chopper circuit and input to the output stage (output differential stage). From the output stage, for example, single-ended signals (VX, VY) Signal) is output. In this way, the offset voltage can be canceled by using chopper type operational amplifiers as the operational amplifiers OPA and OPB. As a result, the non-linearity error of the D / A conversion can be reduced as will be described later with reference to FIG. Further, low frequency band noise such as flicker noise can be reduced.

  For example, in FIG. 1, when the offset voltage of the operational amplifier OPA has one polarity of positive polarity and negative polarity, and the offset voltage of the operational amplifier OPB has the other polarity, the non-linearity error of D / A conversion is large. turn into. In this regard, in FIG. 1, both operational amplifiers OPA and OPB are chopper-type operational amplifiers. Accordingly, it is possible to suppress the deterioration of the non-linearity error of the D / A conversion caused by the offset voltage of the operational amplifier.

  FIG. 2 shows a detailed configuration example of the D / A conversion circuit 80 of the present embodiment. The D / A conversion circuit 80 in FIG. 2 includes D / A converters DACA and DACB (first and second D / A converters). The DACA includes the voltage generation circuit 30 and the voltage selection circuit 40 as described with reference to FIG. The DACB includes a voltage generation circuit 46 and a voltage selection circuit 48.

  For example, the voltage selection circuit 40 of DACA performs voltage selection based on the higher-order bits of the input data DI. Specifically, the voltage selection circuit 40 determines the upper q bits from among the voltages V1 to Vj based on the voltages V1 to Vj from the voltage generation circuit 30 and the upper q bits (q is an integer of 1 or more) of the input data DI. Are output as VK and VL.

  The voltage generation circuit 46 (second voltage generation circuit) of the DACB generates a plurality of voltages V1 to Vl obtained by dividing the voltage between the output voltages VX and VY (first and second output voltages) of the operational amplifiers OPA and OPB. Generate. For example, the voltage generation circuit 46 has a plurality of resistors connected in series between the node of the output voltage VX of the operational amplifier OPA and the node of the output voltage VY of the operational amplifier OPB, and the voltage is divided by the plurality of resistors. Are output as voltages V1 to Vl. These voltages V1 to Vl are voltages obtained by equally dividing the voltage between VX and VY, for example.

  The DACB voltage selection circuit 48 (second voltage selection circuit) performs voltage selection based on the lower-order bits of the input data DI. Specifically, the voltage selection circuit 48 determines the lower p bits from the voltages V1 to Vl based on the voltages V1 to Vl from the voltage generation circuit 46 and the lower p bits (p is an integer of 1 or more) of the input data DI. Is output as a VM.

  The operational amplifier OPC (third operational amplifier) receives the voltage VM from the voltage selection circuit 48 of the DACB and outputs the voltage VDA. The voltage VDA signal is input to the filter circuit 120, and the voltage VQ signal smoothed by the filter circuit 120 is output from the filter circuit 120. A low-pass filter can be used as the filter circuit 120.

  For example, the operational amplifier OPC is connected to a voltage follower, and outputs a voltage corresponding to the voltage VM as VDA. As this operational amplifier OPC, for example, a chopper type operational amplifier can be used. For example, a chopper type operational amplifier that performs a chopping operation at a chopping frequency fp can be used. However, a normal operational amplifier that is not a chopper type may be used as the operational amplifier OPC.

  The circuit for generating the voltage VDA of the D / A conversion result from the voltages VX and VY in FIG. 1 is a circuit (D / A converter) configured by the voltage generation circuit 46, the voltage selection circuit 48, etc. as shown in FIG. It is not limited to. For example, the voltage VDA may be generated by various D / A conversion methods such as a charge redistribution method using a capacitor instead of resistance division.

  FIG. 3 shows a detailed configuration example of DACA and DACB. As shown in FIG. 3, the D / A conversion circuit 80 includes a higher-order D / A converter DACA, a lower-order D / A converter DACB, and operational amplifiers OPA, OPB, OPC (voltage follower connection). Operational amplifier).

  The higher-order DACA includes a plurality of resistors RA1 to RAN connected in series between the VDDA node and the VSS node. Further, the higher-order DACA is based on a plurality of switch elements SA1 to SAN + 1 whose one ends are connected to the voltage dividing nodes by the resistors RA1 to RAN and upper q-bit data of the input data DI, and the switch elements SA1 to SAN + 1. It includes a decoder 104 (switch control circuit) that generates a switch control signal for turning on / off the signal.

  The higher-order DACA outputs one divided voltage to the non-inverting input terminal of the operational amplifier OPA among the divided voltages at both ends of the resistor specified by the upper q-bit data among the plurality of resistors RA1 to RAN, and the other. Are output to the non-inverting input terminal of the operational amplifier OPB. As a result, the one voltage is impedance-converted by the operational amplifier OPA connected as a voltage follower, and is supplied to the lower DACB as the voltage VX. The other voltage is impedance-converted by an operational amplifier OPB connected as a voltage follower, and is supplied as a voltage VY to the lower DACB.

  For example, when the resistor RA1 is specified by upper q-bit data, among the divided voltages at both ends of the resistor RA1, the divided voltage Vj on the high potential side is set as the voltage VK via the switch element SA1 that is turned on. It is supplied to the operational amplifier OPA. Further, the divided voltage Vj−1 on the low potential side is supplied to the operational amplifier OPB as the voltage VL through the switch element SA2 that is turned on. When the resistor RA2 is specified by the upper q-bit data, the divided voltage Vj-2 on the low potential side among the divided voltages at both ends of the resistor RA2 is supplied to the voltage VK via the switch element SA3 that is turned on. To the operational amplifier OPA. Further, the divided voltage Vj−1 on the high potential side is supplied to the operational amplifier OPB as the voltage VL through the switch element SA2 that is turned on. The operational amplifiers OPA and OPB supply voltages VX and VY obtained by impedance conversion of the voltages VK and VL supplied from the upper DACA to the lower DACB.

  The lower-order DACB includes a plurality of resistors RB1 to RBM connected in series between a node of voltage VX and a node of voltage VY. The lower-order DACB is composed of a plurality of switch elements SB1 to SBM + 1 whose one ends are connected to the voltage dividing nodes by the resistors RB1 to RBM, and the switch elements SB1 to SBM + 1 based on the lower p-bit data of the input data DI. Includes a decoder 106 (switch control circuit) for generating a switch control signal for turning on / off.

  Then, the lower-side DACB uses one divided voltage selected by the lower p-bit data among the plurality of divided voltages by the resistors RB1 to RBM as the selected voltage VM and passes through the switched switch element. And output to the non-inverting input terminal of the operational amplifier OPC connected to the voltage follower. The operational amplifier OPC outputs a voltage obtained by impedance conversion of the voltage VM as VDA.

  Next, details of the chopper type operational amplifier will be described. FIG. 4 shows an example in which a normal operational amplifier OP is connected to a voltage follower. In such a connection configuration, the offset voltage VF is generated due to a slight characteristic difference (threshold voltage mismatch) between the transistors of the differential pair of the operational amplifier OP. That is, by connecting the operational amplifier OP to the voltage follower, the output voltage VOUT is ideally equal to the input voltage VIN due to virtual grounding, but if the offset voltage VF exists, VOUT = VIN + VF. Thus, when VOUT = VIN + VF, as will be described later with reference to FIG. 6, the non-linearity error of the D / A conversion increases, and is applied to an oscillator such as a digitally controlled temperature compensated crystal oscillator (DTCXO). In such a case, problems such as frequency hopping occur.

  FIG. 5 shows a configuration example of a chopper type operational amplifier OPH. The operational amplifier OPH is connected to a voltage follower. Specifically, the signal of the input voltage VIN is input to the node N1 on the non-inverting input terminal side of the operational amplifier OPH, and the signal of the output voltage VOUT is fed back and input to the node N2 on the inverting input terminal side. A modulation chopper circuit ASW1 (modulation circuit, switch circuit) is provided between the nodes N1 and N2 and the nodes N3 and N4. The modulation chopper circuit ASW1 is composed of an analog switch element. The node N1 is connected to the node N3 and the node N2 is connected to the node N4. The node N1 is connected to the node N4 and the node N2 is connected to the node N2. The second state connected to the node N3 is switched at a cycle of the chopping frequency fp. This switching is performed based on a modulation control signal having a chopping frequency fp. The nodes N3 and N4 are connected to the non-inverting input terminal and the inverting input terminal of the amplification stage DFC (amplification circuit, input differential stage) of the operational amplifier OPH. In the amplification stage DFC, an offset voltage VF is generated as in FIG.

  A demodulation chopper circuit ASW2 (demodulation circuit, switch circuit) is provided between the amplification stage DFC and the output stage QSC (output circuit) of the operational amplifier OPH. Specifically, a demodulation chopper is provided between a node N5 of the non-inverting output terminal of the amplification stage DFC, a node N6 of the inverting output terminal, a node N7 of the non-inverting input terminal of the output stage QSC, and a node N8 of the inverting input terminal. A circuit ASW2 is provided. The demodulating chopper circuit ASW2 is composed of an analog switch element, and the first state in which the node N5 is connected to the node N7 and the node N6 is connected to the node N8, the node N5 is connected to the node N8, and the node N6 is connected to the node N6. The second state connected to the node N7 is switched at a cycle of the chopping frequency fp. This switching is performed based on a demodulation control signal having a chopping frequency fp. The signal of the output voltage VOUT of the output stage QSC is fed back to the node N2 on the inverting input terminal side of the modulation chopper circuit ASW1. The signal of the output voltage VOUT of the output stage QSC is input to the low pass filter LPF, and the signal of the voltage LPFOUT smoothed by the low pass filter LPF is output. As shown in FIG. 5, the smoothing of the low-pass filter LPF results in LPFOUT = VIN, and the voltage LPFOUT from which the offset voltage VF has been removed (reduced) is output. By performing offset cancellation for removing the offset voltage VF in this way, it is possible to reduce non-linearity errors in D / A conversion.

  FIG. 6 shows an example of the D / A conversion characteristic indicating the relationship between the input data (input code) and the voltage of the D / A conversion result. A1 in FIG. 6 is an ideal D / A conversion characteristic when the offset voltages of the operational amplifiers OPA and OPB in FIGS. 1 to 3 are VF = 0V. A2 is a D / A conversion characteristic when the offset voltages VF of the operational amplifiers OPA and OPB are both the voltage VOF (for example, VOF = + 5.5 mV). On the other hand, A3 is the D / A conversion characteristic when the offset voltage of the operational amplifier OPA is VF = 0V and the offset voltage of the operational amplifier OPB is VF = VOF (for example, VOF = + 5.5 mV). When the offset voltages VF of the operational amplifiers OPA and OPB are the same as shown by A1 and A2, the non-linearity error of the D / A conversion characteristic is small, but the operational amplifiers OPA and OPB have a non-linearity error as shown by A3. If the offset voltage VF is a different voltage, the non-linearity error is worsened. For example, it is not desirable that the non-linearity error is 1 LSB or more. If the normal operational amplifier OP as shown in FIG. 4 is used as the operational amplifiers OPA and OPB shown in FIGS. 1 to 3, the nonlinearity error may be greatly deteriorated as shown by A3 in FIG. May occur.

  In this respect, in this embodiment, chopper type operational amplifiers OPH as shown in FIG. 5 are used as the operational amplifiers OPA and OPB in FIGS. Therefore, the offset voltage VF of the operational amplifiers OPA and OPB can be made substantially close to 0 V, and it is possible to prevent the occurrence of a large non-linearity error as indicated by A3 in FIG.

  FIG. 7 is a frequency characteristic diagram for explaining chopper modulation and demodulation. E1 in FIG. 7 is an input signal (desired signal) of the D / A conversion circuit 80, and its frequency component exists in the baseband band (low frequency band). This input signal (VIN) is frequency-converted (modulated) into a high frequency band as indicated by E2 by modulation by the chopper circuit ASW1. That is, the frequency is converted to a frequency corresponding to the harmonic of the chopping frequency fp. On the other hand, E3 is noise (unnecessary signal) existing in a low frequency band such as flicker noise. Thermal noise is present uniformly from the low frequency band to the high frequency band.

  The frequency component of the input signal frequency-converted to the high frequency band as indicated by E2 is returned to the baseband band as indicated by E4 by demodulation by the chopper circuit ASW2. On the other hand, low frequency band noise such as flicker noise is frequency converted to a high frequency band as indicated by E5. Accordingly, for example, by performing low-pass filter processing using a low-pass filter LPF having a cutoff frequency fc, low-frequency band noise such as flicker noise can be reduced while allowing an input signal to pass.

  Thus, in this embodiment, as the operational amplifier of the D / A conversion circuit 80, a chopper type operational amplifier (OPA, OPB, OPC) is used. By doing so, the non-linearity error of the D / A conversion described with reference to FIG. 6 can be reduced. Further, as described with reference to FIG. 7, low frequency band noise such as flicker noise can be reduced, and the accuracy of D / A conversion can be improved.

  For example, in the normal operational amplifier OP of FIG. 4, the offset voltage VF can be reduced by increasing the area of the differential pair of transistors. However, in order to reduce the offset voltage VF to ½, the area of the transistor needs to be increased by about four times, for example, and the circuit area greatly increases. In this regard, if the chopper type operational amplifier OPH of FIG. 5 is used, the offset voltage VF can be almost 0 V only by providing the chopper circuits ASW1, ASW2, etc., and the increase in circuit area is minimized. There is an advantage that offset cancellation (auto zero) can be realized. Further, as will be described later, by sharing a low-pass filter used in PWM modulation as a low-pass filter for chopper, an increase in circuit area can be further suppressed.

  8 and 9 show detailed configuration examples of the operational amplifier. These are rail-to-rail operational amplifiers, FIG. 8 is a structural example of a rail-to-rail operational amplifier, and FIG. 9 is a structural example of a rail-to-rail operational amplifier.

  The chopper type operational amplifier shown in FIG. 9 is provided with modulation and demodulation chopper circuits ASW1 and ASW2 including a plurality of switch elements (MOS transistors) in addition to the configuration shown in FIG. That is, the chopper type operational amplifier of FIG. 9 includes an amplification stage DFC constituted by transistors TC1 to TC18, an output stage QSC constituted by transistors TC19 and TC20, and chopper circuits ASW1 and ASW2. Note that BP, BN, BP2, and BN2 are bias voltages.

  The modulation chopper circuit ASW1 includes switch elements S1 and S2. The switch element S1 is provided between the node of the input signal NIN and the node NA1 of the gates of the transistors TC2 and TC4 and the node NA2 of the gates of the transistors TC3 and TC5. The switch element S2 is provided between the node of the input signal PIN and the nodes NA1 and NA2. The input signals NIN and PIN constitute a differential signal and correspond to the signals of VOUT and VIN in the example of FIG. The transistors TC2 and TC3 and the transistors TC4 and TC5 each constitute a differential pair of transistors. Then, with these switch elements S1 and S2, in the first state (φ1), the input signal NIN is input to the gates of the transistors TC2 and TC4, and the input signal PIN is input to the gates of the transistors TC3 and TC5. . In the second state (φ2), the input signal NIN is input to the gates of the transistors TC3 and TC5, and the input signal PIN is input to the gates of the transistors TC2 and TC4. This realizes chopper modulation.

  The demodulating chopper circuit ASW2 includes switch elements S3, S4, S5, and S6. The switch element S3 is provided between the nodes NA3 and NA4 of the gates of the transistors TC7 and TC8. The switch element S4 is provided between the nodes NA6 and NA7 of the gates of the transistors TC17 and TC18. The switch element S5 is provided between the nodes NA4 and NA5 and the node NA9 of the gate of the transistor TC19 of the output stage QSC. The switch element S6 is provided between the nodes NA7 and NA8 and the node NA10 of the gate of the transistor TC20 of the output stage QSC.

  By these switch elements S3 to S6, in the first state (φ1), the node NA3 is connected to the node NA4, the node NA6 is connected to the node NA7, the node NA5 is connected to the node NA9, and the node NA8 is Connected to the node NA10. In the second state (φ2), the node NA3 is connected to the node NA5, the node NA6 is connected to the node NA8, the node NA4 is connected to the node NA9, and the node NA7 is connected to the node NA10. As a result, demodulation of the chopper is realized.

  According to the configuration of FIG. 9, the modulation and demodulation of the chopper can be realized while realizing the rail-to-rail operation of the operational amplifier. By performing the rail-to-rail operation, the dead zone of the output can be eliminated. For example, even when the power supply voltage is low, the output amplitude of the operational amplifier can be maximized, and the performance of the D / A converter circuit Can be improved.

2. Voltage Selection Circuit, Voltage Generation Circuit FIG. 10 shows a configuration example of the voltage selection circuit 40. The voltage selection circuit 40 includes a decoder 42. The decoder 42 decodes the input data DI and outputs control signals SC1 to SCi (i is an integer of 2 or more). Input data DI is data to be subjected to D / A conversion. The control signals SC <b> 1 to SCi are signals that turn on or off the transistors that constitute the selector of the voltage selection circuit 40. Since the decoding process performed by the decoder 42 is a known process, detailed description thereof is omitted.

  The voltage selection circuit 40 includes a plurality of selector blocks BLA, BLB, BLC,. Each selector block of BLA... BLF is composed of one or a plurality of selectors, and each selector is composed of, for example, a MOS transistor. Then, the output of the selector included in the preceding selector block is input to the selector included in the succeeding selector block. Specifically, the output of the selector included in the selector block BLA at the first stage (previous stage) is input to the selector block BLB at the second stage (rear stage). The output of the selector included in the second (previous) selector block BLB is input to the third (follower) selector block BLC. The selector block BLF at the final stage receives the selector output of the selector block at the previous stage, performs voltage selection, and outputs the D / A conversion voltage VDQ (VK, VL).

  Voltages V1 to Vj from the voltage generation circuit 30 are input to the first selector block BLA. Then, the selector block BLF at the final stage outputs the D / A conversion voltage VDQ. Specifically, the voltage selection circuit 40 performs voltage selection by the so-called tournament method by the selector blocks BLA to BLF, and outputs the final D / A conversion voltage VDQ. In the tournament method, each selector of the selector block selects a voltage based on a control signal, so that one voltage is selected from a plurality of voltages input to the selector, and thereby the voltage of the block corresponding to the selector is sequentially changed. It is a voltage selection method that is selected by winning the rest.

  Each of the plurality of stages of selector blocks BLA to BLF includes a plurality of transistors (for example, P-type transistors and N-type transistors). Specifically, each selector block BLA to BLF has one or a plurality of selectors, and the selectors are configured by a plurality of transistors.

  In this embodiment, among the plurality of transistors constituting the selector block (at least the final selector block), the second transistor far from the power supply node (VDDA, VSS) is the first transistor on the side close to the power supply node. The threshold voltage is set lower than that of the transistor. Specifically, among the plurality of transistors constituting the selector block (BLA to BLF), the second P-type transistor far from the high potential side power supply node (VDDA) is on the side closer to the high potential side power supply node. The threshold voltage is set lower than that of the first P-type transistor. The second N-type transistor far from the low-potential-side power supply node (VSS) has a lower threshold voltage than the threshold voltage of the first N-type transistor close to the low-potential-side power supply node. Is set to Here, the transistor far from the power supply node means that the transistor input voltage (input voltage range) is far from the power supply voltage (the difference from the power supply voltage is larger) than the transistor closer to the power supply node. Transistor). When the input voltage of the first transistor closer to the power supply node is VIN1, the second transistor far from the power supply node is input voltage VIN2, and the power supply voltage is VPWR, for example, | VPWR-VIN2 |> | VPWR-VIN1 | is established.

  In this way, for example, even when the power supply voltage is lowered to reduce power consumption, the second transistor far from the power supply node is set to a low threshold voltage, so that the voltage Appropriate voltage selection by the selection circuit 40 can be realized. Accordingly, it is possible to output the D / A conversion voltage VDQ by selecting an appropriate voltage while reducing the power consumption.

  FIG. 11 is an explanatory diagram of a detailed configuration example of the voltage selection circuit 40. TA13 to TA20 in FIG. 11 are transistors constituting the selector of the selector block BLA in FIG. 10, and TB7 to TB10 are transistors constituting the selector of the selector block BLB. TF4 and TF5 are transistors constituting the selector of the selector block BLF. The first stage transistors TA13 to TA20 are exclusively turned on or off by the control signal SC1. For example, in FIG. 11, odd-numbered transistors TA13, TA15, TA17, and TA19 are on, and even-numbered transistors TA14, TA16, TA18, and TA20 are off. The second stage transistors TB7 to TB10 are exclusively turned on or off by the control signal SC2. For example, in FIG. 11, the odd-numbered transistors TB7 and TB9 are turned off, and the even-numbered transistors TB8 and TB10 are turned on. In the final stage transistors TF4 and TF5, TF4 is on and TF5 is off. Thus, in FIG. 11, the voltage V15 is selected and the D / A conversion voltage VDQ = V15 is output.

  In this case, for example, the off-leakage current IL also flows in the transistor TF5 that is turned off. This off-leakage current IL flows from the VDDA through the resistance of the ladder resistor circuit 33 (R23 to R19, etc.) and the on-state transistors TA19 and TB10, and then flows into the off-state transistor TF5 and into the on-state transistor TF4. The off-leakage current IL flows into the node of the voltage V15 through the transistors TB8 and TA15 in the on state, and flows to the VSS side through the resistances (R14 to R1) of the ladder resistor circuit 33.

  When the ladder resistor circuit 33 is used in this way, there is an off-leakage current IL, and thus it is necessary to reduce the adverse effect of the off-leakage current IL. For this purpose, in the present embodiment, as shown in FIG. 12, the voltage generation circuit 30 is provided with two ladder resistor circuits 31 and 32.

  Specifically, the voltage generation circuit 30 includes a ladder resistor circuit 31 (first ladder resistor circuit) that resistance-divides the power supply voltage VDDA on the high potential side and the power supply voltage VSS on the low potential side, the power supply voltage VDDA, and the power supply voltage VSS. Includes a ladder resistor circuit 32 (second ladder resistor circuit). Ladder resistor circuit 31 includes resistors RDN, RD0 to RD255, and RDP connected in series between VDDA and VSS. The ladder resistor circuit 32 includes resistors REN, RE0 to RE255, and REP connected in series between VDDA and VSS. When the resistance values of the resistors RD0 to RD255 and RE0 to RE255 are R, the resistance values of the resistors RDN and REN are 24R, and the resistance values of the resistors RDP and REP are 31R.

  Then, the voltage selection circuit 40 outputs the voltage selected from the plurality of divided voltages of the ladder resistor circuit 31 to the operational amplifier OPA as the voltage VK, and converts the voltage selected from the plurality of divided voltages of the ladder resistor circuit 32 to the voltage It is output to the operational amplifier OPB as VL. The voltages VX and VY obtained by impedance conversion of the voltages VK and VL by the operational amplifiers OPA and OPB are supplied to the ladder resistor circuit 47 of the DACB voltage generation circuit 46 of FIG. The voltage selection circuit 48 performs voltage selection based on the lower p bits of the input data DI, and the selected voltage VM is impedance-converted by the operational amplifier OPC and output as the voltage VDA.

  In FIG. 12, a divided voltage V0 (sth divided voltage Vs in a broad sense, where s is an integer equal to or greater than 1) of the ladder resistor circuit 31 is supplied as a voltage VK to the operational amplifier OPA. In this case, the divided voltage V1 (t-th divided voltage Vt in a broad sense, t is an integer equal to or greater than 1) of the ladder resistor circuit 32 is supplied to the operational amplifier OPB as the voltage VL.

  On the other hand, in FIG. 13, the divided voltage V2 (s + 1-th divided voltage Vs + 1 in a broad sense) of the ladder resistor circuit 31 is supplied to the operational amplifier OPA as the voltage VK. In this case, the voltage V1 (t-th divided voltage Vt) of the ladder resistor circuit 32 is supplied to the operational amplifier OPB as the voltage VL. That is, in FIGS. 12 and 13, the connection destination of the operational amplifier OPB remains the node of the divided voltage V1 (Vt), and the connection destination of the operational amplifier OPA is changed from the node of the divided voltage V0 (Vs) to the divided voltage V1 (Vs + 1). ) Node.

  In FIG. 14, the divided voltage V2 (s + 1-th divided voltage Vs + 1) of the ladder resistor circuit 31 is supplied to the operational amplifier OPA as the voltage VK. In this case, the divided voltage V3 (t + 1th divided voltage Vt + 1 in a broad sense) of the ladder resistor circuit 32 is supplied to the operational amplifier OPB as the voltage VL. That is, in FIGS. 13 and 14, the connection destination of the operational amplifier OPA remains the node of the divided voltage V2 (Vs + 1), and the connection destination of the operational amplifier OPB is changed from the node of the divided voltage V1 (Vt) to the divided voltage V3 (Vt + 1). ) Node.

  In this way, for example, at the switching point of D / A conversion (input code) shown in A4 and A5 in FIG. 6, the situation where the voltage changes discontinuously and the D / A conversion characteristics deteriorate is suppressed. become able to. That is, A4 and A5 in FIG. 6 are points at which the D / A conversion voltage is switched with respect to the input data (input code). In the configuration in which the ladder resistor circuit to which the operational amplifiers OPA and OPB are connected is only one ladder resistor circuit as shown in FIG. 3, the connection destinations of both the operational amplifiers OPA and OPB are simultaneously changed at the switching point. If this happens, the voltage will change discontinuously. For example, as described with reference to FIG. 11, the off-leak current IL flows through the transistor of the voltage selection circuit 40. Accordingly, when the connection destinations of the operational amplifiers OPA and OPB are switched, the off-leakage current IL flows to the operational amplifiers OPA and OPB, so that the voltages at the input nodes of the operational amplifiers OPA and OPB change. In a configuration in which only one ladder resistor circuit is connected to the operational amplifiers OPA and OPB, if the connection destinations of both the operational amplifiers OPA and OPB change simultaneously, the input nodes of the operational amplifiers OPA and OPB are changed. Both the voltages change, and a situation occurs in which the voltage changes discontinuously at the switching points A4 and A5 in FIG.

  12, 13, and 14, the connection destination of the operational amplifier OPA is the ladder resistor circuit 31, and the connection destination of the operational amplifier OPB is the ladder resistor circuit 32, and each operational amplifier has a different ladder resistor circuit. It is configured to be connected. 12 and 13, for example, the connection destination of the operational amplifier OPB remains unchanged at the node of the divided voltage V1 of the ladder resistor circuit 32, and only the connection destination of the operational amplifier OPA is divided by the ladder resistor circuit 31. The node is switched from the node of the voltage V0 to the node of the divided voltage V2. As described above, the connection destination of the operational amplifier OPB remains unchanged at the node of the divided voltage V1 of the ladder resistor circuit 32. Therefore, even if the off-leak current IL as shown in FIG. 11 occurs, the input voltage of the operational amplifier OPB is It does not change. Therefore, it is possible to suppress the voltage from changing discontinuously at the D / A conversion switching points as indicated by A4 and A5 in FIG.

  Similarly, in FIG. 13 and FIG. 14, the connection destination of the operational amplifier OPA remains unchanged at the node of the divided voltage V2 of the ladder resistor circuit 31, and only the connection destination of the operational amplifier OPB is connected to the ladder resistor circuit 32. The node of the divided voltage V1 is switched to the node of the divided voltage V3. In this way, the connection destination of the operational amplifier OPA remains unchanged at the node of the divided voltage V2 of the ladder resistor circuit 31. Therefore, even if the off-leak current IL as shown in FIG. 11 occurs, the input voltage of the operational amplifier OPA is It does not change. Therefore, it is possible to suppress the voltage from changing discontinuously at the D / A conversion switching points as indicated by A4 and A5 in FIG. Accordingly, it is possible to prevent the deterioration of the D / A conversion characteristic that occurs in the configuration in which only one ladder resistor circuit is provided for the operational amplifiers OPA and OPB.

3. Circuit Device FIG. 15 shows a configuration example of a circuit device 500 having the D / A conversion circuit 80 of the present embodiment. For example, the circuit device 500 in FIG. 15 is a circuit device (semiconductor chip) that realizes a digital oscillator such as DTCXO or OCXO. The circuit device 500 includes an A / D conversion circuit 20, a processing circuit 50, and an oscillation signal generation circuit 140. The circuit device 500 can include the temperature sensor 10 and the buffer circuit 160. Note that the circuit device 500 is not limited to the configuration shown in FIG. 15, and some of the components (for example, a temperature sensor, a buffer circuit, an A / D conversion circuit, etc.) are omitted, or other components are added. Various modifications are possible.

  The vibrator XTAL is a piezoelectric vibrator such as a quartz vibrator. The vibrator XTAL is a vibrator built in a thermostat crystal oscillator (OCXO) having a thermostat, or a vibrator built in a temperature compensated crystal oscillator (TCXO) not having a thermostat. The resonator XTAL may be a resonator (an electromechanical resonator or an electrical resonance circuit). As the vibrator XTAL, a piezoelectric vibrator, a SAW (Surface Acoustic Wave) resonator, a MEMS (Micro Electro Mechanical Systems) vibrator as a silicon vibrator formed using a silicon substrate, or the like can be employed.

  The temperature sensor 10 outputs a temperature detection voltage VTD. Specifically, a temperature-dependent voltage that changes according to the temperature of the environment (circuit device) is output as the temperature detection voltage VTD.

  The A / D conversion circuit 20 performs A / D conversion of the temperature detection voltage VTD from the temperature sensor 10 and outputs temperature detection data DTD. For example, digital temperature detection data DTD (A / D result data) corresponding to the A / D conversion result of the temperature detection voltage VTD is output. As the A / D conversion method of the A / D conversion circuit 20, for example, a successive approximation method, a method similar to the successive approximation method, or the like can be adopted. In addition, as an A / D conversion method, a counting type, a parallel comparison type, a serial parallel type, or the like may be employed. The D / A conversion circuit 80 of this embodiment can also be used for this A / D conversion circuit 20.

  A processing circuit 50 (DSP: digital signal processing circuit) performs various signal processing. For example, the processing circuit 50 (temperature compensation unit) performs temperature compensation processing of the oscillation frequency (frequency of the oscillation signal) based on the temperature detection data DTD. Then, frequency control data DDS of the oscillation frequency is output. Specifically, the processing circuit 50 has a temperature change based on temperature detection data DTD (temperature-dependent data) that changes according to the temperature, coefficient data for temperature compensation processing (coefficient data of an approximate function), and the like. In this case, temperature compensation processing is performed to keep the oscillation frequency constant. The processing circuit 50 may be realized by an ASIC circuit such as a gate array, or may be realized by a processor and a program operating on the processor.

  The oscillation signal generation circuit 140 generates an oscillation signal SSC. For example, the oscillation signal generation circuit 140 generates an oscillation signal SSC having an oscillation frequency set by the frequency control data DDS, using the frequency control data DDS from the processing circuit 50 and the vibrator XTAL. As an example, the oscillation signal generation circuit 140 oscillates the vibrator XTAL at the oscillation frequency set by the frequency control data DDS, and generates the oscillation signal SSC.

  The oscillation signal generation circuit 140 may be a circuit that generates the oscillation signal SSC by a direct digital synthesizer method. For example, the oscillation signal SSC having the oscillation frequency set by the frequency control data DDS may be digitally generated using the oscillation signal of the vibrator XTAL (an oscillation source having a fixed oscillation frequency) as a reference signal.

  The oscillation signal generation circuit 140 includes a D / A conversion circuit 80 and an oscillation circuit 150. The D / A conversion circuit 80 performs D / A conversion of the frequency control data DDS (output data of the processing circuit) from the processing circuit 50. The frequency control data DDS input to the D / A conversion circuit 80 is frequency control data (frequency control code) after the temperature compensation processing by the processing circuit 50.

  The oscillation circuit 150 generates an oscillation signal SSC using the output voltage VQ of the D / A conversion circuit 80 and the vibrator XTAL. For example, the oscillation circuit 150 generates the oscillation signal SSC by oscillating the vibrator XTAL. Specifically, the oscillation circuit 150 oscillates the vibrator XTAL at an oscillation frequency in which the output voltage VQ of the D / A conversion circuit 80 is a frequency control voltage (oscillation control voltage). In this case, the oscillation circuit 150 can include a variable capacitor (such as a varicap) whose capacitance value changes according to the frequency control voltage.

  The buffer circuit 160 buffers the oscillation signal SSC generated by the oscillation signal generation circuit 140 (oscillation circuit 150), and outputs a buffered signal SQ. The signal SQ is, for example, a clipped sine wave signal or a rectangular wave signal.

  As shown in FIG. 15, the D / A conversion circuit 80 includes a modulation circuit 90, a D / A converter 100, and a filter circuit 120. The D / A converter 100 is a circuit configured by, for example, the D / A converters DACA and DACB, operational amplifiers OPA, OPB, and OPC in FIG.

  The modulation circuit 90 receives i = (n + m) -bit frequency control data DDS from the processing circuit 50 (i, n, m are integers of 1 or more). As an example, i = 20, n = 16, and m = 4. The modulation circuit 90 modulates n-bit (eg, 16 bits) data of the frequency control data DDS based on m-bit (eg, 4 bits) data of the frequency control data DDS. Specifically, the modulation circuit 90 performs PWM modulation of the frequency control data DDS. The modulation method of the modulation circuit 90 is not limited to PWM modulation (pulse width modulation), and may be pulse modulation such as PDM modulation (pulse density modulation), or may be a modulation method other than pulse modulation. . For example, bit expansion (bit expansion from n bits to i bits) may be realized by performing m-bit dither processing (dithering processing) on n-bit data of the frequency control data DDS.

  The D / A converter 100 performs D / A conversion of the n-bit data modulated by the modulation circuit 90. For example, D / A conversion of n = 16 bit data is performed.

  The filter circuit 120 smoothes the voltage VDA obtained by D / A conversion. For example, low-pass filter processing is performed to smooth the voltage VDA. By providing such a filter circuit 120, for example, PWM demodulation of a PWM-modulated signal becomes possible. As the filter circuit 120, for example, a passive filter using a passive element such as a resistor or a capacitor can be employed. However, it is also possible to use an active filter such as SCF as the filter circuit 120.

  For example, a digital oscillator such as DTCXO has a problem that a communication error or the like occurs in a communication device in which the oscillator is incorporated due to frequency drift of the oscillation frequency. For example, a digital oscillator performs A / D conversion on a temperature detection voltage from a temperature sensor, performs temperature compensation processing of frequency control data based on the obtained temperature detection data, and generates an oscillation signal based on the frequency control data. Generate. In this case, it has been found that if the value of the frequency control data changes greatly due to temperature change, this causes a problem of frequency hopping. When such frequency hopping occurs, if a GPS-related communication device is taken as an example, problems such as the GPS being unlocked will occur.

  In order to suppress the occurrence of such a communication error due to frequency hopping and improve the frequency accuracy, it is necessary to increase the resolution of the D / A conversion circuit 80 as much as possible.

  However, it is difficult to realize high-resolution D / A conversion such as i = 20 bits, for example, using only the D / A converter 100 such as a resistor string type. If the output noise (output voltage noise) of the D / A conversion circuit 80 is large, it becomes difficult to improve the frequency accuracy due to the output noise.

  Therefore, in FIG. 15, a modulation circuit 90 is provided in the D / A conversion circuit 80. Further, the processing circuit 50 outputs i = m + n bits of frequency control data DDS having a larger number of bits than n bits (for example, 16 bits) which is the resolution of the D / A converter 100. Since the processing circuit 50 performs a floating point calculation or the like to realize digital signal processing such as temperature compensation processing, for example, i = has a larger number of bits than such n bits (for example, n = 16 bits). It is easy to output m + n-bit frequency control data DDS.

  The modulation circuit 90 modulates n-bit data (i.e., PWM modulation) of i = m + n based on m-bit data of i = m + n, and converts the modulated n-bit data DM to D / A converter 100 to output. Then, the D / A converter 100 performs D / A conversion of the data DM, and the filter circuit 120 performs smoothing processing of the obtained voltage VDA, so that high resolution such as i = m + n bits (for example, 20 bits) is achieved. D / A conversion can be realized.

  According to this configuration, for example, a resistor string type with little output noise can be adopted as the D / A converter 100, so that the output noise of the D / A conversion circuit 80 can be reduced and the deterioration of the frequency accuracy can be easily suppressed. . For example, noise is generated by modulation in the modulation circuit 90, but the noise can also be sufficiently attenuated by setting the cutoff frequency of the filter circuit 120, and deterioration of frequency accuracy caused by the noise can be suppressed. .

  The resolution of the D / A conversion circuit 80 is not limited to i = 20 bits, and may be a resolution higher than 20 bits or a lower resolution. Also, the number of bits of modulation of the modulation circuit 90 is not limited to m = 4 bits, and may be larger than 4 bits (for example, m = 8 bits) or smaller.

  In FIG. 15, the fact that the processing circuit 50 that performs digital signal processing such as temperature compensation processing is provided upstream of the D / A conversion circuit 80 is effectively utilized. That is, the processing circuit 50 executes digital signal processing such as temperature compensation processing with high accuracy by, for example, floating point arithmetic. Therefore, for example, if the lower-order bits of the mantissa part of the floating-point arithmetic result are treated as valid data and converted into binary data, the frequency control data DDS with a high bit number such as i = m + n = 20 bits is also obtained. Can output easily. In FIG. 15, paying attention to this point, this high bit number i = m + n-bit frequency control data DDS is supplied to the D / A conversion circuit 80, and the m-bit modulation circuit 90 and the n-bit D / D Using the A converter 100, a high-resolution D / A conversion such as i = m + n bits has been successfully realized.

  Thus, by making the resolution of the D / A conversion circuit 80 high, occurrence of the above-described frequency hopping can be suppressed. As a result, it is possible to suppress the occurrence of communication errors caused by frequency hopping.

  In addition to the problem of frequency hopping, a digital oscillator such as DTCXO or OCXO requires very high frequency accuracy with respect to the oscillation frequency. For example, in the TDD (Time Division Duplex) method, data is transmitted and received in time division using the same frequency in the upward and downward directions, and a guard time is set between time slots assigned to each device. For this reason, in order to implement | achieve appropriate communication, it is necessary to perform time synchronization in each apparatus, and exact time-measurement of an absolute time is requested | required. For example, when a holdover occurs in which a reference signal (a GPS signal or a signal via the Internet) disappears or becomes abnormal, it is necessary for the oscillator side to accurately time the absolute time without the reference signal. For this reason, an oscillator used for such devices (GPS-related devices, base stations, etc.) is required to have a very high oscillation frequency accuracy.

  In this regard, according to the configuration of the circuit device 500 of FIG. 15, the D / A conversion circuit 80 is simply provided with the modulation circuit 90 and the filter circuit 120. The / A conversion circuit 80 can be realized, and the high resolution can be realized by increasing the resolution as described above. The increase in the chip size and the power consumption of the circuit device 500 due to the provision of the modulation circuit 90 and the filter circuit 120 are not so large. Further, since the processing circuit 50 performs the temperature compensation process by floating point decimal point calculation or the like, it is easy to output the frequency control data DDS such that i ≧ 20 bits to the D / A conversion circuit 80, for example. Therefore, the configuration of the circuit device 500 in FIG. 15 has an advantage that it is possible to achieve both the high accuracy of the oscillation frequency and the suppression of the scale of the circuit device 500 and the increase in power consumption.

When the temperature changes from the first temperature to the second temperature, the processing circuit 50 calculates the second temperature (first temperature) from the first data corresponding to the first temperature (first temperature detection data). Frequency control data DDS that changes in units of k × LSB (changes by k × LSB) is output to second data corresponding to (temperature detection data of 2). Here, k ≧ 1, and k is an integer of 1 or more. For example, assuming that the number of bits of the frequency control data DDS (resolution of the D / A conversion circuit) is i, k <2 ⁱ and k is an integer sufficiently smaller than 2 ⁱ (for example, k = 1 to 8). ). More specifically, k <2 ^m . For example, when k = 1, the processing circuit 50 outputs the frequency control data DDS that changes from the first data to the second data in 1 LSB units (1-bit units). That is, the frequency control data DDS that changes while shifting by 1 LSB (1 bit) from the first data to the second data is output. The change step width of the frequency control data DDS is not limited to 1 LSB, and may be a change step width of 2 × LSB or more, for example, 2 × LSB, 3 × LSB, 4 × LSB,.

  Thus, if the frequency control data DDS output from the processing circuit 50 changes by k × LSB, for example, when the temperature changes from the first temperature to the second temperature, the D / A conversion is performed. It is possible to suppress a situation in which a large voltage change occurs in the output voltage VQ of the circuit 80 and frequency hopping occurs due to this voltage change. As a result, it is possible to prevent a communication error or the like from occurring due to the frequency hopping.

  16, 17, and 18 are explanatory diagrams of PWM modulation. As shown in FIG. 16, the modulation circuit 90 receives i = (n + m) -bit frequency control data DDS from the processing circuit 50. Based on the lower m bits of data (bits b1 to b4) of the frequency control data DDS, the PWM modulation of the upper n bits (bits b5 to b20) of the frequency control data DDS is performed. Of the n-bit data, the upper q-bit data (bits b13 to b20) is input to the upper-side DACA in FIGS. 2 and 3, and the lower p-bit data (bits b5 to b12). Is input to the lower-order DACB.

  FIG. 17 is an explanatory diagram of the first method of PWM modulation. DY and DZ are high-order n-bit data of the data DM, and DY = DZ + 1 holds in the n-bit representation.

  When the duty ratio represented by the low-order m = 4 bit data used for PWM modulation is 8 to 8, for example, as shown in FIG. 17, eight 16-bit data DY and eight pieces of data DY are used. 16-bit data DZ is time-divisionally output from the modulation circuit 90 to the D / A converter 100 (DACA, DACB).

  When the duty ratio represented by the lower order m = 4 bit data is 10 to 6, the 10 data DY and the 6 data DZ are time-divisionally converted from the modulation circuit 90 to the D / A converter. 100 is output. Similarly, when the duty ratio represented by the lower order m = 4 bit data is 14 to 2, 14 data DY and 2 data DZ are output in a time division manner.

  FIG. 18 is an explanatory diagram of the second method of PWM modulation. When each bit b4, b3, b2, b1 of m = 4 bits used for PWM modulation is a logical level “1”, an output pattern (shown on the right side of each bit) corresponding to each bit in FIG. Output pattern) is selected.

  For example, when bit b4 = 1 and b3 = b2 = b1 = 0, only the output pattern associated with bit b4 is output in periods P1 to P16. That is, n = 16-bit data is output from the modulation circuit 90 to the D / A converter 100 in time division in the order of DZ, DY, DZ, DY. As a result, the number of times data DY and DZ are output is eight, and the same PWM modulation as in the case where the duty ratio is 8 to 8 in FIG. 17 is realized.

  When bits b4 = b2 = 1 and b3 = b1 = 0, output patterns associated with bits b4 and b2 are output in periods P1 to P16. As a result, the data DY and DZ are output 10 times and 6 times, respectively, and the same PWM modulation as in the case where the duty ratio is 10 to 6 is realized. Similarly, when bits b4 = b3 = b2 = 1 and b1 = 0, the data DY and DZ are output 14 times and 2 times, respectively, and the duty ratio is 14 to 2. The same PWM modulation is realized.

4). In this embodiment, the filter circuit 120 of FIG. 15 is used as a low-pass filter for the PWM modulation circuit 90 and also as a low-pass filter for chopper type operational amplifiers OPA and OPB. The filter circuit 120 is shared in operation. Specifically, when the modulation frequency of the PWM modulation circuit 90 is fm and the chopping frequency of the chopper type operational amplifiers OPA and OPB (and OPC) is fp, fm = fp is set. For example, when the PWM modulation frequency is fm = 256 KHz, the chopping frequency is also set to fp = 256 KHz.

  The filter circuit 120 is a low-pass filter having a frequency characteristic in which the ripple voltage due to the modulation of the modulation circuit 90 and the ripple voltage due to the chopping of the chopper type operational amplifiers OPA and OPB are attenuated to be smaller than a given voltage level VNS. It has become. This voltage level VNS is determined by the voltage noise level allowed for the frequency control voltage (oscillation control voltage) of the oscillation circuit 150 of FIG. For example, an allowable target level of phase noise of the oscillation frequency is set, and a voltage noise level allowed for the frequency control voltage is determined from the allowable target level of phase noise, and the voltage level VNS is set.

  FIG. 19 is a diagram illustrating an example of a modulation pattern of PWM modulation. VDY and VDZ are voltage levels corresponding to the data DY (= DZ + 1) and DZ described above. VDY-VDZ corresponds to the voltage level of LSB in the D / A conversion of n bits (for example, n = 16) in FIG. Then, a modulation pattern as shown in FIG. 19 is generated according to the PWM modulation m = 4 bit pattern.

  Here, when the bit pattern of PWM modulation m = 4 bits is (1000), the frequency of the modulation pattern is fm = 256 KHz as shown in FIG. 19, and the frequency is the highest. On the other hand, when the bit pattern is (1111), the frequency of the modulation pattern is fmmin = fm / N = 32 KHz (N is an integer of 2 or more), which is the lowest frequency. Since the ripple voltage generated by the modulation circuit 90 has a frequency component of fmmin = 32 KHz, it is necessary to sufficiently attenuate the frequency component of fmmin = 32 KHz by the filter circuit 120.

  For example, FIG. 20 shows an example of the frequency characteristic of the low-pass filter of the filter circuit 120 of this embodiment. In FIG. 20, fc is a cutoff frequency of the filter circuit 120. For example, the filter circuit 120 is a primary RC low-pass filter, and the cutoff frequency fc can be set to about 1 KHz to 10 KHz, for example. As shown in FIG. 20, the filter circuit 120 has a frequency characteristic capable of sufficiently attenuating not only the frequency component of fm = fp = 256 KHz but also the frequency component of fmmin = 32 KHz (for example, attenuation of about −15 DB to 25 DB). ing. By giving such a frequency characteristic, the frequency component of the ripple voltage due to the modulation pattern having a low frequency corresponding to the bit pattern = (1111) in FIG. 19 can be sufficiently attenuated, such as phase noise. It is possible to satisfy the required specifications for.

Thus, in this embodiment, the modulation frequency of the modulation circuit 90 is fm, the frequency of the modulation pattern having the lowest frequency among the modulation patterns of the modulation circuit 90 is fmmin = fm / N (N is an integer of 2 or more), When the cut-off frequency of the filter circuit 120 is fc, the relationship of fc <fmmin is established. For example, when the number of bits of the modulation data is m, N = 2 ^m−1 . When m = 4, N = 8. As is clear from FIG. 20, the relationship of fc <fmmin <fp is established when the chopping frequency of the chopper type operational amplifiers OPA and OPB is fp. By doing so, the ripple voltage due to the modulation of the modulation circuit 90 and the ripple voltage due to the chopping of the chopper type operational amplifiers OPA and OPB are sufficiently attenuated by the low-pass filter of the filter circuit 120, and a request for phase noise or the like is required. The specification can be satisfied.

  In this embodiment, the chopping mode of the chopper type operational amplifiers OPA and OPB can be turned on and off. FIG. 21 shows an example of signal waveforms of VDA and VQ in FIG. 15 when the chopping mode is turned off. VDA is an output voltage of the D / A converter 100, and VQ is an output voltage of the filter circuit 120. FIG. 22 is an example of signal waveforms of VDA and VQ when the chopping mode is turned on. 21 and 22, VLSB is an LSB voltage in n-bit D / A conversion, and VF is the offset voltage described in FIG.

  In FIG. 21, the voltage VDA from the D / A converter 100 changes as indicated by B1 and B2 due to the modulation of the modulation circuit 90. The ripple voltage due to this voltage change is changed to B3, As shown in B4, it is attenuated and smoothed.

  In FIG. 22, the voltage VDA from the D / A converter 100 changes as indicated by B5 and B6 by the modulation of the modulation circuit 90 and the chopping operation of the chopper type operational amplifiers OPA and OPB. The ripple voltage due to the change is attenuated and smoothed by the filter circuit 120 as indicated by B7 and B8.

  The D / A conversion circuit 80 is provided with a modulation circuit 90 and a chopper type operational amplifier, and in the method of this embodiment in which fp = fm or fc <fmmin <fp, the circuit configuration of the D / A conversion circuit is shown in FIG. It is not limited to the configuration described with reference to FIGS. For example, the method of the present embodiment can be applied to various types of D / A conversion circuits (charge redistribution method, Δ sigma method, etc.) using a chopper type operational amplifier as an impedance conversion circuit.

5. Oscillator, Electronic Device, Mobile Object FIG. 23 shows a configuration example of an oscillator 400 including the circuit device 500 of this embodiment. As shown in FIG. 23, the oscillator 400 includes a vibrator XTAL and a circuit device 500 (D / A conversion circuit 80). The vibrator XTAL and the circuit device 500 are mounted in a package 410 of the oscillator 400. The terminals of the vibrator XTAL and the terminals (pads) of the circuit device 500 (IC) are electrically connected by the internal wiring of the package 410.

  FIG. 24 shows a configuration example of an electronic apparatus including the circuit device 500 (D / A conversion circuit 80) of the present embodiment. This electronic apparatus includes a circuit device 500 (D / A conversion circuit 80), a vibrator XTAL, an antenna ANT, a communication unit 510, and a processing unit 520 of the present embodiment. An operation unit 530, a display unit 540, and a storage unit 550 can be included. The oscillator XTAL and the circuit device 500 constitute an oscillator 400. Note that the electronic apparatus is not limited to the configuration in FIG. 24, and various modifications such as omitting some of these components or adding other components are possible.

  24 include wearable devices such as GPS built-in clocks, biological information measuring devices (pulse wave meters, pedometers, etc.) or head-mounted display devices, smartphones, mobile phones, portable game devices, notebooks, and the like. Various devices such as personal digital assistants (mobile terminals) such as PCs or tablet PCs, content providing terminals for distributing content, video equipment such as digital cameras or video cameras, or network-related equipment such as base stations or routers Can be assumed.

  The communication unit 510 (wireless circuit) performs processing of receiving data from the outside via the antenna ANT and transmitting data to the outside. The processing unit 520 performs electronic device control processing, various digital processing of data transmitted and received via the communication unit 510, and the like. The function of the processing unit 520 can be realized by a processor such as a microcomputer. The operation unit 530 is for a user to perform an input operation, and can be realized by an operation button, a touch panel display, or the like. The display unit 540 displays various types of information and can be realized by a display such as a liquid crystal or an organic EL. The storage unit 550 stores data and can be realized by a semiconductor memory such as a RAM or a ROM, an HDD (hard disk drive), or the like.

  FIG. 25 shows an example of a moving object including the circuit device 500 (D / A conversion circuit 80) of this embodiment. The circuit device 500 (oscillator) of this embodiment can be incorporated into various moving bodies such as a car, an airplane, a motorcycle, a bicycle, or a ship. The moving body is, for example, a device / device that moves on the ground, in the sky, or on the sea, including a drive mechanism such as an engine or motor, a steering mechanism such as a steering wheel or rudder, and various electronic devices (on-vehicle devices). FIG. 25 schematically shows an automobile 206 as a specific example of the moving object. The automobile 206 incorporates the circuit device 500 (D / A conversion circuit 80) of the present embodiment and an oscillator (not shown) having a vibrator. The control device 208 is operated by a clock signal generated by this oscillator. The control device 208 controls the hardness of the suspension, for example, according to the posture of the vehicle body 207, and controls the brakes of the individual wheels 209. For example, automatic driving of the automobile 206 may be realized by the control device 208. Note that the device in which the circuit device 500 (D / A conversion circuit 80) and the oscillator of this embodiment are incorporated is not limited to such a control device 208, and various devices (on-vehicle equipment) provided in a moving body such as the automobile 206. Device).

  Although the present embodiment has been described in detail as described above, it will be easily understood by those skilled in the art that many modifications can be made without departing from the novel matters and effects of the present invention. Accordingly, all such modifications are intended to be included in the scope of the present invention. For example, a term described at least once together with a different term having a broader meaning or the same meaning in the specification or the drawings can be replaced with the different term in any part of the specification or the drawings. All combinations of the present embodiment and the modified examples are also included in the scope of the present invention. Further, the configuration / operation of the D / A conversion circuit, circuit device, oscillator, electronic device, and moving body, the D / A conversion method, the chopping method, the modulation method, and the like are not limited to those described in this embodiment, and various Variations are possible.

OPA, OPB, OPC, OPH ... chopper type operational amplifier, OP ... operational amplifier,
ASW1, ASW2 ... chopper circuit, DACA, DACB ... D / A converter,
DFC ... amplification stage, QSC ... output stage,
TC1 to TC20 ... transistors, S1 to S6 ... switch elements,
BLA to BLF ... selector block, XTAL ... vibrator,
DESCRIPTION OF SYMBOLS 10 ... Temperature sensor, 20 ... A / D conversion circuit, 30 ... Voltage generation circuit,
31, 32, 33 ... Ladder resistance circuit, 40 ... Voltage selection circuit, 42 ... Decoder,
46 ... Voltage generation circuit, 47 ... Ladder resistance circuit, 48 ... Voltage selection circuit, 50 ... Processing circuit,
80 ... D / A conversion circuit, 90 ... Modulation circuit, 100 ... D / A converter,
104, 106 ... decoder, 120 ... filter circuit,
140 ... oscillation signal generation circuit, 150 ... oscillation circuit, 160 ... buffer circuit,
206 ... Automobile, 207 ... Car body, 208 ... Control device, 209 ... Wheel,
400 ... Oscillator, 410 package, 500 ... Circuit device, 510 ... Communication unit,
520 ... Processing unit, 530 ... Operating unit, 540 ... Display unit, 550 ... Storage unit

Claims (14)

A voltage generation circuit for generating a plurality of voltages;
A voltage selection circuit that performs voltage selection from the plurality of voltages based on input data, and outputs a Kth voltage and an Lth voltage (K and L are different integers of 1 or more) as selection voltages;
A first operational amplifier to which the Kth voltage is input;
A second operational amplifier to which the Lth voltage is input;
Including
The D / A conversion circuit, wherein the first and second operational amplifiers are chopper type operational amplifiers. The D / A conversion circuit according to claim 1,
A first D / A converter configured by the voltage generation circuit and the voltage selection circuit;
A second D / A converter;
Including
The voltage selection circuit of the first D / A converter includes:
Perform voltage selection based on the upper bits of the input data,
The second D / A converter is:
A second voltage generation circuit that generates a plurality of voltages obtained by voltage-dividing between a first output voltage of the first operational amplifier and a second output voltage of the second operational amplifier;
A second voltage selection circuit that performs voltage selection from the plurality of voltages from the second voltage generation circuit based on lower-order bits of the input data;
A D / A conversion circuit comprising: The D / A converter circuit according to claim 2,
A third operational amplifier to which an output voltage of the second voltage selection circuit is input;
The D / A conversion circuit characterized in that the third operational amplifier is a chopper type operational amplifier. In the D / A converter circuit according to claim 2 or 3,
The voltage generation circuit includes:
A first ladder resistance circuit for resistance-dividing the high-potential side power supply voltage and the low-potential side power supply voltage;
A second ladder resistor circuit that resistance-divides the high-potential-side power supply voltage and the low-potential-side power supply voltage,
The voltage selection circuit includes:
A voltage selected from a plurality of divided voltages of the first ladder resistor circuit is output to the first operational amplifier as the Kth voltage;
A D / A converter circuit that outputs a voltage selected from a plurality of divided voltages of the second ladder resistor circuit to the second operational amplifier as the Lth voltage. The D / A converter circuit according to claim 4,
When the s-th divided voltage (s is an integer equal to or greater than 1) of the first ladder resistor circuit is supplied to the first operational amplifier as the K-th voltage, the second ladder resistor circuit T-th divided voltage (t is an integer equal to or greater than 1) is supplied to the second operational amplifier as the Lth voltage,
When the s + 1th divided voltage of the first ladder resistor circuit is supplied to the first operational amplifier as the Kth voltage, the tth divided voltage of the second ladder resistor circuit is , Supplied to the second operational amplifier as the Lth voltage,
When the s + 1th divided voltage of the first ladder resistor circuit is supplied to the first operational amplifier as the Kth voltage, the t + 1th divided voltage of the second ladder resistor circuit is The D / A conversion circuit is supplied to the second operational amplifier as the Lth voltage. A processing circuit for performing temperature compensation processing of the oscillation frequency based on the temperature detection data and outputting frequency control data of the oscillation frequency;
6. The D according to claim 1, further comprising a filter circuit that performs D / A conversion of the input data that is the frequency control data and smoothes a voltage obtained by the D / A conversion. / A conversion circuit;
An oscillation circuit that generates an oscillation signal of the oscillation frequency set by the frequency control data using an output voltage of the D / A conversion circuit and a vibrator;
A circuit device comprising: The circuit device according to claim 6,
The D / A conversion circuit includes:
And a modulation circuit that receives the frequency control data of i = n + m bits from the processing circuit and modulates the n-bit data of the frequency control data based on the m-bit data of the frequency control data. Circuit device. The circuit device according to claim 7, wherein
A circuit device, wherein fm = fp when the modulation frequency of the modulation circuit is fm and the chopping frequency of the chopper type operational amplifier is fp. A processing circuit for performing temperature compensation processing of the oscillation frequency based on the temperature detection data and outputting frequency control data of the oscillation frequency;
A D / A conversion circuit having a filter circuit for performing D / A conversion of input data which is the frequency control data and smoothing a voltage obtained by the D / A conversion;
An oscillation circuit that generates an oscillation signal of the oscillation frequency set by the frequency control data, using an output voltage and a vibrator of the filter circuit;
Including
The D / A conversion circuit includes:
A chopper-type operational amplifier;
A modulation circuit that receives the frequency control data of i = n + m bits from the processing circuit and modulates the n-bit data of the frequency control data based on the m-bit data of the frequency control data;
Including
A circuit device, wherein fm = fp when the modulation frequency of the modulation circuit is fm and the chopping frequency of the chopper type operational amplifier is fp. The circuit device according to any one of claims 7 to 9,
The modulation frequency of the modulation circuit is fm, the frequency of the modulation pattern having the lowest frequency among the modulation patterns of the modulation circuit is fmmin = fm / N (N is an integer of 2 or more), and the cutoff frequency of the filter circuit is A circuit device, wherein fc <fmmin, where fc. The circuit device according to claim 10, wherein
A circuit device characterized by satisfying fc <fmmin <fp, where chopping frequency of the chopper type operational amplifier is fp. A circuit device according to any one of claims 6 to 11,
The vibrator;
An oscillator comprising:   An electronic apparatus comprising the D / A conversion circuit according to claim 1.   A moving body comprising the D / A conversion circuit according to claim 1.

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