JP2018152510A - Printed Wiring Board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve heat dissipation of a printed wiring board.SOLUTION: A printed wiring board 1 according to an embodiment includes first and second conductor layers 11 and 12 of the outer layers respectively formed on one and the other outermost layers, a third conductor layer 13 of an inner layer formed to be thicker than the conductor layers of the two outer layers, first and second insulating layers 21 and 22 interposed between the first and second conductor layers 11 and 12 and the third conductor layer 13, and a plurality of via conductors connecting the first and second conductor layers 11 and 12 to the third conductor layer 13. A first component mounting pad 2a is formed on the first conductor layer 11, and a first connecting conductor pad 3a is formed at a position overlapping with the first component mounting pad 2a on the second conductor layer 12, and the number of third via conductors 4c connecting the first connecting conductor pad 3a and the third conductor layer 13 is more than the number of first via conductors 4a connecting the first component mounting pad 2a and the third conductor layer 13.SELECTED DRAWING: Figure 3

Description

  The present invention relates to a printed wiring board.

  Patent Document 1 discloses a circuit board including a base, a frame and a circuit board, and a conductive member housed in the frame, which are sequentially stacked. Electronic components are mounted on the circuit board. Heat generated from the electronic component is radiated to the outside mainly through the circuit board, the conductive member, and the base.

JP 2011-138838 A

  In the circuit board of Patent Document 1, a circuit board that transfers heat of an electronic component to a conductive member and a base that transfers heat from the conductive member are insulating materials such as alumina that have a lower thermal conductivity than a metal such as copper. It is made of a functional material. Further, since the conductive member, the circuit board, and the substrate are merely in contact, it is assumed that a gap is likely to be generated at each interface due to heat shrinkage or the like. Therefore, it is considered that sufficient heat dissipation characteristics cannot be obtained. Moreover, it is considered difficult to use the conductive member accommodated in the frame as a conductor layer constituting an arbitrary electric circuit. Therefore, further multilayering may be necessary to realize a desired electric circuit. There is a concern that the structure of the circuit board is complicated, the thickness is increased, and the cost is increased.

  The printed wiring board of the present invention comprises an outer conductor layer formed on one and the other outermost layers, an inner conductor layer formed thicker than the outer conductor layer, the outer conductor layer, An insulating layer interposed between the inner conductor layer and a plurality of via conductors formed densely in the insulating layer and connecting each of the outer conductor layer and the inner conductor layer; doing. A component mounting pad is formed on one of the outer conductor layers, and a connection conductor pad is formed on the other of the outer conductor layers at a position overlapping the component mounting pad. The component mounting pad and the inner layer Are connected by a plurality of via conductors, and the connection conductor pads and the inner conductor layers are connected by a plurality of via conductors, the connection conductor pads and the inner conductors. The number of via conductors that connect layers is greater than the number of via conductors that connect the component mounting pads and the inner conductor layer.

  According to the embodiment of the present invention, it is considered that heat is efficiently conducted through the via conductor from the mounting pad such as an electronic component to the outer conductive layer on the side opposite to the mounting pad. It is considered that a printed wiring board having excellent heat dissipation characteristics can be provided. Further, it is considered that a more complicated electric circuit can be realized with a simple substrate structure with high heat dissipation by having a thick conductor layer.

The top view which shows one surface of the printed wiring board of one Embodiment of this invention. The figure which shows the conductor pattern of the other surface of the printed wiring board of FIG. Sectional drawing in the III-III line of the printed wiring board of FIG. Sectional drawing in the IV-IV line of the printed wiring board of FIG. The figure which shows an example of the component mounting area | region of the printed wiring board of one Embodiment. The figure which shows the other example of the components mounting area | region of the printed wiring board of one Embodiment. The figure which shows an example of the manufacturing method of the printed wiring board of one Embodiment of this invention. The figure which shows an example of the manufacturing method of the printed wiring board of one Embodiment of this invention. The figure which shows an example of the manufacturing method of the printed wiring board of one Embodiment of this invention. The figure which shows an example of the manufacturing method of the printed wiring board of one Embodiment of this invention. The figure which shows an example of the manufacturing method of the printed wiring board of one Embodiment of this invention. The figure which shows an example of the manufacturing method of the printed wiring board of one Embodiment of this invention. The figure which shows an example of the manufacturing method of the printed wiring board of one Embodiment of this invention. The figure which shows an example of the manufacturing method of the printed wiring board of one Embodiment of this invention. The figure which shows an example of the manufacturing method of the printed wiring board of one Embodiment of this invention. The figure which shows an example of the manufacturing method of the printed wiring board of one Embodiment of this invention.

  A printed wiring board according to an embodiment of the present invention will be described with reference to the drawings. 1 to 4 show a printed wiring board 1 according to an embodiment, and a pattern of a conductor layer (first conductor layer 11) formed on one surface of the printed wiring board 1 is shown in FIG. Has been. The pattern of the conductor layer (second conductor layer 12) formed on the other surface is shown in FIG. 1 and 2, the conductor pattern of the inner conductor layer (third conductor layer 13) is also indicated by a broken line. FIG. 2 shows the printed wiring board 1 in a left-right reversal from the state shown in FIG. Therefore, FIG. 2 shows the inner layer conductor pattern in a horizontally reversed shape of the shape shown in FIG. 3 is a cross-sectional view taken along line III-III in FIG. 1, and FIG. 4 is a cross-sectional view taken along line IV-IV. 3 and 4, the thickness direction of the printed wiring board 1 is shown to be larger than the plane direction so that each component can be easily understood. Therefore, in FIG. 3 and FIG. 4, the length in the vertical direction and the length in the horizontal direction are not shown in an accurate ratio.

  As shown in FIGS. 1 to 4, the printed wiring board 1 according to one embodiment includes a first conductor layer 11 formed on the outermost layer on the first surface 1 </ b> F side that is one surface and a first surface that is the other surface. It has the 2nd conductor layer 12 formed in the outermost layer by the side of 2 side 1S, and the 3rd conductor layer 13 formed thicker than the 1st and 2nd conductor layers 11 and 12. FIG. In the printed wiring board 1, the first and second conductor layers 11 and 12 are outer conductor layers formed on the first surface 1F or the second surface 1S, and the third conductor layer 13 is the first conductor. This is an inner conductor layer formed between the layer 11 and the second conductor layer 12. The printed wiring board 1 further includes an insulating layer (a first insulating layer 21 and a second insulating layer 22) interposed between the outer conductor layer and the inner conductor layer.

  As shown in FIGS. 1, 3 and 4, a first component mounting pad 2 a and a second component mounting pad 2 b are formed on the first conductor layer 11. External electronic components E1 and E2 are mounted on the first and second component mounting pads 2a and 2b by a bonding material S such as solder. As shown in FIGS. 2 to 4, the second conductor layer 12 is formed with a first connection conductor pad 3 a and a second connection conductor pad 3 b. The first connection conductor pad 3a is formed at a position at least partially overlapping the first component mounting pad 2a in plan view. The second connection conductor pad 3b is formed at a position at least partially overlapping the second component mounting pad 2b in plan view. The first and second connection conductor pads 3a and 3b are connected to an external element (not shown) such as a mother board. That is, in the printed wiring board 1, the first surface 1F is a component mounting surface, and the second surface 1S side is a connection surface with an external element such as a motherboard. Although not shown in FIGS. 1 and 2 for easy viewing of the first conductor layer 11 and the like, the first surface 1F of the printed wiring board 1 is not shown in FIGS. The solder resist layer 30 which has the opening 32 in the appropriate position may be formed. Although not shown, the solder resist layer 30 may be formed on the second surface 1S or on both surfaces.

  The printed wiring board 1 further includes a plurality of via conductors (a first via conductor 4a, a second via conductor 4b, and a third via conductor 4c) formed densely in each of the first and second insulating layers 21 and 22. And a fourth via conductor 4d). The first and second via conductors 4 a and 4 b are formed in the first insulating layer 21 and connect the first conductor layer 11 and the third conductor layer 13. The third and fourth via conductors 4 c and 4 d are formed in the second insulating layer 22 and connect the second conductor layer 12 and the third conductor layer 13. The first to fourth via conductors 4a to 4d are so-called thermal vias that thermally connect the first to third conductor layers with high thermal conductivity (hereinafter referred to as first to fourth vias). The via conductors 4a to 4d are also simply referred to as “thermal vias”). Therefore, the first to fourth “via conductors” 4a to 4d only need to have good conductivity at least with respect to heat. However, preferably, the first to fourth via conductors 4a to 4d electrically connect the first to third conductor layers 11, 12, and 13 also. In the example of FIGS. 1 to 4, the first insulating layer 21 is also formed with a fifth via conductor 6 b that is a general via conductor whose main purpose is electrical connection.

  The plurality of first via conductors 4a connect the first component mounting pad 2a and the third conductor layer 13 as the inner conductor layer, and the plurality of third via conductors 4c connect the first connection conductor. The pad 3a and the third conductor layer 13 are connected. The second component mounting pad 2b and the third conductor layer 13 are connected by a plurality of second via conductors 4b, and the second connection conductor pad 3b and the third conductor are connected by a plurality of fourth via conductors 4d. Layer 13 is connected. As described above, in this embodiment, each component mounting pad and the third conductor layer 13 having a thick inner layer are connected by a plurality of thermal vias provided in each component mounting pad, and the third conductor layer 13 and each connection are connected. The conductor pads are also connected by a plurality of thermal vias provided in each connection conductor pad. Each via conductor functioning as a thermal via can be formed of a material having high thermal conductivity such as copper, as will be described later. Therefore, it is considered that heat can be efficiently conducted from the component mounting pads on the first surface 1F side to the third conductor layer 13 via the first and second via conductors 4a and 4b. It is considered that the heat conducted to the third conductor layer 13 is efficiently transmitted also in the planar direction (direction perpendicular to the thickness direction of the printed wiring board 1) in the thick third conductor layer 13. Then, it is considered that heat is efficiently conducted from the third conductor layer 13 to each connection conductor pad on the second surface 1S via the third and fourth via conductors 4c and 4d.

  Furthermore, in this embodiment, as FIG. 1-3 shows, the number of the 3rd via conductors 4c is larger than the number of the 1st via conductors 4a. As shown in FIGS. 1, 2 and 4, the number of fourth via conductors 4d is also larger than the number of second via conductors 4b. That is, in the present embodiment, the number of thermal vias connecting each connection conductor pad and the thick third conductor layer 13 of the inner layer is equal to each component mounting pad formed at a position overlapping each of the connection conductor pads. More than the number of thermal vias connecting the third conductor layer 13. When the sizes of the end faces of the individual thermal vias are all the same, the total contact area between the thermal vias on the connection conductor pads 3a, 3b side and the third conductor layer 13 is calculated on the component mounting pads 2a, 2b side. It is larger than the total contact area between the thermal via and the third conductor layer 13. Therefore, it is considered that the heat sufficiently diffused in the plane direction in the thick third conductor layer 13 is efficiently conducted to each connection conductor pad through many heat conduction paths. Therefore, it is considered that the thermal resistance from each component mounting pad to each connection conductor pad is small. Further, as described above, each connection conductor pad can be connected to an external element having a large volume, that is, a large heat capacity, like an external mother board. It is assumed that the substantial heat dissipation of the printed wiring board 1 of the present embodiment is higher than that of the conventional printed wiring board. It is considered that the temperature rise due to heat generation during operation of the electronic component mounted on each component mounting pad can be reduced.

  The electronic components E1 and E2 mounted on the first and second component mounting pads 2a and 2b are, for example, active components such as semiconductor devices and passive components such as resistors and inductors. However, the electronic components E1 and E2 are not limited to these. The printed wiring board of the embodiment that can have high heat dissipation is considered to be particularly suitable for mounting electronic components that generate heat during operation, such as power semiconductor devices, power resistors, and light emitting diodes. .

  The first component mounting pad 2a is a component mounting pad including a pair of conductor pads respectively connected to different electrodes of the electronic component E1 mounted on the first component mounting pad 2a. The second component mounting pad 2b is a component mounting pad including a pair of conductor pads respectively connected to different electrodes of the electronic component E2 mounted on the second component mounting pad 2b. The first and second connection conductor pads 3a and 3b are a pair of conductor pads provided corresponding to the first and second component mounting pads 2a and 2b, respectively. That is, the first connection conductor pad 3a is connected to the first and third via conductors 4a and 4c, the third conductor layer 13, and the first component on different electrodes of the electronic component E1 mounted on the first component mounting pad 2a. It consists of a pair of conductor pads connected to each other via the mounting pad 2a. The second connection conductor pads 3b are formed on the different electrodes of the electronic component E2 mounted on the second component mounting pad 2b, and the second and fourth via conductors 4b and 4d, the third conductor layer 13, and the second component mounting pad. It consists of a pair of conductor pads connected through 2b. In the printed wiring board 1, a plurality of first via conductors 4a are provided over substantially the entire surface of the first component mounting pad 2a, and a plurality of third via conductors 4c are provided over substantially the entire surface of the first connection conductor pad 3a. . The plurality of first via conductors 4a and the plurality of third via conductors 4c are arranged at substantially the same arrangement pitch. However, since the size of each conductor pad in the first connection conductor pad 3a in plan view is larger than the size in plan view of each conductor pad of the first component mounting pad 2a, the number of third via conductors 4c is More than the number of first via conductors 4a.

  On the other hand, as shown in FIGS. 1, 2, and 4, the second component mounting pad 2b and the second connecting conductor pad 3b have substantially the same size. However, the arrangement pitch P4d of the plurality of fourth via conductors 4d is smaller than the arrangement pitch P4b of the plurality of second via conductors 4b. In addition, as shown in FIGS. 1, 2 and 4, the fourth via conductor 4d is formed over almost the entire surface of the second connection conductor pad 3b, whereas the second via conductor 4b is a second component. It is formed so as to leave a blank portion on the mounting pad 2b. As a result, although the second component mounting pad 2b and the second connection conductor pad 3b have substantially the same size, the number of the fourth via conductors 4d is larger than the number of the second via conductors 4b. There are also many.

  As described above, in the printed wiring board of the embodiment, the plurality of via conductors 4c and 4d provided in the connection conductor pads 3a and 3b are more than the plurality of via conductors 4a and 4b provided in the component mounting pads 2a and 2b. May be formed at a small pitch. Further, the via conductors 4a and 4b provided on the component mounting pads 2a and 2b may not be provided on the entire surface of the component mounting pads 2a and 2b. That is, the arrangement density of the thermal vias provided in the connection conductor pads 3a and 3b may be larger than the arrangement density of the thermal vias provided in the component mounting pads 2a and 2b. As a result, the number of thermal vias provided in each connection conductor pad 3a, 3b may be larger than the number of thermal vias provided in each component mounting pad 2a, 2b.

  In the printed wiring board of the embodiment, the number of thermal vias provided in a specific area in each component mounting pad 2a, 2b corresponds to that specific area in each connection conductor pad 3a, 3b. The number of thermal vias provided in the region may be large. As the “specific area”, a component mounting area is exemplified. The component mounting area is an area in each component mounting pad on which an electronic component is actually connected. The “area corresponding to the specific area” is an area that overlaps the component mounting area, that is, an area immediately below the component mounting area (an area occupied by an orthographic image of the component mounting area on the connection conductor pads). Even if the number of thermal vias on the side of each connection conductor pad 3a, 3b is larger than the number of thermal vias on the side of each component mounting pad 2a, 2b in the component mounting region and the region immediately below, as described above, An improvement effect may be obtained. An example of the component mounting area will be described later.

  In the example of FIGS. 1 and 2, the plurality of thermal vias provided in each row are arranged in a so-called staggered arrangement so that individual via conductors can be shifted from each other by approximately half a pitch and close to each other. A plurality of thermal vias can be arranged at a higher density under the constraints of the design and manufacturing aspects of the spacing between adjacent via conductors. The ratio of the total area of the contact surface between each thermal via formed on each pad and each pad to the area of each component mounting pad 2a, 2b and each connecting conductor pad 3a, 3b is preferably 15%. The content is 40% or less, and more preferably 35% or more and 40% or less. However, the arrangement of the plurality of thermal vias provided is not limited to the staggered arrangement. For example, the plurality of thermal vias may be arranged in a grid (matrix) or may be arranged at random. Regardless of the arrangement form of the plurality of thermal vias, the thermal via provided in each connection conductor pad 3a, 3b is provided in each component mounting pad 2a, 2b formed at a position overlapping with each connection conductor pad 3a, 3b. More thermal vias are provided.

  In the printed wiring board of the embodiment, three or more component mounting pads that overlap with the connection conductor pads on the second surface 1S side may be formed, or only one component mounting pad may be formed. When a plurality of sets of component mounting pads and connection conductor pads are formed, in at least one of them, the number of via conductors connecting the connection conductor pads and the inner conductor layer is equal to the number of the component mounting pads and the inner layers. More than the number of via conductors connecting the other conductor layers. In addition, each component mounting pad may be configured by more or less than two conductor pads.

  The first and second conductor layers 11 and 12 including each component mounting pad or each connection conductor pad are formed of, for example, a metal foil and a plating film (in FIG. 3 and FIG. The second conductor layers 11, 12 are shown in a simplified single layer structure). Examples of the material of the first and second conductor layers 11 and 12 include copper and nickel. However, the materials of the first and second conductor layers 11 and 12 are not limited to these. As will be described later, the first and second conductor layers 11 and 12 can be formed to have an arbitrary conductor pattern by a subtractive method or an additive method. In the example of FIG. 1, the first conductor layer 11 includes, in addition to the first and second component mounting pads 2 a and 2 b, two third component mounting pads 6 a composed of a pair of conductor pads, and a third component mounting pad. 6a and a wiring pattern 6c for connecting the first component mounting pad 2a.

  The third conductor layer 13 of the printed wiring board 1 includes a predetermined conductor pattern. As shown in FIGS. 1 and 4, the third conductor layer 13 has an inner layer extending from the inner conductor pad 7a formed between the second component mounting pad 2b and the second connection conductor pad 3b. A wiring pattern 7b is formed. As shown in FIGS. 1 and 3, the inner layer wiring pattern 7b is connected to the first conductor layer 11 by a fifth via conductor 6b at the tip thereof. That is, as described above, the third conductor layer 13 that contributes to the realization of high heat dissipation as a good heat conductor and heat diffuser in the heat dissipation structure of the printed wiring board 1 is formed of the predetermined electric circuit in the printed wiring board 1. It is also used for formation. The third conductor layer 13 of the present embodiment can be easily patterned by, for example, etching as described in the manufacturing method described later. That is, the third conductor layer 13 can basically have an arbitrary conductor pattern. If the desired electric circuit cannot be formed by the first and second conductor layers 11 and 12 alone, the desired electric circuit may be formed without additional conductor layers. Unlike the above-mentioned disclosure of Patent Document 1 in which a conductive member for heat dissipation is embedded in a circuit board, a printed circuit board having high heat dissipation including a more complicated electric circuit can be obtained with a simple structure and an easy manufacturing method. Conceivable.

  The third conductor layer 13 can be made of, for example, a metal foil or a metal plate made of copper or nickel. However, the material of the third conductor layer 13 is not limited to these. In the printed wiring board 1 of one embodiment, the third conductor layer 13 is configured by a metal foil 13a and a metal coating 13b formed on one surface of the metal foil 13a. The metal coating 13b is, for example, an electrolytic plating film or an electroless plating film made of the same material as the metal foil 13a or a laminated film thereof. The metal film 13b may be a metal film formed by a method other than plating. The third conductor layer 13 may thus have a multilayer structure made of two or more materials. For example, the thickness of the third conductor layer 13 can be easily adjusted to a desired thickness by adjusting the thickness of the metal coating 13b.

  The thickness of the 3rd conductor layer 13 is 100 micrometers or more and 2000 micrometers or less, for example, Preferably, they are 200 micrometers or more and 300 micrometers or less. The reason is that if the thickness of the third conductor layer 13 is too thin, a sufficient thermal diffusion effect in the planar direction cannot be obtained, and conversely, if the thickness is too thick, the increase in thermal resistance in the thickness direction becomes remarkable. . However, the thickness of the third conductor layer 13 is not limited to these. As shown in FIGS. 3 and 4, when the third conductor layer 13 has a two-layer structure, the metal foil 13 a preferably has a thickness that occupies 90% or more of the thickness of the third conductor layer 13. . The thickness of the metal coating 13b can be reduced, and the formation time of the metal coating 13b can be shortened.

  In the example of FIGS. 3 and 4, the third conductor layer 13 having a two-layer structure is provided so that the metal foil 13 a side is on each component mounting pad side. The metal foil for printed wiring boards can have a matte surface with a large surface roughness on one side. This mat surface is directed to each component mounting pad side so that the contact area between the third conductor layer 13 and the first insulating layer 21 and the first and second via conductors 4a and 4b has a large surface roughness. Increased by surface irregularities. The third conductor layer 13 and each element on the first surface 1F side are firmly attached. The temperature on the first surface 1F side is presumed to be higher than the temperature on the second surface 1S side due to heat generated by the electronic components E1 and E2 mounted on the component mounting pads. By using the metal foil 13a on each component mounting pad side, peeling due to a difference in thermal expansion coefficient between the element on the first surface 1F side and the third conductor layer 13, which is likely to be exposed to a larger temperature rise, is prevented. It is thought that it is done.

  As described above, the third conductor layer 13 is an inner layer conductor pad 7a formed between the first and second component mounting pads 2a, 2b and the first and second connection conductor pads 3a, 3b. , As well as a conductor pattern such as an inner layer wiring pattern 7b. As shown in FIGS. 3 and 4, the side surface of each conductor pattern of the third conductor layer 13 extends from each connection conductor pad side (second surface 1S side) to each component mounting pad side (first surface 1F side). The conductor pattern is inclined so as to increase in size in plan view. The contact area between the third conductor layer 13 and the first insulating layer 21 is considered to be larger than the contact area between the third conductor layer 13 and the second insulating layer 22. As described above, it is considered that peeling due to the difference in coefficient of thermal expansion between the first insulating layer 21 on the first surface 1F side and the third conductor layer 13 that is likely to be exposed to a larger temperature rise is further prevented. It is done.

  As shown in FIGS. 3 and 4, an in-layer insulator 23 is formed between the conductor patterns of the third conductor layer 13 by filling with an insulator. The in-layer insulator 23 ensures insulation between the conductor patterns of the third conductor layer 13. Both surfaces in the thickness direction of the third conductor layer 13 and both surfaces of the in-layer insulator 23 are substantially flush with each other. The interface between the third conductor layer 13 and the first and second insulating layers 21 and 22 can be almost entirely flat by the in-layer insulator 23. It is considered that the conductor patterns of the first and second conductor layers 11 and 12 can be formed on the flat surfaces of the first and second insulating layers 21 and 22. The in-layer insulator 23 is formed of, for example, an epoxy resin. However, the material of the in-layer insulator 23 is not limited to the epoxy resin, and any insulating material other than the epoxy resin can be used for forming the in-layer insulator 23.

  The first and second insulating layers 21 and 22 are formed of any insulating material made of resin, for example. Preferably, the first and second insulating layers 21 and 22 are formed of an epoxy resin that includes or does not include a reinforcing material such as glass fiber like a prepreg. Bismaleimide triazine resin (BT resin), phenol resin, or the like may be used as the material of the first and second insulating layers 21 and 22. The resin forming each insulating layer may contain an inorganic filler such as silica. The thickness of the 1st and 2nd insulating layers 21 and 22 is 10 micrometers or more and 100 micrometers or less, for example, Preferably it is 30 micrometers.

The first to fourth via conductors 4 a to 4 d are formed in via holes provided in the first insulating layer 21 or the second insulating layer 22. The first to fourth via conductors 4a to 4d are formed of a material having high thermal conductivity such as metal, and are preferably formed of a conductive material. The first to fourth via conductors 4 a to 4 d are preferably made of the same material as the first conductor layer 11 and the second conductor layer 12. As a preferable material of the first to fourth via conductors 4a to 4d, a copper plating film is exemplified. Each via conductor is preferably formed of a material having a thermal conductivity of 60 W / (m · K) or more, more preferably 350 W / (m · K) or more. The first to fourth via conductors 4a to 4d have a tapered shape that becomes narrower toward the third conductor layer 13 side. The sizes of the first to fourth via conductors 4a to 4d are arbitrarily selected according to the thicknesses of the first and second insulating layers 21 and 22, the arrangement pitch of each via conductor, and the like. For example, in the case of the first to fourth via conductors 4 a to 4 d having a substantially circular planar shape, the diameter of each via conductor at the interface with the third conductor layer 13 is 20 μm or more and 300 μm or less. Preferably, the diameter of each via conductor is 150 μm or more at the interface with the third conductor layer 13. Each of the via conductors 4 a to 4 d, with respect to the contact area between the third conductive layer 13, for example, 2,000 [mu] m ² or more, is formed in the area of 70,680Myuemu ² or less, preferably, 17,600Myuemu ² or more areas Formed with. It is considered that sufficient thermal conductivity that can function as a thermal via can be obtained. The fifth via conductor 6b is formed of a copper plating film or the like.

  The aforementioned “component mounting area” is an area in each component mounting pad on which an electronic component is actually connected as described above. That is, when an electronic component is placed on each component mounting pad, the region where the electronic component is actually connected is the component mounting region. Therefore, the “component mounting area” may not be clearly defined in the component mounting pad before the electronic component is arranged. However, as in the example shown in FIGS. 5A and 5B, the component mounting area may be defined by some component in the component mounting pad.

  In the example of FIG. 5A, the component mounting region R is defined along the opening 32 provided in the solder resist 31. The solder resist 31 is formed so as to cover a part of the first component mounting pad 2a. The remaining part of the first component mounting pad 2 a is exposed to the opening 32. This exposed region is the component mounting region R, and the electronic component E1 is disposed in the component mounting region R.

  In the example of FIG. 5B, the component mounting region R is defined by an opening provided in the first component mounting pad 2a. Three slit-shaped openings 33 are formed in each of the pair of conductor pads of the first component mounting pad 2a (the first insulating layer 21 is exposed in the openings 33). A side of the component mounting region R is defined along each of the six openings 33. A region surrounded by the six openings 33 is a component mounting region R. The opening 33 does not have to be a single slit-like opening as in the example of FIG. 5B, and a plurality of openings 33 may be formed continuously like a perforation.

  In the printed wiring board 1 according to the embodiment, on both sides of the third conductor layer 13, one insulating layer and one conductor layer (the first insulating layer 21, the first conductor layer 11, the second insulating layer 22, and A second conductor layer 12) is formed. However, the printed wiring board of the embodiment may have two or more insulating layers and conductor layers on both sides of the thick inner conductor layer. Thermal vias are formed in each insulating layer. The thick inner conductor layer, the component mounting pad formed on one outermost conductor layer, and the connecting conductor pad formed on the other outermost conductor layer are each a thermal formed on a plurality of insulating layers. Connected via. In that case, at least the number of thermal vias that are in direct contact with the connection conductor pads is greater than the number of thermal vias that are in direct contact with the component mounting pads. Preferably, the number of thermal vias formed in each insulating layer on the connection conductor pad side is larger than the number of thermal vias formed on any insulating layer on the component mounting pad side.

  Taking the printed wiring board 1 shown in FIG. 1 as an example, an example of a method for manufacturing a printed wiring board according to an embodiment will be described below with reference to FIGS. 6A to 6J show cross sections corresponding to FIG.

  As shown in FIG. 6A, a support plate 80 having a metal foil 11a on the surface is prepared. The metal foil 11a constitutes the first conductor layer 11 (see FIG. 3) when the printed wiring board 1 is completed. The metal foil 11a includes a carrier metal foil 81 bonded to one surface, and a surface of the carrier metal foil 81 opposite to the metal foil 11a is joined to one surface of the support plate 80 by thermocompression bonding or the like. The metal foil 11a and the carrier metal foil 81 are bonded with a separable adhesive such as a thermoplastic adhesive, for example. The metal foil 11a and the carrier metal foil 81 may be bonded only at a blank portion near the outer periphery. For the support plate 80, for example, a prepreg formed by impregnating a core material such as glass fiber with a resin material such as epoxy resin is used. This prepreg can be fully cured at the time of thermocompression bonding with the carrier metal foil 81. A metal plate such as copper may be used for the support plate 80. Moreover, a double-sided copper clad laminate may be used as the support plate 80 provided with the carrier metal foil 81. The metal foil 11a and the carrier metal foil 81 are preferably copper foils. Other metal foils such as nickel foil may be used. The thickness of the metal foil 11a is, for example, 3 μm or more and 10 μm or less. 6A to 6J are not intended to show the exact ratios of the thicknesses of the components.

  In the example of FIG. 6A, metal foil 11 a is provided on both the front and back surfaces of the support plate 80. The printed wiring board 1 can be formed simultaneously on both sides of the support plate 80. The printed wiring board 1 can be manufactured efficiently. However, the metal foil 11 a is not necessarily provided on both the front and back surfaces of the support plate 80. In FIGS. 6B to 6G and the following description, symbols and descriptions relating to the printed wiring board formed on the upper side of the support plate 80 are appropriately omitted in each drawing. 6B to 6G show only one printed wiring board being manufactured on each surface of the support plate 80. However, a plurality of printed wiring boards may be simultaneously formed in juxtaposition on each surface of the support plate 80.

  As shown in FIG. 6B, an insulating material to be the first insulating layer 21 is laminated on the surface of the metal foil 11a, and a thick metal foil 13a to be the third conductor layer 13 (see FIG. 3) is further formed on the insulating material. Are stacked. By being pressurized from the metal foil 13a side and further heated, the insulating material is joined to the metal foil 11a and the metal foil 13a, and the first insulating layer 21 is formed. The insulating material to be the first insulating layer 21 is, for example, a prepreg formed by impregnating an epoxy resin into a reinforcing material such as an epoxy resin molded into a film or glass fiber. The metal foil 13a is an arbitrary metal foil such as a copper foil or a nickel foil. Preferably, a metal foil having a matte surface is used for the metal foil 13a. Preferably, as shown in the partially enlarged view in FIG. 6B, the metal foil 13a is laminated with the mat surface (the surface having the unevenness 13aG) side directed toward the insulating material serving as the first insulating layer 21 (note that The concavo-convex portion 13aG is shown only in each of the partial enlarged views in FIGS. 6B, 6D, 6E, 6F and 6G, and is omitted in the other drawings).

  As shown in FIG. 6C, a metal film 13b is formed on the entire surface of one surface of the metal foil 13a. The metal coating 13b is formed by electroless plating or electrolytic plating using the metal foil 13a as a seed layer. A third conductor layer 13 composed of the metal foil 13a and the metal coating 13b is obtained. For example, when the metal foil 13a is thinner than the desired thickness of the third conductor layer 13, a metal coating 13b is formed as necessary. Therefore, in the production of the printed wiring board according to the embodiment, the metal coating 13b is not necessarily formed. The metal coating 13b may be formed on one surface of the metal foil 13a by sputtering or vapor deposition.

  As shown in FIG. 6D, the third conductor layer 13 is patterned to have a desired conductor pattern. For example, an etching mask having an opening corresponding to a desired conductor pattern of the third conductor layer 13 is formed on the third conductor layer 13. Then, the third conductor layer 13 is patterned by removing the portion exposed in the opening by etching. As a result, the third conductor layer 13 is separated into individual conductor patterns such as an inner layer conductor pad 7a and an inner layer wiring pattern 7b. The removed portion by etching may have a tapered shape that becomes narrower toward the metal foil 11a side, as shown in FIG. 6D, depending on the characteristics of the etching solution and the etching conditions. The third conductor layer 13 may be patterned by dry etching such as sand blasting or ion etching. In this case, individual conductor patterns having substantially no tapered shape can be formed. Etching is performed over a period of time corresponding to the thickness of the third conductor layer 13. Etching of the third conductor layer 13 may be performed in multiple steps.

  After the patterning of the third conductor layer 13, preferably, the exposed surface of the third conductor layer 13 including the side surface of each conductor pattern of the third conductor layer 13 is roughened. As a result, as shown in the partially enlarged view in FIG. 6D, irregularities 13G are formed on the exposed surfaces of the metal foil 13a and the metal coating 13b. The unevenness 13G is smaller than the unevenness 13aG on the mat surface of the metal foil 13a. Examples of the roughening treatment include blackening treatment by immersion in a strong alkaline solution and microetching by immersion in an organic acid-based etching agent. It is considered that the roughening treatment improves the adhesion between the later-described in-layer insulator 23 (see FIG. 6E) and the third conductor layer 13. In addition, the trace of the unevenness | corrugation 13aG may remain on the exposed surface by the side of the metal foil 13a of the 1st insulating layer 21 after the etching of the 3rd conductor layer 13, or a roughening process. However, since the partial enlarged view in FIG. 6D is for showing the effect of the roughening process on the third conductor layer 13, the unevenness of the exposed surface of the first insulating layer 21 is omitted. Also in FIGS. 6E, 6F and 6G, which will be described later, the unevenness at the interface between the first insulating layer 21 and the in-layer insulator 23 (see FIG. 6E) is omitted.

  As shown in FIG. 6E, the in-layer insulator 23 is formed in the removed portion of the third conductor layer 13 by etching between the conductor patterns. For example, an epoxy resin is printed on the third conductor layer 13. The in-layer insulator 23 is formed by the resin that enters between the conductor patterns in the printed epoxy resin. If necessary, the epoxy resin is cured by heating or the like. As described above, the in-layer insulator 23 may be formed using any insulating material other than epoxy. As shown in the partially enlarged view in FIG. 6E, the unevenness 13G is present at the interface between the metal foil 13a and the metal coating 13b with the in-layer insulator 23, as shown in the partially enlarged view in FIG. 6D described above. It remains in almost the same state.

  When the material constituting the in-layer insulator 23 is applied by printing or the like, as shown in FIG. 6E, not only between the conductor patterns of the third conductor layer 13 but opposite to the metal foil 11a of each conductor pattern. It can also be applied on the side surface. In this case, as shown in FIG. 6F, the constituent material of the in-layer insulator 23 applied onto each conductor pattern of the third conductor layer 13 is exposed until the surface of each conductor pattern of the third conductor layer 13 is exposed. , CMP (chemical mechanical polishing) or the like. One surface of each conductor pattern of the third conductor layer 13 is exposed, and the one surface is substantially flush with the one surface of the in-layer insulator 23 opposite to the metal foil 11a side. As shown in the partially enlarged view in FIG. 6F, on the surface of the conductor film 13b, the unevenness 13G may be almost eliminated by polishing, or only slight unevenness may remain on the surface of the conductor film 13b.

  Thereafter, the exposed surface of the third conductor layer 13 is preferably roughened by blackening or microetching. As described above, the polishing process of the in-layer insulator on the third conductor layer 13 can substantially eliminate the unevenness 13G (see FIG. 6E) or at least change its surface state. The exposed surface of the three conductor layer 13 is roughened again. It is considered that the roughening treatment improves the adhesion between the second insulating layer 22 (see FIG. 6G) described later and the third conductor layer 13.

  As shown in FIG. 6G, an insulating material to be the second insulating layer 22 is laminated on the exposed surfaces of the third conductor layer 13 and the in-layer insulator 23, and the second conductor layer 12 ( A metal foil 12a to be formed (see FIG. 3) is laminated. By being pressurized from the metal foil 12a side and further heated, the insulating material is joined to the third conductor layer 13a, the in-layer insulator 23 and the metal foil 12a, and the second insulating layer 22 is formed. The insulating material to be the second insulating layer 22 is, for example, an epoxy resin or a prepreg formed into a film shape, and is preferably the same as the insulating material to be the first insulating layer 21 described above. The metal foil 12a is an arbitrary metal foil such as a copper foil or a nickel foil. Preferably, a metal foil having the same material and substantially the same thickness as the metal foil 11a is used for the metal foil 12a. As shown in the enlarged view in FIG. 6G, unevenness 13bG is formed on the surface of the conductor coating 13b (interface with the second insulating layer 22) by the roughening treatment after polishing of the in-layer insulator 23 described above. Has been. In the above-described polishing step of the in-layer insulator 23, some unevenness may remain on the surface of the conductor coating 13b. In that case, the remaining unevenness can be roughened again. Therefore, the unevenness 13bG may be slightly larger than the unevenness 13G formed by the roughening process before the formation of the in-layer insulator 23.

  After the formation of the second insulating layer 22, the carrier metal foil 81 and the metal foil 11a are separated. As a result, the printed wiring board and the support plate 80 in the manufacturing process are separated. For example, the thermoplastic adhesive that bonds the metal foil 11a and the carrier metal foil 81 is heated to soften, and in this state, the metal foil 11a and the carrier metal foil 81 are pulled apart. When the metal foil 11a and the carrier metal foil 81 are bonded only at the outer peripheral portion, the metal foil 11a and the carrier metal foil 81 are cut at the inner peripheral side of the bonded portion so that the bonded portion is removed. May be.

As shown in FIG. 6H, the metal foil 11a and the first insulating layer 21 or the metal foil 12a and the first insulating layer 21 are formed at the positions where the first, third and fifth via conductors 4a, 4c and 6b (see FIG. 3) are formed. 2 A via hole 41 penetrating the insulating layer 22 is formed. Although not shown, via holes are similarly formed at the formation positions of the second and fourth via conductors 4b and 4d (see FIG. 4). For example, CO ₂ laser light is applied to predetermined positions on the metal foil 11a and the metal foil 12a. Tapered via holes 41 having diameters reduced toward the third conductor layer 13 due to laser light irradiation from the opposite sides of the metal foil 11 a and the metal foil 12 a to the third conductor layer 13 are provided on both sides of the third conductor layer 13. It is formed in an insulating layer. More via holes 41 are formed in the first connection conductor pad formation region 3a1 than in the first component mounting pad formation region 2a1. Although not shown, via holes 41 are formed in the formation region of the second connection conductor pads 3b (see FIG. 4) more than the formation region of the second component mounting pads 2b (see FIG. 4).

  Subsequently, a metal film (not shown) is formed in the via hole 41 and on the surfaces of the metal foils 11a and 12a by electroless plating or sputtering. Electrolytic plating is performed using this metal film as a seed layer, and an electrolytic plating film is formed in the via hole 41 and on the metal foils 11a and 12a. Electroplating is performed over an appropriate plating time according to the hole diameter, depth, and number of the via holes 41. The electrolytic plating process may be performed a plurality of times depending on the characteristics of the plating solution and the plating conditions. As a result, as shown in FIG. 6I, the first conductor layer 11 is formed on the first insulating layer 21, and the second conductor layer 12 is formed on the second insulating layer 22. First and second conductor layers 11 and 12 are metal foil 11a or metal foil 12a (see FIG. 6H), a metal film formed by electroless plating, and electrolytic plating formed using the metal film as a seed layer. It can be constituted by a membrane. However, in FIG. 6I and FIG. 6J described later, the first and second conductor layers 11 and 12 are each shown in a single layer structure for convenience.

  In each via hole 41 on the first conductor layer 11 side, a first via conductor 4a, a second via conductor 4b (see FIG. 4), and a fifth via that connect the first conductor layer 11 and the third conductor layer 13 are provided. A conductor 6b is formed. Similarly, a third via conductor 4c and a fourth via conductor 4d (see FIG. 4) that connect the second conductor layer 12 and the third conductor layer 13 are formed in each via hole 41 on the second conductor layer 12 side. The The first via conductor 4a is formed in the first component mounting pad formation region 2a1, and the third via conductor 4c is formed in the first connection conductor pad formation region 3a1. Although not shown, the second via conductor 4b is formed in the formation region of the second component mounting pad 2b (see FIG. 4), and the fourth via conductor 4d is the second connection conductor pad 3b ( (See FIG. 4). In the first connection conductor pad formation region 3a1, a larger number of third via conductors 4c are formed than the via conductor (first via conductor 4a) formed in the first component mounting pad formation region 2a1. Although not shown, the number of fourth vias in the formation region of the second connection conductor pads 3b is larger than the number of via conductors (second via conductors 4b) formed in the formation region of the second component mounting pads 2b. A conductor 4d is formed. In addition, after the formation of the first and second conductor layers 11 and 12, preferably, the first and second conductor layers 11 and 12 are made of a chemical solution made of hydrogen peroxide, sulfuric acid or the like for planarization of the surface. Used for soft etching.

  Thereafter, the first and second conductor layers 11 and 12 are patterned into a desired conductor pattern. That is, each of the first and second conductor layers 11, 12 such as the first and second component mounting pads 2a, 2b and the first and second connection conductor pads 3a, 3b (see FIGS. 3 and 4). A conductor pattern is formed. As shown in FIG. 6J, an etching resist 82 is formed to cover the regions of the first and second conductor layers 11 and 12 that are to be the conductor patterns. The formation region of the first component mounting pad, the formation region of the first connection conductor pad, and the like are masked by the etching resist 82. Then, portions of the first and second conductor layers 11 and 12 that are exposed without being covered with the etching resist 82 are removed by etching. As a result, the first and second conductor layers 11 and 12 are patterned so as to have a desired conductor pattern. Through these steps, the printed wiring board 1 shown in FIGS. 1 to 4 is completed.

  As described above, the solder resist layer 30 may be formed on the printed wiring board 1. The solder resist layer 30 can be formed, for example, by applying a photosensitive epoxy resin or the like to almost the entire first surface 1F and / or the second surface 1S by printing or spraying. The solder resist layer 30 is provided with an opening 32 that exposes each component mounting pad, each connection conductor pad, and the like using a photolithography technique. Furthermore, a surface protective film may be formed on the surface of each component mounting pad or each connection conductor pad by electroless plating such as nickel, palladium, or gold, if necessary.

  When a printed wiring board having two or more insulating layers and conductor layers on both sides of the thick inner conductor layer is manufactured, for example, after patterning the conductor layers on both sides shown in FIG. An insulating material to be an insulating layer is laminated. And the process similar to the process shown by FIGS. 6H-6J is repeated. An arbitrary number of insulating layers and conductor layers and via conductors (thermal vias) can be formed on both sides of the thick inner conductor layer.

  Unlike the subtractive method shown in FIGS. 6I and 6J, the first and second conductor layers 11 and 12 having a desired conductor pattern may be formed by a so-called semi-additive method. Moreover, the 3rd conductor layer 13 does not need to be patterned after lamination | stacking of the metal foil 13a, as FIG. 6B-6D shows. For example, the third conductor layer 13 may be patterned in advance so as to have a desired conductor pattern by etching or sandblasting, and then laminated on the first insulating layer 21. The manufacturing method of the printed wiring board of embodiment is not limited to the method demonstrated with reference to FIG. In the printed wiring board manufacturing method of the embodiment, an arbitrary process may be added in addition to the above-described processes, and a part of the processes described in the above description may be omitted.

DESCRIPTION OF SYMBOLS 1 Printed wiring board 1F 1st surface 1S 2nd surface 2a 1st component mounting pad 2a1 1st component mounting pad formation area 2b 2nd component mounting pad 3a 1st connection conductor pad 3a1 1st connection conductor pad formation area 3b Second connection conductor pad 4a First via conductor 4b Second via conductor 4c Third via conductor 4d Fourth via conductor 41 Via hole 7a Inner layer conductor pad 7b Inner layer wiring pattern 11 First conductor layer 12 Second conductor layer 13 Third conductor layer 13a Metal foil 13b Metal coating 21 First insulating layer 22 Second insulating layer 23 Insulator 30 Solder resist layer 31 Solder resist 80 Support plate 82 Etching resist R Component mounting region

Claims (8)

A printed wiring board, wherein the printed wiring board is
An outer conductor layer formed on one and the other outermost layers,
An inner conductor layer formed thicker than the outer conductor layer;
An insulating layer interposed between the outer conductor layer and the inner conductor layer;
A plurality of via conductors formed densely in the insulating layer and connecting each of the outer conductor layers and the inner conductor layer;
A component mounting pad is formed on one of the outer conductor layers,
On the other side of the outer conductor layer, a connecting conductor pad is formed at a position overlapping the component mounting pad,
The component mounting pad and the inner conductor layer are connected by a plurality of the via conductors,
The connection conductor pad and the inner conductor layer are connected by a plurality of the via conductors,
The number of via conductors that connect the connection conductor pads and the inner conductor layer is greater than the number of via conductors that connect the component mounting pads and the inner conductor layer. The printed wiring board according to claim 1, wherein the component mounting pad includes a pair of conductor pads respectively connected to different electrodes of an electronic component mounted on the component mounting pad. 2. The printed wiring board according to claim 1, wherein the connection conductor pad includes a pair of conductor pads respectively connected to different electrodes of an electronic component mounted on the component mounting pad. The printed wiring board according to claim 1, wherein the connection conductor pad is larger than the component mounting pad. 2. The printed wiring board according to claim 1, wherein the via conductor that connects the connection conductor pad and the inner conductor layer is more than the via conductor that connects the component mounting pad and the inner conductor layer. 3. Are formed at a small arrangement pitch. 2. The printed wiring board according to claim 1, wherein the inner conductor layer includes a metal foil having a thickness that occupies 90% or more of the thickness of the inner conductor layer, and a metal film formed on one surface of the metal foil. Is included. 7. The printed wiring board according to claim 6, wherein a surface of the inner conductive layer on the metal foil side is directed to the one side of the outer conductive layer including the component mounting pad. 2. The printed wiring board according to claim 1, wherein the conductor layer of the inner layer is patterned into a predetermined conductor pattern, and a side surface of the conductor pattern of the conductor layer of the inner layer is mounted on the component from the connection conductor pad side. The conductor pattern is inclined so as to increase toward the pad side.

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