JP2018152470A - Normally-off type HFET and method of manufacturing the same - Google Patents

Abstract

Kind Code: A1 An HFET capable of achieving normally-off relatively well and reducing on-resistance and a method of manufacturing the same are provided. A first semiconductor layer (3) made of a nitride semiconductor; a second semiconductor layer (4) made of a nitride semiconductor having a composition different from that of the first semiconductor layer (3) on the first semiconductor layer; a main semiconductor region comprising a two-dimensional carrier gas generated in the first semiconductor layer near the interface between the semiconductor layer 3 and the second semiconductor layer 4; and a first semiconductor region electrically connected to the two-dimensional carrier gas. a main electrode 9; a second main electrode 10 electrically connected to the two-dimensional carrier gas and formed apart from the first main electrode 9; a third semiconductor layer 5 formed between the main electrode 9 and the second main electrode 10 and having p-type conductivity, covering the second semiconductor layer and at least part of the third semiconductor layer; and includes a fourth semiconductor layer 6 made of a nitride semiconductor and a control electrode 8 electrically connected to the third semiconductor layer 5 . [Selection drawing] Fig. 1

Description

The present invention relates to a normally-off type HFET (Hetero Field Effect Transistor) and a method for manufacturing the same.

A conventional HFET includes a semiconductor substrate made of SiC (or Si, GaN, sapphire, etc.), a buffer layer made of a nitride semiconductor such as AlN formed on the semiconductor substrate, and non-doped GaN formed on the buffer layer. An electron transit layer comprising: an electron supply layer comprising non-doped AlGaN formed on the electron transit layer or a laminate including the non-doped AlGaN layer; and an insulation comprising SiNx or SiOx formed on the electron supply layer and partially open. The film includes a gate electrode, a source electrode, and a drain electrode formed on the electron supply layer. Here, non-doped means that no impurity is intentionally introduced into the semiconductor layer.

Since the band gap of AlGaN is larger than the band gap of GaN and the lattice constant of AlGaN is smaller than the lattice constant of GaN, when an electron supply layer made of AlGaN is formed on the electron transit layer made of GaN, the electron supply layer is pulled. Stress acts to cause piezo (piezoelectric) polarization. Since spontaneous polarization also occurs in the electron supply layer, an electric field due to piezo polarization and spontaneous polarization acts near the heterojunction interface between the electron transit layer and the electron supply layer, for example, a two-dimensional carrier gas of a two-dimensional electron gas (2DEG) layer Will occur. The HFET is used as a switching element that can control the flow of electrons from the drain to the source via the channel by using the 2DEG layer as a channel.

On the other hand, in the conventional HFET, the energy level at the heterojunction interface between the electron transit layer and the electron supply layer is equal to or lower than the Fermi level. Therefore, the conventional HFET has a normally-on (depletion type) characteristic having a negative threshold value. However, when a conventional HFET is applied to a power supply device as a power semiconductor element, for example, it is necessary to be a normally-off (enhancement) type having a positive threshold value in order to ensure safety in the event of an abnormality. HFET which solves this problem is disclosed by patent document 1. FIG.

FIG. 6 is a diagram showing a cross-sectional structure of an HFET using a GaN-based material having normally-off characteristics. A semiconductor substrate 1 made of SiC, a buffer layer 2 made of AlN formed on the semiconductor substrate 1, an electron transit layer 3 made of non-doped GaN formed on the buffer layer 2, and formed on the electron transit layer 3 An electron supply layer 4 made of non-doped AlGaN, a p-type semiconductor layer 5 made of p-type GaN formed on a part of the electron supply layer 4, and a p + -type GaN formed on the p-type semiconductor layer 5. A high-concentration p-type semiconductor layer 51, and an insulating film 7 made of SiOx formed on the electron supply layer 4, on the side surface of the p-type semiconductor layer 5, on the side surface and on the side surface of the high-concentration p-type semiconductor layer 51, and partially opened. The gate electrode 8 made of Pd formed on the high-concentration p-type semiconductor layer 51 and in ohmic contact with the high-concentration p-type semiconductor layer 51 and the p-type semiconductor layer 5 on the electron supply layer 4 are provided therebetween. P-type semiconductor 5 and spaced between Ti and Al which is formed with the source electrode 9 and drain electrode 10 made of, and a. In the HFET of FIG. 6, a p-type semiconductor layer 51 made of p-type GaN is formed on the electron supply layer 4 immediately below the gate electrode 8. Thereby, the energy level of the electron transit layer 4 and the electron supply layer 5 is raised, and an HFET having normally-off characteristics is obtained.

Japanese Unexamined Patent Publication No. 2009-200395

In order to achieve normally-off in the HFET as in Patent Document 1, it is necessary to reduce the carrier concentration of the two-dimensional electron gas in the electron transit layer 3 immediately below the p-type GaN layer 5. Therefore, the electron supply layer 4 immediately below the p-type GaN layer 5 is formed thin. As a result, the electron supply layer 4 immediately below the p-type GaN layer 5 is also thinned, and the carrier concentration of the two-dimensional electron gas generated in the electron transit layer 3 is lowered, and the on-resistance of the HFET is increased. Further, when the electron supply layer 4 immediately below the p-type GaN layer 5 is formed thick, there is a problem that the HFET cannot be turned off satisfactorily.

Therefore, an object of the present invention is to provide a normally-off type HFET (Hetero Field Effect Transistor) that can realize normally-off well and reduce on-resistance.

In order to solve the above problems and achieve the above object, a normally-off HFET includes a first semiconductor layer made of a nitride semiconductor and a nitride semiconductor having a composition different from that of the first semiconductor layer on the first semiconductor layer. A main semiconductor region comprising: a second semiconductor layer comprising: a two-dimensional carrier gas generated in the first semiconductor layer in the vicinity of the interface between the first semiconductor layer and the second semiconductor layer; On the second semiconductor layer, a first main electrode that is electrically connected, a second main electrode that is electrically connected to the two-dimensional carrier gas and is spaced apart from the first main electrode, and A third semiconductor layer formed between the first main electrode and the second main electrode and having a p-type conductivity, and at least part of the second semiconductor layer and the third semiconductor layer; A fourth semiconductor layer made of a nitride semiconductor, Characterized in that it comprises between the semiconductor layer and the control electrode electrically connecting the.

In order to solve the above problems and achieve the above object, a normally-off type HFET manufacturing method includes a nitride semiconductor having a composition different from that of the first semiconductor layer on the first semiconductor layer made of a nitride semiconductor. Forming a second semiconductor layer comprising: a third semiconductor layer having a p-type conductivity type on the second semiconductor layer; removing at least a part of the third semiconductor layer; Forming a fourth semiconductor layer made of a nitride semiconductor and covering at least a part of the third semiconductor layer and penetrating the fourth semiconductor layer, and forming a third semiconductor layer Forming a gate electrode electrically connected to the layer.

According to the present invention, it is possible to provide a normally-off type HFET that can realize normally-off well and reduce on-resistance, and a method for manufacturing the normally-off HFET.

It is sectional drawing which shows the structure of HFET of 1st Example of this invention. It is sectional drawing which shows the structure of HFET of 1st Example of this invention. It is process sectional drawing which shows the manufacturing method of normally-off type HFET of 1st Example of this invention. It is process sectional drawing which shows the manufacturing method of normally-off type HFET of the modification of 1st Example of this invention. It is sectional drawing which shows the structure of normally-off type HFET of 2nd Example of this invention. It is sectional drawing which shows the structure of the conventional normally-off type HFET.

Next, an example of a semiconductor device (normally-off type HFET) and a manufacturing method thereof according to the embodiment of the present invention will be described with reference to FIGS.

1 and 2 are views showing a cross-sectional structure of a semiconductor device according to a first embodiment of the present invention. The semiconductor device of FIG. 1 includes a silicon-based semiconductor substrate 1 made of SiC or Si, a nitride semiconductor buffer layer 2 made of AlN formed on the semiconductor substrate 1, and non-doped GaN formed on the buffer layer 2. The first nitride semiconductor layer 3 (first semiconductor layer) and the first nitride semiconductor layer 3 formed on the first nitride semiconductor layer 3 and made of non-doped AlGaN are formed with different compositions. A non-doped or n-type impurity doped second nitride semiconductor layer 4 (second semiconductor layer) and p-type AlGaN or p-type GaN formed on a part of the second nitride semiconductor layer 4 For example, the third semiconductor layer 5 (third semiconductor layer) of a p-type conductivity type nitride semiconductor, the second nitride semiconductor layer 4 and at least a part of the third semiconductor layer 5 are covered. Side surface of the third semiconductor layer 5 A fourth semiconductor layer made of a nitride semiconductor, which is thicker than the thickness y1 of the second nitride semiconductor layer 4 immediately below the third semiconductor layer 5 and is doped with a non-doped or n-type impurity. 6 (fourth semiconductor layer). The first nitride semiconductor layer 3 serves as an electron transit layer, and the portion of the fourth semiconductor layer 6 in contact with the second nitride semiconductor layer 4 and the second nitride semiconductor layer 4 serve as an electron supply layer. A two-dimensional electron gas layer is not formed in at least a part of the electron transit layer in the vicinity of the interface between the electron supply layer and the electron transit layer immediately below the third semiconductor layer 5, and between the gate and drain except this region. Between the gate and the source, a two-dimensional electron gas layer is formed in the electron transit layer in the vicinity of the interface between the electron supply layer and the electron transit layer. The first nitride semiconductor layer 3, the second nitride semiconductor layer 4, and the portion of the fourth semiconductor layer 6 in contact with the second nitride semiconductor layer 4 constitute the main semiconductor region. The thickness y1 of the second nitride semiconductor layer 4 is, for example, 5 nm to 10 nm. The thickness of the third semiconductor layer 5 is, for example, 50 nm to 200 nm. The thickness y2 of the fourth semiconductor layer 6 is, for example, 20 nm to 50 nm, and the thickness of the third semiconductor layer 5 is larger than the thickness y2 of the fourth semiconductor layer 6. The thickness y2 of the fourth semiconductor layer 6 is formed to be thicker than the thickness y3 of the fourth semiconductor layer 6 on the side surface of the third semiconductor layer 5.

Further, the thickness y2 of the sixth nitride semiconductor layer 6 outside the third semiconductor layer 5 is larger than the thickness y4 of the portion of the second nitride semiconductor layer 4 outside just below the third semiconductor layer 5. It is formed thick. According to the semiconductor device of Example 1, by providing the fourth semiconductor layer 6 so as to cover at least a part of the third semiconductor layer 5, normally-off can be satisfactorily realized and the on-resistance can be reduced.

The third semiconductor layer 5 is formed only in a part of the region on the second nitride semiconductor layer 4. There is no step on the lower surface of the third semiconductor layer 5, and the lower surface of the third semiconductor layer 5 is not formed. The width is wider than the width of the upper surface of the third semiconductor layer 5. The side surface of the third semiconductor layer 5 has a gentle slope.

On the second nitride semiconductor layer 4 and on the side surface of the third semiconductor layer 5, the fourth semiconductor layer 6 is formed with a composition different from that of the first nitride semiconductor layer 3, for example, the second nitride It consists of the same composition (AlGaN) as the semiconductor layer 4. Note that the fourth semiconductor layer 6 may be a nitride semiconductor made of AlGaN having a higher Al content than the second nitride semiconductor layer 4. Thereby, the two-dimensional electron gas in the electron transit layer can be increased, and a semiconductor device with a low on-voltage can be provided.

The second nitride semiconductor layer 4 is preferably a non-doped nitride semiconductor, and the fourth semiconductor layer 6 is preferably a nitride semiconductor containing an n-type dopant such as silicon. Thereby, the channel resistance of the portion of the second nitride semiconductor layer 4 immediately below the third semiconductor layer 5 is relatively increased, and the channel resistance of the fourth semiconductor layer 6 outside the portion immediately below the third semiconductor layer 5 is increased. Can be reduced. Further, the thickness y1 of the portion of the second nitride semiconductor layer 4 immediately below the third semiconductor layer 5 is larger than the thickness y4 of the portion of the second nitride semiconductor layer 4 outside the portion immediately below the third semiconductor layer 5. Thick is desirable. Thereby, since the second nitride semiconductor layer 4 has lower N-type impurities than the fourth semiconductor layer 6, it is possible to increase the resistance of the second nitride semiconductor layer 4 immediately below the third semiconductor layer 5. The gate leakage current can be suppressed while the on-resistance is kept low. Further, the fourth semiconductor layer 6 may be provided not only on the side surface of the third semiconductor layer 5 but also on the upper surface of the third semiconductor layer 5.

On the fourth semiconductor layer 6, an insulating film 7 made of SiNx or SiOx (x is an integer of 1 to 2) partially opened is provided. Here, it is desirable to form the insulating film 7 as a film having a strain so as to generate a stress that increases the carrier concentration of the two-dimensional electron gas layer with respect to the fourth semiconductor layer 6. Thereby, the carrier concentration of the two-dimensional electron gas layer is increased, and the on-voltage of the HFET can be reduced.

The gate electrode (control electrode) 8 penetrates the fourth semiconductor layer 6 through the opening of the insulating film 7 and is electrically connected to the third semiconductor layer 5. The gate electrode 8 is made of, for example, Pd or Ni so as to form a Schottky junction with the fourth semiconductor layer 6. An insulating film 7 may be provided between the side surface or upper surface of the gate electrode 8 and the fourth semiconductor layer 6.

The source electrode (first main electrode) 9 and the drain electrode (second main electrode) 10 are disposed on the first nitride semiconductor layer 3 so as to provide the gate electrode 8 therebetween. For example, Ti and Al It consists of. The source electrode 9 and the drain electrode 10 are provided so as to penetrate the second nitride semiconductor layer 4 and the fourth semiconductor layer 6 through the opening of the insulating film 7. What is necessary is just to be electrically connected to the three-dimensional electron gas layer with low resistance. For example, the source electrode 9 and the drain electrode 10 may be formed on the second nitride semiconductor layer 4 so as not to penetrate the second nitride semiconductor layer 4. Further, the source electrode 9 and the drain electrode 10 may be formed on the fourth semiconductor layer 6 so as not to penetrate the fourth semiconductor layer 6.

FIG. 3 is a process sectional view showing the method of manufacturing the semiconductor device according to the first embodiment of the present invention. First, as shown in FIG. 3A, a buffer layer 2 made of AlN having a thickness of, for example, 100 nm and a first nitride semiconductor layer 3 made of, for example, GaN having a thickness of, for example, 2 μm, are epitaxially grown on the semiconductor substrate 1. And second nitride semiconductor layer 4 made of AlGaN, and a third semiconductor layer of p-type conductivity type nitride semiconductor made of p-type AlGaN or p-type GaN having an impurity concentration of, for example, 1 × 10 ¹⁹ cm ⁻³ 5 are laminated in this order by MOCVD method or MBE method. At this time, the thickness of the second nitride semiconductor layer 4 and the thickness of the third semiconductor layer 5 are such that a two-dimensional electron gas layer is not generated in the region of the first nitride semiconductor layer 3 immediately below the third semiconductor layer 5. The thickness is determined.

Next, as shown in FIG. 3B, a mask such as a silicon oxide film is formed on a part of the third semiconductor layer 5 to be a gate formation region (control region), and ICP (Inductive-Coupled Plasma). By dry etching such as the method, the region portion of the third semiconductor layer 5 other than the gate formation region and the second nitride semiconductor layer 4 outside the third semiconductor layer 5 are removed in the thickness direction, and the third semiconductor is removed. The thickness y4 of the region of the second nitride semiconductor layer 4 outside the third semiconductor layer 5 is thinner than the thickness y1 of the second nitride semiconductor layer 4 immediately below the layer 5. By this dry etching, an inclination is formed on the side surface of the third semiconductor layer 5 so that the width of the lower surface of the third semiconductor layer 5 is wider than the width of the upper surface of the third semiconductor layer 5. Note that the third semiconductor layer 5 may not be etched.

Further, the region of the second nitride semiconductor layer 4 outside the third semiconductor layer 5 may be completely removed instead of being part of it. In this case, after the second nitride semiconductor layer 4 is completely removed and before the next step shown in FIG. 3C, the second nitride semiconductor layer 4 is replaced with the first nitride semiconductor layer. The second nitride semiconductor layer 4 may be formed on the substrate 3 again by the MOCVD method or the MBE method.

Next, as shown in FIG. 3C, the fourth semiconductor layer 6 having a thickness of 25 nm is formed by selective growth of an epitaxial layer such as MOCVD or MBE so as to cover at least a part of the third semiconductor layer 5. Form. The fourth semiconductor layer 6 is formed with a composition different from that of the first nitride semiconductor layer 3 and is made of, for example, the same composition (AlGaN) as that of the second nitride semiconductor layer 4. By providing the fourth semiconductor layer 6, a high-concentration two-dimensional electron gas layer can be formed in the first nitride semiconductor layer 3 excluding at least a part immediately below the third semiconductor layer 5.

Here, the fourth semiconductor layer 6 may be a nitride semiconductor made of AlGaN having a higher Al content than the second nitride semiconductor layer 4. Thereby, the two-dimensional electron gas concentration at the interface between the third semiconductor layer 5 and the fourth semiconductor layer 6 is increased, and the on-resistance can be reduced. The second nitride semiconductor layer 4 is preferably a non-doped nitride semiconductor, and the fourth semiconductor layer 6 is preferably a nitride semiconductor containing an n-type dopant such as silicon. Thereby, the channel resistance of the portion of the second nitride semiconductor layer 4 immediately below the third semiconductor layer 5 is relatively increased, and the channel resistance of the fourth semiconductor layer 6 outside the portion immediately below the third semiconductor layer 5 is increased. Can be reduced. Furthermore, the thickness y4 of the portion of the second nitride semiconductor layer 4 corresponding to the region below the drain-gate formation region and the source-gate formation region outside the region directly below the third semiconductor layer 5 is the third semiconductor layer. It is desirable that the thickness of the fourth nitride semiconductor layer 6 is less than 5 below the thickness y2, and the fourth semiconductor layer 6 contains an n-type dopant such as silicon. Thereby, the channel resistance of the portion of the second nitride semiconductor layer 4 immediately below the third semiconductor layer 5 is relatively increased, and the channel resistance of the fourth semiconductor layer 6 outside the portion immediately below the third semiconductor layer 5 is increased. Can be reduced. Therefore, the gate leakage current can be suppressed while the on-resistance is kept low.

When the fourth semiconductor layer 6 is provided on the side surface of the third semiconductor layer 5, the thickness y <b> 2 of the fourth semiconductor layer 6 on the second nitride semiconductor layer 4 is on the side surface of the third semiconductor layer 5. It is formed thicker than the thickness y3. Note that the fourth semiconductor layer 6 may be formed by selective growth such as MOCVD or MBE without removing the mask on the third semiconductor layer 5. Thereby, the fourth semiconductor layer 6 can be formed by self-alignment.

Further, as shown in FIG. 3C, the fourth semiconductor layer 6 may be provided not only on the side surface of the third semiconductor layer 5 but also on the upper surface of the third semiconductor layer 5.

Further, by using the SiOx film as the mask, only the fourth semiconductor layer 6 is n-type doped due to the effect of oxygen and Si incorporation in the fourth semiconductor layer 6, which can contribute to lowering the resistance of the HFET. .

Next, as shown in FIG. 3D, a part of the insulating film 7 is opened by dry etching, and a hole penetrating the fourth nitride semiconductor layer 6 is formed in the opening of the insulating film 7. The gate electrode 8 and the third semiconductor layer 5 are connected to each other by the gate electrode 8 formed in the above. Here, the activation rate of the third semiconductor layer 5 may be improved by performing an active heat treatment by laser annealing or the like before forming the hole and forming the gate electrode 8.

Further, a part of the insulating film 7 is opened so as to be separated from the gate electrode 8 and provided on both sides of the gate electrode 8, and the fourth nitride semiconductor layer 6 and the second nitride semiconductor layer 4 are formed in the opening. A through-hole is formed, and the source electrode 9 and the drain electrode 10 are formed.

Here, the gate electrode 8, the source electrode 9, and the drain electrode 10 may be formed before the insulating film 7.

In forming the third semiconductor layer 5, a region portion of the third semiconductor layer 5 other than the gate formation region and a region outside the third semiconductor layer 5 are formed by dry etching such as an ICP (Inductive-Coupled Plasma) method. The second nitride semiconductor layer 4 is removed in the thickness direction, and the second nitride outside the third semiconductor layer 5 than the thickness y1 of the second nitride semiconductor layer 4 immediately below the third semiconductor layer 5 is removed. The thickness y4 of the region of the semiconductor layer 4 is reduced. Alternatively, when the thickness of the region of the second nitride semiconductor layer 4 outside the third semiconductor layer 5 is increased, the thickness y1 of the second nitride semiconductor layer 4 immediately below the third semiconductor layer 5 is increased, The third semiconductor layer 5 cannot fully exhibit the normally-off function of blocking the two-dimensional electron gas. However, according to the method for manufacturing the semiconductor device according to the first embodiment, since the fourth nitride semiconductor layer 6 is formed thereafter, the second nitride semiconductor layer 4 immediately below the third semiconductor layer 5 is formed. It is possible to increase the concentration of the two-dimensional electron gas layer while making the thickness y1 sufficiently thick to exhibit the normally-off characteristic. Therefore, according to the method for manufacturing the semiconductor device according to the first embodiment, the channel resistance can be reduced and the on-voltage can be reduced. Further, since no recess is formed immediately below the gate electrode 8, there is no variation in threshold due to variation in recess shape, and the threshold can be easily controlled. Further, even if the thickness of the second nitride semiconductor layer 4 varies somewhat by dry etching as shown in FIG. 3B, the variation in channel resistance can be achieved by adjusting the thickness of the fourth nitride semiconductor layer 6. Can be suppressed.

(Modification) FIG. 4 shows a modification of the semiconductor device of the first embodiment. In addition, the same code | symbol is attached | subjected to the same member in principle, and the repeated description is abbreviate | omitted. 4 (a) is the same as FIG. 3 (a). Thereafter, in FIG. 4B, a mask such as a silicon oxide film is formed on a part of the third semiconductor layer 5 to be a gate formation region (control region), and an ICP (Inductive-Coupled Plasma) method or the like is used. By dry etching, the region of the third semiconductor layer 5 other than the gate formation region and the second nitride semiconductor layer 4 outside the third semiconductor layer 5 are completely removed. At this time, a part of the upper surface side of the first nitride semiconductor layer 3 outside the third semiconductor layer 5 may also be removed.

Next, in FIG. 4C, the fifth semiconductor layer 61 and the sixth semiconductor layer having a thickness of 25 nm are formed by selective growth such as MOCVD or MBE so as to cover at least a part of the third semiconductor layer 5. 62. The fifth semiconductor layer 61 is made of GaN, and the fifth semiconductor layer 61 and the first nitride semiconductor layer 3 constitute an electron transit layer. The sixth semiconductor layer 62 is made of AlGaN, and the region of the sixth semiconductor layer 62 on the region of the fifth semiconductor layer 61 in contact with the first nitride semiconductor layer 3 functions as an electron supply layer. Thereby, a high-concentration two-dimensional electron gas layer is formed in the vicinity of the interface between the sixth semiconductor layer 62 and the region of the fifth semiconductor layer 61 in contact with the first nitride semiconductor layer 3. Then, an insulating film 7 made of SiNx or SiOx (x is an integer of 1 to 2) is formed on the fourth semiconductor layer 6. The insulating film 7 may be added with a large amount of hydrogen.

Next, as shown in FIG. 4D, a part of the insulating film 7 is opened by dry etching, and a hole penetrating the fifth semiconductor layer 61 and the sixth semiconductor layer 62 in the opening of the insulating film 7. The gate electrode 8 and the third semiconductor layer 5 are connected by the gate electrode 8 formed in the hole. Further, a part of the insulating film 7 is opened on both sides of the gate electrode 8 apart from the gate electrode 8, and a hole penetrating the fifth semiconductor layer 61 and the sixth semiconductor layer 62 is formed in the opening, A source electrode 9 and a drain electrode 10 are formed.

According to the modification of the semiconductor device of Example 1, since the electron supply layer is determined by the thickness of the sixth semiconductor layer 62 that is selectively grown, variation in the thickness of the electron supply layer can be suppressed. In addition, the upper surface of the electron transit layer becomes the upper surface of the fifth semiconductor layer 61 that is selectively grown, and the upper surface of the electron transit layer is not affected by damage due to dry etching, and variation in on-resistance can be suppressed. Note that the fifth semiconductor layer 61 may be formed to have a carbon concentration lower than that of the first nitride semiconductor layer 3. When the carbon concentration of the fifth semiconductor layer 61 is lower than the carbon concentration of the first nitride semiconductor layer 3, a high concentration two-dimensional electron gas can be generated in the fifth semiconductor layer 61.

Second Embodiment FIG. 5 is a cross-sectional view showing an HFET of a second embodiment. In the semiconductor device of FIG. 5, the gate electrode 8 also extends through the insulating film 7 on the inclined side surface of the fourth nitride semiconductor layer 6 on the drain electrode 10 side of the third semiconductor layer 5. Different from the HFET of FIG. By forming the gate electrode 8 as shown in FIG. 5, the electric field concentration of the third semiconductor layer 5 on the drain electrode 10 side can be easily relaxed, and the leakage current of the HFET can be suppressed.

The HFET of the present invention is not limited to the above-described embodiments, and various modifications can be made. For example, the semiconductor substrate 1 may be made of Si, GaN, or sapphire. Further, the buffer layer 2 may be formed of a multilayer film including AlGaN, GaN, or the like on the AlN layer, or a multilayer buffer layer in which at least two of an AlN layer, AlGaN, and GaN are repeatedly stacked. The second nitride semiconductor layer 4, the third semiconductor layer 5, and the fourth semiconductor layer 6 may be nitride semiconductors including In, Al, and Ga such as InGaN and InAlN. In particular, the third semiconductor layer 5 may be a material that generates a strong piezoelectric field. A cap layer made of a nitride semiconductor such as GaN may be formed between the fourth semiconductor layer 6 and the insulating film 7. Further, the upper surface of the third semiconductor layer 5 on which the gate electrode 5 is formed may be a recess. Further, a conductive layer made of a conductive material different from that of the gate electrode 9 may be formed between the gate electrode 9 and the third semiconductor layer 5. Further, a spacer layer made of a nitride semiconductor layer having an Al content higher than that of the second nitride semiconductor layer 4 is formed on the first nitride semiconductor layer 3, and the second nitride semiconductor layer 4 is formed thereon. May be formed.

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Buffer layer 3 1st nitride semiconductor layer 4 2nd nitride semiconductor layer 5 3rd semiconductor layer 6 4th semiconductor layer 7 Insulating film 8 Gate electrode 9 Source electrode 10 Drain electrode

Claims (12)

A first semiconductor layer made of a nitride semiconductor; a second semiconductor layer made of a nitride semiconductor having a composition different from that of the first semiconductor layer on the first semiconductor layer; the first semiconductor layer; A main semiconductor region comprising a two-dimensional carrier gas generated in the first semiconductor layer in the vicinity of the interface with the second semiconductor layer; a first main electrode electrically connected to the two-dimensional carrier gas; A second main electrode electrically connected to the two-dimensional carrier gas and spaced apart from the first main electrode; on the second semiconductor layer, the first main electrode; and A third semiconductor layer formed between the second main electrode and having a p-type conductivity, and formed on the second semiconductor layer and so as to cover at least a part of the third semiconductor layer. A fourth semiconductor layer made of a nitride semiconductor, and the third semiconductor layer, Normally-off HFET including a control electrode for gas connecting the. 2. The normally-off HFET according to claim 1, wherein a thickness of the fourth semiconductor layer on the second semiconductor layer is thicker than a thickness of the second semiconductor layer immediately below the third semiconductor layer. . 3. The normally-off type HFET according to claim 1, wherein there is no step on the lower surface of the third semiconductor layer. The fourth semiconductor layer extends on the upper surface of the third semiconductor layer via a side surface of the third semiconductor layer, and the control electrode is disposed on the second main electrode side via an insulating film. The normally-off type HFET according to claim 1, wherein the normally-off type HFET is stretched on the fourth semiconductor layer. 2. The two-dimensional electron gas is not generated in the first semiconductor layer in the vicinity of the interface between the first semiconductor layer and the second semiconductor layer in at least a part immediately below the control electrode. Item 5. A normally-off HFET according to any one of Items 1 to 4. 6. The fourth semiconductor layer according to claim 1, wherein the fourth semiconductor layer includes an n-type dopant, and the fourth semiconductor layer has an n-type impurity higher than that of the second semiconductor layer. Normally-off type HFET. 7. The normally-off type HFET according to claim 1, wherein the Al content of the fourth semiconductor layer is higher than the Al content of the second semiconductor layer. A second semiconductor layer made of a nitride semiconductor having a composition different from that of the first semiconductor layer is formed on the first semiconductor layer made of a nitride semiconductor, and a p-type conductivity type is formed on the second semiconductor layer. Forming a third semiconductor layer, removing at least a part of the third semiconductor layer, and covering at least a part of the third semiconductor layer and the second semiconductor layer Forming a fourth semiconductor layer formed of a nitride semiconductor, and forming a control electrode penetrating the fourth semiconductor layer and electrically connected to the third semiconductor layer. A method of manufacturing a normally-off type HFET, comprising: 9. The normally-off type HFET manufacturing method according to claim 8, further comprising the step of removing at least a part of the third semiconductor layer outside the control region before forming the fourth semiconductor layer. A normally-off type HFET manufacturing method in which the control electrode is provided between first and second main electrodes electrically connected to a two-dimensional electron gas layer formed in the first semiconductor layer. The step of forming the fourth semiconductor layer is a step of extending from the second semiconductor layer to the upper surface of the third semiconductor layer via the side surface of the third semiconductor layer. The method for manufacturing a normally-off type HFET according to claim 9, wherein the control electrode is a step of extending on the fourth semiconductor layer on the second main electrode side through an insulating film. 11. The fourth semiconductor layer according to claim 8, wherein the fourth semiconductor layer contains an n-type dopant, and the fourth semiconductor layer has an n-type impurity higher than that of the second semiconductor layer. Manufacturing method of normally-off type HFET. 12. The thickness of the fourth semiconductor layer on the second semiconductor layer is greater than the thickness of the second semiconductor layer immediately below the third semiconductor layer. 12. A method for producing a normally-off HFET as described in one of the above.

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